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1 6 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
30
////                                                              ////
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//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
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`timescale 1 ns/100 ps
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// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
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        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
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endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
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output o;
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`ifdef SIM_GBUF
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assign o=i;
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`else
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gbuf gbuf_i0 ( .CLK(i), .GL(o));
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`endif
64
endmodule
65
 //ACTEL
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// sync reset
67
// input active lo async reset, normally from external reset generetaor and/or switch
68
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73
reg [0:1] tmp;
74
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76
        tmp <= 2'b00;
77
else
78
        tmp <= {1'b1,tmp[0]};
79
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
80
endmodule
81
// vl_pll
82
`timescale 1 ns/100 ps
83
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84
parameter index = 0;
85
parameter number_of_clk = 1;
86
parameter period_time_0 = 20;
87
parameter period_time_1 = 20;
88
parameter period_time_2 = 20;
89
parameter lock_delay = 2000;
90
input clk_i, rst_n_i;
91
output lock;
92
output reg [0:number_of_clk-1] clk_o;
93
output [0:number_of_clk-1] rst_o;
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`ifdef SIM_PLL
95
always
96
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97
generate if (number_of_clk > 1)
98
always
99
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100
endgenerate
101
generate if (number_of_clk > 2)
102
always
103
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110
assign #lock_delay lock = rst_n_i;
111
endmodule
112
`else
113
generate if (number_of_clk==1 & index==0) begin
114
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115
end
116
endgenerate // index==0
117
generate if (number_of_clk==1 & index==1) begin
118
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==1
121
generate if (number_of_clk==1 & index==2) begin
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        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==2
125
generate if (number_of_clk==1 & index==3) begin
126
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==0
129
generate if (number_of_clk==2 & index==0) begin
130
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==1) begin
134
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==1
137
generate if (number_of_clk==2 & index==2) begin
138
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==2
141
generate if (number_of_clk==2 & index==3) begin
142
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==0
145
generate if (number_of_clk==3 & index==0) begin
146
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==1) begin
150
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==1
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generate if (number_of_clk==3 & index==2) begin
154
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==2
157
generate if (number_of_clk==3 & index==3) begin
158
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==0
161
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164
end
165
endgenerate
166
endmodule
167
`endif
168
 //actel
169
//////////////////////////////////////////////////////////////////////
170
////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
178
////   - add more different registers                             ////
179
////                                                              ////
180
////  Author(s):                                                  ////
181
////      - Michael Unneback, unneback@opencores.org              ////
182
////        ORSoC AB                                              ////
183
////                                                              ////
184
//////////////////////////////////////////////////////////////////////
185
////                                                              ////
186
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187
////                                                              ////
188
//// This source file may be used and distributed without         ////
189
//// restriction provided that this copyright statement is not    ////
190
//// removed from the file and that any derivative work contains  ////
191
//// the original copyright notice and the associated disclaimer. ////
192
////                                                              ////
193
//// This source file is free software; you can redistribute it   ////
194
//// and/or modify it under the terms of the GNU Lesser General   ////
195
//// Public License as published by the Free Software Foundation; ////
196
//// either version 2.1 of the License, or (at your option) any   ////
197
//// later version.                                               ////
198
////                                                              ////
199
//// This source is distributed in the hope that it will be       ////
200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203
//// details.                                                     ////
204
////                                                              ////
205
//// You should have received a copy of the GNU Lesser General    ////
206
//// Public License along with this source; if not, download it   ////
207
//// from http://www.opencores.org/lgpl.shtml                     ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210
module dff ( d, q, clk, rst);
211
        parameter width = 1;
212
        parameter reset_value = 0;
213
        input [width-1:0] d;
214
        input clk, rst;
215
        output reg [width-1:0] q;
216
        always @ (posedge clk or posedge rst)
217
        if (rst)
218
                q <= reset_value;
219
        else
220
                q <= d;
221
endmodule
222
module dff_array ( d, q, clk, rst);
223
        parameter width = 1;
224
        parameter depth = 2;
225
        parameter reset_value = 1'b0;
226
        input [width-1:0] d;
227
        input clk, rst;
228
        output [width-1:0] q;
229
        reg  [0:depth-1] q_tmp [width-1:0];
230
        integer i;
231
        always @ (posedge clk or posedge rst)
232
        if (rst) begin
233
            for (i=0;i<depth;i=i+1)
234
                q_tmp[i] <= {width{reset_value}};
235
        end else begin
236
            q_tmp[0] <= d;
237
            for (i=1;i<depth;i=i+1)
238
                q_tmp[i] <= q_tmp[i-1];
239
        end
240
    assign q = q_tmp[depth-1];
241
endmodule
242
module dff_ce ( d, ce, q, clk, rst);
243
        parameter width = 1;
244
        parameter reset_value = 0;
245
        input [width-1:0] d;
246
        input ce, clk, rst;
247
        output reg [width-1:0] q;
248
        always @ (posedge clk or posedge rst)
249
        if (rst)
250
                q <= reset_value;
251
        else
252
                if (ce)
253
                        q <= d;
254
endmodule
255
module dff_sr ( aclr, aset, clock, data, q);
256
    input         aclr;
257
    input         aset;
258
    input         clock;
259
    input         data;
260
    output reg    q;
261
   always @ (posedge clock or posedge aclr or posedge aset)
262
     if (aclr)
263
       q <= 1'b0;
264
     else if (aset)
265
       q <= 1'b1;
266
     else
267
       q <= data;
268
endmodule
269
// LATCH
270
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
271
module latch ( d, le, q, clk);
272
input d, le;
273
output q;
274
input clk;/*
275
   always @ (posedge direction_set or posedge direction_clr)
276
     if (direction_clr)
277
       direction <= going_empty;
278
     else
279
       direction <= going_full;*/
280
endmodule
281
//////////////////////////////////////////////////////////////////////
282
////                                                              ////
283
////  Versatile counter                                           ////
284
////                                                              ////
285
////  Description                                                 ////
286
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
287
////  counter                                                     ////
288
////                                                              ////
289
////  To Do:                                                      ////
290
////   - add LFSR with more taps                                  ////
291
////                                                              ////
292
////  Author(s):                                                  ////
293
////      - Michael Unneback, unneback@opencores.org              ////
294
////        ORSoC AB                                              ////
295
////                                                              ////
296
//////////////////////////////////////////////////////////////////////
297
////                                                              ////
298
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
299
////                                                              ////
300
//// This source file may be used and distributed without         ////
301
//// restriction provided that this copyright statement is not    ////
302
//// removed from the file and that any derivative work contains  ////
303
//// the original copyright notice and the associated disclaimer. ////
304
////                                                              ////
305
//// This source file is free software; you can redistribute it   ////
306
//// and/or modify it under the terms of the GNU Lesser General   ////
307
//// Public License as published by the Free Software Foundation; ////
308
//// either version 2.1 of the License, or (at your option) any   ////
309
//// later version.                                               ////
310
////                                                              ////
311
//// This source is distributed in the hope that it will be       ////
312
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
313
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
314
//// PURPOSE.  See the GNU Lesser General Public License for more ////
315
//// details.                                                     ////
316
////                                                              ////
317
//// You should have received a copy of the GNU Lesser General    ////
318
//// Public License along with this source; if not, download it   ////
319
//// from http://www.opencores.org/lgpl.shtml                     ////
320
////                                                              ////
321
//////////////////////////////////////////////////////////////////////
322
// binary counter
323
module cnt_bin_ce ( cke, q, rst, clk);
324
   parameter length = 4;
325
   input cke;
326
   output [length:1] q;
327
   input rst;
328
   input clk;
329
   parameter clear_value = 0;
330
   parameter set_value = 1;
331
   parameter wrap_value = 0;
332
   parameter level1_value = 15;
333
   reg  [length:1] qi;
334
   wire [length:1] q_next;
335
   assign q_next = qi + {{length-1{1'b0}},1'b1};
336
   always @ (posedge clk or posedge rst)
337
     if (rst)
338
       qi <= {length{1'b0}};
339
     else
340
     if (cke)
341
       qi <= q_next;
342
   assign q = qi;
343
endmodule
344
//////////////////////////////////////////////////////////////////////
345
////                                                              ////
346
////  Versatile counter                                           ////
347
////                                                              ////
348
////  Description                                                 ////
349
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
350
////  counter                                                     ////
351
////                                                              ////
352
////  To Do:                                                      ////
353
////   - add LFSR with more taps                                  ////
354
////                                                              ////
355
////  Author(s):                                                  ////
356
////      - Michael Unneback, unneback@opencores.org              ////
357
////        ORSoC AB                                              ////
358
////                                                              ////
359
//////////////////////////////////////////////////////////////////////
360
////                                                              ////
361
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
362
////                                                              ////
363
//// This source file may be used and distributed without         ////
364
//// restriction provided that this copyright statement is not    ////
365
//// removed from the file and that any derivative work contains  ////
366
//// the original copyright notice and the associated disclaimer. ////
367
////                                                              ////
368
//// This source file is free software; you can redistribute it   ////
369
//// and/or modify it under the terms of the GNU Lesser General   ////
370
//// Public License as published by the Free Software Foundation; ////
371
//// either version 2.1 of the License, or (at your option) any   ////
372
//// later version.                                               ////
373
////                                                              ////
374
//// This source is distributed in the hope that it will be       ////
375
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
376
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
377
//// PURPOSE.  See the GNU Lesser General Public License for more ////
378
//// details.                                                     ////
379
////                                                              ////
380
//// You should have received a copy of the GNU Lesser General    ////
381
//// Public License along with this source; if not, download it   ////
382
//// from http://www.opencores.org/lgpl.shtml                     ////
383
////                                                              ////
384
//////////////////////////////////////////////////////////////////////
385
// binary counter
386
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
387
   parameter length = 4;
388
   input clear;
389
   input cke;
390
   output [length:1] q;
391
   input rst;
392
   input clk;
393
   parameter clear_value = 0;
394
   parameter set_value = 1;
395
   parameter wrap_value = 0;
396
   parameter level1_value = 15;
397
   reg  [length:1] qi;
398
   wire [length:1] q_next;
399
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
400
   always @ (posedge clk or posedge rst)
401
     if (rst)
402
       qi <= {length{1'b0}};
403
     else
404
     if (cke)
405
       qi <= q_next;
406
   assign q = qi;
407
endmodule
408
//////////////////////////////////////////////////////////////////////
409
////                                                              ////
410
////  Versatile counter                                           ////
411
////                                                              ////
412
////  Description                                                 ////
413
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
414
////  counter                                                     ////
415
////                                                              ////
416
////  To Do:                                                      ////
417
////   - add LFSR with more taps                                  ////
418
////                                                              ////
419
////  Author(s):                                                  ////
420
////      - Michael Unneback, unneback@opencores.org              ////
421
////        ORSoC AB                                              ////
422
////                                                              ////
423
//////////////////////////////////////////////////////////////////////
424
////                                                              ////
425
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
426
////                                                              ////
427
//// This source file may be used and distributed without         ////
428
//// restriction provided that this copyright statement is not    ////
429
//// removed from the file and that any derivative work contains  ////
430
//// the original copyright notice and the associated disclaimer. ////
431
////                                                              ////
432
//// This source file is free software; you can redistribute it   ////
433
//// and/or modify it under the terms of the GNU Lesser General   ////
434
//// Public License as published by the Free Software Foundation; ////
435
//// either version 2.1 of the License, or (at your option) any   ////
436
//// later version.                                               ////
437
////                                                              ////
438
//// This source is distributed in the hope that it will be       ////
439
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
440
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
441
//// PURPOSE.  See the GNU Lesser General Public License for more ////
442
//// details.                                                     ////
443
////                                                              ////
444
//// You should have received a copy of the GNU Lesser General    ////
445
//// Public License along with this source; if not, download it   ////
446
//// from http://www.opencores.org/lgpl.shtml                     ////
447
////                                                              ////
448
//////////////////////////////////////////////////////////////////////
449
// binary counter
450
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
451
   parameter length = 4;
452
   input clear;
453
   input set;
454
   input cke;
455
   input rew;
456
   output [length:1] q;
457
   input rst;
458
   input clk;
459
   parameter clear_value = 0;
460
   parameter set_value = 1;
461
   parameter wrap_value = 0;
462
   parameter level1_value = 15;
463
   reg  [length:1] qi;
464
   wire  [length:1] q_next, q_next_fw, q_next_rew;
465
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
466
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
467
   assign q_next = rew ? q_next_rew : q_next_fw;
468
   always @ (posedge clk or posedge rst)
469
     if (rst)
470
       qi <= {length{1'b0}};
471
     else
472
     if (cke)
473
       qi <= q_next;
474
   assign q = qi;
475
endmodule
476
//////////////////////////////////////////////////////////////////////
477
////                                                              ////
478
////  Versatile counter                                           ////
479
////                                                              ////
480
////  Description                                                 ////
481
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
482
////  counter                                                     ////
483
////                                                              ////
484
////  To Do:                                                      ////
485
////   - add LFSR with more taps                                  ////
486
////                                                              ////
487
////  Author(s):                                                  ////
488
////      - Michael Unneback, unneback@opencores.org              ////
489
////        ORSoC AB                                              ////
490
////                                                              ////
491
//////////////////////////////////////////////////////////////////////
492
////                                                              ////
493
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
494
////                                                              ////
495
//// This source file may be used and distributed without         ////
496
//// restriction provided that this copyright statement is not    ////
497
//// removed from the file and that any derivative work contains  ////
498
//// the original copyright notice and the associated disclaimer. ////
499
////                                                              ////
500
//// This source file is free software; you can redistribute it   ////
501
//// and/or modify it under the terms of the GNU Lesser General   ////
502
//// Public License as published by the Free Software Foundation; ////
503
//// either version 2.1 of the License, or (at your option) any   ////
504
//// later version.                                               ////
505
////                                                              ////
506
//// This source is distributed in the hope that it will be       ////
507
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
508
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
509
//// PURPOSE.  See the GNU Lesser General Public License for more ////
510
//// details.                                                     ////
511
////                                                              ////
512
//// You should have received a copy of the GNU Lesser General    ////
513
//// Public License along with this source; if not, download it   ////
514
//// from http://www.opencores.org/lgpl.shtml                     ////
515
////                                                              ////
516
//////////////////////////////////////////////////////////////////////
517
// binary counter
518
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
519
   parameter length = 4;
520
   input cke;
521
   input rew;
522
   output reg level1;
523
   input rst;
524
   input clk;
525
   parameter clear_value = 0;
526
   parameter set_value = 1;
527
   parameter wrap_value = 1;
528
   parameter level1_value = 15;
529
   reg  [length:1] qi;
530
   wire  [length:1] q_next, q_next_fw, q_next_rew;
531
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
532
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
533
   assign q_next = rew ? q_next_rew : q_next_fw;
534
   always @ (posedge clk or posedge rst)
535
     if (rst)
536
       qi <= {length{1'b0}};
537
     else
538
     if (cke)
539
       qi <= q_next;
540
    always @ (posedge clk or posedge rst)
541
    if (rst)
542
        level1 <= 1'b0;
543
    else
544
    if (cke)
545
    if (q_next == level1_value)
546
        level1 <= 1'b1;
547
    else if (qi == level1_value & rew)
548
        level1 <= 1'b0;
549
endmodule
550
//////////////////////////////////////////////////////////////////////
551
////                                                              ////
552
////  Versatile counter                                           ////
553
////                                                              ////
554
////  Description                                                 ////
555
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
556
////  counter                                                     ////
557
////                                                              ////
558
////  To Do:                                                      ////
559
////   - add LFSR with more taps                                  ////
560
////                                                              ////
561
////  Author(s):                                                  ////
562
////      - Michael Unneback, unneback@opencores.org              ////
563
////        ORSoC AB                                              ////
564
////                                                              ////
565
//////////////////////////////////////////////////////////////////////
566
////                                                              ////
567
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
568
////                                                              ////
569
//// This source file may be used and distributed without         ////
570
//// restriction provided that this copyright statement is not    ////
571
//// removed from the file and that any derivative work contains  ////
572
//// the original copyright notice and the associated disclaimer. ////
573
////                                                              ////
574
//// This source file is free software; you can redistribute it   ////
575
//// and/or modify it under the terms of the GNU Lesser General   ////
576
//// Public License as published by the Free Software Foundation; ////
577
//// either version 2.1 of the License, or (at your option) any   ////
578
//// later version.                                               ////
579
////                                                              ////
580
//// This source is distributed in the hope that it will be       ////
581
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
582
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
583
//// PURPOSE.  See the GNU Lesser General Public License for more ////
584
//// details.                                                     ////
585
////                                                              ////
586
//// You should have received a copy of the GNU Lesser General    ////
587
//// Public License along with this source; if not, download it   ////
588
//// from http://www.opencores.org/lgpl.shtml                     ////
589
////                                                              ////
590
//////////////////////////////////////////////////////////////////////
591
// LFSR counter
592
module cnt_lfsr_zq ( zq, rst, clk);
593
   parameter length = 4;
594
   output reg zq;
595
   input rst;
596
   input clk;
597
   parameter clear_value = 0;
598
   parameter set_value = 1;
599
   parameter wrap_value = 8;
600
   parameter level1_value = 15;
601
   reg  [length:1] qi;
602
   reg lfsr_fb;
603
   wire [length:1] q_next;
604
   reg [32:1] polynom;
605
   integer i;
606
   always @ (qi)
607
   begin
608
        case (length)
609
         2: polynom = 32'b11;                               // 0x3
610
         3: polynom = 32'b110;                              // 0x6
611
         4: polynom = 32'b1100;                             // 0xC
612
         5: polynom = 32'b10100;                            // 0x14
613
         6: polynom = 32'b110000;                           // 0x30
614
         7: polynom = 32'b1100000;                          // 0x60
615
         8: polynom = 32'b10111000;                         // 0xb8
616
         9: polynom = 32'b100010000;                        // 0x110
617
        10: polynom = 32'b1001000000;                       // 0x240
618
        11: polynom = 32'b10100000000;                      // 0x500
619
        12: polynom = 32'b100000101001;                     // 0x829
620
        13: polynom = 32'b1000000001100;                    // 0x100C
621
        14: polynom = 32'b10000000010101;                   // 0x2015
622
        15: polynom = 32'b110000000000000;                  // 0x6000
623
        16: polynom = 32'b1101000000001000;                 // 0xD008
624
        17: polynom = 32'b10010000000000000;                // 0x12000
625
        18: polynom = 32'b100000010000000000;               // 0x20400
626
        19: polynom = 32'b1000000000000100011;              // 0x40023
627
        20: polynom = 32'b10000010000000000000;             // 0x82000
628
        21: polynom = 32'b101000000000000000000;            // 0x140000
629
        22: polynom = 32'b1100000000000000000000;           // 0x300000
630
        23: polynom = 32'b10000100000000000000000;          // 0x420000
631
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
632
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
633
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
634
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
635
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
636
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
637
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
638
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
639
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
640
        default: polynom = 32'b0;
641
        endcase
642
        lfsr_fb = qi[length];
643
        for (i=length-1; i>=1; i=i-1) begin
644
            if (polynom[i])
645
                lfsr_fb = lfsr_fb  ~^ qi[i];
646
        end
647
    end
648
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
649
   always @ (posedge clk or posedge rst)
650
     if (rst)
651
       qi <= {length{1'b0}};
652
     else
653
       qi <= q_next;
654
   always @ (posedge clk or posedge rst)
655
     if (rst)
656
       zq <= 1'b1;
657
     else
658
       zq <= q_next == {length{1'b0}};
659
endmodule
660
//////////////////////////////////////////////////////////////////////
661
////                                                              ////
662
////  Versatile counter                                           ////
663
////                                                              ////
664
////  Description                                                 ////
665
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
666
////  counter                                                     ////
667
////                                                              ////
668
////  To Do:                                                      ////
669
////   - add LFSR with more taps                                  ////
670
////                                                              ////
671
////  Author(s):                                                  ////
672
////      - Michael Unneback, unneback@opencores.org              ////
673
////        ORSoC AB                                              ////
674
////                                                              ////
675
//////////////////////////////////////////////////////////////////////
676
////                                                              ////
677
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
678
////                                                              ////
679
//// This source file may be used and distributed without         ////
680
//// restriction provided that this copyright statement is not    ////
681
//// removed from the file and that any derivative work contains  ////
682
//// the original copyright notice and the associated disclaimer. ////
683
////                                                              ////
684
//// This source file is free software; you can redistribute it   ////
685
//// and/or modify it under the terms of the GNU Lesser General   ////
686
//// Public License as published by the Free Software Foundation; ////
687
//// either version 2.1 of the License, or (at your option) any   ////
688
//// later version.                                               ////
689
////                                                              ////
690
//// This source is distributed in the hope that it will be       ////
691
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
692
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
693
//// PURPOSE.  See the GNU Lesser General Public License for more ////
694
//// details.                                                     ////
695
////                                                              ////
696
//// You should have received a copy of the GNU Lesser General    ////
697
//// Public License along with this source; if not, download it   ////
698
//// from http://www.opencores.org/lgpl.shtml                     ////
699
////                                                              ////
700
//////////////////////////////////////////////////////////////////////
701
// LFSR counter
702
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
703
   parameter length = 4;
704
   input cke;
705
   output reg zq;
706
   input rst;
707
   input clk;
708
   parameter clear_value = 0;
709
   parameter set_value = 1;
710
   parameter wrap_value = 8;
711
   parameter level1_value = 15;
712
   reg  [length:1] qi;
713
   reg lfsr_fb;
714
   wire [length:1] q_next;
715
   reg [32:1] polynom;
716
   integer i;
717
   always @ (qi)
718
   begin
719
        case (length)
720
         2: polynom = 32'b11;                               // 0x3
721
         3: polynom = 32'b110;                              // 0x6
722
         4: polynom = 32'b1100;                             // 0xC
723
         5: polynom = 32'b10100;                            // 0x14
724
         6: polynom = 32'b110000;                           // 0x30
725
         7: polynom = 32'b1100000;                          // 0x60
726
         8: polynom = 32'b10111000;                         // 0xb8
727
         9: polynom = 32'b100010000;                        // 0x110
728
        10: polynom = 32'b1001000000;                       // 0x240
729
        11: polynom = 32'b10100000000;                      // 0x500
730
        12: polynom = 32'b100000101001;                     // 0x829
731
        13: polynom = 32'b1000000001100;                    // 0x100C
732
        14: polynom = 32'b10000000010101;                   // 0x2015
733
        15: polynom = 32'b110000000000000;                  // 0x6000
734
        16: polynom = 32'b1101000000001000;                 // 0xD008
735
        17: polynom = 32'b10010000000000000;                // 0x12000
736
        18: polynom = 32'b100000010000000000;               // 0x20400
737
        19: polynom = 32'b1000000000000100011;              // 0x40023
738
        20: polynom = 32'b10000010000000000000;             // 0x82000
739
        21: polynom = 32'b101000000000000000000;            // 0x140000
740
        22: polynom = 32'b1100000000000000000000;           // 0x300000
741
        23: polynom = 32'b10000100000000000000000;          // 0x420000
742
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
743
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
744
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
745
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
746
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
747
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
748
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
749
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
750
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
751
        default: polynom = 32'b0;
752
        endcase
753
        lfsr_fb = qi[length];
754
        for (i=length-1; i>=1; i=i-1) begin
755
            if (polynom[i])
756
                lfsr_fb = lfsr_fb  ~^ qi[i];
757
        end
758
    end
759
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
760
   always @ (posedge clk or posedge rst)
761
     if (rst)
762
       qi <= {length{1'b0}};
763
     else
764
     if (cke)
765
       qi <= q_next;
766
   always @ (posedge clk or posedge rst)
767
     if (rst)
768
       zq <= 1'b1;
769
     else
770
     if (cke)
771
       zq <= q_next == {length{1'b0}};
772
endmodule
773
//////////////////////////////////////////////////////////////////////
774
////                                                              ////
775
////  Versatile counter                                           ////
776
////                                                              ////
777
////  Description                                                 ////
778
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
779
////  counter                                                     ////
780
////                                                              ////
781
////  To Do:                                                      ////
782
////   - add LFSR with more taps                                  ////
783
////                                                              ////
784
////  Author(s):                                                  ////
785
////      - Michael Unneback, unneback@opencores.org              ////
786
////        ORSoC AB                                              ////
787
////                                                              ////
788
//////////////////////////////////////////////////////////////////////
789
////                                                              ////
790
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
791
////                                                              ////
792
//// This source file may be used and distributed without         ////
793
//// restriction provided that this copyright statement is not    ////
794
//// removed from the file and that any derivative work contains  ////
795
//// the original copyright notice and the associated disclaimer. ////
796
////                                                              ////
797
//// This source file is free software; you can redistribute it   ////
798
//// and/or modify it under the terms of the GNU Lesser General   ////
799
//// Public License as published by the Free Software Foundation; ////
800
//// either version 2.1 of the License, or (at your option) any   ////
801
//// later version.                                               ////
802
////                                                              ////
803
//// This source is distributed in the hope that it will be       ////
804
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
805
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
806
//// PURPOSE.  See the GNU Lesser General Public License for more ////
807
//// details.                                                     ////
808
////                                                              ////
809
//// You should have received a copy of the GNU Lesser General    ////
810
//// Public License along with this source; if not, download it   ////
811
//// from http://www.opencores.org/lgpl.shtml                     ////
812
////                                                              ////
813
//////////////////////////////////////////////////////////////////////
814
// LFSR counter
815
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
816
   parameter length = 4;
817
   input cke;
818
   input rew;
819
   output reg level1;
820
   input rst;
821
   input clk;
822
   parameter clear_value = 0;
823
   parameter set_value = 1;
824
   parameter wrap_value = 8;
825
   parameter level1_value = 15;
826
   reg  [length:1] qi;
827
   reg lfsr_fb, lfsr_fb_rew;
828
   wire  [length:1] q_next, q_next_fw, q_next_rew;
829
   reg [32:1] polynom_rew;
830
   integer j;
831
   reg [32:1] polynom;
832
   integer i;
833
   always @ (qi)
834
   begin
835
        case (length)
836
         2: polynom = 32'b11;                               // 0x3
837
         3: polynom = 32'b110;                              // 0x6
838
         4: polynom = 32'b1100;                             // 0xC
839
         5: polynom = 32'b10100;                            // 0x14
840
         6: polynom = 32'b110000;                           // 0x30
841
         7: polynom = 32'b1100000;                          // 0x60
842
         8: polynom = 32'b10111000;                         // 0xb8
843
         9: polynom = 32'b100010000;                        // 0x110
844
        10: polynom = 32'b1001000000;                       // 0x240
845
        11: polynom = 32'b10100000000;                      // 0x500
846
        12: polynom = 32'b100000101001;                     // 0x829
847
        13: polynom = 32'b1000000001100;                    // 0x100C
848
        14: polynom = 32'b10000000010101;                   // 0x2015
849
        15: polynom = 32'b110000000000000;                  // 0x6000
850
        16: polynom = 32'b1101000000001000;                 // 0xD008
851
        17: polynom = 32'b10010000000000000;                // 0x12000
852
        18: polynom = 32'b100000010000000000;               // 0x20400
853
        19: polynom = 32'b1000000000000100011;              // 0x40023
854
        20: polynom = 32'b10000010000000000000;             // 0x82000
855
        21: polynom = 32'b101000000000000000000;            // 0x140000
856
        22: polynom = 32'b1100000000000000000000;           // 0x300000
857
        23: polynom = 32'b10000100000000000000000;          // 0x420000
858
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
859
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
860
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
861
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
862
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
863
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
864
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
865
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
866
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
867
        default: polynom = 32'b0;
868
        endcase
869
        lfsr_fb = qi[length];
870
        for (i=length-1; i>=1; i=i-1) begin
871
            if (polynom[i])
872
                lfsr_fb = lfsr_fb  ~^ qi[i];
873
        end
874
    end
875
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
876
   always @ (qi)
877
   begin
878
        case (length)
879
         2: polynom_rew = 32'b11;
880
         3: polynom_rew = 32'b110;
881
         4: polynom_rew = 32'b1100;
882
         5: polynom_rew = 32'b10100;
883
         6: polynom_rew = 32'b110000;
884
         7: polynom_rew = 32'b1100000;
885
         8: polynom_rew = 32'b10111000;
886
         9: polynom_rew = 32'b100010000;
887
        10: polynom_rew = 32'b1001000000;
888
        11: polynom_rew = 32'b10100000000;
889
        12: polynom_rew = 32'b100000101001;
890
        13: polynom_rew = 32'b1000000001100;
891
        14: polynom_rew = 32'b10000000010101;
892
        15: polynom_rew = 32'b110000000000000;
893
        16: polynom_rew = 32'b1101000000001000;
894
        17: polynom_rew = 32'b10010000000000000;
895
        18: polynom_rew = 32'b100000010000000000;
896
        19: polynom_rew = 32'b1000000000000100011;
897
        20: polynom_rew = 32'b10000010000000000000;
898
        21: polynom_rew = 32'b101000000000000000000;
899
        22: polynom_rew = 32'b1100000000000000000000;
900
        23: polynom_rew = 32'b10000100000000000000000;
901
        24: polynom_rew = 32'b111000010000000000000000;
902
        25: polynom_rew = 32'b1001000000000000000000000;
903
        26: polynom_rew = 32'b10000000000000000000100011;
904
        27: polynom_rew = 32'b100000000000000000000010011;
905
        28: polynom_rew = 32'b1100100000000000000000000000;
906
        29: polynom_rew = 32'b10100000000000000000000000000;
907
        30: polynom_rew = 32'b100000000000000000000000101001;
908
        31: polynom_rew = 32'b1001000000000000000000000000000;
909
        32: polynom_rew = 32'b10000000001000000000000000000011;
910
        default: polynom_rew = 32'b0;
911
        endcase
912
        // rotate left
913
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
914
        lfsr_fb_rew = qi[length];
915
        for (i=length-1; i>=1; i=i-1) begin
916
            if (polynom_rew[i])
917
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
918
        end
919
    end
920
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
921
   assign q_next = rew ? q_next_rew : q_next_fw;
922
   always @ (posedge clk or posedge rst)
923
     if (rst)
924
       qi <= {length{1'b0}};
925
     else
926
     if (cke)
927
       qi <= q_next;
928
    always @ (posedge clk or posedge rst)
929
    if (rst)
930
        level1 <= 1'b0;
931
    else
932
    if (cke)
933
    if (q_next == level1_value)
934
        level1 <= 1'b1;
935
    else if (qi == level1_value & rew)
936
        level1 <= 1'b0;
937
endmodule
938
//////////////////////////////////////////////////////////////////////
939
////                                                              ////
940
////  Versatile counter                                           ////
941
////                                                              ////
942
////  Description                                                 ////
943
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
944
////  counter                                                     ////
945
////                                                              ////
946
////  To Do:                                                      ////
947
////   - add LFSR with more taps                                  ////
948
////                                                              ////
949
////  Author(s):                                                  ////
950
////      - Michael Unneback, unneback@opencores.org              ////
951
////        ORSoC AB                                              ////
952
////                                                              ////
953
//////////////////////////////////////////////////////////////////////
954
////                                                              ////
955
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
956
////                                                              ////
957
//// This source file may be used and distributed without         ////
958
//// restriction provided that this copyright statement is not    ////
959
//// removed from the file and that any derivative work contains  ////
960
//// the original copyright notice and the associated disclaimer. ////
961
////                                                              ////
962
//// This source file is free software; you can redistribute it   ////
963
//// and/or modify it under the terms of the GNU Lesser General   ////
964
//// Public License as published by the Free Software Foundation; ////
965
//// either version 2.1 of the License, or (at your option) any   ////
966
//// later version.                                               ////
967
////                                                              ////
968
//// This source is distributed in the hope that it will be       ////
969
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
970
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
971
//// PURPOSE.  See the GNU Lesser General Public License for more ////
972
//// details.                                                     ////
973
////                                                              ////
974
//// You should have received a copy of the GNU Lesser General    ////
975
//// Public License along with this source; if not, download it   ////
976
//// from http://www.opencores.org/lgpl.shtml                     ////
977
////                                                              ////
978
//////////////////////////////////////////////////////////////////////
979
// GRAY counter
980
module cnt_gray ( q, rst, clk);
981
   parameter length = 4;
982
   output reg [length:1] q;
983
   input rst;
984
   input clk;
985
   parameter clear_value = 0;
986
   parameter set_value = 1;
987
   parameter wrap_value = 8;
988
   parameter level1_value = 15;
989
   reg  [length:1] qi;
990
   wire [length:1] q_next;
991
   assign q_next = qi + {{length-1{1'b0}},1'b1};
992
   always @ (posedge clk or posedge rst)
993
     if (rst)
994
       qi <= {length{1'b0}};
995
     else
996
       qi <= q_next;
997
   always @ (posedge clk or posedge rst)
998
     if (rst)
999
       q <= {length{1'b0}};
1000
     else
1001
         q <= (q_next>>1) ^ q_next;
1002
endmodule
1003
//////////////////////////////////////////////////////////////////////
1004
////                                                              ////
1005
////  Versatile counter                                           ////
1006
////                                                              ////
1007
////  Description                                                 ////
1008
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1009
////  counter                                                     ////
1010
////                                                              ////
1011
////  To Do:                                                      ////
1012
////   - add LFSR with more taps                                  ////
1013
////                                                              ////
1014
////  Author(s):                                                  ////
1015
////      - Michael Unneback, unneback@opencores.org              ////
1016
////        ORSoC AB                                              ////
1017
////                                                              ////
1018
//////////////////////////////////////////////////////////////////////
1019
////                                                              ////
1020
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1021
////                                                              ////
1022
//// This source file may be used and distributed without         ////
1023
//// restriction provided that this copyright statement is not    ////
1024
//// removed from the file and that any derivative work contains  ////
1025
//// the original copyright notice and the associated disclaimer. ////
1026
////                                                              ////
1027
//// This source file is free software; you can redistribute it   ////
1028
//// and/or modify it under the terms of the GNU Lesser General   ////
1029
//// Public License as published by the Free Software Foundation; ////
1030
//// either version 2.1 of the License, or (at your option) any   ////
1031
//// later version.                                               ////
1032
////                                                              ////
1033
//// This source is distributed in the hope that it will be       ////
1034
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1035
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1036
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1037
//// details.                                                     ////
1038
////                                                              ////
1039
//// You should have received a copy of the GNU Lesser General    ////
1040
//// Public License along with this source; if not, download it   ////
1041
//// from http://www.opencores.org/lgpl.shtml                     ////
1042
////                                                              ////
1043
//////////////////////////////////////////////////////////////////////
1044
// GRAY counter
1045
module cnt_gray_ce ( cke, q, rst, clk);
1046
   parameter length = 4;
1047
   input cke;
1048
   output reg [length:1] q;
1049
   input rst;
1050
   input clk;
1051
   parameter clear_value = 0;
1052
   parameter set_value = 1;
1053
   parameter wrap_value = 8;
1054
   parameter level1_value = 15;
1055
   reg  [length:1] qi;
1056
   wire [length:1] q_next;
1057
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1058
   always @ (posedge clk or posedge rst)
1059
     if (rst)
1060
       qi <= {length{1'b0}};
1061
     else
1062
     if (cke)
1063
       qi <= q_next;
1064
   always @ (posedge clk or posedge rst)
1065
     if (rst)
1066
       q <= {length{1'b0}};
1067
     else
1068
       if (cke)
1069
         q <= (q_next>>1) ^ q_next;
1070
endmodule
1071
//////////////////////////////////////////////////////////////////////
1072
////                                                              ////
1073
////  Versatile counter                                           ////
1074
////                                                              ////
1075
////  Description                                                 ////
1076
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1077
////  counter                                                     ////
1078
////                                                              ////
1079
////  To Do:                                                      ////
1080
////   - add LFSR with more taps                                  ////
1081
////                                                              ////
1082
////  Author(s):                                                  ////
1083
////      - Michael Unneback, unneback@opencores.org              ////
1084
////        ORSoC AB                                              ////
1085
////                                                              ////
1086
//////////////////////////////////////////////////////////////////////
1087
////                                                              ////
1088
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1089
////                                                              ////
1090
//// This source file may be used and distributed without         ////
1091
//// restriction provided that this copyright statement is not    ////
1092
//// removed from the file and that any derivative work contains  ////
1093
//// the original copyright notice and the associated disclaimer. ////
1094
////                                                              ////
1095
//// This source file is free software; you can redistribute it   ////
1096
//// and/or modify it under the terms of the GNU Lesser General   ////
1097
//// Public License as published by the Free Software Foundation; ////
1098
//// either version 2.1 of the License, or (at your option) any   ////
1099
//// later version.                                               ////
1100
////                                                              ////
1101
//// This source is distributed in the hope that it will be       ////
1102
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1103
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1104
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1105
//// details.                                                     ////
1106
////                                                              ////
1107
//// You should have received a copy of the GNU Lesser General    ////
1108
//// Public License along with this source; if not, download it   ////
1109
//// from http://www.opencores.org/lgpl.shtml                     ////
1110
////                                                              ////
1111
//////////////////////////////////////////////////////////////////////
1112
// GRAY counter
1113
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1114
   parameter length = 4;
1115
   input cke;
1116
   output reg [length:1] q;
1117
   output [length:1] q_bin;
1118
   input rst;
1119
   input clk;
1120
   parameter clear_value = 0;
1121
   parameter set_value = 1;
1122
   parameter wrap_value = 8;
1123
   parameter level1_value = 15;
1124
   reg  [length:1] qi;
1125
   wire [length:1] q_next;
1126
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1127
   always @ (posedge clk or posedge rst)
1128
     if (rst)
1129
       qi <= {length{1'b0}};
1130
     else
1131
     if (cke)
1132
       qi <= q_next;
1133
   always @ (posedge clk or posedge rst)
1134
     if (rst)
1135
       q <= {length{1'b0}};
1136
     else
1137
       if (cke)
1138
         q <= (q_next>>1) ^ q_next;
1139
   assign q_bin = qi;
1140
endmodule
1141
//////////////////////////////////////////////////////////////////////
1142
////                                                              ////
1143
////  Versatile library, counters                                 ////
1144
////                                                              ////
1145
////  Description                                                 ////
1146
////  counters                                                    ////
1147
////                                                              ////
1148
////                                                              ////
1149
////  To Do:                                                      ////
1150
////   - add more counters                                        ////
1151
////                                                              ////
1152
////  Author(s):                                                  ////
1153
////      - Michael Unneback, unneback@opencores.org              ////
1154
////        ORSoC AB                                              ////
1155
////                                                              ////
1156
//////////////////////////////////////////////////////////////////////
1157
////                                                              ////
1158
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1159
////                                                              ////
1160
//// This source file may be used and distributed without         ////
1161
//// restriction provided that this copyright statement is not    ////
1162
//// removed from the file and that any derivative work contains  ////
1163
//// the original copyright notice and the associated disclaimer. ////
1164
////                                                              ////
1165
//// This source file is free software; you can redistribute it   ////
1166
//// and/or modify it under the terms of the GNU Lesser General   ////
1167
//// Public License as published by the Free Software Foundation; ////
1168
//// either version 2.1 of the License, or (at your option) any   ////
1169
//// later version.                                               ////
1170
////                                                              ////
1171
//// This source is distributed in the hope that it will be       ////
1172
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1173
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1174
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1175
//// details.                                                     ////
1176
////                                                              ////
1177
//// You should have received a copy of the GNU Lesser General    ////
1178
//// Public License along with this source; if not, download it   ////
1179
//// from http://www.opencores.org/lgpl.shtml                     ////
1180
////                                                              ////
1181
//////////////////////////////////////////////////////////////////////
1182
module cnt_shreg_wrap ( q, rst, clk);
1183
   parameter length = 4;
1184
   output reg [0:length-1] q;
1185
   input rst;
1186
   input clk;
1187
    always @ (posedge clk or posedge rst)
1188
    if (rst)
1189
        q <= {1'b1,{length-1{1'b0}}};
1190
    else
1191
        q <= {q[length-1],q[0:length-2]};
1192
endmodule
1193
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1194
   parameter length = 4;
1195
   input cke;
1196
   output reg [0:length-1] q;
1197
   input rst;
1198
   input clk;
1199
    always @ (posedge clk or posedge rst)
1200
    if (rst)
1201
        q <= {1'b1,{length-1{1'b0}}};
1202
    else
1203
        if (cke)
1204
            q <= {q[length-1],q[0:length-2]};
1205
endmodule
1206
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1207
   parameter length = 4;
1208
   input cke, clear;
1209
   output reg [0:length-1] q;
1210
   input rst;
1211
   input clk;
1212
    always @ (posedge clk or posedge rst)
1213
    if (rst)
1214
        q <= {1'b1,{length-1{1'b0}}};
1215
    else
1216
        if (cke)
1217
            if (clear)
1218
                q <= {1'b1,{length-1{1'b0}}};
1219
            else
1220
                q <= q >> 1;
1221
endmodule
1222
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1223
   parameter length = 4;
1224
   input cke, clear;
1225
   output reg [0:length-1] q;
1226
   input rst;
1227
   input clk;
1228
    always @ (posedge clk or posedge rst)
1229
    if (rst)
1230
        q <= {1'b1,{length-1{1'b0}}};
1231
    else
1232
        if (cke)
1233
            if (clear)
1234
                q <= {1'b1,{length-1{1'b0}}};
1235
            else
1236
            q <= {q[length-1],q[0:length-2]};
1237
endmodule
1238
//////////////////////////////////////////////////////////////////////
1239
////                                                              ////
1240
////  Versatile library, memories                                 ////
1241
////                                                              ////
1242
////  Description                                                 ////
1243
////  memories                                                    ////
1244
////                                                              ////
1245
////                                                              ////
1246
////  To Do:                                                      ////
1247
////   - add more memory types                                    ////
1248
////                                                              ////
1249
////  Author(s):                                                  ////
1250
////      - Michael Unneback, unneback@opencores.org              ////
1251
////        ORSoC AB                                              ////
1252
////                                                              ////
1253
//////////////////////////////////////////////////////////////////////
1254
////                                                              ////
1255
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1256
////                                                              ////
1257
//// This source file may be used and distributed without         ////
1258
//// restriction provided that this copyright statement is not    ////
1259
//// removed from the file and that any derivative work contains  ////
1260
//// the original copyright notice and the associated disclaimer. ////
1261
////                                                              ////
1262
//// This source file is free software; you can redistribute it   ////
1263
//// and/or modify it under the terms of the GNU Lesser General   ////
1264
//// Public License as published by the Free Software Foundation; ////
1265
//// either version 2.1 of the License, or (at your option) any   ////
1266
//// later version.                                               ////
1267
////                                                              ////
1268
//// This source is distributed in the hope that it will be       ////
1269
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1270
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1271
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1272
//// details.                                                     ////
1273
////                                                              ////
1274
//// You should have received a copy of the GNU Lesser General    ////
1275
//// Public License along with this source; if not, download it   ////
1276
//// from http://www.opencores.org/lgpl.shtml                     ////
1277
////                                                              ////
1278
//////////////////////////////////////////////////////////////////////
1279
/// ROM
1280
module vl_rom ( a, q, clk);
1281
parameter data_width = 32;
1282
parameter addr_width = 4;
1283
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1284
    {32'h18000000},
1285
    {32'hA8200000},
1286
    {32'hA8200000},
1287
    {32'hA8200000},
1288
    {32'h44003000},
1289
    {32'h15000000},
1290
    {32'h15000000},
1291
    {32'h15000000},
1292
    {32'h15000000},
1293
    {32'h15000000},
1294
    {32'h15000000},
1295
    {32'h15000000},
1296
    {32'h15000000},
1297
    {32'h15000000},
1298
    {32'h15000000},
1299
    {32'h15000000}};
1300
input [addr_width-1:0] a;
1301
output reg [data_width-1:0] q;
1302
input clk;
1303
always @ (posedge clk)
1304
    q <= data[a];
1305
endmodule
1306
// Single port RAM
1307
module vl_ram ( d, adr, we, q, clk);
1308
   parameter data_width = 32;
1309
   parameter addr_width = 8;
1310
   input [(data_width-1):0]      d;
1311
   input [(addr_width-1):0]       adr;
1312
   input                         we;
1313
   output reg [(data_width-1):0]          q;
1314
   input                         clk;
1315
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1316
   always @ (posedge clk)
1317
   begin
1318
   if (we)
1319
     ram[adr] <= d;
1320
   q <= ram[adr];
1321
   end
1322
endmodule
1323
// Dual port RAM
1324
// ACTEL FPGA should not use logic to handle rw collision
1325
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1326
   parameter data_width = 32;
1327
   parameter addr_width = 8;
1328
   input [(data_width-1):0]      d_a;
1329
   input [(addr_width-1):0]       adr_a;
1330
   input [(addr_width-1):0]       adr_b;
1331
   input                         we_a;
1332
   output [(data_width-1):0]      q_b;
1333
   input                         clk_a, clk_b;
1334
   reg [(addr_width-1):0]         adr_b_reg;
1335
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1336
   always @ (posedge clk_a)
1337
   if (we_a)
1338
     ram[adr_a] <= d_a;
1339
   always @ (posedge clk_b)
1340
   adr_b_reg <= adr_b;
1341
   assign q_b = ram[adr_b_reg];
1342
endmodule
1343
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1344
   parameter data_width = 32;
1345
   parameter addr_width = 8;
1346
   input [(data_width-1):0]      d_a;
1347
   input [(addr_width-1):0]       adr_a;
1348
   input [(addr_width-1):0]       adr_b;
1349
   input                         we_a;
1350
   output [(data_width-1):0]      q_b;
1351
   output reg [(data_width-1):0] q_a;
1352
   input                         clk_a, clk_b;
1353
   reg [(data_width-1):0]         q_b;
1354
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1355
   always @ (posedge clk_a)
1356
     begin
1357
        q_a <= ram[adr_a];
1358
        if (we_a)
1359
             ram[adr_a] <= d_a;
1360
     end
1361
   always @ (posedge clk_b)
1362
          q_b <= ram[adr_b];
1363
endmodule
1364
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
1365
   parameter data_width = 32;
1366
   parameter addr_width = 8;
1367
   input [(data_width-1):0]      d_a;
1368
   input [(addr_width-1):0]       adr_a;
1369
   input [(addr_width-1):0]       adr_b;
1370
   input                         we_a;
1371
   output [(data_width-1):0]      q_b;
1372
   input [(data_width-1):0]       d_b;
1373
   output reg [(data_width-1):0] q_a;
1374
   input                         we_b;
1375
   input                         clk_a, clk_b;
1376
   reg [(data_width-1):0]         q_b;
1377
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1378
   always @ (posedge clk_a)
1379
     begin
1380
        q_a <= ram[adr_a];
1381
        if (we_a)
1382
             ram[adr_a] <= d_a;
1383
     end
1384
   always @ (posedge clk_b)
1385
     begin
1386
        q_b <= ram[adr_b];
1387
        if (we_b)
1388
          ram[adr_b] <= d_b;
1389
     end
1390
endmodule
1391
// Content addresable memory, CAM
1392
// FIFO
1393
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1394
   parameter ADDR_WIDTH = 4;
1395
   parameter N = ADDR_WIDTH-1;
1396
   parameter Q1 = 2'b00;
1397
   parameter Q2 = 2'b01;
1398
   parameter Q3 = 2'b11;
1399
   parameter Q4 = 2'b10;
1400
   parameter going_empty = 1'b0;
1401
   parameter going_full  = 1'b1;
1402
   input [N:0]  wptr, rptr;
1403
   output reg   fifo_empty;
1404
   output       fifo_full;
1405
   input        wclk, rclk, rst;
1406
   wire direction;
1407
   reg  direction_set, direction_clr;
1408
   wire async_empty, async_full;
1409
   wire fifo_full2;
1410
   reg  fifo_empty2;
1411
   // direction_set
1412
   always @ (wptr[N:N-1] or rptr[N:N-1])
1413
     case ({wptr[N:N-1],rptr[N:N-1]})
1414
       {Q1,Q2} : direction_set <= 1'b1;
1415
       {Q2,Q3} : direction_set <= 1'b1;
1416
       {Q3,Q4} : direction_set <= 1'b1;
1417
       {Q4,Q1} : direction_set <= 1'b1;
1418
       default : direction_set <= 1'b0;
1419
     endcase
1420
   // direction_clear
1421
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1422
     if (rst)
1423
       direction_clr <= 1'b1;
1424
     else
1425
       case ({wptr[N:N-1],rptr[N:N-1]})
1426
         {Q2,Q1} : direction_clr <= 1'b1;
1427
         {Q3,Q2} : direction_clr <= 1'b1;
1428
         {Q4,Q3} : direction_clr <= 1'b1;
1429
         {Q1,Q4} : direction_clr <= 1'b1;
1430
         default : direction_clr <= 1'b0;
1431
       endcase
1432
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1433
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1434
   assign async_full  = (wptr == rptr) && (direction==going_full);
1435
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1436
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1437
/*
1438
   always @ (posedge wclk or posedge rst or posedge async_full)
1439
     if (rst)
1440
       {fifo_full, fifo_full2} <= 2'b00;
1441
     else if (async_full)
1442
       {fifo_full, fifo_full2} <= 2'b11;
1443
     else
1444
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1445
*/
1446
   always @ (posedge rclk or posedge async_empty)
1447
     if (async_empty)
1448
       {fifo_empty, fifo_empty2} <= 2'b11;
1449
     else
1450
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
1451
endmodule // async_comp
1452
module vl_fifo_1r1w_async (
1453
    d, wr, fifo_full, wr_clk, wr_rst,
1454
    q, rd, fifo_empty, rd_clk, rd_rst
1455
    );
1456
parameter data_width = 18;
1457
parameter addr_width = 4;
1458
// write side
1459
input  [data_width-1:0] d;
1460
input                   wr;
1461
output                  fifo_full;
1462
input                   wr_clk;
1463
input                   wr_rst;
1464
// read side
1465
output [data_width-1:0] q;
1466
input                   rd;
1467
output                  fifo_empty;
1468
input                   rd_clk;
1469
input                   rd_rst;
1470
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1471
vl_fifo_1r1w_async (
1472
    d, wr, fifo_full, wr_clk, wr_rst,
1473
    q, rd, fifo_empty, rd_clk, rd_rst
1474
    );
1475
adr_gen
1476
    # ( .length(addr_width))
1477
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1478
adr_gen
1479
    # (.length(addr_width))
1480
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1481
vl_dual_port_ram_1r1w
1482
    # (.data_width(data_width), .addr_width(addr_width))
1483
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1484
vl_fifo_cmp_async
1485
    # (.addr_width(addr_width))
1486
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1487
endmodule
1488
module vl_fifo_2r2w (
1489
    // a side
1490
    a_d, a_wr, a_fifo_full,
1491
    a_q, a_rd, a_fifo_empty,
1492
    a_clk, a_rst,
1493
    // b side
1494
    b_d, b_wr, b_fifo_full,
1495
    b_q, b_rd, b_fifo_empty,
1496
    b_clk, b_rst
1497
    );
1498
parameter data_width = 18;
1499
parameter addr_width = 4;
1500
// a side
1501
input  [data_width-1:0] a_d;
1502
input                   a_wr;
1503
output                  a_fifo_full;
1504
output [data_width-1:0] a_q;
1505
input                   a_rd;
1506
output                  a_fifo_empty;
1507
input                   a_clk;
1508
input                   a_rst;
1509
// b side
1510
input  [data_width-1:0] b_d;
1511
input                   b_wr;
1512
output                  b_fifo_full;
1513
output [data_width-1:0] b_q;
1514
input                   b_rd;
1515
output                  b_fifo_empty;
1516
input                   b_clk;
1517
input                   b_rst;
1518
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1519
vl_fifo_1r1w_async_a (
1520
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1521
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1522
    );
1523
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1524
vl_fifo_1r1w_async_b (
1525
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1526
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1527
    );
1528
endmodule
1529
module vl_fifo_2r2w_simplex (
1530
    // a side
1531
    a_d, a_wr, a_fifo_full,
1532
    a_q, a_rd, a_fifo_empty,
1533
    a_clk, a_rst,
1534
    // b side
1535
    b_d, b_wr, b_fifo_full,
1536
    b_q, b_rd, b_fifo_empty,
1537
    b_clk, b_rst
1538
    );
1539
parameter data_width = 18;
1540
parameter addr_width = 4;
1541
// a side
1542
input  [data_width-1:0] a_d;
1543
input                   a_wr;
1544
output                  a_fifo_full;
1545
output [data_width-1:0] a_q;
1546
input                   a_rd;
1547
output                  a_fifo_empty;
1548
input                   a_clk;
1549
input                   a_rst;
1550
// b side
1551
input  [data_width-1:0] b_d;
1552
input                   b_wr;
1553
output                  b_fifo_full;
1554
output [data_width-1:0] b_q;
1555
input                   b_rd;
1556
output                  b_fifo_empty;
1557
input                   b_clk;
1558
input                   b_rst;
1559
// adr_gen
1560
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1561
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1562
// dpram
1563
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1564
adr_gen
1565
    # ( .length(addr_width))
1566
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1567
adr_gen
1568
    # (.length(addr_width))
1569
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1570
adr_gen
1571
    # ( .length(addr_width))
1572
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1573
adr_gen
1574
    # (.length(addr_width))
1575
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1576
// mux read or write adr to DPRAM
1577
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1578
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1579
vfifo_dual_port_ram_dc_dw
1580
    # (.data_width(data_width), .addr_width(addr_width+1))
1581
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1582
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1583
vl_fifo_async_cmp
1584
    # (.addr_width(addr_width))
1585
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1586
versatile_fifo_async_cmp
1587
    # (.addr_width(addr_width))
1588
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1589
endmodule

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