OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Blame information for rev 65

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 60 unneback
// default SYN_KEEP definition
2 6 unneback
//////////////////////////////////////////////////////////////////////
3
////                                                              ////
4
////  Versatile library, clock and reset                          ////
5
////                                                              ////
6
////  Description                                                 ////
7
////  Logic related to clock and reset                            ////
8
////                                                              ////
9
////                                                              ////
10
////  To Do:                                                      ////
11
////   - add more different registers                             ////
12
////                                                              ////
13
////  Author(s):                                                  ////
14
////      - Michael Unneback, unneback@opencores.org              ////
15
////        ORSoC AB                                              ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43 48 unneback
`timescale 1 ns/100 ps
44 6 unneback
// Global buffer
45
// usage:
46
// use to enable global buffers for high fan out signals such as clock and reset
47
// Version: 8.4 8.4.0.33
48
module gbuf(GL,CLK);
49
output GL;
50
input  CLK;
51
    wire GND;
52
    GND GND_1_net(.Y(GND));
53
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
54
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
55
endmodule
56
`timescale 1 ns/1 ns
57
module vl_gbuf ( i, o);
58
input i;
59
output o;
60
`ifdef SIM_GBUF
61
assign o=i;
62
`else
63
gbuf gbuf_i0 ( .CLK(i), .GL(o));
64
`endif
65
endmodule
66
 //ACTEL
67
// sync reset
68 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
69 6 unneback
// output active high global reset sync with two DFFs 
70
`timescale 1 ns/100 ps
71
module vl_sync_rst ( rst_n_i, rst_o, clk);
72
input rst_n_i, clk;
73
output rst_o;
74 18 unneback
reg [1:0] tmp;
75 6 unneback
always @ (posedge clk or negedge rst_n_i)
76
if (!rst_n_i)
77 17 unneback
        tmp <= 2'b11;
78 6 unneback
else
79 33 unneback
        tmp <= {1'b0,tmp[1]};
80 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
81 6 unneback
endmodule
82
// vl_pll
83 32 unneback
///////////////////////////////////////////////////////////////////////////////
84 17 unneback
`timescale 1 ps/1 ps
85 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
86
parameter index = 0;
87
parameter number_of_clk = 1;
88 17 unneback
parameter period_time_0 = 20000;
89
parameter period_time_1 = 20000;
90
parameter period_time_2 = 20000;
91
parameter lock_delay = 2000000;
92 6 unneback
input clk_i, rst_n_i;
93
output lock;
94
output reg [0:number_of_clk-1] clk_o;
95
output [0:number_of_clk-1] rst_o;
96
`ifdef SIM_PLL
97
always
98
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
99
generate if (number_of_clk > 1)
100
always
101
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
102
endgenerate
103
generate if (number_of_clk > 2)
104
always
105
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
106
endgenerate
107
genvar i;
108
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
109
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
110
end
111
endgenerate
112
assign #lock_delay lock = rst_n_i;
113
endmodule
114
`else
115
generate if (number_of_clk==1 & index==0) begin
116
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
117
end
118
endgenerate // index==0
119
generate if (number_of_clk==1 & index==1) begin
120
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
121
end
122
endgenerate // index==1
123
generate if (number_of_clk==1 & index==2) begin
124
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
125
end
126
endgenerate // index==2
127
generate if (number_of_clk==1 & index==3) begin
128
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
129
end
130
endgenerate // index==0
131
generate if (number_of_clk==2 & index==0) begin
132
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
133
end
134
endgenerate // index==0
135
generate if (number_of_clk==2 & index==1) begin
136
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
137
end
138
endgenerate // index==1
139
generate if (number_of_clk==2 & index==2) begin
140
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
141
end
142
endgenerate // index==2
143
generate if (number_of_clk==2 & index==3) begin
144
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
145
end
146
endgenerate // index==0
147
generate if (number_of_clk==3 & index==0) begin
148
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
149
end
150
endgenerate // index==0
151
generate if (number_of_clk==3 & index==1) begin
152
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
153
end
154
endgenerate // index==1
155
generate if (number_of_clk==3 & index==2) begin
156
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
157
end
158
endgenerate // index==2
159
generate if (number_of_clk==3 & index==3) begin
160
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
161
end
162
endgenerate // index==0
163
genvar i;
164
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
165 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
166 6 unneback
end
167
endgenerate
168
endmodule
169
`endif
170 32 unneback
///////////////////////////////////////////////////////////////////////////////
171 6 unneback
 //actel
172
//////////////////////////////////////////////////////////////////////
173
////                                                              ////
174
////  Versatile library, registers                                ////
175
////                                                              ////
176
////  Description                                                 ////
177
////  Different type of registers                                 ////
178
////                                                              ////
179
////                                                              ////
180
////  To Do:                                                      ////
181
////   - add more different registers                             ////
182
////                                                              ////
183
////  Author(s):                                                  ////
184
////      - Michael Unneback, unneback@opencores.org              ////
185
////        ORSoC AB                                              ////
186
////                                                              ////
187
//////////////////////////////////////////////////////////////////////
188
////                                                              ////
189
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
190
////                                                              ////
191
//// This source file may be used and distributed without         ////
192
//// restriction provided that this copyright statement is not    ////
193
//// removed from the file and that any derivative work contains  ////
194
//// the original copyright notice and the associated disclaimer. ////
195
////                                                              ////
196
//// This source file is free software; you can redistribute it   ////
197
//// and/or modify it under the terms of the GNU Lesser General   ////
198
//// Public License as published by the Free Software Foundation; ////
199
//// either version 2.1 of the License, or (at your option) any   ////
200
//// later version.                                               ////
201
////                                                              ////
202
//// This source is distributed in the hope that it will be       ////
203
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
204
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
205
//// PURPOSE.  See the GNU Lesser General Public License for more ////
206
//// details.                                                     ////
207
////                                                              ////
208
//// You should have received a copy of the GNU Lesser General    ////
209
//// Public License along with this source; if not, download it   ////
210
//// from http://www.opencores.org/lgpl.shtml                     ////
211
////                                                              ////
212
//////////////////////////////////////////////////////////////////////
213 18 unneback
module vl_dff ( d, q, clk, rst);
214 6 unneback
        parameter width = 1;
215
        parameter reset_value = 0;
216
        input [width-1:0] d;
217
        input clk, rst;
218
        output reg [width-1:0] q;
219
        always @ (posedge clk or posedge rst)
220
        if (rst)
221
                q <= reset_value;
222
        else
223
                q <= d;
224
endmodule
225 18 unneback
module vl_dff_array ( d, q, clk, rst);
226 6 unneback
        parameter width = 1;
227
        parameter depth = 2;
228
        parameter reset_value = 1'b0;
229
        input [width-1:0] d;
230
        input clk, rst;
231
        output [width-1:0] q;
232
        reg  [0:depth-1] q_tmp [width-1:0];
233
        integer i;
234
        always @ (posedge clk or posedge rst)
235
        if (rst) begin
236
            for (i=0;i<depth;i=i+1)
237
                q_tmp[i] <= {width{reset_value}};
238
        end else begin
239
            q_tmp[0] <= d;
240
            for (i=1;i<depth;i=i+1)
241
                q_tmp[i] <= q_tmp[i-1];
242
        end
243
    assign q = q_tmp[depth-1];
244
endmodule
245 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
246 6 unneback
        parameter width = 1;
247
        parameter reset_value = 0;
248
        input [width-1:0] d;
249
        input ce, clk, rst;
250
        output reg [width-1:0] q;
251
        always @ (posedge clk or posedge rst)
252
        if (rst)
253
                q <= reset_value;
254
        else
255
                if (ce)
256
                        q <= d;
257
endmodule
258 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
259 8 unneback
        parameter width = 1;
260
        parameter reset_value = 0;
261
        input [width-1:0] d;
262 10 unneback
        input ce, clear, clk, rst;
263 8 unneback
        output reg [width-1:0] q;
264
        always @ (posedge clk or posedge rst)
265
        if (rst)
266
            q <= reset_value;
267
        else
268
            if (ce)
269
                if (clear)
270
                    q <= {width{1'b0}};
271
                else
272
                    q <= d;
273
endmodule
274 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
275
        parameter width = 1;
276
        parameter reset_value = 0;
277
        input [width-1:0] d;
278
        input ce, set, clk, rst;
279
        output reg [width-1:0] q;
280
        always @ (posedge clk or posedge rst)
281
        if (rst)
282
            q <= reset_value;
283
        else
284
            if (ce)
285
                if (set)
286
                    q <= {width{1'b1}};
287
                else
288
                    q <= d;
289
endmodule
290 29 unneback
module vl_spr ( sp, r, q, clk, rst);
291 64 unneback
        //parameter width = 1;
292
        parameter reset_value = 1'b0;
293 29 unneback
        input sp, r;
294
        output reg q;
295
        input clk, rst;
296
        always @ (posedge clk or posedge rst)
297
        if (rst)
298
            q <= reset_value;
299
        else
300
            if (sp)
301
                q <= 1'b1;
302
            else if (r)
303
                q <= 1'b0;
304
endmodule
305
module vl_srp ( s, rp, q, clk, rst);
306
        parameter width = 1;
307
        parameter reset_value = 0;
308
        input s, rp;
309
        output reg q;
310
        input clk, rst;
311
        always @ (posedge clk or posedge rst)
312
        if (rst)
313
            q <= reset_value;
314
        else
315
            if (rp)
316
                q <= 1'b0;
317
            else if (s)
318
                q <= 1'b1;
319
endmodule
320 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
321 6 unneback
    input         aclr;
322
    input         aset;
323
    input         clock;
324
    input         data;
325
    output reg    q;
326
   always @ (posedge clock or posedge aclr or posedge aset)
327
     if (aclr)
328
       q <= 1'b0;
329
     else if (aset)
330
       q <= 1'b1;
331
     else
332
       q <= data;
333
endmodule
334
// LATCH
335
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
336 40 unneback
module vl_latch ( d, le, q, clk);
337 6 unneback
input d, le;
338 48 unneback
input clk;
339
always @ (le or d)
340 60 unneback
if (le)
341 48 unneback
    d <= q;
342 6 unneback
endmodule
343 18 unneback
module vl_shreg ( d, q, clk, rst);
344 17 unneback
parameter depth = 10;
345
input d;
346
output q;
347
input clk, rst;
348
reg [1:depth] dffs;
349
always @ (posedge clk or posedge rst)
350
if (rst)
351
    dffs <= {depth{1'b0}};
352
else
353
    dffs <= {d,dffs[1:depth-1]};
354
assign q = dffs[depth];
355
endmodule
356 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
357 17 unneback
parameter depth = 10;
358
input d, ce;
359
output q;
360
input clk, rst;
361
reg [1:depth] dffs;
362
always @ (posedge clk or posedge rst)
363
if (rst)
364
    dffs <= {depth{1'b0}};
365
else
366
    if (ce)
367
        dffs <= {d,dffs[1:depth-1]};
368
assign q = dffs[depth];
369
endmodule
370 18 unneback
module vl_delay ( d, q, clk, rst);
371 15 unneback
parameter depth = 10;
372
input d;
373
output q;
374
input clk, rst;
375
reg [1:depth] dffs;
376
always @ (posedge clk or posedge rst)
377
if (rst)
378
    dffs <= {depth{1'b0}};
379
else
380
    dffs <= {d,dffs[1:depth-1]};
381
assign q = dffs[depth];
382
endmodule
383 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
384 17 unneback
parameter depth = 10;
385
input d;
386
output q, emptyflag;
387
input clk, rst;
388
reg [1:depth] dffs;
389
always @ (posedge clk or posedge rst)
390
if (rst)
391
    dffs <= {depth{1'b0}};
392
else
393
    dffs <= {d,dffs[1:depth-1]};
394
assign q = dffs[depth];
395
assign emptyflag = !(|dffs);
396
endmodule
397 6 unneback
//////////////////////////////////////////////////////////////////////
398
////                                                              ////
399 18 unneback
////  Logic functions                                             ////
400
////                                                              ////
401
////  Description                                                 ////
402
////  Logic functions such as multiplexers                        ////
403
////                                                              ////
404
////                                                              ////
405
////  To Do:                                                      ////
406
////   -                                                          ////
407
////                                                              ////
408
////  Author(s):                                                  ////
409
////      - Michael Unneback, unneback@opencores.org              ////
410
////        ORSoC AB                                              ////
411
////                                                              ////
412
//////////////////////////////////////////////////////////////////////
413
////                                                              ////
414
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
415
////                                                              ////
416
//// This source file may be used and distributed without         ////
417
//// restriction provided that this copyright statement is not    ////
418
//// removed from the file and that any derivative work contains  ////
419
//// the original copyright notice and the associated disclaimer. ////
420
////                                                              ////
421
//// This source file is free software; you can redistribute it   ////
422
//// and/or modify it under the terms of the GNU Lesser General   ////
423
//// Public License as published by the Free Software Foundation; ////
424
//// either version 2.1 of the License, or (at your option) any   ////
425
//// later version.                                               ////
426
////                                                              ////
427
//// This source is distributed in the hope that it will be       ////
428
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
429
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
430
//// PURPOSE.  See the GNU Lesser General Public License for more ////
431
//// details.                                                     ////
432
////                                                              ////
433
//// You should have received a copy of the GNU Lesser General    ////
434
//// Public License along with this source; if not, download it   ////
435
//// from http://www.opencores.org/lgpl.shtml                     ////
436
////                                                              ////
437
//////////////////////////////////////////////////////////////////////
438 36 unneback
module vl_mux_andor ( a, sel, dout);
439
parameter width = 32;
440
parameter nr_of_ports = 4;
441
input [nr_of_ports*width-1:0] a;
442
input [nr_of_ports-1:0] sel;
443
output reg [width-1:0] dout;
444 38 unneback
integer i,j;
445 36 unneback
always @ (a, sel)
446
begin
447
    dout = a[width-1:0] & {width{sel[0]}};
448 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
449
        for (j=0;j<width;j=j+1)
450
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
451 36 unneback
end
452
endmodule
453 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
454
parameter width = 32;
455 35 unneback
localparam nr_of_ports = 2;
456 34 unneback
input [width-1:0] a1, a0;
457
input [nr_of_ports-1:0] sel;
458
output [width-1:0] dout;
459 36 unneback
vl_mux_andor
460 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
461 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
462 34 unneback
endmodule
463
module vl_mux3_andor ( a2, a1, a0, sel, dout);
464
parameter width = 32;
465 35 unneback
localparam nr_of_ports = 3;
466 34 unneback
input [width-1:0] a2, a1, a0;
467
input [nr_of_ports-1:0] sel;
468
output [width-1:0] dout;
469 36 unneback
vl_mux_andor
470 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
471 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
472 34 unneback
endmodule
473 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
474
parameter width = 32;
475 35 unneback
localparam nr_of_ports = 4;
476 18 unneback
input [width-1:0] a3, a2, a1, a0;
477
input [nr_of_ports-1:0] sel;
478 22 unneback
output [width-1:0] dout;
479 36 unneback
vl_mux_andor
480 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
481 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
482 18 unneback
endmodule
483
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
484
parameter width = 32;
485 35 unneback
localparam nr_of_ports = 5;
486 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
487
input [nr_of_ports-1:0] sel;
488 22 unneback
output [width-1:0] dout;
489 36 unneback
vl_mux_andor
490 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
491 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
492 18 unneback
endmodule
493
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
494
parameter width = 32;
495 35 unneback
localparam nr_of_ports = 6;
496 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
497
input [nr_of_ports-1:0] sel;
498 22 unneback
output [width-1:0] dout;
499 36 unneback
vl_mux_andor
500 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
501 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
502 18 unneback
endmodule
503 43 unneback
module vl_parity_generate (data, parity);
504
parameter word_size = 32;
505
parameter chunk_size = 8;
506
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
507
input [word_size-1:0] data;
508
output reg [word_size/chunk_size-1:0] parity;
509
integer i,j;
510
always @ (data)
511
for (i=0;i<word_size/chunk_size;i=i+1) begin
512
    parity[i] = parity_type;
513
    for (j=0;j<chunk_size;j=j+1) begin
514 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
515 43 unneback
    end
516
end
517
endmodule
518
module vl_parity_check( data, parity, parity_error);
519
parameter word_size = 32;
520
parameter chunk_size = 8;
521
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
522
input [word_size-1:0] data;
523
input [word_size/chunk_size-1:0] parity;
524
output parity_error;
525 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
526 43 unneback
integer i,j;
527
always @ (data or parity)
528
for (i=0;i<word_size/chunk_size;i=i+1) begin
529
    error_flag[i] = parity[i] ^ parity_type;
530
    for (j=0;j<chunk_size;j=j+1) begin
531 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
532 43 unneback
    end
533
end
534
assign parity_error = |error_flag;
535
endmodule
536 18 unneback
//////////////////////////////////////////////////////////////////////
537
////                                                              ////
538 44 unneback
////  IO functions                                                ////
539
////                                                              ////
540
////  Description                                                 ////
541
////  IO functions such as IOB flip-flops                         ////
542
////                                                              ////
543
////                                                              ////
544
////  To Do:                                                      ////
545
////   -                                                          ////
546
////                                                              ////
547
////  Author(s):                                                  ////
548
////      - Michael Unneback, unneback@opencores.org              ////
549
////        ORSoC AB                                              ////
550
////                                                              ////
551
//////////////////////////////////////////////////////////////////////
552
////                                                              ////
553
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
554
////                                                              ////
555
//// This source file may be used and distributed without         ////
556
//// restriction provided that this copyright statement is not    ////
557
//// removed from the file and that any derivative work contains  ////
558
//// the original copyright notice and the associated disclaimer. ////
559
////                                                              ////
560
//// This source file is free software; you can redistribute it   ////
561
//// and/or modify it under the terms of the GNU Lesser General   ////
562
//// Public License as published by the Free Software Foundation; ////
563
//// either version 2.1 of the License, or (at your option) any   ////
564
//// later version.                                               ////
565
////                                                              ////
566
//// This source is distributed in the hope that it will be       ////
567
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
568
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
569
//// PURPOSE.  See the GNU Lesser General Public License for more ////
570
//// details.                                                     ////
571
////                                                              ////
572
//// You should have received a copy of the GNU Lesser General    ////
573
//// Public License along with this source; if not, download it   ////
574
//// from http://www.opencores.org/lgpl.shtml                     ////
575
////                                                              ////
576
//////////////////////////////////////////////////////////////////////
577 45 unneback
`timescale 1ns/1ns
578 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
579
parameter width = 1;
580 45 unneback
parameter reset_value = {width{1'b0}};
581
input  [width-1:0]  d_i;
582 44 unneback
output [width-1:0] o_pad;
583
input clk, rst;
584
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
585 45 unneback
reg  [width-1:0] o_pad_int;
586 44 unneback
assign d_i_int = d_i;
587
genvar i;
588 45 unneback
generate
589 44 unneback
for (i=0;i<width;i=i+1) begin
590
    always @ (posedge clk or posedge rst)
591
    if (rst)
592 45 unneback
        o_pad_int[i] <= reset_value[i];
593 44 unneback
    else
594 45 unneback
        o_pad_int[i] <= d_i_int[i];
595
    assign #1 o_pad[i] = o_pad_int[i];
596 44 unneback
end
597
endgenerate
598
endmodule
599 45 unneback
`timescale 1ns/1ns
600 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
601
parameter width = 1;
602
input  [width-1:0] d_o;
603
output reg [width-1:0] d_i;
604
input oe;
605
inout [width-1:0] io_pad;
606
input clk, rst;
607
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
608
reg [width-1:0] oe_q;
609
reg [width-1:0] d_o_q;
610
assign oe_d = {width{oe}};
611
genvar i;
612
generate
613
for (i=0;i<width;i=i+1) begin
614
    always @ (posedge clk or posedge rst)
615
    if (rst)
616
        oe_q[i] <= 1'b0;
617
    else
618
        oe_q[i] <= oe_d[i];
619
    always @ (posedge clk or posedge rst)
620
    if (rst)
621
        d_o_q[i] <= 1'b0;
622
    else
623
        d_o_q[i] <= d_o[i];
624
    always @ (posedge clk or posedge rst)
625
    if (rst)
626
        d_i[i] <= 1'b0;
627
    else
628
        d_i[i] <= io_pad[i];
629 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
630 44 unneback
end
631
endgenerate
632
endmodule
633
//////////////////////////////////////////////////////////////////////
634
////                                                              ////
635 6 unneback
////  Versatile counter                                           ////
636
////                                                              ////
637
////  Description                                                 ////
638
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
639
////  counter                                                     ////
640
////                                                              ////
641
////  To Do:                                                      ////
642
////   - add LFSR with more taps                                  ////
643
////                                                              ////
644
////  Author(s):                                                  ////
645
////      - Michael Unneback, unneback@opencores.org              ////
646
////        ORSoC AB                                              ////
647
////                                                              ////
648
//////////////////////////////////////////////////////////////////////
649
////                                                              ////
650
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
651
////                                                              ////
652
//// This source file may be used and distributed without         ////
653
//// restriction provided that this copyright statement is not    ////
654
//// removed from the file and that any derivative work contains  ////
655
//// the original copyright notice and the associated disclaimer. ////
656
////                                                              ////
657
//// This source file is free software; you can redistribute it   ////
658
//// and/or modify it under the terms of the GNU Lesser General   ////
659
//// Public License as published by the Free Software Foundation; ////
660
//// either version 2.1 of the License, or (at your option) any   ////
661
//// later version.                                               ////
662
////                                                              ////
663
//// This source is distributed in the hope that it will be       ////
664
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
665
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
666
//// PURPOSE.  See the GNU Lesser General Public License for more ////
667
//// details.                                                     ////
668
////                                                              ////
669
//// You should have received a copy of the GNU Lesser General    ////
670
//// Public License along with this source; if not, download it   ////
671
//// from http://www.opencores.org/lgpl.shtml                     ////
672
////                                                              ////
673
//////////////////////////////////////////////////////////////////////
674
// binary counter
675 40 unneback
module vl_cnt_bin_ce (
676
 cke, q, rst, clk);
677 22 unneback
   parameter length = 4;
678 6 unneback
   input cke;
679
   output [length:1] q;
680
   input rst;
681
   input clk;
682
   parameter clear_value = 0;
683
   parameter set_value = 1;
684
   parameter wrap_value = 0;
685
   parameter level1_value = 15;
686
   reg  [length:1] qi;
687
   wire [length:1] q_next;
688
   assign q_next = qi + {{length-1{1'b0}},1'b1};
689
   always @ (posedge clk or posedge rst)
690
     if (rst)
691
       qi <= {length{1'b0}};
692
     else
693
     if (cke)
694
       qi <= q_next;
695
   assign q = qi;
696
endmodule
697
//////////////////////////////////////////////////////////////////////
698
////                                                              ////
699
////  Versatile counter                                           ////
700
////                                                              ////
701
////  Description                                                 ////
702
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
703
////  counter                                                     ////
704
////                                                              ////
705
////  To Do:                                                      ////
706
////   - add LFSR with more taps                                  ////
707
////                                                              ////
708
////  Author(s):                                                  ////
709
////      - Michael Unneback, unneback@opencores.org              ////
710
////        ORSoC AB                                              ////
711
////                                                              ////
712
//////////////////////////////////////////////////////////////////////
713
////                                                              ////
714
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
715
////                                                              ////
716
//// This source file may be used and distributed without         ////
717
//// restriction provided that this copyright statement is not    ////
718
//// removed from the file and that any derivative work contains  ////
719
//// the original copyright notice and the associated disclaimer. ////
720
////                                                              ////
721
//// This source file is free software; you can redistribute it   ////
722
//// and/or modify it under the terms of the GNU Lesser General   ////
723
//// Public License as published by the Free Software Foundation; ////
724
//// either version 2.1 of the License, or (at your option) any   ////
725
//// later version.                                               ////
726
////                                                              ////
727
//// This source is distributed in the hope that it will be       ////
728
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
729
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
730
//// PURPOSE.  See the GNU Lesser General Public License for more ////
731
//// details.                                                     ////
732
////                                                              ////
733
//// You should have received a copy of the GNU Lesser General    ////
734
//// Public License along with this source; if not, download it   ////
735
//// from http://www.opencores.org/lgpl.shtml                     ////
736
////                                                              ////
737
//////////////////////////////////////////////////////////////////////
738
// binary counter
739 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
740
 cke, rew, zq, level1, rst, clk);
741 6 unneback
   parameter length = 4;
742
   input cke;
743
   input rew;
744 25 unneback
   output reg zq;
745
   output reg level1;
746
   input rst;
747
   input clk;
748
   parameter clear_value = 0;
749
   parameter set_value = 1;
750
   parameter wrap_value = 1;
751
   parameter level1_value = 15;
752 29 unneback
   wire clear;
753 30 unneback
   assign clear = 1'b0;
754 25 unneback
   reg  [length:1] qi;
755
   wire  [length:1] q_next, q_next_fw, q_next_rew;
756
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
757
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
758
   assign q_next = rew ? q_next_rew : q_next_fw;
759
   always @ (posedge clk or posedge rst)
760
     if (rst)
761
       qi <= {length{1'b0}};
762
     else
763
     if (cke)
764
       qi <= q_next;
765
   always @ (posedge clk or posedge rst)
766
     if (rst)
767
       zq <= 1'b1;
768
     else
769
     if (cke)
770
       zq <= q_next == {length{1'b0}};
771
    always @ (posedge clk or posedge rst)
772
    if (rst)
773
        level1 <= 1'b0;
774
    else
775
    if (cke)
776 29 unneback
    if (clear)
777
        level1 <= 1'b0;
778
    else if (q_next == level1_value)
779 25 unneback
        level1 <= 1'b1;
780
    else if (qi == level1_value & rew)
781
        level1 <= 1'b0;
782
endmodule
783
//////////////////////////////////////////////////////////////////////
784
////                                                              ////
785
////  Versatile counter                                           ////
786
////                                                              ////
787
////  Description                                                 ////
788
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
789
////  counter                                                     ////
790
////                                                              ////
791
////  To Do:                                                      ////
792
////   - add LFSR with more taps                                  ////
793
////                                                              ////
794
////  Author(s):                                                  ////
795
////      - Michael Unneback, unneback@opencores.org              ////
796
////        ORSoC AB                                              ////
797
////                                                              ////
798
//////////////////////////////////////////////////////////////////////
799
////                                                              ////
800
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
801
////                                                              ////
802
//// This source file may be used and distributed without         ////
803
//// restriction provided that this copyright statement is not    ////
804
//// removed from the file and that any derivative work contains  ////
805
//// the original copyright notice and the associated disclaimer. ////
806
////                                                              ////
807
//// This source file is free software; you can redistribute it   ////
808
//// and/or modify it under the terms of the GNU Lesser General   ////
809
//// Public License as published by the Free Software Foundation; ////
810
//// either version 2.1 of the License, or (at your option) any   ////
811
//// later version.                                               ////
812
////                                                              ////
813
//// This source is distributed in the hope that it will be       ////
814
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
815
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
816
//// PURPOSE.  See the GNU Lesser General Public License for more ////
817
//// details.                                                     ////
818
////                                                              ////
819
//// You should have received a copy of the GNU Lesser General    ////
820
//// Public License along with this source; if not, download it   ////
821
//// from http://www.opencores.org/lgpl.shtml                     ////
822
////                                                              ////
823
//////////////////////////////////////////////////////////////////////
824
// binary counter
825 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
826
 cke, rew, q, zq, level1, rst, clk);
827 25 unneback
   parameter length = 4;
828
   input cke;
829
   input rew;
830
   output [length:1] q;
831
   output reg zq;
832
   output reg level1;
833
   input rst;
834
   input clk;
835
   parameter clear_value = 0;
836
   parameter set_value = 1;
837
   parameter wrap_value = 1;
838
   parameter level1_value = 15;
839 29 unneback
   wire clear;
840 30 unneback
   assign clear = 1'b0;
841 25 unneback
   reg  [length:1] qi;
842
   wire  [length:1] q_next, q_next_fw, q_next_rew;
843
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
844
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
845
   assign q_next = rew ? q_next_rew : q_next_fw;
846
   always @ (posedge clk or posedge rst)
847
     if (rst)
848
       qi <= {length{1'b0}};
849
     else
850
     if (cke)
851
       qi <= q_next;
852
   assign q = qi;
853
   always @ (posedge clk or posedge rst)
854
     if (rst)
855
       zq <= 1'b1;
856
     else
857
     if (cke)
858
       zq <= q_next == {length{1'b0}};
859
    always @ (posedge clk or posedge rst)
860
    if (rst)
861
        level1 <= 1'b0;
862
    else
863
    if (cke)
864 29 unneback
    if (clear)
865
        level1 <= 1'b0;
866
    else if (q_next == level1_value)
867 25 unneback
        level1 <= 1'b1;
868
    else if (qi == level1_value & rew)
869
        level1 <= 1'b0;
870
endmodule
871
//////////////////////////////////////////////////////////////////////
872
////                                                              ////
873
////  Versatile counter                                           ////
874
////                                                              ////
875
////  Description                                                 ////
876
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
877
////  counter                                                     ////
878
////                                                              ////
879
////  To Do:                                                      ////
880
////   - add LFSR with more taps                                  ////
881
////                                                              ////
882
////  Author(s):                                                  ////
883
////      - Michael Unneback, unneback@opencores.org              ////
884
////        ORSoC AB                                              ////
885
////                                                              ////
886
//////////////////////////////////////////////////////////////////////
887
////                                                              ////
888
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
889
////                                                              ////
890
//// This source file may be used and distributed without         ////
891
//// restriction provided that this copyright statement is not    ////
892
//// removed from the file and that any derivative work contains  ////
893
//// the original copyright notice and the associated disclaimer. ////
894
////                                                              ////
895
//// This source file is free software; you can redistribute it   ////
896
//// and/or modify it under the terms of the GNU Lesser General   ////
897
//// Public License as published by the Free Software Foundation; ////
898
//// either version 2.1 of the License, or (at your option) any   ////
899
//// later version.                                               ////
900
////                                                              ////
901
//// This source is distributed in the hope that it will be       ////
902
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
903
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
904
//// PURPOSE.  See the GNU Lesser General Public License for more ////
905
//// details.                                                     ////
906
////                                                              ////
907
//// You should have received a copy of the GNU Lesser General    ////
908
//// Public License along with this source; if not, download it   ////
909
//// from http://www.opencores.org/lgpl.shtml                     ////
910
////                                                              ////
911
//////////////////////////////////////////////////////////////////////
912 6 unneback
// GRAY counter
913 40 unneback
module vl_cnt_gray_ce_bin (
914
 cke, q, q_bin, rst, clk);
915 6 unneback
   parameter length = 4;
916
   input cke;
917
   output reg [length:1] q;
918
   output [length:1] q_bin;
919
   input rst;
920
   input clk;
921
   parameter clear_value = 0;
922
   parameter set_value = 1;
923
   parameter wrap_value = 8;
924
   parameter level1_value = 15;
925
   reg  [length:1] qi;
926
   wire [length:1] q_next;
927
   assign q_next = qi + {{length-1{1'b0}},1'b1};
928
   always @ (posedge clk or posedge rst)
929
     if (rst)
930
       qi <= {length{1'b0}};
931
     else
932
     if (cke)
933
       qi <= q_next;
934
   always @ (posedge clk or posedge rst)
935
     if (rst)
936
       q <= {length{1'b0}};
937
     else
938
       if (cke)
939
         q <= (q_next>>1) ^ q_next;
940
   assign q_bin = qi;
941
endmodule
942
//////////////////////////////////////////////////////////////////////
943
////                                                              ////
944
////  Versatile library, counters                                 ////
945
////                                                              ////
946
////  Description                                                 ////
947
////  counters                                                    ////
948
////                                                              ////
949
////                                                              ////
950
////  To Do:                                                      ////
951
////   - add more counters                                        ////
952
////                                                              ////
953
////  Author(s):                                                  ////
954
////      - Michael Unneback, unneback@opencores.org              ////
955
////        ORSoC AB                                              ////
956
////                                                              ////
957
//////////////////////////////////////////////////////////////////////
958
////                                                              ////
959
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
960
////                                                              ////
961
//// This source file may be used and distributed without         ////
962
//// restriction provided that this copyright statement is not    ////
963
//// removed from the file and that any derivative work contains  ////
964
//// the original copyright notice and the associated disclaimer. ////
965
////                                                              ////
966
//// This source file is free software; you can redistribute it   ////
967
//// and/or modify it under the terms of the GNU Lesser General   ////
968
//// Public License as published by the Free Software Foundation; ////
969
//// either version 2.1 of the License, or (at your option) any   ////
970
//// later version.                                               ////
971
////                                                              ////
972
//// This source is distributed in the hope that it will be       ////
973
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
974
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
975
//// PURPOSE.  See the GNU Lesser General Public License for more ////
976
//// details.                                                     ////
977
////                                                              ////
978
//// You should have received a copy of the GNU Lesser General    ////
979
//// Public License along with this source; if not, download it   ////
980
//// from http://www.opencores.org/lgpl.shtml                     ////
981
////                                                              ////
982
//////////////////////////////////////////////////////////////////////
983 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
984 6 unneback
   parameter length = 4;
985
   output reg [0:length-1] q;
986
   input rst;
987
   input clk;
988
    always @ (posedge clk or posedge rst)
989
    if (rst)
990
        q <= {1'b1,{length-1{1'b0}}};
991
    else
992
        q <= {q[length-1],q[0:length-2]};
993
endmodule
994 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
995 6 unneback
   parameter length = 4;
996
   input cke;
997
   output reg [0:length-1] q;
998
   input rst;
999
   input clk;
1000
    always @ (posedge clk or posedge rst)
1001
    if (rst)
1002
        q <= {1'b1,{length-1{1'b0}}};
1003
    else
1004
        if (cke)
1005
            q <= {q[length-1],q[0:length-2]};
1006
endmodule
1007 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1008 6 unneback
   parameter length = 4;
1009
   input cke, clear;
1010
   output reg [0:length-1] q;
1011
   input rst;
1012
   input clk;
1013
    always @ (posedge clk or posedge rst)
1014
    if (rst)
1015
        q <= {1'b1,{length-1{1'b0}}};
1016
    else
1017
        if (cke)
1018
            if (clear)
1019
                q <= {1'b1,{length-1{1'b0}}};
1020
            else
1021
                q <= q >> 1;
1022
endmodule
1023 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1024 6 unneback
   parameter length = 4;
1025
   input cke, clear;
1026
   output reg [0:length-1] q;
1027
   input rst;
1028
   input clk;
1029
    always @ (posedge clk or posedge rst)
1030
    if (rst)
1031
        q <= {1'b1,{length-1{1'b0}}};
1032
    else
1033
        if (cke)
1034
            if (clear)
1035
                q <= {1'b1,{length-1{1'b0}}};
1036
            else
1037
            q <= {q[length-1],q[0:length-2]};
1038
endmodule
1039
//////////////////////////////////////////////////////////////////////
1040
////                                                              ////
1041
////  Versatile library, memories                                 ////
1042
////                                                              ////
1043
////  Description                                                 ////
1044
////  memories                                                    ////
1045
////                                                              ////
1046
////                                                              ////
1047
////  To Do:                                                      ////
1048
////   - add more memory types                                    ////
1049
////                                                              ////
1050
////  Author(s):                                                  ////
1051
////      - Michael Unneback, unneback@opencores.org              ////
1052
////        ORSoC AB                                              ////
1053
////                                                              ////
1054
//////////////////////////////////////////////////////////////////////
1055
////                                                              ////
1056
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1057
////                                                              ////
1058
//// This source file may be used and distributed without         ////
1059
//// restriction provided that this copyright statement is not    ////
1060
//// removed from the file and that any derivative work contains  ////
1061
//// the original copyright notice and the associated disclaimer. ////
1062
////                                                              ////
1063
//// This source file is free software; you can redistribute it   ////
1064
//// and/or modify it under the terms of the GNU Lesser General   ////
1065
//// Public License as published by the Free Software Foundation; ////
1066
//// either version 2.1 of the License, or (at your option) any   ////
1067
//// later version.                                               ////
1068
////                                                              ////
1069
//// This source is distributed in the hope that it will be       ////
1070
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1071
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1072
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1073
//// details.                                                     ////
1074
////                                                              ////
1075
//// You should have received a copy of the GNU Lesser General    ////
1076
//// Public License along with this source; if not, download it   ////
1077
//// from http://www.opencores.org/lgpl.shtml                     ////
1078
////                                                              ////
1079
//////////////////////////////////////////////////////////////////////
1080
/// ROM
1081 7 unneback
module vl_rom_init ( adr, q, clk);
1082
   parameter data_width = 32;
1083
   parameter addr_width = 8;
1084
   input [(addr_width-1):0]       adr;
1085
   output reg [(data_width-1):0] q;
1086
   input                         clk;
1087
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1088
   parameter memory_file = "vl_rom.vmem";
1089
   initial
1090
     begin
1091
        $readmemh(memory_file, rom);
1092
     end
1093
   always @ (posedge clk)
1094
     q <= rom[adr];
1095
endmodule
1096 6 unneback
// Single port RAM
1097
module vl_ram ( d, adr, we, q, clk);
1098
   parameter data_width = 32;
1099
   parameter addr_width = 8;
1100
   input [(data_width-1):0]      d;
1101
   input [(addr_width-1):0]       adr;
1102
   input                         we;
1103 7 unneback
   output reg [(data_width-1):0] q;
1104 6 unneback
   input                         clk;
1105
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1106 7 unneback
   parameter init = 0;
1107
   parameter memory_file = "vl_ram.vmem";
1108
   generate if (init) begin : init_mem
1109
   initial
1110
     begin
1111
        $readmemh(memory_file, ram);
1112
     end
1113
   end
1114
   endgenerate
1115 6 unneback
   always @ (posedge clk)
1116
   begin
1117
   if (we)
1118
     ram[adr] <= d;
1119
   q <= ram[adr];
1120
   end
1121
endmodule
1122 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1123
   parameter data_width = 32;
1124
   parameter addr_width = 8;
1125
   input [(data_width-1):0]      d;
1126
   input [(addr_width-1):0]       adr;
1127
   input [(addr_width/4)-1:0]    be;
1128
   input                         we;
1129
   output reg [(data_width-1):0] q;
1130
   input                         clk;
1131 65 unneback
`ifdef SYSTEMVERILOG
1132
   logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
1133
`else
1134 7 unneback
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1135 65 unneback
`endif
1136 60 unneback
   parameter memory_init = 0;
1137 7 unneback
   parameter memory_file = "vl_ram.vmem";
1138 60 unneback
   generate if (memory_init) begin : init_mem
1139 7 unneback
   initial
1140
     begin
1141
        $readmemh(memory_file, ram);
1142
     end
1143
   end
1144
   endgenerate
1145 60 unneback
`ifdef SYSTEMVERILOG
1146
// use a multi-dimensional packed array
1147
//to model individual bytes within the word
1148
always_ff@(posedge clk)
1149
begin
1150
    if(we) begin // note: we should have a for statement to support any bus width
1151 65 unneback
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
1152
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
1153
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
1154
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
1155 60 unneback
    end
1156 65 unneback
    q <= ram[adr];
1157 60 unneback
end
1158
`else
1159 7 unneback
   genvar i;
1160
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1161
      always @ (posedge clk)
1162
      if (we & be[i])
1163
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1164
   end
1165
   endgenerate
1166
   always @ (posedge clk)
1167
      q <= ram[adr];
1168 60 unneback
`endif
1169 7 unneback
endmodule
1170 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
1171 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1172 6 unneback
   parameter data_width = 32;
1173
   parameter addr_width = 8;
1174
   input [(data_width-1):0]      d_a;
1175
   input [(addr_width-1):0]       adr_a;
1176
   input [(addr_width-1):0]       adr_b;
1177
   input                         we_a;
1178
   output [(data_width-1):0]      q_b;
1179
   input                         clk_a, clk_b;
1180
   reg [(addr_width-1):0]         adr_b_reg;
1181
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1182 7 unneback
   parameter init = 0;
1183
   parameter memory_file = "vl_ram.vmem";
1184
   generate if (init) begin : init_mem
1185
   initial
1186
     begin
1187
        $readmemh(memory_file, ram);
1188
     end
1189
   end
1190
   endgenerate
1191 6 unneback
   always @ (posedge clk_a)
1192
   if (we_a)
1193
     ram[adr_a] <= d_a;
1194
   always @ (posedge clk_b)
1195
   adr_b_reg <= adr_b;
1196
   assign q_b = ram[adr_b_reg];
1197
endmodule
1198 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1199 6 unneback
   parameter data_width = 32;
1200
   parameter addr_width = 8;
1201
   input [(data_width-1):0]      d_a;
1202
   input [(addr_width-1):0]       adr_a;
1203
   input [(addr_width-1):0]       adr_b;
1204
   input                         we_a;
1205
   output [(data_width-1):0]      q_b;
1206
   output reg [(data_width-1):0] q_a;
1207
   input                         clk_a, clk_b;
1208
   reg [(data_width-1):0]         q_b;
1209
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1210 7 unneback
   parameter init = 0;
1211
   parameter memory_file = "vl_ram.vmem";
1212
   generate if (init) begin : init_mem
1213
   initial
1214
     begin
1215
        $readmemh(memory_file, ram);
1216
     end
1217
   end
1218
   endgenerate
1219 6 unneback
   always @ (posedge clk_a)
1220
     begin
1221
        q_a <= ram[adr_a];
1222
        if (we_a)
1223
             ram[adr_a] <= d_a;
1224
     end
1225
   always @ (posedge clk_b)
1226
          q_b <= ram[adr_b];
1227
endmodule
1228 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1229 6 unneback
   parameter data_width = 32;
1230
   parameter addr_width = 8;
1231
   input [(data_width-1):0]      d_a;
1232
   input [(addr_width-1):0]       adr_a;
1233
   input [(addr_width-1):0]       adr_b;
1234
   input                         we_a;
1235
   output [(data_width-1):0]      q_b;
1236
   input [(data_width-1):0]       d_b;
1237
   output reg [(data_width-1):0] q_a;
1238
   input                         we_b;
1239
   input                         clk_a, clk_b;
1240
   reg [(data_width-1):0]         q_b;
1241
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1242 7 unneback
   parameter init = 0;
1243
   parameter memory_file = "vl_ram.vmem";
1244
   generate if (init) begin : init_mem
1245
   initial
1246
     begin
1247
        $readmemh(memory_file, ram);
1248
     end
1249
   end
1250
   endgenerate
1251 6 unneback
   always @ (posedge clk_a)
1252
     begin
1253
        q_a <= ram[adr_a];
1254
        if (we_a)
1255
             ram[adr_a] <= d_a;
1256
     end
1257
   always @ (posedge clk_b)
1258
     begin
1259
        q_b <= ram[adr_b];
1260
        if (we_b)
1261
          ram[adr_b] <= d_b;
1262
     end
1263
endmodule
1264
// Content addresable memory, CAM
1265
// FIFO
1266 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1267
    d, wr, fifo_full,
1268
    q, rd, fifo_empty,
1269
    fill_level,
1270
    clk, rst
1271
    );
1272
parameter data_width = 18;
1273
parameter addr_width = 4;
1274
// write side
1275
input  [data_width-1:0] d;
1276
input                   wr;
1277
output                  fifo_full;
1278
// read side
1279
output [data_width-1:0] q;
1280
input                   rd;
1281
output                  fifo_empty;
1282
// common
1283
output [addr_width:0]   fill_level;
1284
input rst, clk;
1285
wire [addr_width:1] wadr, radr;
1286
vl_cnt_bin_ce
1287
    # ( .length(addr_width))
1288
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1289
vl_cnt_bin_ce
1290
    # (.length(addr_width))
1291
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1292
vl_dpram_1r1w
1293
    # (.data_width(data_width), .addr_width(addr_width))
1294
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1295 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1296 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1297 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1298
endmodule
1299 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1300
// RAM is supposed to be larger than the two FIFOs
1301
// LFSR counters used adr pointers
1302
module vl_fifo_2r2w_sync_simplex (
1303
    // a side
1304
    a_d, a_wr, a_fifo_full,
1305
    a_q, a_rd, a_fifo_empty,
1306
    a_fill_level,
1307
    // b side
1308
    b_d, b_wr, b_fifo_full,
1309
    b_q, b_rd, b_fifo_empty,
1310
    b_fill_level,
1311
    // common
1312
    clk, rst
1313
    );
1314
parameter data_width = 8;
1315
parameter addr_width = 5;
1316
parameter fifo_full_level = (1<<addr_width)-1;
1317
// a side
1318
input  [data_width-1:0] a_d;
1319
input                   a_wr;
1320
output                  a_fifo_full;
1321
output [data_width-1:0] a_q;
1322
input                   a_rd;
1323
output                  a_fifo_empty;
1324
output [addr_width-1:0] a_fill_level;
1325
// b side
1326
input  [data_width-1:0] b_d;
1327
input                   b_wr;
1328
output                  b_fifo_full;
1329
output [data_width-1:0] b_q;
1330
input                   b_rd;
1331
output                  b_fifo_empty;
1332
output [addr_width-1:0] b_fill_level;
1333
input                   clk;
1334
input                   rst;
1335
// adr_gen
1336
wire [addr_width:1] a_wadr, a_radr;
1337
wire [addr_width:1] b_wadr, b_radr;
1338
// dpram
1339
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1340
vl_cnt_lfsr_ce
1341
    # ( .length(addr_width))
1342
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1343
vl_cnt_lfsr_ce
1344
    # (.length(addr_width))
1345
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1346
vl_cnt_lfsr_ce
1347
    # ( .length(addr_width))
1348
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1349
vl_cnt_lfsr_ce
1350
    # (.length(addr_width))
1351
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1352
// mux read or write adr to DPRAM
1353
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1354
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1355
vl_dpram_2r2w
1356
    # (.data_width(data_width), .addr_width(addr_width+1))
1357
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1358
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1359
vl_cnt_bin_ce_rew_zq_l1
1360 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1361 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1362
vl_cnt_bin_ce_rew_zq_l1
1363 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1364 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1365
endmodule
1366 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1367 11 unneback
   parameter addr_width = 4;
1368
   parameter N = addr_width-1;
1369 6 unneback
   parameter Q1 = 2'b00;
1370
   parameter Q2 = 2'b01;
1371
   parameter Q3 = 2'b11;
1372
   parameter Q4 = 2'b10;
1373
   parameter going_empty = 1'b0;
1374
   parameter going_full  = 1'b1;
1375
   input [N:0]  wptr, rptr;
1376 14 unneback
   output       fifo_empty;
1377 6 unneback
   output       fifo_full;
1378
   input        wclk, rclk, rst;
1379
   wire direction;
1380
   reg  direction_set, direction_clr;
1381
   wire async_empty, async_full;
1382
   wire fifo_full2;
1383 14 unneback
   wire fifo_empty2;
1384 6 unneback
   // direction_set
1385
   always @ (wptr[N:N-1] or rptr[N:N-1])
1386
     case ({wptr[N:N-1],rptr[N:N-1]})
1387
       {Q1,Q2} : direction_set <= 1'b1;
1388
       {Q2,Q3} : direction_set <= 1'b1;
1389
       {Q3,Q4} : direction_set <= 1'b1;
1390
       {Q4,Q1} : direction_set <= 1'b1;
1391
       default : direction_set <= 1'b0;
1392
     endcase
1393
   // direction_clear
1394
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1395
     if (rst)
1396
       direction_clr <= 1'b1;
1397
     else
1398
       case ({wptr[N:N-1],rptr[N:N-1]})
1399
         {Q2,Q1} : direction_clr <= 1'b1;
1400
         {Q3,Q2} : direction_clr <= 1'b1;
1401
         {Q4,Q3} : direction_clr <= 1'b1;
1402
         {Q1,Q4} : direction_clr <= 1'b1;
1403
         default : direction_clr <= 1'b0;
1404
       endcase
1405 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1406 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1407
   assign async_full  = (wptr == rptr) && (direction==going_full);
1408 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1409
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1410 6 unneback
/*
1411
   always @ (posedge wclk or posedge rst or posedge async_full)
1412
     if (rst)
1413
       {fifo_full, fifo_full2} <= 2'b00;
1414
     else if (async_full)
1415
       {fifo_full, fifo_full2} <= 2'b11;
1416
     else
1417
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1418
*/
1419 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1420 6 unneback
     if (async_empty)
1421
       {fifo_empty, fifo_empty2} <= 2'b11;
1422
     else
1423 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1424 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1425
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1426 27 unneback
endmodule // async_compb
1427 6 unneback
module vl_fifo_1r1w_async (
1428
    d, wr, fifo_full, wr_clk, wr_rst,
1429
    q, rd, fifo_empty, rd_clk, rd_rst
1430
    );
1431
parameter data_width = 18;
1432
parameter addr_width = 4;
1433
// write side
1434
input  [data_width-1:0] d;
1435
input                   wr;
1436
output                  fifo_full;
1437
input                   wr_clk;
1438
input                   wr_rst;
1439
// read side
1440
output [data_width-1:0] q;
1441
input                   rd;
1442
output                  fifo_empty;
1443
input                   rd_clk;
1444
input                   rd_rst;
1445
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1446 18 unneback
vl_cnt_gray_ce_bin
1447 6 unneback
    # ( .length(addr_width))
1448
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1449 18 unneback
vl_cnt_gray_ce_bin
1450 6 unneback
    # (.length(addr_width))
1451 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1452 7 unneback
vl_dpram_1r1w
1453 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1454
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1455
vl_fifo_cmp_async
1456
    # (.addr_width(addr_width))
1457
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1458
endmodule
1459 8 unneback
module vl_fifo_2r2w_async (
1460 6 unneback
    // a side
1461
    a_d, a_wr, a_fifo_full,
1462
    a_q, a_rd, a_fifo_empty,
1463
    a_clk, a_rst,
1464
    // b side
1465
    b_d, b_wr, b_fifo_full,
1466
    b_q, b_rd, b_fifo_empty,
1467
    b_clk, b_rst
1468
    );
1469
parameter data_width = 18;
1470
parameter addr_width = 4;
1471
// a side
1472
input  [data_width-1:0] a_d;
1473
input                   a_wr;
1474
output                  a_fifo_full;
1475
output [data_width-1:0] a_q;
1476
input                   a_rd;
1477
output                  a_fifo_empty;
1478
input                   a_clk;
1479
input                   a_rst;
1480
// b side
1481
input  [data_width-1:0] b_d;
1482
input                   b_wr;
1483
output                  b_fifo_full;
1484
output [data_width-1:0] b_q;
1485
input                   b_rd;
1486
output                  b_fifo_empty;
1487
input                   b_clk;
1488
input                   b_rst;
1489
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1490
vl_fifo_1r1w_async_a (
1491
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1492
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1493
    );
1494
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1495
vl_fifo_1r1w_async_b (
1496
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1497
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1498
    );
1499
endmodule
1500 8 unneback
module vl_fifo_2r2w_async_simplex (
1501 6 unneback
    // a side
1502
    a_d, a_wr, a_fifo_full,
1503
    a_q, a_rd, a_fifo_empty,
1504
    a_clk, a_rst,
1505
    // b side
1506
    b_d, b_wr, b_fifo_full,
1507
    b_q, b_rd, b_fifo_empty,
1508
    b_clk, b_rst
1509
    );
1510
parameter data_width = 18;
1511
parameter addr_width = 4;
1512
// a side
1513
input  [data_width-1:0] a_d;
1514
input                   a_wr;
1515
output                  a_fifo_full;
1516
output [data_width-1:0] a_q;
1517
input                   a_rd;
1518
output                  a_fifo_empty;
1519
input                   a_clk;
1520
input                   a_rst;
1521
// b side
1522
input  [data_width-1:0] b_d;
1523
input                   b_wr;
1524
output                  b_fifo_full;
1525
output [data_width-1:0] b_q;
1526
input                   b_rd;
1527
output                  b_fifo_empty;
1528
input                   b_clk;
1529
input                   b_rst;
1530
// adr_gen
1531
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1532
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1533
// dpram
1534
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1535 18 unneback
vl_cnt_gray_ce_bin
1536 6 unneback
    # ( .length(addr_width))
1537
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1538 18 unneback
vl_cnt_gray_ce_bin
1539 6 unneback
    # (.length(addr_width))
1540
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1541 18 unneback
vl_cnt_gray_ce_bin
1542 6 unneback
    # ( .length(addr_width))
1543
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1544 18 unneback
vl_cnt_gray_ce_bin
1545 6 unneback
    # (.length(addr_width))
1546
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1547
// mux read or write adr to DPRAM
1548
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1549
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1550 11 unneback
vl_dpram_2r2w
1551 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1552
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1553
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1554 11 unneback
vl_fifo_cmp_async
1555 6 unneback
    # (.addr_width(addr_width))
1556
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1557 11 unneback
vl_fifo_cmp_async
1558 6 unneback
    # (.addr_width(addr_width))
1559
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1560
endmodule
1561 48 unneback
module vl_reg_file (
1562
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1563
);
1564
parameter data_width = 32;
1565
parameter addr_width = 5;
1566
input [addr_width-1:0] a1, a2, a3;
1567
input [data_width-1:0] wd3;
1568
input we3;
1569
output [data_width-1:0] rd1, rd2;
1570
input clk;
1571
reg [data_width-1:0] wd3_reg;
1572
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
1573
reg we3_reg;
1574
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1575
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1576
always @ (posedge clk or posedge rst)
1577
if (rst)
1578
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
1579
else
1580
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
1581
    always @ (negedge clk)
1582
    if (we3_reg)
1583
        ram1[a3_reg] <= wd3;
1584
    always @ (posedge clk)
1585
        a1_reg <= a1;
1586
    assign rd1 = ram1[a1_reg];
1587
    always @ (negedge clk)
1588
    if (we3_reg)
1589
        ram2[a3_reg] <= wd3;
1590
    always @ (posedge clk)
1591
        a2_reg <= a2;
1592
    assign rd2 = ram2[a2_reg];
1593
endmodule
1594 12 unneback
//////////////////////////////////////////////////////////////////////
1595
////                                                              ////
1596
////  Versatile library, wishbone stuff                           ////
1597
////                                                              ////
1598
////  Description                                                 ////
1599
////  Wishbone compliant modules                                  ////
1600
////                                                              ////
1601
////                                                              ////
1602
////  To Do:                                                      ////
1603
////   -                                                          ////
1604
////                                                              ////
1605
////  Author(s):                                                  ////
1606
////      - Michael Unneback, unneback@opencores.org              ////
1607
////        ORSoC AB                                              ////
1608
////                                                              ////
1609
//////////////////////////////////////////////////////////////////////
1610
////                                                              ////
1611
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1612
////                                                              ////
1613
//// This source file may be used and distributed without         ////
1614
//// restriction provided that this copyright statement is not    ////
1615
//// removed from the file and that any derivative work contains  ////
1616
//// the original copyright notice and the associated disclaimer. ////
1617
////                                                              ////
1618
//// This source file is free software; you can redistribute it   ////
1619
//// and/or modify it under the terms of the GNU Lesser General   ////
1620
//// Public License as published by the Free Software Foundation; ////
1621
//// either version 2.1 of the License, or (at your option) any   ////
1622
//// later version.                                               ////
1623
////                                                              ////
1624
//// This source is distributed in the hope that it will be       ////
1625
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1626
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1627
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1628
//// details.                                                     ////
1629
////                                                              ////
1630
//// You should have received a copy of the GNU Lesser General    ////
1631
//// Public License along with this source; if not, download it   ////
1632
//// from http://www.opencores.org/lgpl.shtml                     ////
1633
////                                                              ////
1634
//////////////////////////////////////////////////////////////////////
1635
// async wb3 - wb3 bridge
1636
`timescale 1ns/1ns
1637 18 unneback
module vl_wb3wb3_bridge (
1638 12 unneback
        // wishbone slave side
1639
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1640
        // wishbone master side
1641
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1642
input [31:0] wbs_dat_i;
1643
input [31:2] wbs_adr_i;
1644
input [3:0]  wbs_sel_i;
1645
input [1:0]  wbs_bte_i;
1646
input [2:0]  wbs_cti_i;
1647
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1648
output [31:0] wbs_dat_o;
1649 14 unneback
output wbs_ack_o;
1650 12 unneback
input wbs_clk, wbs_rst;
1651
output [31:0] wbm_dat_o;
1652
output reg [31:2] wbm_adr_o;
1653
output [3:0]  wbm_sel_o;
1654
output reg [1:0]  wbm_bte_o;
1655
output reg [2:0]  wbm_cti_o;
1656 14 unneback
output reg wbm_we_o;
1657
output wbm_cyc_o;
1658 12 unneback
output wbm_stb_o;
1659
input [31:0]  wbm_dat_i;
1660
input wbm_ack_i;
1661
input wbm_clk, wbm_rst;
1662
parameter addr_width = 4;
1663
// bte
1664
parameter linear       = 2'b00;
1665
parameter wrap4        = 2'b01;
1666
parameter wrap8        = 2'b10;
1667
parameter wrap16       = 2'b11;
1668
// cti
1669
parameter classic      = 3'b000;
1670
parameter incburst     = 3'b010;
1671
parameter endofburst   = 3'b111;
1672
parameter wbs_adr  = 1'b0;
1673
parameter wbs_data = 1'b1;
1674 33 unneback
parameter wbm_adr0      = 2'b00;
1675
parameter wbm_adr1      = 2'b01;
1676
parameter wbm_data      = 2'b10;
1677
parameter wbm_data_wait = 2'b11;
1678 12 unneback
reg [1:0] wbs_bte_reg;
1679
reg wbs;
1680
wire wbs_eoc_alert, wbm_eoc_alert;
1681
reg wbs_eoc, wbm_eoc;
1682
reg [1:0] wbm;
1683 14 unneback
wire [1:16] wbs_count, wbm_count;
1684 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1685
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1686
reg a_rd_reg;
1687
wire b_rd_adr, b_rd_data;
1688 14 unneback
wire b_rd_data_reg;
1689
wire [35:0] temp;
1690 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1691
always @ (posedge wbs_clk or posedge wbs_rst)
1692
if (wbs_rst)
1693
        wbs_eoc <= 1'b0;
1694
else
1695
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1696
                wbs_eoc <= wbs_bte_i==linear;
1697
        else if (wbs_eoc_alert & (a_rd | a_wr))
1698
                wbs_eoc <= 1'b1;
1699 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1700 12 unneback
    cnt0 (
1701
        .cke(wbs_ack_o),
1702
        .clear(wbs_eoc),
1703
        .q(wbs_count),
1704
        .rst(wbs_rst),
1705
        .clk(wbs_clk));
1706
always @ (posedge wbs_clk or posedge wbs_rst)
1707
if (wbs_rst)
1708
        wbs <= wbs_adr;
1709
else
1710
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1711
                wbs <= wbs_data;
1712
        else if (wbs_eoc & wbs_ack_o)
1713
                wbs <= wbs_adr;
1714
// wbs FIFO
1715
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1716
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1717
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1718
              1'b0;
1719
assign a_rd = !a_fifo_empty;
1720
always @ (posedge wbs_clk or posedge wbs_rst)
1721
if (wbs_rst)
1722
        a_rd_reg <= 1'b0;
1723
else
1724
        a_rd_reg <= a_rd;
1725
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1726
assign wbs_dat_o = a_q[35:4];
1727
always @ (posedge wbs_clk or posedge wbs_rst)
1728
if (wbs_rst)
1729 13 unneback
        wbs_bte_reg <= 2'b00;
1730 12 unneback
else
1731 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1732 12 unneback
// wbm FIFO
1733
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1734
always @ (posedge wbm_clk or posedge wbm_rst)
1735
if (wbm_rst)
1736
        wbm_eoc <= 1'b0;
1737
else
1738
        if (wbm==wbm_adr0 & !b_fifo_empty)
1739
                wbm_eoc <= b_q[4:3] == linear;
1740
        else if (wbm_eoc_alert & wbm_ack_i)
1741
                wbm_eoc <= 1'b1;
1742
always @ (posedge wbm_clk or posedge wbm_rst)
1743
if (wbm_rst)
1744
        wbm <= wbm_adr0;
1745
else
1746 33 unneback
/*
1747 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1748
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1749
        (wbm==wbm_adr1 & !wbm_we_o) |
1750
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1751
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1752 33 unneback
*/
1753
    case (wbm)
1754
    wbm_adr0:
1755
        if (!b_fifo_empty)
1756
            wbm <= wbm_adr1;
1757
    wbm_adr1:
1758
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1759
            wbm <= wbm_data;
1760
    wbm_data:
1761
        if (wbm_ack_i & wbm_eoc)
1762
            wbm <= wbm_adr0;
1763
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1764
            wbm <= wbm_data_wait;
1765
    wbm_data_wait:
1766
        if (!b_fifo_empty)
1767
            wbm <= wbm_data;
1768
    endcase
1769 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1770
assign b_wr = !wbm_we_o & wbm_ack_i;
1771
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1772
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1773
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1774 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1775 12 unneback
                   1'b0;
1776
assign b_rd = b_rd_adr | b_rd_data;
1777 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1778
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1779 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1780 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1781 12 unneback
    cnt1 (
1782
        .cke(wbm_ack_i),
1783
        .clear(wbm_eoc),
1784
        .q(wbm_count),
1785
        .rst(wbm_rst),
1786
        .clk(wbm_clk));
1787 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1788
assign wbm_stb_o = (wbm==wbm_data);
1789 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1790
if (wbm_rst)
1791
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1792
else begin
1793
        if (wbm==wbm_adr0 & !b_fifo_empty)
1794
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1795
        else if (wbm_eoc_alert & wbm_ack_i)
1796
                wbm_cti_o <= endofburst;
1797
end
1798
//async_fifo_dw_simplex_top
1799
vl_fifo_2r2w_async_simplex
1800
# ( .data_width(36), .addr_width(addr_width))
1801
fifo (
1802
    // a side
1803
    .a_d(a_d),
1804
    .a_wr(a_wr),
1805
    .a_fifo_full(a_fifo_full),
1806
    .a_q(a_q),
1807
    .a_rd(a_rd),
1808
    .a_fifo_empty(a_fifo_empty),
1809
    .a_clk(wbs_clk),
1810
    .a_rst(wbs_rst),
1811
    // b side
1812
    .b_d(b_d),
1813
    .b_wr(b_wr),
1814
    .b_fifo_full(b_fifo_full),
1815
    .b_q(b_q),
1816
    .b_rd(b_rd),
1817
    .b_fifo_empty(b_fifo_empty),
1818
    .b_clk(wbm_clk),
1819
    .b_rst(wbm_rst)
1820
    );
1821
endmodule
1822 39 unneback
module vl_wb3_arbiter_type1 (
1823
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1824
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1825
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1826
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1827
    wb_clk, wb_rst
1828
);
1829
parameter nr_of_ports = 3;
1830
parameter adr_size = 26;
1831
parameter adr_lo   = 2;
1832
parameter dat_size = 32;
1833
parameter sel_size = dat_size/8;
1834
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1835
localparam dw = dat_size * nr_of_ports;
1836
localparam sw = sel_size * nr_of_ports;
1837
localparam cw = 3 * nr_of_ports;
1838
localparam bw = 2 * nr_of_ports;
1839
input  [dw-1:0] wbm_dat_o;
1840
input  [aw-1:0] wbm_adr_o;
1841
input  [sw-1:0] wbm_sel_o;
1842
input  [cw-1:0] wbm_cti_o;
1843
input  [bw-1:0] wbm_bte_o;
1844
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1845
output [dw-1:0] wbm_dat_i;
1846
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1847
output [dat_size-1:0] wbs_dat_i;
1848
output [adr_size-1:adr_lo] wbs_adr_i;
1849
output [sel_size-1:0] wbs_sel_i;
1850
output [2:0] wbs_cti_i;
1851
output [1:0] wbs_bte_i;
1852
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1853
input  [dat_size-1:0] wbs_dat_o;
1854
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1855
input wb_clk, wb_rst;
1856 44 unneback
reg  [nr_of_ports-1:0] select;
1857 39 unneback
wire [nr_of_ports-1:0] state;
1858
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1859
wire [nr_of_ports-1:0] sel;
1860
wire idle;
1861
genvar i;
1862
assign idle = !(|state);
1863
generate
1864
if (nr_of_ports == 2) begin
1865
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1866
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1867 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1868
    always @ (idle or wbm_cyc_o)
1869
    if (idle)
1870
        casex (wbm_cyc_o)
1871
        2'b1x : select = 2'b10;
1872
        2'b01 : select = 2'b01;
1873
        default : select = {nr_of_ports{1'b0}};
1874
        endcase
1875
    else
1876
        select = {nr_of_ports{1'b0}};
1877 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1878
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1879
end
1880
endgenerate
1881
generate
1882
if (nr_of_ports == 3) begin
1883
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1884
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1885 44 unneback
    always @ (idle or wbm_cyc_o)
1886
    if (idle)
1887
        casex (wbm_cyc_o)
1888
        3'b1xx : select = 3'b100;
1889
        3'b01x : select = 3'b010;
1890
        3'b001 : select = 3'b001;
1891
        default : select = {nr_of_ports{1'b0}};
1892
        endcase
1893
    else
1894
        select = {nr_of_ports{1'b0}};
1895
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1896 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1897
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1898
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1899
end
1900
endgenerate
1901
generate
1902 44 unneback
if (nr_of_ports == 4) begin
1903
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1904
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1905
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1906
    always @ (idle or wbm_cyc_o)
1907
    if (idle)
1908
        casex (wbm_cyc_o)
1909
        4'b1xxx : select = 4'b1000;
1910
        4'b01xx : select = 4'b0100;
1911
        4'b001x : select = 4'b0010;
1912
        4'b0001 : select = 4'b0001;
1913
        default : select = {nr_of_ports{1'b0}};
1914
        endcase
1915
    else
1916
        select = {nr_of_ports{1'b0}};
1917
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
1918
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1919
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1920
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1921
end
1922
endgenerate
1923
generate
1924
if (nr_of_ports == 5) begin
1925
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1926
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1927
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1928
    always @ (idle or wbm_cyc_o)
1929
    if (idle)
1930
        casex (wbm_cyc_o)
1931
        5'b1xxxx : select = 5'b10000;
1932
        5'b01xxx : select = 5'b01000;
1933
        5'b001xx : select = 5'b00100;
1934
        5'b0001x : select = 5'b00010;
1935
        5'b00001 : select = 5'b00001;
1936
        default : select = {nr_of_ports{1'b0}};
1937
        endcase
1938
    else
1939
        select = {nr_of_ports{1'b0}};
1940
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
1941
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
1942
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1943
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1944
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1945
end
1946
endgenerate
1947
generate
1948 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
1949 39 unneback
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
1950
end
1951
endgenerate
1952
    assign sel = select | state;
1953
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
1954
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
1955
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
1956
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
1957
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
1958
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
1959
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
1960
    assign wbs_cyc_i = |sel;
1961
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
1962
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
1963
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
1964
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
1965
endmodule
1966 49 unneback
// WB RAM with byte enable
1967 59 unneback
module vl_wb_b3_ram_be (
1968 61 unneback
    wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
1969 59 unneback
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
1970 60 unneback
parameter nr_of_ports = 3;
1971
parameter wb_arbiter_type = 1;
1972
parameter adr_size = 26;
1973
parameter adr_lo   = 2;
1974
parameter dat_size = 32;
1975
parameter memory_init = 1;
1976
parameter memory_file = "vl_ram.vmem";
1977
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1978
localparam dw = dat_size * nr_of_ports;
1979
localparam sw = dat_size/8 * nr_of_ports;
1980
localparam cw = 3 * nr_of_ports;
1981
localparam bw = 2 * nr_of_ports;
1982
input [dw-1:0] wb_dat_i;
1983
input [aw-1:0] wb_adr_i;
1984
input [cw-1:0] wb_cti_i;
1985 61 unneback
input [bw-1:0] wb_bte_i;
1986 60 unneback
input [sw-1:0] wb_sel_i;
1987
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
1988
output [dw-1:0] wb_dat_o;
1989 59 unneback
output wb_ack_o;
1990
input wb_clk, wb_rst;
1991 60 unneback
wire [sw-1:0] cke;
1992
// local wb slave
1993
wire [dat_size-1:0] wbs_dat_i;
1994
wire [adr_size-1:0] wbs_adr_i;
1995
wire [2:0] wbs_cti_i;
1996 61 unneback
wire [1:0] wbs_bte_i;
1997 60 unneback
wire [(dat_size/8)-1:0] wbs_sel_i;
1998
wire  wbs_we_i, wbs_stb_i, wbs_cyc_i;
1999
wire [dat_size-1:0] wbs_dat_o;
2000
reg wbs_ack_o;
2001 59 unneback
generate
2002 60 unneback
if (nr_of_ports == 1) begin
2003
    assign wbs_dat_i = wb_dat_i;
2004
    assign wbs_adr_i = wb_adr_i;
2005
    assign wbs_cti_i = wb_cti_i;
2006
    assign wbs_sel_i = wb_sel_i;
2007
    assign wbs_we_i  = wb_we_i;
2008
    assign wbs_stb_i = wb_stb_i;
2009
    assign wbs_cyc_i = wb_cyc_i;
2010
    assign wb_dat_o  = wbs_dat_o;
2011
    assign wb_ack_o  = wbs_ack_o;
2012 59 unneback
end
2013
endgenerate
2014 60 unneback
generate
2015
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin
2016
vl_wb3_arbiter_type1 wb_arbiter0(
2017
    .wbm_dat_o(wb_dat_i),
2018
    .wbm_adr_o(wb_adr_i),
2019
    .wbm_sel_o(wb_sel_i),
2020
    .wbm_cti_o(wb_cti_i),
2021
    .wbm_bte_o(wb_bte_i),
2022
    .wbm_we_o(wb_we_i),
2023
    .wbm_stb_o(wb_stb_i),
2024
    .wbm_cyc_o(wb_cyc_i),
2025
    .wbm_dat_i(wb_dat_o),
2026
    .wbm_ack_i(wb_ack_o),
2027
    .wbm_err_i(),
2028
    .wbm_rty_i(),
2029
    .wbs_dat_i(wbs_dat_i),
2030
    .wbs_adr_i(wbs_adr_i),
2031
    .wbs_sel_i(wbs_sel_i),
2032
    .wbs_cti_i(wbs_cti_i),
2033
    .wbs_bte_i(wbs_bte_i),
2034
    .wbs_we_i(wbs_we_i),
2035
    .wbs_stb_i(wbs_stb_i),
2036
    .wbs_cyc_i(wbs_cyc_i),
2037
    .wbs_dat_o(wbs_dat_o),
2038
    .wbs_ack_o(wbs_ack_o),
2039
    .wbs_err_o(1'b0),
2040
    .wbs_rty_o(1'b0),
2041
    .wb_clk(wb_clk),
2042
    .wb_rst(wb_rst)
2043
);
2044
end
2045
endgenerate
2046
vl_ram_be # (
2047
    .data_width(dat_size),
2048
    .addr_width(adr_size),
2049
    .memory_init(1),
2050
    .memory_file("memory_file"))
2051
ram0(
2052
    .d(wbs_dat_i),
2053
    .adr(wbs_adr_i[adr_size-1:2]),
2054
    .be(wbs_sel_i),
2055
    .we(wbs_we_i),
2056
    .q(wbs_dat_o),
2057
    .clk(wb_clk)
2058
);
2059 59 unneback
always @ (posedge wb_clk or posedge wb_rst)
2060
if (wb_rst)
2061 60 unneback
    wbs_ack_o <= 1'b0;
2062 59 unneback
else
2063 60 unneback
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
2064
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
2065 59 unneback
    else
2066 60 unneback
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
2067 59 unneback
endmodule
2068
// WB RAM with byte enable
2069 49 unneback
module vl_wb_b4_ram_be (
2070
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
2071 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
2072 49 unneback
    parameter dat_width = 32;
2073
    parameter adr_width = 8;
2074
input [dat_width-1:0] wb_dat_i;
2075
input [adr_width-1:0] wb_adr_i;
2076
input [dat_width/8-1:0] wb_sel_i;
2077
input wb_we_i, wb_stb_i, wb_cyc_i;
2078
output [dat_width-1:0] wb_dat_o;
2079 51 unneback
reg [dat_width-1:0] wb_dat_o;
2080 52 unneback
output wb_stall_o;
2081 49 unneback
output wb_ack_o;
2082
reg wb_ack_o;
2083
input wb_clk, wb_rst;
2084 56 unneback
wire [dat_width/8-1:0] cke;
2085 49 unneback
generate
2086
if (dat_width==32) begin
2087 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
2088
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
2089
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
2090
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
2091 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
2092 49 unneback
    always @ (posedge wb_clk)
2093
    begin
2094 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
2095
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
2096
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
2097
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
2098 49 unneback
    end
2099 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
2100
    begin
2101
        if (wb_rst)
2102
            wb_dat_o <= 32'h0;
2103
        else
2104
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
2105
    end
2106 49 unneback
end
2107
endgenerate
2108 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
2109 55 unneback
if (wb_rst)
2110 52 unneback
    wb_ack_o <= 1'b0;
2111
else
2112 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
2113 52 unneback
assign wb_stall_o = 1'b0;
2114 49 unneback
endmodule
2115 17 unneback
// WB ROM
2116 48 unneback
module vl_wb_b4_rom (
2117
    wb_adr_i, wb_stb_i, wb_cyc_i,
2118
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
2119
    parameter dat_width = 32;
2120
    parameter dat_default = 32'h15000000;
2121
    parameter adr_width = 32;
2122
/*
2123
`ifndef ROM
2124
`define ROM "rom.v"
2125
`endif
2126
*/
2127
    input [adr_width-1:2]   wb_adr_i;
2128
    input                   wb_stb_i;
2129
    input                   wb_cyc_i;
2130
    output [dat_width-1:0]  wb_dat_o;
2131
    reg [dat_width-1:0]     wb_dat_o;
2132
    output                  wb_ack_o;
2133
    reg                     wb_ack_o;
2134
    output                  stall_o;
2135
    input                   wb_clk;
2136
    input                   wb_rst;
2137
always @ (posedge wb_clk or posedge wb_rst)
2138
    if (wb_rst)
2139
        wb_dat_o <= {dat_width{1'b0}};
2140
    else
2141
         case (wb_adr_i[adr_width-1:2])
2142
`ifdef ROM
2143
`include `ROM
2144
`endif
2145
           default:
2146
             wb_dat_o <= dat_default;
2147
         endcase // case (wb_adr_i)
2148
always @ (posedge wb_clk or posedge wb_rst)
2149
    if (wb_rst)
2150
        wb_ack_o <= 1'b0;
2151
    else
2152
        wb_ack_o <= wb_stb_i & wb_cyc_i;
2153
assign stall_o = 1'b0;
2154
endmodule
2155
// WB ROM
2156 18 unneback
module vl_wb_boot_rom (
2157 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2158 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2159
    parameter adr_hi = 31;
2160
    parameter adr_lo = 28;
2161
    parameter adr_sel = 4'hf;
2162
    parameter addr_width = 5;
2163 33 unneback
/*
2164 17 unneback
`ifndef BOOT_ROM
2165
`define BOOT_ROM "boot_rom.v"
2166
`endif
2167 33 unneback
*/
2168 18 unneback
    input [adr_hi:2]    wb_adr_i;
2169
    input               wb_stb_i;
2170
    input               wb_cyc_i;
2171
    output [31:0]        wb_dat_o;
2172
    output              wb_ack_o;
2173
    output              hit_o;
2174
    input               wb_clk;
2175
    input               wb_rst;
2176
    wire hit;
2177
    reg [31:0] wb_dat;
2178
    reg wb_ack;
2179
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2180 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2181
    if (wb_rst)
2182 18 unneback
        wb_dat <= 32'h15000000;
2183 17 unneback
    else
2184 18 unneback
         case (wb_adr_i[addr_width-1:2])
2185 33 unneback
`ifdef BOOT_ROM
2186 17 unneback
`include `BOOT_ROM
2187 33 unneback
`endif
2188 17 unneback
           /*
2189
            // Zero r0 and jump to 0x00000100
2190 18 unneback
 
2191
            1 : wb_dat <= 32'hA8200000;
2192
            2 : wb_dat <= 32'hA8C00100;
2193
            3 : wb_dat <= 32'h44003000;
2194
            4 : wb_dat <= 32'h15000000;
2195 17 unneback
            */
2196
           default:
2197 18 unneback
             wb_dat <= 32'h00000000;
2198 17 unneback
         endcase // case (wb_adr_i)
2199
always @ (posedge wb_clk or posedge wb_rst)
2200
    if (wb_rst)
2201 18 unneback
        wb_ack <= 1'b0;
2202 17 unneback
    else
2203 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2204
assign hit_o = hit;
2205
assign wb_dat_o = wb_dat & {32{wb_ack}};
2206
assign wb_ack_o = wb_ack;
2207 17 unneback
endmodule
2208 32 unneback
module vl_wb_dpram (
2209
        // wishbone slave side a
2210
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
2211
        wbsa_clk, wbsa_rst,
2212
        // wishbone slave side a
2213
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
2214
        wbsb_clk, wbsb_rst);
2215
parameter data_width = 32;
2216
parameter addr_width = 8;
2217
parameter dat_o_mask_a = 1;
2218
parameter dat_o_mask_b = 1;
2219
input [31:0] wbsa_dat_i;
2220
input [addr_width-1:2] wbsa_adr_i;
2221
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2222
output [31:0] wbsa_dat_o;
2223
output wbsa_ack_o;
2224
input wbsa_clk, wbsa_rst;
2225
input [31:0] wbsb_dat_i;
2226
input [addr_width-1:2] wbsb_adr_i;
2227
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2228
output [31:0] wbsb_dat_o;
2229
output wbsb_ack_o;
2230
input wbsb_clk, wbsb_rst;
2231
wire wbsa_dat_tmp, wbsb_dat_tmp;
2232
vl_dpram_2r2w # (
2233 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
2234 32 unneback
dpram0(
2235
    .d_a(wbsa_dat_i),
2236
    .q_a(wbsa_dat_tmp),
2237
    .adr_a(wbsa_adr_i),
2238
    .we_a(wbsa_we_i),
2239
    .clk_a(wbsa_clk),
2240
    .d_b(wbsb_dat_i),
2241
    .q_b(wbsb_dat_tmp),
2242
    .adr_b(wbsb_adr_i),
2243
    .we_b(wbsb_we_i),
2244
    .clk_b(wbsb_clk) );
2245 33 unneback
generate if (dat_o_mask_a==1)
2246 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
2247
endgenerate
2248 33 unneback
generate if (dat_o_mask_a==0)
2249 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
2250
endgenerate
2251 33 unneback
generate if (dat_o_mask_b==1)
2252 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
2253
endgenerate
2254 33 unneback
generate if (dat_o_mask_b==0)
2255 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
2256
endgenerate
2257
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2258
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2259
endmodule
2260 18 unneback
//////////////////////////////////////////////////////////////////////
2261
////                                                              ////
2262
////  Arithmetic functions                                        ////
2263
////                                                              ////
2264
////  Description                                                 ////
2265
////  Arithmetic functions for ALU and DSP                        ////
2266
////                                                              ////
2267
////                                                              ////
2268
////  To Do:                                                      ////
2269
////   -                                                          ////
2270
////                                                              ////
2271
////  Author(s):                                                  ////
2272
////      - Michael Unneback, unneback@opencores.org              ////
2273
////        ORSoC AB                                              ////
2274
////                                                              ////
2275
//////////////////////////////////////////////////////////////////////
2276
////                                                              ////
2277
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2278
////                                                              ////
2279
//// This source file may be used and distributed without         ////
2280
//// restriction provided that this copyright statement is not    ////
2281
//// removed from the file and that any derivative work contains  ////
2282
//// the original copyright notice and the associated disclaimer. ////
2283
////                                                              ////
2284
//// This source file is free software; you can redistribute it   ////
2285
//// and/or modify it under the terms of the GNU Lesser General   ////
2286
//// Public License as published by the Free Software Foundation; ////
2287
//// either version 2.1 of the License, or (at your option) any   ////
2288
//// later version.                                               ////
2289
////                                                              ////
2290
//// This source is distributed in the hope that it will be       ////
2291
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2292
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2293
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2294
//// details.                                                     ////
2295
////                                                              ////
2296
//// You should have received a copy of the GNU Lesser General    ////
2297
//// Public License along with this source; if not, download it   ////
2298
//// from http://www.opencores.org/lgpl.shtml                     ////
2299
////                                                              ////
2300
//////////////////////////////////////////////////////////////////////
2301
// signed multiplication
2302
module vl_mults (a,b,p);
2303
parameter operand_a_width = 18;
2304
parameter operand_b_width = 18;
2305
parameter result_hi = 35;
2306
parameter result_lo = 0;
2307
input [operand_a_width-1:0] a;
2308
input [operand_b_width-1:0] b;
2309
output [result_hi:result_lo] p;
2310
wire signed [operand_a_width-1:0] ai;
2311
wire signed [operand_b_width-1:0] bi;
2312
wire signed [operand_a_width+operand_b_width-1:0] result;
2313
    assign ai = a;
2314
    assign bi = b;
2315
    assign result = ai * bi;
2316
    assign p = result[result_hi:result_lo];
2317
endmodule
2318
module vl_mults18x18 (a,b,p);
2319
input [17:0] a,b;
2320
output [35:0] p;
2321
vl_mult
2322
    # (.operand_a_width(18), .operand_b_width(18))
2323
    mult0 (.a(a), .b(b), .p(p));
2324
endmodule
2325
// unsigned multiplication
2326
module vl_mult (a,b,p);
2327
parameter operand_a_width = 18;
2328
parameter operand_b_width = 18;
2329
parameter result_hi = 35;
2330
parameter result_lo = 0;
2331
input [operand_a_width-1:0] a;
2332
input [operand_b_width-1:0] b;
2333
output [result_hi:result_hi] p;
2334
wire [operand_a_width+operand_b_width-1:0] result;
2335
    assign result = a * b;
2336
    assign p = result[result_hi:result_lo];
2337
endmodule
2338
// shift unit
2339
// supporting the following shift functions
2340
//   SLL
2341
//   SRL
2342
//   SRA
2343
module vl_shift_unit_32( din, s, dout, opcode);
2344
input [31:0] din; // data in operand
2345
input [4:0] s; // shift operand
2346
input [1:0] opcode;
2347
output [31:0] dout;
2348
parameter opcode_sll = 2'b00;
2349
//parameter opcode_srl = 2'b01;
2350
parameter opcode_sra = 2'b10;
2351
//parameter opcode_ror = 2'b11;
2352
wire sll, sra;
2353
assign sll = opcode == opcode_sll;
2354
assign sra = opcode == opcode_sra;
2355
wire [15:1] s1;
2356
wire [3:0] sign;
2357
wire [7:0] tmp [0:3];
2358
// first stage is multiplier based
2359
// shift operand as fractional 8.7
2360
assign s1[15] = sll & s[2:0]==3'd7;
2361
assign s1[14] = sll & s[2:0]==3'd6;
2362
assign s1[13] = sll & s[2:0]==3'd5;
2363
assign s1[12] = sll & s[2:0]==3'd4;
2364
assign s1[11] = sll & s[2:0]==3'd3;
2365
assign s1[10] = sll & s[2:0]==3'd2;
2366
assign s1[ 9] = sll & s[2:0]==3'd1;
2367
assign s1[ 8] = s[2:0]==3'd0;
2368
assign s1[ 7] = !sll & s[2:0]==3'd1;
2369
assign s1[ 6] = !sll & s[2:0]==3'd2;
2370
assign s1[ 5] = !sll & s[2:0]==3'd3;
2371
assign s1[ 4] = !sll & s[2:0]==3'd4;
2372
assign s1[ 3] = !sll & s[2:0]==3'd5;
2373
assign s1[ 2] = !sll & s[2:0]==3'd6;
2374
assign s1[ 1] = !sll & s[2:0]==3'd7;
2375
assign sign[3] = din[31] & sra;
2376
assign sign[