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1 60 unneback
// default SYN_KEEP definition
2 6 unneback
//////////////////////////////////////////////////////////////////////
3
////                                                              ////
4
////  Versatile library, clock and reset                          ////
5
////                                                              ////
6
////  Description                                                 ////
7
////  Logic related to clock and reset                            ////
8
////                                                              ////
9
////                                                              ////
10
////  To Do:                                                      ////
11
////   - add more different registers                             ////
12
////                                                              ////
13
////  Author(s):                                                  ////
14
////      - Michael Unneback, unneback@opencores.org              ////
15
////        ORSoC AB                                              ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43 48 unneback
`timescale 1 ns/100 ps
44 6 unneback
// Global buffer
45
// usage:
46
// use to enable global buffers for high fan out signals such as clock and reset
47
// Version: 8.4 8.4.0.33
48
module gbuf(GL,CLK);
49
output GL;
50
input  CLK;
51
    wire GND;
52
    GND GND_1_net(.Y(GND));
53
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
54
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
55
endmodule
56
`timescale 1 ns/1 ns
57
module vl_gbuf ( i, o);
58
input i;
59
output o;
60
`ifdef SIM_GBUF
61
assign o=i;
62
`else
63
gbuf gbuf_i0 ( .CLK(i), .GL(o));
64
`endif
65
endmodule
66
 //ACTEL
67
// sync reset
68 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
69 6 unneback
// output active high global reset sync with two DFFs 
70
`timescale 1 ns/100 ps
71
module vl_sync_rst ( rst_n_i, rst_o, clk);
72
input rst_n_i, clk;
73
output rst_o;
74 18 unneback
reg [1:0] tmp;
75 6 unneback
always @ (posedge clk or negedge rst_n_i)
76
if (!rst_n_i)
77 17 unneback
        tmp <= 2'b11;
78 6 unneback
else
79 33 unneback
        tmp <= {1'b0,tmp[1]};
80 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
81 6 unneback
endmodule
82
// vl_pll
83 32 unneback
///////////////////////////////////////////////////////////////////////////////
84 17 unneback
`timescale 1 ps/1 ps
85 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
86
parameter index = 0;
87
parameter number_of_clk = 1;
88 17 unneback
parameter period_time_0 = 20000;
89
parameter period_time_1 = 20000;
90
parameter period_time_2 = 20000;
91
parameter lock_delay = 2000000;
92 6 unneback
input clk_i, rst_n_i;
93
output lock;
94
output reg [0:number_of_clk-1] clk_o;
95
output [0:number_of_clk-1] rst_o;
96
`ifdef SIM_PLL
97
always
98
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
99
generate if (number_of_clk > 1)
100
always
101
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
102
endgenerate
103
generate if (number_of_clk > 2)
104
always
105
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
106
endgenerate
107
genvar i;
108
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
109
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
110
end
111
endgenerate
112
assign #lock_delay lock = rst_n_i;
113
endmodule
114
`else
115
generate if (number_of_clk==1 & index==0) begin
116
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
117
end
118
endgenerate // index==0
119
generate if (number_of_clk==1 & index==1) begin
120
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
121
end
122
endgenerate // index==1
123
generate if (number_of_clk==1 & index==2) begin
124
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
125
end
126
endgenerate // index==2
127
generate if (number_of_clk==1 & index==3) begin
128
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
129
end
130
endgenerate // index==0
131
generate if (number_of_clk==2 & index==0) begin
132
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
133
end
134
endgenerate // index==0
135
generate if (number_of_clk==2 & index==1) begin
136
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
137
end
138
endgenerate // index==1
139
generate if (number_of_clk==2 & index==2) begin
140
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
141
end
142
endgenerate // index==2
143
generate if (number_of_clk==2 & index==3) begin
144
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
145
end
146
endgenerate // index==0
147
generate if (number_of_clk==3 & index==0) begin
148
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
149
end
150
endgenerate // index==0
151
generate if (number_of_clk==3 & index==1) begin
152
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
153
end
154
endgenerate // index==1
155
generate if (number_of_clk==3 & index==2) begin
156
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
157
end
158
endgenerate // index==2
159
generate if (number_of_clk==3 & index==3) begin
160
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
161
end
162
endgenerate // index==0
163
genvar i;
164
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
165 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
166 6 unneback
end
167
endgenerate
168
endmodule
169
`endif
170 32 unneback
///////////////////////////////////////////////////////////////////////////////
171 6 unneback
 //actel
172
//////////////////////////////////////////////////////////////////////
173
////                                                              ////
174
////  Versatile library, registers                                ////
175
////                                                              ////
176
////  Description                                                 ////
177
////  Different type of registers                                 ////
178
////                                                              ////
179
////                                                              ////
180
////  To Do:                                                      ////
181
////   - add more different registers                             ////
182
////                                                              ////
183
////  Author(s):                                                  ////
184
////      - Michael Unneback, unneback@opencores.org              ////
185
////        ORSoC AB                                              ////
186
////                                                              ////
187
//////////////////////////////////////////////////////////////////////
188
////                                                              ////
189
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
190
////                                                              ////
191
//// This source file may be used and distributed without         ////
192
//// restriction provided that this copyright statement is not    ////
193
//// removed from the file and that any derivative work contains  ////
194
//// the original copyright notice and the associated disclaimer. ////
195
////                                                              ////
196
//// This source file is free software; you can redistribute it   ////
197
//// and/or modify it under the terms of the GNU Lesser General   ////
198
//// Public License as published by the Free Software Foundation; ////
199
//// either version 2.1 of the License, or (at your option) any   ////
200
//// later version.                                               ////
201
////                                                              ////
202
//// This source is distributed in the hope that it will be       ////
203
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
204
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
205
//// PURPOSE.  See the GNU Lesser General Public License for more ////
206
//// details.                                                     ////
207
////                                                              ////
208
//// You should have received a copy of the GNU Lesser General    ////
209
//// Public License along with this source; if not, download it   ////
210
//// from http://www.opencores.org/lgpl.shtml                     ////
211
////                                                              ////
212
//////////////////////////////////////////////////////////////////////
213 18 unneback
module vl_dff ( d, q, clk, rst);
214 6 unneback
        parameter width = 1;
215
        parameter reset_value = 0;
216
        input [width-1:0] d;
217
        input clk, rst;
218
        output reg [width-1:0] q;
219
        always @ (posedge clk or posedge rst)
220
        if (rst)
221
                q <= reset_value;
222
        else
223
                q <= d;
224
endmodule
225 18 unneback
module vl_dff_array ( d, q, clk, rst);
226 6 unneback
        parameter width = 1;
227
        parameter depth = 2;
228
        parameter reset_value = 1'b0;
229
        input [width-1:0] d;
230
        input clk, rst;
231
        output [width-1:0] q;
232
        reg  [0:depth-1] q_tmp [width-1:0];
233
        integer i;
234
        always @ (posedge clk or posedge rst)
235
        if (rst) begin
236
            for (i=0;i<depth;i=i+1)
237
                q_tmp[i] <= {width{reset_value}};
238
        end else begin
239
            q_tmp[0] <= d;
240
            for (i=1;i<depth;i=i+1)
241
                q_tmp[i] <= q_tmp[i-1];
242
        end
243
    assign q = q_tmp[depth-1];
244
endmodule
245 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
246 6 unneback
        parameter width = 1;
247
        parameter reset_value = 0;
248
        input [width-1:0] d;
249
        input ce, clk, rst;
250
        output reg [width-1:0] q;
251
        always @ (posedge clk or posedge rst)
252
        if (rst)
253
                q <= reset_value;
254
        else
255
                if (ce)
256
                        q <= d;
257
endmodule
258 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
259 8 unneback
        parameter width = 1;
260
        parameter reset_value = 0;
261
        input [width-1:0] d;
262 10 unneback
        input ce, clear, clk, rst;
263 8 unneback
        output reg [width-1:0] q;
264
        always @ (posedge clk or posedge rst)
265
        if (rst)
266
            q <= reset_value;
267
        else
268
            if (ce)
269
                if (clear)
270
                    q <= {width{1'b0}};
271
                else
272
                    q <= d;
273
endmodule
274 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
275
        parameter width = 1;
276
        parameter reset_value = 0;
277
        input [width-1:0] d;
278
        input ce, set, clk, rst;
279
        output reg [width-1:0] q;
280
        always @ (posedge clk or posedge rst)
281
        if (rst)
282
            q <= reset_value;
283
        else
284
            if (ce)
285
                if (set)
286
                    q <= {width{1'b1}};
287
                else
288
                    q <= d;
289
endmodule
290 29 unneback
module vl_spr ( sp, r, q, clk, rst);
291 64 unneback
        //parameter width = 1;
292
        parameter reset_value = 1'b0;
293 29 unneback
        input sp, r;
294
        output reg q;
295
        input clk, rst;
296
        always @ (posedge clk or posedge rst)
297
        if (rst)
298
            q <= reset_value;
299
        else
300
            if (sp)
301
                q <= 1'b1;
302
            else if (r)
303
                q <= 1'b0;
304
endmodule
305
module vl_srp ( s, rp, q, clk, rst);
306
        parameter width = 1;
307
        parameter reset_value = 0;
308
        input s, rp;
309
        output reg q;
310
        input clk, rst;
311
        always @ (posedge clk or posedge rst)
312
        if (rst)
313
            q <= reset_value;
314
        else
315
            if (rp)
316
                q <= 1'b0;
317
            else if (s)
318
                q <= 1'b1;
319
endmodule
320 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
321 6 unneback
    input         aclr;
322
    input         aset;
323
    input         clock;
324
    input         data;
325
    output reg    q;
326
   always @ (posedge clock or posedge aclr or posedge aset)
327
     if (aclr)
328
       q <= 1'b0;
329
     else if (aset)
330
       q <= 1'b1;
331
     else
332
       q <= data;
333
endmodule
334
// LATCH
335
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
336 40 unneback
module vl_latch ( d, le, q, clk);
337 6 unneback
input d, le;
338 48 unneback
input clk;
339
always @ (le or d)
340 60 unneback
if (le)
341 48 unneback
    d <= q;
342 6 unneback
endmodule
343 18 unneback
module vl_shreg ( d, q, clk, rst);
344 17 unneback
parameter depth = 10;
345
input d;
346
output q;
347
input clk, rst;
348
reg [1:depth] dffs;
349
always @ (posedge clk or posedge rst)
350
if (rst)
351
    dffs <= {depth{1'b0}};
352
else
353
    dffs <= {d,dffs[1:depth-1]};
354
assign q = dffs[depth];
355
endmodule
356 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
357 17 unneback
parameter depth = 10;
358
input d, ce;
359
output q;
360
input clk, rst;
361
reg [1:depth] dffs;
362
always @ (posedge clk or posedge rst)
363
if (rst)
364
    dffs <= {depth{1'b0}};
365
else
366
    if (ce)
367
        dffs <= {d,dffs[1:depth-1]};
368
assign q = dffs[depth];
369
endmodule
370 18 unneback
module vl_delay ( d, q, clk, rst);
371 15 unneback
parameter depth = 10;
372
input d;
373
output q;
374
input clk, rst;
375
reg [1:depth] dffs;
376
always @ (posedge clk or posedge rst)
377
if (rst)
378
    dffs <= {depth{1'b0}};
379
else
380
    dffs <= {d,dffs[1:depth-1]};
381
assign q = dffs[depth];
382
endmodule
383 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
384 17 unneback
parameter depth = 10;
385
input d;
386
output q, emptyflag;
387
input clk, rst;
388
reg [1:depth] dffs;
389
always @ (posedge clk or posedge rst)
390
if (rst)
391
    dffs <= {depth{1'b0}};
392
else
393
    dffs <= {d,dffs[1:depth-1]};
394
assign q = dffs[depth];
395
assign emptyflag = !(|dffs);
396
endmodule
397 6 unneback
//////////////////////////////////////////////////////////////////////
398
////                                                              ////
399 18 unneback
////  Logic functions                                             ////
400
////                                                              ////
401
////  Description                                                 ////
402
////  Logic functions such as multiplexers                        ////
403
////                                                              ////
404
////                                                              ////
405
////  To Do:                                                      ////
406
////   -                                                          ////
407
////                                                              ////
408
////  Author(s):                                                  ////
409
////      - Michael Unneback, unneback@opencores.org              ////
410
////        ORSoC AB                                              ////
411
////                                                              ////
412
//////////////////////////////////////////////////////////////////////
413
////                                                              ////
414
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
415
////                                                              ////
416
//// This source file may be used and distributed without         ////
417
//// restriction provided that this copyright statement is not    ////
418
//// removed from the file and that any derivative work contains  ////
419
//// the original copyright notice and the associated disclaimer. ////
420
////                                                              ////
421
//// This source file is free software; you can redistribute it   ////
422
//// and/or modify it under the terms of the GNU Lesser General   ////
423
//// Public License as published by the Free Software Foundation; ////
424
//// either version 2.1 of the License, or (at your option) any   ////
425
//// later version.                                               ////
426
////                                                              ////
427
//// This source is distributed in the hope that it will be       ////
428
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
429
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
430
//// PURPOSE.  See the GNU Lesser General Public License for more ////
431
//// details.                                                     ////
432
////                                                              ////
433
//// You should have received a copy of the GNU Lesser General    ////
434
//// Public License along with this source; if not, download it   ////
435
//// from http://www.opencores.org/lgpl.shtml                     ////
436
////                                                              ////
437
//////////////////////////////////////////////////////////////////////
438 36 unneback
module vl_mux_andor ( a, sel, dout);
439
parameter width = 32;
440
parameter nr_of_ports = 4;
441
input [nr_of_ports*width-1:0] a;
442
input [nr_of_ports-1:0] sel;
443
output reg [width-1:0] dout;
444 38 unneback
integer i,j;
445 36 unneback
always @ (a, sel)
446
begin
447
    dout = a[width-1:0] & {width{sel[0]}};
448 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
449
        for (j=0;j<width;j=j+1)
450
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
451 36 unneback
end
452
endmodule
453 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
454
parameter width = 32;
455 35 unneback
localparam nr_of_ports = 2;
456 34 unneback
input [width-1:0] a1, a0;
457
input [nr_of_ports-1:0] sel;
458
output [width-1:0] dout;
459 36 unneback
vl_mux_andor
460 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
461 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
462 34 unneback
endmodule
463
module vl_mux3_andor ( a2, a1, a0, sel, dout);
464
parameter width = 32;
465 35 unneback
localparam nr_of_ports = 3;
466 34 unneback
input [width-1:0] a2, a1, a0;
467
input [nr_of_ports-1:0] sel;
468
output [width-1:0] dout;
469 36 unneback
vl_mux_andor
470 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
471 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
472 34 unneback
endmodule
473 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
474
parameter width = 32;
475 35 unneback
localparam nr_of_ports = 4;
476 18 unneback
input [width-1:0] a3, a2, a1, a0;
477
input [nr_of_ports-1:0] sel;
478 22 unneback
output [width-1:0] dout;
479 36 unneback
vl_mux_andor
480 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
481 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
482 18 unneback
endmodule
483
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
484
parameter width = 32;
485 35 unneback
localparam nr_of_ports = 5;
486 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
487
input [nr_of_ports-1:0] sel;
488 22 unneback
output [width-1:0] dout;
489 36 unneback
vl_mux_andor
490 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
491 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
492 18 unneback
endmodule
493
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
494
parameter width = 32;
495 35 unneback
localparam nr_of_ports = 6;
496 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
497
input [nr_of_ports-1:0] sel;
498 22 unneback
output [width-1:0] dout;
499 36 unneback
vl_mux_andor
500 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
501 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
502 18 unneback
endmodule
503 43 unneback
module vl_parity_generate (data, parity);
504
parameter word_size = 32;
505
parameter chunk_size = 8;
506
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
507
input [word_size-1:0] data;
508
output reg [word_size/chunk_size-1:0] parity;
509
integer i,j;
510
always @ (data)
511
for (i=0;i<word_size/chunk_size;i=i+1) begin
512
    parity[i] = parity_type;
513
    for (j=0;j<chunk_size;j=j+1) begin
514 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
515 43 unneback
    end
516
end
517
endmodule
518
module vl_parity_check( data, parity, parity_error);
519
parameter word_size = 32;
520
parameter chunk_size = 8;
521
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
522
input [word_size-1:0] data;
523
input [word_size/chunk_size-1:0] parity;
524
output parity_error;
525 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
526 43 unneback
integer i,j;
527
always @ (data or parity)
528
for (i=0;i<word_size/chunk_size;i=i+1) begin
529
    error_flag[i] = parity[i] ^ parity_type;
530
    for (j=0;j<chunk_size;j=j+1) begin
531 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
532 43 unneback
    end
533
end
534
assign parity_error = |error_flag;
535
endmodule
536 18 unneback
//////////////////////////////////////////////////////////////////////
537
////                                                              ////
538 44 unneback
////  IO functions                                                ////
539
////                                                              ////
540
////  Description                                                 ////
541
////  IO functions such as IOB flip-flops                         ////
542
////                                                              ////
543
////                                                              ////
544
////  To Do:                                                      ////
545
////   -                                                          ////
546
////                                                              ////
547
////  Author(s):                                                  ////
548
////      - Michael Unneback, unneback@opencores.org              ////
549
////        ORSoC AB                                              ////
550
////                                                              ////
551
//////////////////////////////////////////////////////////////////////
552
////                                                              ////
553
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
554
////                                                              ////
555
//// This source file may be used and distributed without         ////
556
//// restriction provided that this copyright statement is not    ////
557
//// removed from the file and that any derivative work contains  ////
558
//// the original copyright notice and the associated disclaimer. ////
559
////                                                              ////
560
//// This source file is free software; you can redistribute it   ////
561
//// and/or modify it under the terms of the GNU Lesser General   ////
562
//// Public License as published by the Free Software Foundation; ////
563
//// either version 2.1 of the License, or (at your option) any   ////
564
//// later version.                                               ////
565
////                                                              ////
566
//// This source is distributed in the hope that it will be       ////
567
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
568
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
569
//// PURPOSE.  See the GNU Lesser General Public License for more ////
570
//// details.                                                     ////
571
////                                                              ////
572
//// You should have received a copy of the GNU Lesser General    ////
573
//// Public License along with this source; if not, download it   ////
574
//// from http://www.opencores.org/lgpl.shtml                     ////
575
////                                                              ////
576
//////////////////////////////////////////////////////////////////////
577 45 unneback
`timescale 1ns/1ns
578 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
579
parameter width = 1;
580 45 unneback
parameter reset_value = {width{1'b0}};
581
input  [width-1:0]  d_i;
582 44 unneback
output [width-1:0] o_pad;
583
input clk, rst;
584
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
585 45 unneback
reg  [width-1:0] o_pad_int;
586 44 unneback
assign d_i_int = d_i;
587
genvar i;
588 45 unneback
generate
589 44 unneback
for (i=0;i<width;i=i+1) begin
590
    always @ (posedge clk or posedge rst)
591
    if (rst)
592 45 unneback
        o_pad_int[i] <= reset_value[i];
593 44 unneback
    else
594 45 unneback
        o_pad_int[i] <= d_i_int[i];
595
    assign #1 o_pad[i] = o_pad_int[i];
596 44 unneback
end
597
endgenerate
598
endmodule
599 45 unneback
`timescale 1ns/1ns
600 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
601
parameter width = 1;
602
input  [width-1:0] d_o;
603
output reg [width-1:0] d_i;
604
input oe;
605
inout [width-1:0] io_pad;
606
input clk, rst;
607
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
608
reg [width-1:0] oe_q;
609
reg [width-1:0] d_o_q;
610
assign oe_d = {width{oe}};
611
genvar i;
612
generate
613
for (i=0;i<width;i=i+1) begin
614
    always @ (posedge clk or posedge rst)
615
    if (rst)
616
        oe_q[i] <= 1'b0;
617
    else
618
        oe_q[i] <= oe_d[i];
619
    always @ (posedge clk or posedge rst)
620
    if (rst)
621
        d_o_q[i] <= 1'b0;
622
    else
623
        d_o_q[i] <= d_o[i];
624
    always @ (posedge clk or posedge rst)
625
    if (rst)
626
        d_i[i] <= 1'b0;
627
    else
628
        d_i[i] <= io_pad[i];
629 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
630 44 unneback
end
631
endgenerate
632
endmodule
633
//////////////////////////////////////////////////////////////////////
634
////                                                              ////
635 6 unneback
////  Versatile counter                                           ////
636
////                                                              ////
637
////  Description                                                 ////
638
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
639
////  counter                                                     ////
640
////                                                              ////
641
////  To Do:                                                      ////
642
////   - add LFSR with more taps                                  ////
643
////                                                              ////
644
////  Author(s):                                                  ////
645
////      - Michael Unneback, unneback@opencores.org              ////
646
////        ORSoC AB                                              ////
647
////                                                              ////
648
//////////////////////////////////////////////////////////////////////
649
////                                                              ////
650
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
651
////                                                              ////
652
//// This source file may be used and distributed without         ////
653
//// restriction provided that this copyright statement is not    ////
654
//// removed from the file and that any derivative work contains  ////
655
//// the original copyright notice and the associated disclaimer. ////
656
////                                                              ////
657
//// This source file is free software; you can redistribute it   ////
658
//// and/or modify it under the terms of the GNU Lesser General   ////
659
//// Public License as published by the Free Software Foundation; ////
660
//// either version 2.1 of the License, or (at your option) any   ////
661
//// later version.                                               ////
662
////                                                              ////
663
//// This source is distributed in the hope that it will be       ////
664
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
665
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
666
//// PURPOSE.  See the GNU Lesser General Public License for more ////
667
//// details.                                                     ////
668
////                                                              ////
669
//// You should have received a copy of the GNU Lesser General    ////
670
//// Public License along with this source; if not, download it   ////
671
//// from http://www.opencores.org/lgpl.shtml                     ////
672
////                                                              ////
673
//////////////////////////////////////////////////////////////////////
674
// binary counter
675 40 unneback
module vl_cnt_bin_ce (
676
 cke, q, rst, clk);
677 22 unneback
   parameter length = 4;
678 6 unneback
   input cke;
679
   output [length:1] q;
680
   input rst;
681
   input clk;
682
   parameter clear_value = 0;
683
   parameter set_value = 1;
684
   parameter wrap_value = 0;
685
   parameter level1_value = 15;
686
   reg  [length:1] qi;
687
   wire [length:1] q_next;
688
   assign q_next = qi + {{length-1{1'b0}},1'b1};
689
   always @ (posedge clk or posedge rst)
690
     if (rst)
691
       qi <= {length{1'b0}};
692
     else
693
     if (cke)
694
       qi <= q_next;
695
   assign q = qi;
696
endmodule
697
//////////////////////////////////////////////////////////////////////
698
////                                                              ////
699
////  Versatile counter                                           ////
700
////                                                              ////
701
////  Description                                                 ////
702
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
703
////  counter                                                     ////
704
////                                                              ////
705
////  To Do:                                                      ////
706
////   - add LFSR with more taps                                  ////
707
////                                                              ////
708
////  Author(s):                                                  ////
709
////      - Michael Unneback, unneback@opencores.org              ////
710
////        ORSoC AB                                              ////
711
////                                                              ////
712
//////////////////////////////////////////////////////////////////////
713
////                                                              ////
714
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
715
////                                                              ////
716
//// This source file may be used and distributed without         ////
717
//// restriction provided that this copyright statement is not    ////
718
//// removed from the file and that any derivative work contains  ////
719
//// the original copyright notice and the associated disclaimer. ////
720
////                                                              ////
721
//// This source file is free software; you can redistribute it   ////
722
//// and/or modify it under the terms of the GNU Lesser General   ////
723
//// Public License as published by the Free Software Foundation; ////
724
//// either version 2.1 of the License, or (at your option) any   ////
725
//// later version.                                               ////
726
////                                                              ////
727
//// This source is distributed in the hope that it will be       ////
728
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
729
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
730
//// PURPOSE.  See the GNU Lesser General Public License for more ////
731
//// details.                                                     ////
732
////                                                              ////
733
//// You should have received a copy of the GNU Lesser General    ////
734
//// Public License along with this source; if not, download it   ////
735
//// from http://www.opencores.org/lgpl.shtml                     ////
736
////                                                              ////
737
//////////////////////////////////////////////////////////////////////
738
// binary counter
739 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
740
 cke, rew, zq, level1, rst, clk);
741 6 unneback
   parameter length = 4;
742
   input cke;
743
   input rew;
744 25 unneback
   output reg zq;
745
   output reg level1;
746
   input rst;
747
   input clk;
748
   parameter clear_value = 0;
749
   parameter set_value = 1;
750
   parameter wrap_value = 1;
751
   parameter level1_value = 15;
752 29 unneback
   wire clear;
753 30 unneback
   assign clear = 1'b0;
754 25 unneback
   reg  [length:1] qi;
755
   wire  [length:1] q_next, q_next_fw, q_next_rew;
756
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
757
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
758
   assign q_next = rew ? q_next_rew : q_next_fw;
759
   always @ (posedge clk or posedge rst)
760
     if (rst)
761
       qi <= {length{1'b0}};
762
     else
763
     if (cke)
764
       qi <= q_next;
765
   always @ (posedge clk or posedge rst)
766
     if (rst)
767
       zq <= 1'b1;
768
     else
769
     if (cke)
770
       zq <= q_next == {length{1'b0}};
771
    always @ (posedge clk or posedge rst)
772
    if (rst)
773
        level1 <= 1'b0;
774
    else
775
    if (cke)
776 29 unneback
    if (clear)
777
        level1 <= 1'b0;
778
    else if (q_next == level1_value)
779 25 unneback
        level1 <= 1'b1;
780
    else if (qi == level1_value & rew)
781
        level1 <= 1'b0;
782
endmodule
783
//////////////////////////////////////////////////////////////////////
784
////                                                              ////
785
////  Versatile counter                                           ////
786
////                                                              ////
787
////  Description                                                 ////
788
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
789
////  counter                                                     ////
790
////                                                              ////
791
////  To Do:                                                      ////
792
////   - add LFSR with more taps                                  ////
793
////                                                              ////
794
////  Author(s):                                                  ////
795
////      - Michael Unneback, unneback@opencores.org              ////
796
////        ORSoC AB                                              ////
797
////                                                              ////
798
//////////////////////////////////////////////////////////////////////
799
////                                                              ////
800
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
801
////                                                              ////
802
//// This source file may be used and distributed without         ////
803
//// restriction provided that this copyright statement is not    ////
804
//// removed from the file and that any derivative work contains  ////
805
//// the original copyright notice and the associated disclaimer. ////
806
////                                                              ////
807
//// This source file is free software; you can redistribute it   ////
808
//// and/or modify it under the terms of the GNU Lesser General   ////
809
//// Public License as published by the Free Software Foundation; ////
810
//// either version 2.1 of the License, or (at your option) any   ////
811
//// later version.                                               ////
812
////                                                              ////
813
//// This source is distributed in the hope that it will be       ////
814
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
815
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
816
//// PURPOSE.  See the GNU Lesser General Public License for more ////
817
//// details.                                                     ////
818
////                                                              ////
819
//// You should have received a copy of the GNU Lesser General    ////
820
//// Public License along with this source; if not, download it   ////
821
//// from http://www.opencores.org/lgpl.shtml                     ////
822
////                                                              ////
823
//////////////////////////////////////////////////////////////////////
824
// binary counter
825 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
826
 cke, rew, q, zq, level1, rst, clk);
827 25 unneback
   parameter length = 4;
828
   input cke;
829
   input rew;
830
   output [length:1] q;
831
   output reg zq;
832
   output reg level1;
833
   input rst;
834
   input clk;
835
   parameter clear_value = 0;
836
   parameter set_value = 1;
837
   parameter wrap_value = 1;
838
   parameter level1_value = 15;
839 29 unneback
   wire clear;
840 30 unneback
   assign clear = 1'b0;
841 25 unneback
   reg  [length:1] qi;
842
   wire  [length:1] q_next, q_next_fw, q_next_rew;
843
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
844
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
845
   assign q_next = rew ? q_next_rew : q_next_fw;
846
   always @ (posedge clk or posedge rst)
847
     if (rst)
848
       qi <= {length{1'b0}};
849
     else
850
     if (cke)
851
       qi <= q_next;
852
   assign q = qi;
853
   always @ (posedge clk or posedge rst)
854
     if (rst)
855
       zq <= 1'b1;
856
     else
857
     if (cke)
858
       zq <= q_next == {length{1'b0}};
859
    always @ (posedge clk or posedge rst)
860
    if (rst)
861
        level1 <= 1'b0;
862
    else
863
    if (cke)
864 29 unneback
    if (clear)
865
        level1 <= 1'b0;
866
    else if (q_next == level1_value)
867 25 unneback
        level1 <= 1'b1;
868
    else if (qi == level1_value & rew)
869
        level1 <= 1'b0;
870
endmodule
871
//////////////////////////////////////////////////////////////////////
872
////                                                              ////
873
////  Versatile counter                                           ////
874
////                                                              ////
875
////  Description                                                 ////
876
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
877
////  counter                                                     ////
878
////                                                              ////
879
////  To Do:                                                      ////
880
////   - add LFSR with more taps                                  ////
881
////                                                              ////
882
////  Author(s):                                                  ////
883
////      - Michael Unneback, unneback@opencores.org              ////
884
////        ORSoC AB                                              ////
885
////                                                              ////
886
//////////////////////////////////////////////////////////////////////
887
////                                                              ////
888
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
889
////                                                              ////
890
//// This source file may be used and distributed without         ////
891
//// restriction provided that this copyright statement is not    ////
892
//// removed from the file and that any derivative work contains  ////
893
//// the original copyright notice and the associated disclaimer. ////
894
////                                                              ////
895
//// This source file is free software; you can redistribute it   ////
896
//// and/or modify it under the terms of the GNU Lesser General   ////
897
//// Public License as published by the Free Software Foundation; ////
898
//// either version 2.1 of the License, or (at your option) any   ////
899
//// later version.                                               ////
900
////                                                              ////
901
//// This source is distributed in the hope that it will be       ////
902
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
903
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
904
//// PURPOSE.  See the GNU Lesser General Public License for more ////
905
//// details.                                                     ////
906
////                                                              ////
907
//// You should have received a copy of the GNU Lesser General    ////
908
//// Public License along with this source; if not, download it   ////
909
//// from http://www.opencores.org/lgpl.shtml                     ////
910
////                                                              ////
911
//////////////////////////////////////////////////////////////////////
912 75 unneback
// LFSR counter
913
module vl_cnt_lfsr_ce (
914
 cke, zq, rst, clk);
915
   parameter length = 4;
916
   input cke;
917
   output reg zq;
918
   input rst;
919
   input clk;
920
   parameter clear_value = 0;
921
   parameter set_value = 1;
922
   parameter wrap_value = 0;
923
   parameter level1_value = 15;
924
   reg  [length:1] qi;
925
   reg lfsr_fb;
926
   wire [length:1] q_next;
927
   reg [32:1] polynom;
928
   integer i;
929
   always @ (qi)
930
   begin
931
        case (length)
932
         2: polynom = 32'b11;                               // 0x3
933
         3: polynom = 32'b110;                              // 0x6
934
         4: polynom = 32'b1100;                             // 0xC
935
         5: polynom = 32'b10100;                            // 0x14
936
         6: polynom = 32'b110000;                           // 0x30
937
         7: polynom = 32'b1100000;                          // 0x60
938
         8: polynom = 32'b10111000;                         // 0xb8
939
         9: polynom = 32'b100010000;                        // 0x110
940
        10: polynom = 32'b1001000000;                       // 0x240
941
        11: polynom = 32'b10100000000;                      // 0x500
942
        12: polynom = 32'b100000101001;                     // 0x829
943
        13: polynom = 32'b1000000001100;                    // 0x100C
944
        14: polynom = 32'b10000000010101;                   // 0x2015
945
        15: polynom = 32'b110000000000000;                  // 0x6000
946
        16: polynom = 32'b1101000000001000;                 // 0xD008
947
        17: polynom = 32'b10010000000000000;                // 0x12000
948
        18: polynom = 32'b100000010000000000;               // 0x20400
949
        19: polynom = 32'b1000000000000100011;              // 0x40023
950
        20: polynom = 32'b10010000000000000000;             // 0x90000
951
        21: polynom = 32'b101000000000000000000;            // 0x140000
952
        22: polynom = 32'b1100000000000000000000;           // 0x300000
953
        23: polynom = 32'b10000100000000000000000;          // 0x420000
954
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
955
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
956
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
957
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
958
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
959
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
960
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
961
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
962
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
963
        default: polynom = 32'b0;
964
        endcase
965
        lfsr_fb = qi[length];
966
        for (i=length-1; i>=1; i=i-1) begin
967
            if (polynom[i])
968
                lfsr_fb = lfsr_fb  ~^ qi[i];
969
        end
970
    end
971
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
972
   always @ (posedge clk or posedge rst)
973
     if (rst)
974
       qi <= {length{1'b0}};
975
     else
976
     if (cke)
977
       qi <= q_next;
978
   always @ (posedge clk or posedge rst)
979
     if (rst)
980
       zq <= 1'b1;
981
     else
982
     if (cke)
983
       zq <= q_next == {length{1'b0}};
984
endmodule
985
//////////////////////////////////////////////////////////////////////
986
////                                                              ////
987
////  Versatile counter                                           ////
988
////                                                              ////
989
////  Description                                                 ////
990
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
991
////  counter                                                     ////
992
////                                                              ////
993
////  To Do:                                                      ////
994
////   - add LFSR with more taps                                  ////
995
////                                                              ////
996
////  Author(s):                                                  ////
997
////      - Michael Unneback, unneback@opencores.org              ////
998
////        ORSoC AB                                              ////
999
////                                                              ////
1000
//////////////////////////////////////////////////////////////////////
1001
////                                                              ////
1002
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1003
////                                                              ////
1004
//// This source file may be used and distributed without         ////
1005
//// restriction provided that this copyright statement is not    ////
1006
//// removed from the file and that any derivative work contains  ////
1007
//// the original copyright notice and the associated disclaimer. ////
1008
////                                                              ////
1009
//// This source file is free software; you can redistribute it   ////
1010
//// and/or modify it under the terms of the GNU Lesser General   ////
1011
//// Public License as published by the Free Software Foundation; ////
1012
//// either version 2.1 of the License, or (at your option) any   ////
1013
//// later version.                                               ////
1014
////                                                              ////
1015
//// This source is distributed in the hope that it will be       ////
1016
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1017
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1018
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1019
//// details.                                                     ////
1020
////                                                              ////
1021
//// You should have received a copy of the GNU Lesser General    ////
1022
//// Public License along with this source; if not, download it   ////
1023
//// from http://www.opencores.org/lgpl.shtml                     ////
1024
////                                                              ////
1025
//////////////////////////////////////////////////////////////////////
1026 6 unneback
// GRAY counter
1027 40 unneback
module vl_cnt_gray_ce_bin (
1028
 cke, q, q_bin, rst, clk);
1029 6 unneback
   parameter length = 4;
1030
   input cke;
1031
   output reg [length:1] q;
1032
   output [length:1] q_bin;
1033
   input rst;
1034
   input clk;
1035
   parameter clear_value = 0;
1036
   parameter set_value = 1;
1037
   parameter wrap_value = 8;
1038
   parameter level1_value = 15;
1039
   reg  [length:1] qi;
1040
   wire [length:1] q_next;
1041
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1042
   always @ (posedge clk or posedge rst)
1043
     if (rst)
1044
       qi <= {length{1'b0}};
1045
     else
1046
     if (cke)
1047
       qi <= q_next;
1048
   always @ (posedge clk or posedge rst)
1049
     if (rst)
1050
       q <= {length{1'b0}};
1051
     else
1052
       if (cke)
1053
         q <= (q_next>>1) ^ q_next;
1054
   assign q_bin = qi;
1055
endmodule
1056
//////////////////////////////////////////////////////////////////////
1057
////                                                              ////
1058
////  Versatile library, counters                                 ////
1059
////                                                              ////
1060
////  Description                                                 ////
1061
////  counters                                                    ////
1062
////                                                              ////
1063
////                                                              ////
1064
////  To Do:                                                      ////
1065
////   - add more counters                                        ////
1066
////                                                              ////
1067
////  Author(s):                                                  ////
1068
////      - Michael Unneback, unneback@opencores.org              ////
1069
////        ORSoC AB                                              ////
1070
////                                                              ////
1071
//////////////////////////////////////////////////////////////////////
1072
////                                                              ////
1073
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1074
////                                                              ////
1075
//// This source file may be used and distributed without         ////
1076
//// restriction provided that this copyright statement is not    ////
1077
//// removed from the file and that any derivative work contains  ////
1078
//// the original copyright notice and the associated disclaimer. ////
1079
////                                                              ////
1080
//// This source file is free software; you can redistribute it   ////
1081
//// and/or modify it under the terms of the GNU Lesser General   ////
1082
//// Public License as published by the Free Software Foundation; ////
1083
//// either version 2.1 of the License, or (at your option) any   ////
1084
//// later version.                                               ////
1085
////                                                              ////
1086
//// This source is distributed in the hope that it will be       ////
1087
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1088
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1089
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1090
//// details.                                                     ////
1091
////                                                              ////
1092
//// You should have received a copy of the GNU Lesser General    ////
1093
//// Public License along with this source; if not, download it   ////
1094
//// from http://www.opencores.org/lgpl.shtml                     ////
1095
////                                                              ////
1096
//////////////////////////////////////////////////////////////////////
1097 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1098 6 unneback
   parameter length = 4;
1099
   output reg [0:length-1] q;
1100
   input rst;
1101
   input clk;
1102
    always @ (posedge clk or posedge rst)
1103
    if (rst)
1104
        q <= {1'b1,{length-1{1'b0}}};
1105
    else
1106
        q <= {q[length-1],q[0:length-2]};
1107
endmodule
1108 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1109 6 unneback
   parameter length = 4;
1110
   input cke;
1111
   output reg [0:length-1] q;
1112
   input rst;
1113
   input clk;
1114
    always @ (posedge clk or posedge rst)
1115
    if (rst)
1116
        q <= {1'b1,{length-1{1'b0}}};
1117
    else
1118
        if (cke)
1119
            q <= {q[length-1],q[0:length-2]};
1120
endmodule
1121 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1122 6 unneback
   parameter length = 4;
1123
   input cke, clear;
1124
   output reg [0:length-1] q;
1125
   input rst;
1126
   input clk;
1127
    always @ (posedge clk or posedge rst)
1128
    if (rst)
1129
        q <= {1'b1,{length-1{1'b0}}};
1130
    else
1131
        if (cke)
1132
            if (clear)
1133
                q <= {1'b1,{length-1{1'b0}}};
1134
            else
1135
                q <= q >> 1;
1136
endmodule
1137 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1138 6 unneback
   parameter length = 4;
1139
   input cke, clear;
1140
   output reg [0:length-1] q;
1141
   input rst;
1142
   input clk;
1143
    always @ (posedge clk or posedge rst)
1144
    if (rst)
1145
        q <= {1'b1,{length-1{1'b0}}};
1146
    else
1147
        if (cke)
1148
            if (clear)
1149
                q <= {1'b1,{length-1{1'b0}}};
1150
            else
1151
            q <= {q[length-1],q[0:length-2]};
1152
endmodule
1153
//////////////////////////////////////////////////////////////////////
1154
////                                                              ////
1155
////  Versatile library, memories                                 ////
1156
////                                                              ////
1157
////  Description                                                 ////
1158
////  memories                                                    ////
1159
////                                                              ////
1160
////                                                              ////
1161
////  To Do:                                                      ////
1162
////   - add more memory types                                    ////
1163
////                                                              ////
1164
////  Author(s):                                                  ////
1165
////      - Michael Unneback, unneback@opencores.org              ////
1166
////        ORSoC AB                                              ////
1167
////                                                              ////
1168
//////////////////////////////////////////////////////////////////////
1169
////                                                              ////
1170
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1171
////                                                              ////
1172
//// This source file may be used and distributed without         ////
1173
//// restriction provided that this copyright statement is not    ////
1174
//// removed from the file and that any derivative work contains  ////
1175
//// the original copyright notice and the associated disclaimer. ////
1176
////                                                              ////
1177
//// This source file is free software; you can redistribute it   ////
1178
//// and/or modify it under the terms of the GNU Lesser General   ////
1179
//// Public License as published by the Free Software Foundation; ////
1180
//// either version 2.1 of the License, or (at your option) any   ////
1181
//// later version.                                               ////
1182
////                                                              ////
1183
//// This source is distributed in the hope that it will be       ////
1184
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1185
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1186
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1187
//// details.                                                     ////
1188
////                                                              ////
1189
//// You should have received a copy of the GNU Lesser General    ////
1190
//// Public License along with this source; if not, download it   ////
1191
//// from http://www.opencores.org/lgpl.shtml                     ////
1192
////                                                              ////
1193
//////////////////////////////////////////////////////////////////////
1194
/// ROM
1195 7 unneback
module vl_rom_init ( adr, q, clk);
1196
   parameter data_width = 32;
1197
   parameter addr_width = 8;
1198 75 unneback
   parameter mem_size = 1<<addr_width;
1199 7 unneback
   input [(addr_width-1):0]       adr;
1200
   output reg [(data_width-1):0] q;
1201
   input                         clk;
1202 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1203 7 unneback
   parameter memory_file = "vl_rom.vmem";
1204
   initial
1205
     begin
1206
        $readmemh(memory_file, rom);
1207
     end
1208
   always @ (posedge clk)
1209
     q <= rom[adr];
1210
endmodule
1211 6 unneback
// Single port RAM
1212
module vl_ram ( d, adr, we, q, clk);
1213
   parameter data_width = 32;
1214
   parameter addr_width = 8;
1215 75 unneback
   parameter mem_size = 1<<addr_width;
1216 6 unneback
   input [(data_width-1):0]      d;
1217
   input [(addr_width-1):0]       adr;
1218
   input                         we;
1219 7 unneback
   output reg [(data_width-1):0] q;
1220 6 unneback
   input                         clk;
1221 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
1222 7 unneback
   parameter init = 0;
1223
   parameter memory_file = "vl_ram.vmem";
1224
   generate if (init) begin : init_mem
1225
   initial
1226
     begin
1227
        $readmemh(memory_file, ram);
1228
     end
1229
   end
1230
   endgenerate
1231 6 unneback
   always @ (posedge clk)
1232
   begin
1233
   if (we)
1234
     ram[adr] <= d;
1235
   q <= ram[adr];
1236
   end
1237
endmodule
1238 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1239 7 unneback
   parameter data_width = 32;
1240 72 unneback
   parameter addr_width = 6;
1241 75 unneback
   parameter mem_size = 1<<addr_width;
1242 7 unneback
   input [(data_width-1):0]      d;
1243
   input [(addr_width-1):0]       adr;
1244 73 unneback
   input [(data_width/8)-1:0]    be;
1245 7 unneback
   input                         we;
1246
   output reg [(data_width-1):0] q;
1247
   input                         clk;
1248 65 unneback
`ifdef SYSTEMVERILOG
1249 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
1250 65 unneback
`else
1251 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1252
    wire [data_width/8-1:0] cke;
1253 65 unneback
`endif
1254 60 unneback
   parameter memory_init = 0;
1255 7 unneback
   parameter memory_file = "vl_ram.vmem";
1256 60 unneback
   generate if (memory_init) begin : init_mem
1257 7 unneback
   initial
1258
     begin
1259
        $readmemh(memory_file, ram);
1260
     end
1261
   end
1262
   endgenerate
1263 60 unneback
`ifdef SYSTEMVERILOG
1264
// use a multi-dimensional packed array
1265
//to model individual bytes within the word
1266
always_ff@(posedge clk)
1267
begin
1268
    if(we) begin // note: we should have a for statement to support any bus width
1269 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1270
        if(be[2]) ram[adr][2] <= d[23:16];
1271
        if(be[1]) ram[adr][1] <= d[15:8];
1272
        if(be[0]) ram[adr][0] <= d[7:0];
1273 60 unneback
    end
1274 90 unneback
        q <= ram[adr];
1275 60 unneback
end
1276
`else
1277 85 unneback
assign cke = {data_width/8{we}} & be;
1278 7 unneback
   genvar i;
1279 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1280 7 unneback
      always @ (posedge clk)
1281 85 unneback
      if (cke[i])
1282 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1283
   end
1284
   endgenerate
1285
   always @ (posedge clk)
1286
      q <= ram[adr];
1287 60 unneback
`endif
1288 93 unneback
`ifdef verilator
1289 85 unneback
   // Function to access RAM (for use by Verilator).
1290
   function [31:0] get_mem;
1291
      // verilator public
1292 90 unneback
      input [addr_width-1:0]             addr;
1293 85 unneback
      get_mem = ram[addr];
1294
   endfunction // get_mem
1295
   // Function to write RAM (for use by Verilator).
1296
   function set_mem;
1297
      // verilator public
1298 90 unneback
      input [addr_width-1:0]             addr;
1299
      input [data_width-1:0]             data;
1300 85 unneback
      ram[addr] = data;
1301
   endfunction // set_mem
1302 93 unneback
`endif
1303 7 unneback
endmodule
1304 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
1305 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1306 6 unneback
   parameter data_width = 32;
1307
   parameter addr_width = 8;
1308 75 unneback
   parameter mem_size = 1<<addr_width;
1309 6 unneback
   input [(data_width-1):0]      d_a;
1310
   input [(addr_width-1):0]       adr_a;
1311
   input [(addr_width-1):0]       adr_b;
1312
   input                         we_a;
1313
   output [(data_width-1):0]      q_b;
1314
   input                         clk_a, clk_b;
1315
   reg [(addr_width-1):0]         adr_b_reg;
1316 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1317 7 unneback
   parameter init = 0;
1318
   parameter memory_file = "vl_ram.vmem";
1319
   generate if (init) begin : init_mem
1320
   initial
1321
     begin
1322
        $readmemh(memory_file, ram);
1323
     end
1324
   end
1325
   endgenerate
1326 6 unneback
   always @ (posedge clk_a)
1327
   if (we_a)
1328
     ram[adr_a] <= d_a;
1329
   always @ (posedge clk_b)
1330
   adr_b_reg <= adr_b;
1331
   assign q_b = ram[adr_b_reg];
1332
endmodule
1333 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1334 6 unneback
   parameter data_width = 32;
1335
   parameter addr_width = 8;
1336 75 unneback
   parameter mem_size = 1<<addr_width;
1337 6 unneback
   input [(data_width-1):0]      d_a;
1338
   input [(addr_width-1):0]       adr_a;
1339
   input [(addr_width-1):0]       adr_b;
1340
   input                         we_a;
1341
   output [(data_width-1):0]      q_b;
1342
   output reg [(data_width-1):0] q_a;
1343
   input                         clk_a, clk_b;
1344
   reg [(data_width-1):0]         q_b;
1345 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1346 7 unneback
   parameter init = 0;
1347
   parameter memory_file = "vl_ram.vmem";
1348
   generate if (init) begin : init_mem
1349
   initial
1350
     begin
1351
        $readmemh(memory_file, ram);
1352
     end
1353
   end
1354
   endgenerate
1355 6 unneback
   always @ (posedge clk_a)
1356
     begin
1357
        q_a <= ram[adr_a];
1358
        if (we_a)
1359
             ram[adr_a] <= d_a;
1360
     end
1361
   always @ (posedge clk_b)
1362
          q_b <= ram[adr_b];
1363
endmodule
1364 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1365 6 unneback
   parameter data_width = 32;
1366
   parameter addr_width = 8;
1367 75 unneback
   parameter mem_size = 1<<addr_width;
1368 6 unneback
   input [(data_width-1):0]      d_a;
1369
   input [(addr_width-1):0]       adr_a;
1370
   input [(addr_width-1):0]       adr_b;
1371
   input                         we_a;
1372
   output [(data_width-1):0]      q_b;
1373
   input [(data_width-1):0]       d_b;
1374
   output reg [(data_width-1):0] q_a;
1375
   input                         we_b;
1376
   input                         clk_a, clk_b;
1377
   reg [(data_width-1):0]         q_b;
1378 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1379 7 unneback
   parameter init = 0;
1380
   parameter memory_file = "vl_ram.vmem";
1381
   generate if (init) begin : init_mem
1382
   initial
1383
     begin
1384
        $readmemh(memory_file, ram);
1385
     end
1386
   end
1387
   endgenerate
1388 6 unneback
   always @ (posedge clk_a)
1389
     begin
1390
        q_a <= ram[adr_a];
1391
        if (we_a)
1392
             ram[adr_a] <= d_a;
1393
     end
1394
   always @ (posedge clk_b)
1395
     begin
1396
        q_b <= ram[adr_b];
1397
        if (we_b)
1398
          ram[adr_b] <= d_b;
1399
     end
1400
endmodule
1401 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
1402 75 unneback
   parameter a_data_width = 32;
1403
   parameter a_addr_width = 8;
1404 92 unneback
   parameter b_data_width = a_data_width;
1405 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1406
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
1407 75 unneback
   input [(a_data_width-1):0]      d_a;
1408 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1409
   input [(a_data_width/8-1):0]    be_a;
1410
   input                           we_a;
1411 75 unneback
   output reg [(a_data_width-1):0] q_a;
1412 91 unneback
   input [(b_data_width-1):0]       d_b;
1413
   input [(b_addr_width-1):0]       adr_b;
1414 92 unneback
   input [(b_data_width/8-1):0]    be_b;
1415
   input                           we_b;
1416
   output reg [(b_data_width-1):0]          q_b;
1417 91 unneback
   input                           clk_a, clk_b;
1418
`ifdef SYSTEMVERILOG
1419
// use a multi-dimensional packed array
1420
//to model individual bytes within the word
1421 75 unneback
generate
1422 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1423
   logic [3:0][7:0] ram [0:mem_size-1];
1424
    always_ff@(posedge clk_a)
1425
    begin
1426
        if(we_a) begin
1427
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1428
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1429
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1430
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1431
        end
1432
    end
1433 92 unneback
    always@(posedge clk_a)
1434
        q_a = ram[adr_a];
1435 91 unneback
    always_ff@(posedge clk_b)
1436 92 unneback
    begin
1437
        if(we_b) begin
1438
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1439
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1440
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1441
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1442
        end
1443
    end
1444
    always@(posedge clk_b)
1445
        q_b = ram[adr_b];
1446 75 unneback
end
1447
endgenerate
1448 91 unneback
`else
1449 92 unneback
    // This modules requires SystemVerilog
1450 91 unneback
`endif
1451 75 unneback
endmodule
1452 6 unneback
// FIFO
1453 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1454
    d, wr, fifo_full,
1455
    q, rd, fifo_empty,
1456
    fill_level,
1457
    clk, rst
1458
    );
1459
parameter data_width = 18;
1460
parameter addr_width = 4;
1461
// write side
1462
input  [data_width-1:0] d;
1463
input                   wr;
1464
output                  fifo_full;
1465
// read side
1466
output [data_width-1:0] q;
1467
input                   rd;
1468
output                  fifo_empty;
1469
// common
1470
output [addr_width:0]   fill_level;
1471
input rst, clk;
1472
wire [addr_width:1] wadr, radr;
1473
vl_cnt_bin_ce
1474
    # ( .length(addr_width))
1475
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1476
vl_cnt_bin_ce
1477
    # (.length(addr_width))
1478
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1479
vl_dpram_1r1w
1480
    # (.data_width(data_width), .addr_width(addr_width))
1481
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1482 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1483 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1484 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1485
endmodule
1486 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1487
// RAM is supposed to be larger than the two FIFOs
1488
// LFSR counters used adr pointers
1489
module vl_fifo_2r2w_sync_simplex (
1490
    // a side
1491
    a_d, a_wr, a_fifo_full,
1492
    a_q, a_rd, a_fifo_empty,
1493
    a_fill_level,
1494
    // b side
1495
    b_d, b_wr, b_fifo_full,
1496
    b_q, b_rd, b_fifo_empty,
1497
    b_fill_level,
1498
    // common
1499
    clk, rst
1500
    );
1501
parameter data_width = 8;
1502
parameter addr_width = 5;
1503
parameter fifo_full_level = (1<<addr_width)-1;
1504
// a side
1505
input  [data_width-1:0] a_d;
1506
input                   a_wr;
1507
output                  a_fifo_full;
1508
output [data_width-1:0] a_q;
1509
input                   a_rd;
1510
output                  a_fifo_empty;
1511
output [addr_width-1:0] a_fill_level;
1512
// b side
1513
input  [data_width-1:0] b_d;
1514
input                   b_wr;
1515
output                  b_fifo_full;
1516
output [data_width-1:0] b_q;
1517
input                   b_rd;
1518
output                  b_fifo_empty;
1519
output [addr_width-1:0] b_fill_level;
1520
input                   clk;
1521
input                   rst;
1522
// adr_gen
1523
wire [addr_width:1] a_wadr, a_radr;
1524
wire [addr_width:1] b_wadr, b_radr;
1525
// dpram
1526
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1527
vl_cnt_lfsr_ce
1528
    # ( .length(addr_width))
1529
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1530
vl_cnt_lfsr_ce
1531
    # (.length(addr_width))
1532
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1533
vl_cnt_lfsr_ce
1534
    # ( .length(addr_width))
1535
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1536
vl_cnt_lfsr_ce
1537
    # (.length(addr_width))
1538
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1539
// mux read or write adr to DPRAM
1540
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1541
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1542
vl_dpram_2r2w
1543
    # (.data_width(data_width), .addr_width(addr_width+1))
1544
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1545
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1546
vl_cnt_bin_ce_rew_zq_l1
1547 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1548 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1549
vl_cnt_bin_ce_rew_zq_l1
1550 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1551 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1552
endmodule
1553 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1554 11 unneback
   parameter addr_width = 4;
1555
   parameter N = addr_width-1;
1556 6 unneback
   parameter Q1 = 2'b00;
1557
   parameter Q2 = 2'b01;
1558
   parameter Q3 = 2'b11;
1559
   parameter Q4 = 2'b10;
1560
   parameter going_empty = 1'b0;
1561
   parameter going_full  = 1'b1;
1562
   input [N:0]  wptr, rptr;
1563 14 unneback
   output       fifo_empty;
1564 6 unneback
   output       fifo_full;
1565
   input        wclk, rclk, rst;
1566
   wire direction;
1567
   reg  direction_set, direction_clr;
1568
   wire async_empty, async_full;
1569
   wire fifo_full2;
1570 14 unneback
   wire fifo_empty2;
1571 6 unneback
   // direction_set
1572
   always @ (wptr[N:N-1] or rptr[N:N-1])
1573
     case ({wptr[N:N-1],rptr[N:N-1]})
1574
       {Q1,Q2} : direction_set <= 1'b1;
1575
       {Q2,Q3} : direction_set <= 1'b1;
1576
       {Q3,Q4} : direction_set <= 1'b1;
1577
       {Q4,Q1} : direction_set <= 1'b1;
1578
       default : direction_set <= 1'b0;
1579
     endcase
1580
   // direction_clear
1581
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1582
     if (rst)
1583
       direction_clr <= 1'b1;
1584
     else
1585
       case ({wptr[N:N-1],rptr[N:N-1]})
1586
         {Q2,Q1} : direction_clr <= 1'b1;
1587
         {Q3,Q2} : direction_clr <= 1'b1;
1588
         {Q4,Q3} : direction_clr <= 1'b1;
1589
         {Q1,Q4} : direction_clr <= 1'b1;
1590
         default : direction_clr <= 1'b0;
1591
       endcase
1592 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1593 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1594
   assign async_full  = (wptr == rptr) && (direction==going_full);
1595 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1596
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1597 6 unneback
/*
1598
   always @ (posedge wclk or posedge rst or posedge async_full)
1599
     if (rst)
1600
       {fifo_full, fifo_full2} <= 2'b00;
1601
     else if (async_full)
1602
       {fifo_full, fifo_full2} <= 2'b11;
1603
     else
1604
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1605
*/
1606 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1607 6 unneback
     if (async_empty)
1608
       {fifo_empty, fifo_empty2} <= 2'b11;
1609
     else
1610 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1611 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1612
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1613 27 unneback
endmodule // async_compb
1614 6 unneback
module vl_fifo_1r1w_async (
1615
    d, wr, fifo_full, wr_clk, wr_rst,
1616
    q, rd, fifo_empty, rd_clk, rd_rst
1617
    );
1618
parameter data_width = 18;
1619
parameter addr_width = 4;
1620
// write side
1621
input  [data_width-1:0] d;
1622
input                   wr;
1623
output                  fifo_full;
1624
input                   wr_clk;
1625
input                   wr_rst;
1626
// read side
1627
output [data_width-1:0] q;
1628
input                   rd;
1629
output                  fifo_empty;
1630
input                   rd_clk;
1631
input                   rd_rst;
1632
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1633 18 unneback
vl_cnt_gray_ce_bin
1634 6 unneback
    # ( .length(addr_width))
1635
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1636 18 unneback
vl_cnt_gray_ce_bin
1637 6 unneback
    # (.length(addr_width))
1638 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1639 7 unneback
vl_dpram_1r1w
1640 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1641
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1642
vl_fifo_cmp_async
1643
    # (.addr_width(addr_width))
1644
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1645
endmodule
1646 8 unneback
module vl_fifo_2r2w_async (
1647 6 unneback
    // a side
1648
    a_d, a_wr, a_fifo_full,
1649
    a_q, a_rd, a_fifo_empty,
1650
    a_clk, a_rst,
1651
    // b side
1652
    b_d, b_wr, b_fifo_full,
1653
    b_q, b_rd, b_fifo_empty,
1654
    b_clk, b_rst
1655
    );
1656
parameter data_width = 18;
1657
parameter addr_width = 4;
1658
// a side
1659
input  [data_width-1:0] a_d;
1660
input                   a_wr;
1661
output                  a_fifo_full;
1662
output [data_width-1:0] a_q;
1663
input                   a_rd;
1664
output                  a_fifo_empty;
1665
input                   a_clk;
1666
input                   a_rst;
1667
// b side
1668
input  [data_width-1:0] b_d;
1669
input                   b_wr;
1670
output                  b_fifo_full;
1671
output [data_width-1:0] b_q;
1672
input                   b_rd;
1673
output                  b_fifo_empty;
1674
input                   b_clk;
1675
input                   b_rst;
1676
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1677
vl_fifo_1r1w_async_a (
1678
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1679
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1680
    );
1681
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1682
vl_fifo_1r1w_async_b (
1683
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1684
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1685
    );
1686
endmodule
1687 8 unneback
module vl_fifo_2r2w_async_simplex (
1688 6 unneback
    // a side
1689
    a_d, a_wr, a_fifo_full,
1690
    a_q, a_rd, a_fifo_empty,
1691
    a_clk, a_rst,
1692
    // b side
1693
    b_d, b_wr, b_fifo_full,
1694
    b_q, b_rd, b_fifo_empty,
1695
    b_clk, b_rst
1696
    );
1697
parameter data_width = 18;
1698
parameter addr_width = 4;
1699
// a side
1700
input  [data_width-1:0] a_d;
1701
input                   a_wr;
1702
output                  a_fifo_full;
1703
output [data_width-1:0] a_q;
1704
input                   a_rd;
1705
output                  a_fifo_empty;
1706
input                   a_clk;
1707
input                   a_rst;
1708
// b side
1709
input  [data_width-1:0] b_d;
1710
input                   b_wr;
1711
output                  b_fifo_full;
1712
output [data_width-1:0] b_q;
1713
input                   b_rd;
1714
output                  b_fifo_empty;
1715
input                   b_clk;
1716
input                   b_rst;
1717
// adr_gen
1718
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1719
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1720
// dpram
1721
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1722 18 unneback
vl_cnt_gray_ce_bin
1723 6 unneback
    # ( .length(addr_width))
1724
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1725 18 unneback
vl_cnt_gray_ce_bin
1726 6 unneback
    # (.length(addr_width))
1727
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1728 18 unneback
vl_cnt_gray_ce_bin
1729 6 unneback
    # ( .length(addr_width))
1730
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1731 18 unneback
vl_cnt_gray_ce_bin
1732 6 unneback
    # (.length(addr_width))
1733
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1734
// mux read or write adr to DPRAM
1735
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1736
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1737 11 unneback
vl_dpram_2r2w
1738 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1739
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1740
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1741 11 unneback
vl_fifo_cmp_async
1742 6 unneback
    # (.addr_width(addr_width))
1743
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1744 11 unneback
vl_fifo_cmp_async
1745 6 unneback
    # (.addr_width(addr_width))
1746
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1747
endmodule
1748 48 unneback
module vl_reg_file (
1749
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1750
);
1751
parameter data_width = 32;
1752
parameter addr_width = 5;
1753
input [addr_width-1:0] a1, a2, a3;
1754
input [data_width-1:0] wd3;
1755
input we3;
1756
output [data_width-1:0] rd1, rd2;
1757
input clk;
1758
reg [data_width-1:0] wd3_reg;
1759
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
1760
reg we3_reg;
1761
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1762
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1763
always @ (posedge clk or posedge rst)
1764
if (rst)
1765
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
1766
else
1767
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
1768
    always @ (negedge clk)
1769
    if (we3_reg)
1770
        ram1[a3_reg] <= wd3;
1771
    always @ (posedge clk)
1772
        a1_reg <= a1;
1773
    assign rd1 = ram1[a1_reg];
1774
    always @ (negedge clk)
1775
    if (we3_reg)
1776
        ram2[a3_reg] <= wd3;
1777
    always @ (posedge clk)
1778
        a2_reg <= a2;
1779
    assign rd2 = ram2[a2_reg];
1780
endmodule
1781 12 unneback
//////////////////////////////////////////////////////////////////////
1782
////                                                              ////
1783
////  Versatile library, wishbone stuff                           ////
1784
////                                                              ////
1785
////  Description                                                 ////
1786
////  Wishbone compliant modules                                  ////
1787
////                                                              ////
1788
////                                                              ////
1789
////  To Do:                                                      ////
1790
////   -                                                          ////
1791
////                                                              ////
1792
////  Author(s):                                                  ////
1793
////      - Michael Unneback, unneback@opencores.org              ////
1794
////        ORSoC AB                                              ////
1795
////                                                              ////
1796
//////////////////////////////////////////////////////////////////////
1797
////                                                              ////
1798
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1799
////                                                              ////
1800
//// This source file may be used and distributed without         ////
1801
//// restriction provided that this copyright statement is not    ////
1802
//// removed from the file and that any derivative work contains  ////
1803
//// the original copyright notice and the associated disclaimer. ////
1804
////                                                              ////
1805
//// This source file is free software; you can redistribute it   ////
1806
//// and/or modify it under the terms of the GNU Lesser General   ////
1807
//// Public License as published by the Free Software Foundation; ////
1808
//// either version 2.1 of the License, or (at your option) any   ////
1809
//// later version.                                               ////
1810
////                                                              ////
1811
//// This source is distributed in the hope that it will be       ////
1812
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1813
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1814
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1815
//// details.                                                     ////
1816
////                                                              ////
1817
//// You should have received a copy of the GNU Lesser General    ////
1818
//// Public License along with this source; if not, download it   ////
1819
//// from http://www.opencores.org/lgpl.shtml                     ////
1820
////                                                              ////
1821
//////////////////////////////////////////////////////////////////////
1822
// async wb3 - wb3 bridge
1823
`timescale 1ns/1ns
1824 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
1825 83 unneback
parameter adr_width = 10;
1826
parameter max_burst_width = 4;
1827 85 unneback
input cyc_i, stb_i, we_i;
1828 83 unneback
input [2:0] cti_i;
1829
input [1:0] bte_i;
1830
input [adr_width-1:0] adr_i;
1831
output [adr_width-1:0] adr_o;
1832
output ack_o;
1833
input clk, rst;
1834
reg [adr_width-1:0] adr;
1835 90 unneback
wire [max_burst_width-1:0] to_adr;
1836 91 unneback
reg [max_burst_width-1:0] last_adr;
1837 92 unneback
reg last_cycle;
1838
localparam idle_or_eoc = 1'b0;
1839
localparam cyc_or_ws   = 1'b1;
1840 91 unneback
always @ (posedge clk or posedge rst)
1841
if (rst)
1842
    last_adr <= {max_burst_width{1'b0}};
1843
else
1844
    if (stb_i)
1845 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
1846 83 unneback
generate
1847
if (max_burst_width==0) begin : inst_0
1848
    reg ack_o;
1849
    assign adr_o = adr_i;
1850
    always @ (posedge clk or posedge rst)
1851
    if (rst)
1852
        ack_o <= 1'b0;
1853
    else
1854
        ack_o <= cyc_i & stb_i & !ack_o;
1855
end else begin
1856
    always @ (posedge clk or posedge rst)
1857
    if (rst)
1858 92 unneback
        last_cycle <= idle_or_eoc;
1859 83 unneback
    else
1860 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
1861
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
1862
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
1863
                      cyc_or_ws; // cyc
1864
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
1865 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
1866 91 unneback
                                        (!stb_i) ? last_adr :
1867 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
1868 85 unneback
                                        adr[max_burst_width-1:0];
1869 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
1870 83 unneback
end
1871
endgenerate
1872
generate
1873
if (max_burst_width==2) begin : inst_2
1874
    always @ (posedge clk or posedge rst)
1875
    if (rst)
1876
        adr <= 2'h0;
1877
    else
1878
        if (cyc_i & stb_i)
1879
            adr[1:0] <= to_adr[1:0] + 2'd1;
1880
        else
1881
            adr <= to_adr[1:0];
1882
end
1883
endgenerate
1884
generate
1885
if (max_burst_width==3) begin : inst_3
1886
    always @ (posedge clk or posedge rst)
1887
    if (rst)
1888
        adr <= 3'h0;
1889
    else
1890
        if (cyc_i & stb_i)
1891
            case (bte_i)
1892
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
1893
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
1894
            endcase
1895
        else
1896
            adr <= to_adr[2:0];
1897
end
1898
endgenerate
1899
generate
1900
if (max_burst_width==4) begin : inst_4
1901
    always @ (posedge clk or posedge rst)
1902
    if (rst)
1903
        adr <= 4'h0;
1904
    else
1905 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
1906 83 unneback
            case (bte_i)
1907
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
1908
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
1909
            default: adr[3:0] <= to_adr + 4'd1;
1910
            endcase
1911
        else
1912
            adr <= to_adr[3:0];
1913
end
1914
endgenerate
1915
generate
1916
if (adr_width > max_burst_width) begin : pass_through
1917
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
1918
end
1919
endgenerate
1920
endmodule
1921
// async wb3 - wb3 bridge
1922
`timescale 1ns/1ns
1923 18 unneback
module vl_wb3wb3_bridge (
1924 12 unneback
        // wishbone slave side
1925
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1926
        // wishbone master side
1927
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1928
input [31:0] wbs_dat_i;
1929
input [31:2] wbs_adr_i;
1930
input [3:0]  wbs_sel_i;
1931
input [1:0]  wbs_bte_i;
1932
input [2:0]  wbs_cti_i;
1933
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1934
output [31:0] wbs_dat_o;
1935 14 unneback
output wbs_ack_o;
1936 12 unneback
input wbs_clk, wbs_rst;
1937
output [31:0] wbm_dat_o;
1938
output reg [31:2] wbm_adr_o;
1939
output [3:0]  wbm_sel_o;
1940
output reg [1:0]  wbm_bte_o;
1941
output reg [2:0]  wbm_cti_o;
1942 14 unneback
output reg wbm_we_o;
1943
output wbm_cyc_o;
1944 12 unneback
output wbm_stb_o;
1945
input [31:0]  wbm_dat_i;
1946
input wbm_ack_i;
1947
input wbm_clk, wbm_rst;
1948
parameter addr_width = 4;
1949
// bte
1950
parameter linear       = 2'b00;
1951
parameter wrap4        = 2'b01;
1952
parameter wrap8        = 2'b10;
1953
parameter wrap16       = 2'b11;
1954
// cti
1955
parameter classic      = 3'b000;
1956
parameter incburst     = 3'b010;
1957
parameter endofburst   = 3'b111;
1958
parameter wbs_adr  = 1'b0;
1959
parameter wbs_data = 1'b1;
1960 33 unneback
parameter wbm_adr0      = 2'b00;
1961
parameter wbm_adr1      = 2'b01;
1962
parameter wbm_data      = 2'b10;
1963
parameter wbm_data_wait = 2'b11;
1964 12 unneback
reg [1:0] wbs_bte_reg;
1965
reg wbs;
1966
wire wbs_eoc_alert, wbm_eoc_alert;
1967
reg wbs_eoc, wbm_eoc;
1968
reg [1:0] wbm;
1969 14 unneback
wire [1:16] wbs_count, wbm_count;
1970 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1971
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1972
reg a_rd_reg;
1973
wire b_rd_adr, b_rd_data;
1974 14 unneback
wire b_rd_data_reg;
1975
wire [35:0] temp;
1976 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1977
always @ (posedge wbs_clk or posedge wbs_rst)
1978
if (wbs_rst)
1979
        wbs_eoc <= 1'b0;
1980
else
1981
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1982 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
1983 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
1984
                wbs_eoc <= 1'b1;
1985 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1986 12 unneback
    cnt0 (
1987
        .cke(wbs_ack_o),
1988
        .clear(wbs_eoc),
1989
        .q(wbs_count),
1990
        .rst(wbs_rst),
1991
        .clk(wbs_clk));
1992
always @ (posedge wbs_clk or posedge wbs_rst)
1993
if (wbs_rst)
1994
        wbs <= wbs_adr;
1995
else
1996 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
1997 12 unneback
                wbs <= wbs_data;
1998
        else if (wbs_eoc & wbs_ack_o)
1999
                wbs <= wbs_adr;
2000
// wbs FIFO
2001 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
2002
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
2003 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2004
              1'b0;
2005
assign a_rd = !a_fifo_empty;
2006
always @ (posedge wbs_clk or posedge wbs_rst)
2007
if (wbs_rst)
2008
        a_rd_reg <= 1'b0;
2009
else
2010
        a_rd_reg <= a_rd;
2011
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2012
assign wbs_dat_o = a_q[35:4];
2013
always @ (posedge wbs_clk or posedge wbs_rst)
2014
if (wbs_rst)
2015 13 unneback
        wbs_bte_reg <= 2'b00;
2016 12 unneback
else
2017 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2018 12 unneback
// wbm FIFO
2019
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2020
always @ (posedge wbm_clk or posedge wbm_rst)
2021
if (wbm_rst)
2022
        wbm_eoc <= 1'b0;
2023
else
2024
        if (wbm==wbm_adr0 & !b_fifo_empty)
2025
                wbm_eoc <= b_q[4:3] == linear;
2026
        else if (wbm_eoc_alert & wbm_ack_i)
2027
                wbm_eoc <= 1'b1;
2028
always @ (posedge wbm_clk or posedge wbm_rst)
2029
if (wbm_rst)
2030
        wbm <= wbm_adr0;
2031
else
2032 33 unneback
/*
2033 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2034
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2035
        (wbm==wbm_adr1 & !wbm_we_o) |
2036
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2037
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2038 33 unneback
*/
2039
    case (wbm)
2040
    wbm_adr0:
2041
        if (!b_fifo_empty)
2042
            wbm <= wbm_adr1;
2043
    wbm_adr1:
2044
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
2045
            wbm <= wbm_data;
2046
    wbm_data:
2047
        if (wbm_ack_i & wbm_eoc)
2048
            wbm <= wbm_adr0;
2049
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
2050
            wbm <= wbm_data_wait;
2051
    wbm_data_wait:
2052
        if (!b_fifo_empty)
2053
            wbm <= wbm_data;
2054
    endcase
2055 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
2056
assign b_wr = !wbm_we_o & wbm_ack_i;
2057
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2058
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2059
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2060 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
2061 12 unneback
                   1'b0;
2062
assign b_rd = b_rd_adr | b_rd_data;
2063 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2064
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2065 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2066 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2067 12 unneback
    cnt1 (
2068
        .cke(wbm_ack_i),
2069
        .clear(wbm_eoc),
2070
        .q(wbm_count),
2071
        .rst(wbm_rst),
2072
        .clk(wbm_clk));
2073 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
2074
assign wbm_stb_o = (wbm==wbm_data);
2075 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
2076
if (wbm_rst)
2077
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2078
else begin
2079
        if (wbm==wbm_adr0 & !b_fifo_empty)
2080
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2081
        else if (wbm_eoc_alert & wbm_ack_i)
2082
                wbm_cti_o <= endofburst;
2083
end
2084
//async_fifo_dw_simplex_top
2085
vl_fifo_2r2w_async_simplex
2086
# ( .data_width(36), .addr_width(addr_width))
2087
fifo (
2088
    // a side
2089
    .a_d(a_d),
2090
    .a_wr(a_wr),
2091
    .a_fifo_full(a_fifo_full),
2092
    .a_q(a_q),
2093
    .a_rd(a_rd),
2094
    .a_fifo_empty(a_fifo_empty),
2095
    .a_clk(wbs_clk),
2096
    .a_rst(wbs_rst),
2097
    // b side
2098
    .b_d(b_d),
2099
    .b_wr(b_wr),
2100
    .b_fifo_full(b_fifo_full),
2101
    .b_q(b_q),
2102
    .b_rd(b_rd),
2103
    .b_fifo_empty(b_fifo_empty),
2104
    .b_clk(wbm_clk),
2105
    .b_rst(wbm_rst)
2106
    );
2107
endmodule
2108 75 unneback
module vl_wb3avalon_bridge (
2109
        // wishbone slave side
2110
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2111 77 unneback
        // avalon master side
2112 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
2113 85 unneback
parameter linewrapburst = 1'b0;
2114 75 unneback
input [31:0] wbs_dat_i;
2115
input [31:2] wbs_adr_i;
2116
input [3:0]  wbs_sel_i;
2117
input [1:0]  wbs_bte_i;
2118
input [2:0]  wbs_cti_i;
2119 83 unneback
input wbs_we_i;
2120
input wbs_cyc_i;
2121
input wbs_stb_i;
2122 75 unneback
output [31:0] wbs_dat_o;
2123
output wbs_ack_o;
2124
input wbs_clk, wbs_rst;
2125
input [31:0] readdata;
2126
output [31:0] writedata;
2127
output [31:2] address;
2128
output [3:0]  be;
2129
output write;
2130 81 unneback
output read;
2131 75 unneback
output beginbursttransfer;
2132
output [3:0] burstcount;
2133
input readdatavalid;
2134
input waitrequest;
2135
input clk;
2136
input rst;
2137
wire [1:0] wbm_bte_o;
2138
wire [2:0] wbm_cti_o;
2139
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
2140
reg last_cyc;
2141 79 unneback
reg [3:0] counter;
2142 82 unneback
reg read_busy;
2143 75 unneback
always @ (posedge clk or posedge rst)
2144
if (rst)
2145
    last_cyc <= 1'b0;
2146
else
2147
    last_cyc <= wbm_cyc_o;
2148 79 unneback
always @ (posedge clk or posedge rst)
2149
if (rst)
2150 82 unneback
    read_busy <= 1'b0;
2151 79 unneback
else
2152 82 unneback
    if (read & !waitrequest)
2153
        read_busy <= 1'b1;
2154
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
2155
        read_busy <= 1'b0;
2156
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
2157 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
2158
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
2159
                    (wbm_bte_o==2'b10) ? 4'd8 :
2160 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
2161
                    4'd1;
2162 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
2163 79 unneback
always @ (posedge clk or posedge rst)
2164
if (rst) begin
2165
    counter <= 4'd0;
2166
end else
2167 80 unneback
    if (wbm_we_o) begin
2168
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
2169 85 unneback
            counter <= burstcount -4'd1;
2170 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
2171
            counter <= burstcount;
2172
        end else if (!waitrequest & wbm_stb_o) begin
2173
            counter <= counter - 4'd1;
2174
        end
2175 82 unneback
    end
2176 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
2177 77 unneback
vl_wb3wb3_bridge wbwb3inst (
2178 75 unneback
    // wishbone slave side
2179
    .wbs_dat_i(wbs_dat_i),
2180
    .wbs_adr_i(wbs_adr_i),
2181
    .wbs_sel_i(wbs_sel_i),
2182
    .wbs_bte_i(wbs_bte_i),
2183
    .wbs_cti_i(wbs_cti_i),
2184
    .wbs_we_i(wbs_we_i),
2185
    .wbs_cyc_i(wbs_cyc_i),
2186
    .wbs_stb_i(wbs_stb_i),
2187
    .wbs_dat_o(wbs_dat_o),
2188
    .wbs_ack_o(wbs_ack_o),
2189
    .wbs_clk(wbs_clk),
2190
    .wbs_rst(wbs_rst),
2191
    // wishbone master side
2192
    .wbm_dat_o(writedata),
2193 78 unneback
    .wbm_adr_o(address),
2194 75 unneback
    .wbm_sel_o(be),
2195
    .wbm_bte_o(wbm_bte_o),
2196
    .wbm_cti_o(wbm_cti_o),
2197
    .wbm_we_o(wbm_we_o),
2198
    .wbm_cyc_o(wbm_cyc_o),
2199
    .wbm_stb_o(wbm_stb_o),
2200
    .wbm_dat_i(readdata),
2201
    .wbm_ack_i(wbm_ack_i),
2202
    .wbm_clk(clk),
2203
    .wbm_rst(rst));
2204
endmodule
2205 39 unneback
module vl_wb3_arbiter_type1 (
2206
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
2207
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
2208
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
2209
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
2210
    wb_clk, wb_rst
2211
);
2212
parameter nr_of_ports = 3;
2213
parameter adr_size = 26;
2214
parameter adr_lo   = 2;
2215
parameter dat_size = 32;
2216
parameter sel_size = dat_size/8;
2217
localparam aw = (adr_size - adr_lo) * nr_of_ports;
2218
localparam dw = dat_size * nr_of_ports;
2219
localparam sw = sel_size * nr_of_ports;
2220
localparam cw = 3 * nr_of_ports;
2221
localparam bw = 2 * nr_of_ports;
2222
input  [dw-1:0] wbm_dat_o;
2223
input  [aw-1:0] wbm_adr_o;
2224
input  [sw-1:0] wbm_sel_o;
2225
input  [cw-1:0] wbm_cti_o;
2226
input  [bw-1:0] wbm_bte_o;
2227
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
2228
output [dw-1:0] wbm_dat_i;
2229
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
2230
output [dat_size-1:0] wbs_dat_i;
2231
output [adr_size-1:adr_lo] wbs_adr_i;
2232
output [sel_size-1:0] wbs_sel_i;
2233
output [2:0] wbs_cti_i;
2234
output [1:0] wbs_bte_i;
2235
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
2236
input  [dat_size-1:0] wbs_dat_o;
2237
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
2238
input wb_clk, wb_rst;
2239 44 unneback
reg  [nr_of_ports-1:0] select;
2240 39 unneback
wire [nr_of_ports-1:0] state;
2241
wire [nr_of_ports-1:0] eoc; // end-of-cycle
2242
wire [nr_of_ports-1:0] sel;
2243
wire idle;
2244
genvar i;
2245
assign idle = !(|state);
2246
generate
2247
if (nr_of_ports == 2) begin
2248
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
2249
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2250 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2251
    always @ (idle or wbm_cyc_o)
2252
    if (idle)
2253
        casex (wbm_cyc_o)
2254
        2'b1x : select = 2'b10;
2255
        2'b01 : select = 2'b01;
2256
        default : select = {nr_of_ports{1'b0}};
2257
        endcase
2258
    else
2259
        select = {nr_of_ports{1'b0}};
2260 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2261
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2262
end
2263
endgenerate
2264
generate
2265
if (nr_of_ports == 3) begin
2266
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2267
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2268 44 unneback
    always @ (idle or wbm_cyc_o)
2269
    if (idle)
2270
        casex (wbm_cyc_o)
2271
        3'b1xx : select = 3'b100;
2272
        3'b01x : select = 3'b010;
2273
        3'b001 : select = 3'b001;
2274
        default : select = {nr_of_ports{1'b0}};
2275
        endcase
2276
    else
2277
        select = {nr_of_ports{1'b0}};
2278
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2279 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2280
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2281
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2282
end
2283
endgenerate
2284
generate
2285 44 unneback
if (nr_of_ports == 4) begin
2286
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2287
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2288
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2289
    always @ (idle or wbm_cyc_o)
2290
    if (idle)
2291
        casex (wbm_cyc_o)
2292
        4'b1xxx : select = 4'b1000;
2293
        4'b01xx : select = 4'b0100;
2294
        4'b001x : select = 4'b0010;
2295
        4'b0001 : select = 4'b0001;
2296
        default : select = {nr_of_ports{1'b0}};
2297
        endcase
2298
    else
2299
        select = {nr_of_ports{1'b0}};
2300
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
2301
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2302
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2303
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2304
end
2305
endgenerate
2306
generate
2307
if (nr_of_ports == 5) begin
2308
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2309
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2310
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2311
    always @ (idle or wbm_cyc_o)
2312
    if (idle)
2313
        casex (wbm_cyc_o)
2314
        5'b1xxxx : select = 5'b10000;
2315
        5'b01xxx : select = 5'b01000;
2316
        5'b001xx : select = 5'b00100;
2317
        5'b0001x : select = 5'b00010;
2318
        5'b00001 : select = 5'b00001;
2319
        default : select = {nr_of_ports{1'b0}};
2320
        endcase
2321
    else
2322
        select = {nr_of_ports{1'b0}};
2323
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
2324
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
2325
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2326
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2327
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2328
end
2329
endgenerate
2330
generate
2331 67 unneback
if (nr_of_ports == 6) begin
2332
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2333
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2334
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2335
    always @ (idle or wbm_cyc_o)
2336
    if (idle)
2337
        casex (wbm_cyc_o)
2338
        6'b1xxxxx : select = 6'b100000;
2339
        6'b01xxxx : select = 6'b010000;
2340
        6'b001xxx : select = 6'b001000;
2341
        6'b0001xx : select = 6'b000100;
2342
        6'b00001x : select = 6'b000010;
2343
        6'b000001 : select = 6'b000001;
2344
        default : select = {nr_of_ports{1'b0}};
2345
        endcase
2346
    else
2347
        select = {nr_of_ports{1'b0}};
2348
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o