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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Blame information for rev 94

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1 60 unneback
// default SYN_KEEP definition
2 6 unneback
//////////////////////////////////////////////////////////////////////
3
////                                                              ////
4
////  Versatile library, clock and reset                          ////
5
////                                                              ////
6
////  Description                                                 ////
7
////  Logic related to clock and reset                            ////
8
////                                                              ////
9
////                                                              ////
10
////  To Do:                                                      ////
11
////   - add more different registers                             ////
12
////                                                              ////
13
////  Author(s):                                                  ////
14
////      - Michael Unneback, unneback@opencores.org              ////
15
////        ORSoC AB                                              ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43 48 unneback
`timescale 1 ns/100 ps
44 6 unneback
// Global buffer
45
// usage:
46
// use to enable global buffers for high fan out signals such as clock and reset
47
// Version: 8.4 8.4.0.33
48
module gbuf(GL,CLK);
49
output GL;
50
input  CLK;
51
    wire GND;
52
    GND GND_1_net(.Y(GND));
53
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
54
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
55
endmodule
56
`timescale 1 ns/1 ns
57
module vl_gbuf ( i, o);
58
input i;
59
output o;
60
`ifdef SIM_GBUF
61
assign o=i;
62
`else
63
gbuf gbuf_i0 ( .CLK(i), .GL(o));
64
`endif
65
endmodule
66
 //ACTEL
67
// sync reset
68 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
69 6 unneback
// output active high global reset sync with two DFFs 
70
`timescale 1 ns/100 ps
71
module vl_sync_rst ( rst_n_i, rst_o, clk);
72
input rst_n_i, clk;
73
output rst_o;
74 18 unneback
reg [1:0] tmp;
75 6 unneback
always @ (posedge clk or negedge rst_n_i)
76
if (!rst_n_i)
77 17 unneback
        tmp <= 2'b11;
78 6 unneback
else
79 33 unneback
        tmp <= {1'b0,tmp[1]};
80 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
81 6 unneback
endmodule
82
// vl_pll
83 32 unneback
///////////////////////////////////////////////////////////////////////////////
84 17 unneback
`timescale 1 ps/1 ps
85 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
86
parameter index = 0;
87
parameter number_of_clk = 1;
88 17 unneback
parameter period_time_0 = 20000;
89
parameter period_time_1 = 20000;
90
parameter period_time_2 = 20000;
91
parameter lock_delay = 2000000;
92 6 unneback
input clk_i, rst_n_i;
93
output lock;
94
output reg [0:number_of_clk-1] clk_o;
95
output [0:number_of_clk-1] rst_o;
96
`ifdef SIM_PLL
97
always
98
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
99
generate if (number_of_clk > 1)
100
always
101
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
102
endgenerate
103
generate if (number_of_clk > 2)
104
always
105
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
106
endgenerate
107
genvar i;
108
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
109
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
110
end
111
endgenerate
112
assign #lock_delay lock = rst_n_i;
113
endmodule
114
`else
115
generate if (number_of_clk==1 & index==0) begin
116
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
117
end
118
endgenerate // index==0
119
generate if (number_of_clk==1 & index==1) begin
120
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
121
end
122
endgenerate // index==1
123
generate if (number_of_clk==1 & index==2) begin
124
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
125
end
126
endgenerate // index==2
127
generate if (number_of_clk==1 & index==3) begin
128
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
129
end
130
endgenerate // index==0
131
generate if (number_of_clk==2 & index==0) begin
132
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
133
end
134
endgenerate // index==0
135
generate if (number_of_clk==2 & index==1) begin
136
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
137
end
138
endgenerate // index==1
139
generate if (number_of_clk==2 & index==2) begin
140
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
141
end
142
endgenerate // index==2
143
generate if (number_of_clk==2 & index==3) begin
144
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
145
end
146
endgenerate // index==0
147
generate if (number_of_clk==3 & index==0) begin
148
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
149
end
150
endgenerate // index==0
151
generate if (number_of_clk==3 & index==1) begin
152
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
153
end
154
endgenerate // index==1
155
generate if (number_of_clk==3 & index==2) begin
156
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
157
end
158
endgenerate // index==2
159
generate if (number_of_clk==3 & index==3) begin
160
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
161
end
162
endgenerate // index==0
163
genvar i;
164
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
165 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
166 6 unneback
end
167
endgenerate
168
endmodule
169
`endif
170 32 unneback
///////////////////////////////////////////////////////////////////////////////
171 6 unneback
 //actel
172
//////////////////////////////////////////////////////////////////////
173
////                                                              ////
174
////  Versatile library, registers                                ////
175
////                                                              ////
176
////  Description                                                 ////
177
////  Different type of registers                                 ////
178
////                                                              ////
179
////                                                              ////
180
////  To Do:                                                      ////
181
////   - add more different registers                             ////
182
////                                                              ////
183
////  Author(s):                                                  ////
184
////      - Michael Unneback, unneback@opencores.org              ////
185
////        ORSoC AB                                              ////
186
////                                                              ////
187
//////////////////////////////////////////////////////////////////////
188
////                                                              ////
189
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
190
////                                                              ////
191
//// This source file may be used and distributed without         ////
192
//// restriction provided that this copyright statement is not    ////
193
//// removed from the file and that any derivative work contains  ////
194
//// the original copyright notice and the associated disclaimer. ////
195
////                                                              ////
196
//// This source file is free software; you can redistribute it   ////
197
//// and/or modify it under the terms of the GNU Lesser General   ////
198
//// Public License as published by the Free Software Foundation; ////
199
//// either version 2.1 of the License, or (at your option) any   ////
200
//// later version.                                               ////
201
////                                                              ////
202
//// This source is distributed in the hope that it will be       ////
203
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
204
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
205
//// PURPOSE.  See the GNU Lesser General Public License for more ////
206
//// details.                                                     ////
207
////                                                              ////
208
//// You should have received a copy of the GNU Lesser General    ////
209
//// Public License along with this source; if not, download it   ////
210
//// from http://www.opencores.org/lgpl.shtml                     ////
211
////                                                              ////
212
//////////////////////////////////////////////////////////////////////
213 18 unneback
module vl_dff ( d, q, clk, rst);
214 6 unneback
        parameter width = 1;
215
        parameter reset_value = 0;
216
        input [width-1:0] d;
217
        input clk, rst;
218
        output reg [width-1:0] q;
219
        always @ (posedge clk or posedge rst)
220
        if (rst)
221
                q <= reset_value;
222
        else
223
                q <= d;
224
endmodule
225 18 unneback
module vl_dff_array ( d, q, clk, rst);
226 6 unneback
        parameter width = 1;
227
        parameter depth = 2;
228
        parameter reset_value = 1'b0;
229
        input [width-1:0] d;
230
        input clk, rst;
231
        output [width-1:0] q;
232
        reg  [0:depth-1] q_tmp [width-1:0];
233
        integer i;
234
        always @ (posedge clk or posedge rst)
235
        if (rst) begin
236
            for (i=0;i<depth;i=i+1)
237
                q_tmp[i] <= {width{reset_value}};
238
        end else begin
239
            q_tmp[0] <= d;
240
            for (i=1;i<depth;i=i+1)
241
                q_tmp[i] <= q_tmp[i-1];
242
        end
243
    assign q = q_tmp[depth-1];
244
endmodule
245 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
246 6 unneback
        parameter width = 1;
247
        parameter reset_value = 0;
248
        input [width-1:0] d;
249
        input ce, clk, rst;
250
        output reg [width-1:0] q;
251
        always @ (posedge clk or posedge rst)
252
        if (rst)
253
                q <= reset_value;
254
        else
255
                if (ce)
256
                        q <= d;
257
endmodule
258 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
259 8 unneback
        parameter width = 1;
260
        parameter reset_value = 0;
261
        input [width-1:0] d;
262 10 unneback
        input ce, clear, clk, rst;
263 8 unneback
        output reg [width-1:0] q;
264
        always @ (posedge clk or posedge rst)
265
        if (rst)
266
            q <= reset_value;
267
        else
268
            if (ce)
269
                if (clear)
270
                    q <= {width{1'b0}};
271
                else
272
                    q <= d;
273
endmodule
274 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
275
        parameter width = 1;
276
        parameter reset_value = 0;
277
        input [width-1:0] d;
278
        input ce, set, clk, rst;
279
        output reg [width-1:0] q;
280
        always @ (posedge clk or posedge rst)
281
        if (rst)
282
            q <= reset_value;
283
        else
284
            if (ce)
285
                if (set)
286
                    q <= {width{1'b1}};
287
                else
288
                    q <= d;
289
endmodule
290 29 unneback
module vl_spr ( sp, r, q, clk, rst);
291 64 unneback
        //parameter width = 1;
292
        parameter reset_value = 1'b0;
293 29 unneback
        input sp, r;
294
        output reg q;
295
        input clk, rst;
296
        always @ (posedge clk or posedge rst)
297
        if (rst)
298
            q <= reset_value;
299
        else
300
            if (sp)
301
                q <= 1'b1;
302
            else if (r)
303
                q <= 1'b0;
304
endmodule
305
module vl_srp ( s, rp, q, clk, rst);
306
        parameter width = 1;
307
        parameter reset_value = 0;
308
        input s, rp;
309
        output reg q;
310
        input clk, rst;
311
        always @ (posedge clk or posedge rst)
312
        if (rst)
313
            q <= reset_value;
314
        else
315
            if (rp)
316
                q <= 1'b0;
317
            else if (s)
318
                q <= 1'b1;
319
endmodule
320 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
321 6 unneback
    input         aclr;
322
    input         aset;
323
    input         clock;
324
    input         data;
325
    output reg    q;
326
   always @ (posedge clock or posedge aclr or posedge aset)
327
     if (aclr)
328
       q <= 1'b0;
329
     else if (aset)
330
       q <= 1'b1;
331
     else
332
       q <= data;
333
endmodule
334
// LATCH
335
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
336 40 unneback
module vl_latch ( d, le, q, clk);
337 6 unneback
input d, le;
338 48 unneback
input clk;
339
always @ (le or d)
340 60 unneback
if (le)
341 48 unneback
    d <= q;
342 6 unneback
endmodule
343 18 unneback
module vl_shreg ( d, q, clk, rst);
344 17 unneback
parameter depth = 10;
345
input d;
346
output q;
347
input clk, rst;
348
reg [1:depth] dffs;
349
always @ (posedge clk or posedge rst)
350
if (rst)
351
    dffs <= {depth{1'b0}};
352
else
353
    dffs <= {d,dffs[1:depth-1]};
354
assign q = dffs[depth];
355
endmodule
356 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
357 17 unneback
parameter depth = 10;
358
input d, ce;
359
output q;
360
input clk, rst;
361
reg [1:depth] dffs;
362
always @ (posedge clk or posedge rst)
363
if (rst)
364
    dffs <= {depth{1'b0}};
365
else
366
    if (ce)
367
        dffs <= {d,dffs[1:depth-1]};
368
assign q = dffs[depth];
369
endmodule
370 18 unneback
module vl_delay ( d, q, clk, rst);
371 15 unneback
parameter depth = 10;
372
input d;
373
output q;
374
input clk, rst;
375
reg [1:depth] dffs;
376
always @ (posedge clk or posedge rst)
377
if (rst)
378
    dffs <= {depth{1'b0}};
379
else
380
    dffs <= {d,dffs[1:depth-1]};
381
assign q = dffs[depth];
382
endmodule
383 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
384 17 unneback
parameter depth = 10;
385
input d;
386
output q, emptyflag;
387
input clk, rst;
388
reg [1:depth] dffs;
389
always @ (posedge clk or posedge rst)
390
if (rst)
391
    dffs <= {depth{1'b0}};
392
else
393
    dffs <= {d,dffs[1:depth-1]};
394
assign q = dffs[depth];
395
assign emptyflag = !(|dffs);
396
endmodule
397 94 unneback
module vl_pules2toggle ( pl, q, clk, rst)
398
input pl;
399
output q;
400
input clk, rst;
401
input
402
always @ (posedge clk or posedge rst)
403
if (rst)
404
    q <= 1'b0;
405
else
406
    q <= pl ^ q;
407
endmodule
408
module vl_toggle2pulse; (d, pl, clk, rst);
409
input d;
410
output pl;
411
input clk, rst;
412
reg dff;
413
always @ (posedge clk or posedge rst)
414
if (rst)
415
    dff <= 1'b0;
416
else
417
    dff <= d;
418
assign d ^ dff;
419
endmodule
420
module vl_synchronizer (d, q, clk, rst);
421
input d;
422
output reg q;
423
output clk, rst;
424
reg dff;
425
always @ (posedge clk or posedge rst)
426
if (rst)
427
    {dff,q} <= 2'b00;
428
else
429
    {dff,q} <= {d,dff};
430
endmodule
431
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst)
432
input start_pl;
433
output take_it_pl;
434
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
435
output got_it_pl;
436
input clk_src, rst_src;
437
input clk_dst, rst_dst;
438
wire take_it_tg, take_it_tg_sync;
439
wire got_it_tg, got_it_tg_sync;
440
// src -> dst
441
vl_pulse2toggle p2t0 (
442
    .pl(start_pl),
443
    .q(take_it_tg),
444
    .clk(clk_src),
445
    .rst(rst_src));
446
vl_synchronizer sync0 (
447
    .d(take_it_tg),
448
    .q(take_it_tg_sync),
449
    .clk(clk_dst),
450
    .rst(rst_dst));
451
vl_toggle2pulse t2p0 (
452
    .d(take_it_sync),
453
    .pl(take_it_pl),
454
    .clk(clk_dst),
455
    .rst(rst_dst));
456
// dst -> src
457
vl_pulse2toggle p2t0 (
458
    .pl(take_it_grant_pl),
459
    .q(got_it_tg),
460
    .clk(clk_dst),
461
    .rst(rst_dst));
462
vl_synchronizer sync1 (
463
    .d(got_it_tg),
464
    .q(got_it_tg_sync),
465
    .clk(clk_src),
466
    .rst(rst_src));
467
vl_toggle2pulse t2p1 (
468
    .d(take_it_grant_tg_sync),
469
    .pl(got_it_pl),
470
    .clk(clk_src),
471
    .rst(rst_src));
472
endmodule
473 6 unneback
//////////////////////////////////////////////////////////////////////
474
////                                                              ////
475 18 unneback
////  Logic functions                                             ////
476
////                                                              ////
477
////  Description                                                 ////
478
////  Logic functions such as multiplexers                        ////
479
////                                                              ////
480
////                                                              ////
481
////  To Do:                                                      ////
482
////   -                                                          ////
483
////                                                              ////
484
////  Author(s):                                                  ////
485
////      - Michael Unneback, unneback@opencores.org              ////
486
////        ORSoC AB                                              ////
487
////                                                              ////
488
//////////////////////////////////////////////////////////////////////
489
////                                                              ////
490
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
491
////                                                              ////
492
//// This source file may be used and distributed without         ////
493
//// restriction provided that this copyright statement is not    ////
494
//// removed from the file and that any derivative work contains  ////
495
//// the original copyright notice and the associated disclaimer. ////
496
////                                                              ////
497
//// This source file is free software; you can redistribute it   ////
498
//// and/or modify it under the terms of the GNU Lesser General   ////
499
//// Public License as published by the Free Software Foundation; ////
500
//// either version 2.1 of the License, or (at your option) any   ////
501
//// later version.                                               ////
502
////                                                              ////
503
//// This source is distributed in the hope that it will be       ////
504
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
505
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
506
//// PURPOSE.  See the GNU Lesser General Public License for more ////
507
//// details.                                                     ////
508
////                                                              ////
509
//// You should have received a copy of the GNU Lesser General    ////
510
//// Public License along with this source; if not, download it   ////
511
//// from http://www.opencores.org/lgpl.shtml                     ////
512
////                                                              ////
513
//////////////////////////////////////////////////////////////////////
514 36 unneback
module vl_mux_andor ( a, sel, dout);
515
parameter width = 32;
516
parameter nr_of_ports = 4;
517
input [nr_of_ports*width-1:0] a;
518
input [nr_of_ports-1:0] sel;
519
output reg [width-1:0] dout;
520 38 unneback
integer i,j;
521 36 unneback
always @ (a, sel)
522
begin
523
    dout = a[width-1:0] & {width{sel[0]}};
524 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
525
        for (j=0;j<width;j=j+1)
526
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
527 36 unneback
end
528
endmodule
529 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
530
parameter width = 32;
531 35 unneback
localparam nr_of_ports = 2;
532 34 unneback
input [width-1:0] a1, a0;
533
input [nr_of_ports-1:0] sel;
534
output [width-1:0] dout;
535 36 unneback
vl_mux_andor
536 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
537 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
538 34 unneback
endmodule
539
module vl_mux3_andor ( a2, a1, a0, sel, dout);
540
parameter width = 32;
541 35 unneback
localparam nr_of_ports = 3;
542 34 unneback
input [width-1:0] a2, a1, a0;
543
input [nr_of_ports-1:0] sel;
544
output [width-1:0] dout;
545 36 unneback
vl_mux_andor
546 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
547 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
548 34 unneback
endmodule
549 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
550
parameter width = 32;
551 35 unneback
localparam nr_of_ports = 4;
552 18 unneback
input [width-1:0] a3, a2, a1, a0;
553
input [nr_of_ports-1:0] sel;
554 22 unneback
output [width-1:0] dout;
555 36 unneback
vl_mux_andor
556 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
557 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
558 18 unneback
endmodule
559
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
560
parameter width = 32;
561 35 unneback
localparam nr_of_ports = 5;
562 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
563
input [nr_of_ports-1:0] sel;
564 22 unneback
output [width-1:0] dout;
565 36 unneback
vl_mux_andor
566 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
567 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
568 18 unneback
endmodule
569
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
570
parameter width = 32;
571 35 unneback
localparam nr_of_ports = 6;
572 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
573
input [nr_of_ports-1:0] sel;
574 22 unneback
output [width-1:0] dout;
575 36 unneback
vl_mux_andor
576 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
577 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
578 18 unneback
endmodule
579 43 unneback
module vl_parity_generate (data, parity);
580
parameter word_size = 32;
581
parameter chunk_size = 8;
582
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
583
input [word_size-1:0] data;
584
output reg [word_size/chunk_size-1:0] parity;
585
integer i,j;
586
always @ (data)
587
for (i=0;i<word_size/chunk_size;i=i+1) begin
588
    parity[i] = parity_type;
589
    for (j=0;j<chunk_size;j=j+1) begin
590 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
591 43 unneback
    end
592
end
593
endmodule
594
module vl_parity_check( data, parity, parity_error);
595
parameter word_size = 32;
596
parameter chunk_size = 8;
597
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
598
input [word_size-1:0] data;
599
input [word_size/chunk_size-1:0] parity;
600
output parity_error;
601 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
602 43 unneback
integer i,j;
603
always @ (data or parity)
604
for (i=0;i<word_size/chunk_size;i=i+1) begin
605
    error_flag[i] = parity[i] ^ parity_type;
606
    for (j=0;j<chunk_size;j=j+1) begin
607 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
608 43 unneback
    end
609
end
610
assign parity_error = |error_flag;
611
endmodule
612 18 unneback
//////////////////////////////////////////////////////////////////////
613
////                                                              ////
614 44 unneback
////  IO functions                                                ////
615
////                                                              ////
616
////  Description                                                 ////
617
////  IO functions such as IOB flip-flops                         ////
618
////                                                              ////
619
////                                                              ////
620
////  To Do:                                                      ////
621
////   -                                                          ////
622
////                                                              ////
623
////  Author(s):                                                  ////
624
////      - Michael Unneback, unneback@opencores.org              ////
625
////        ORSoC AB                                              ////
626
////                                                              ////
627
//////////////////////////////////////////////////////////////////////
628
////                                                              ////
629
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
630
////                                                              ////
631
//// This source file may be used and distributed without         ////
632
//// restriction provided that this copyright statement is not    ////
633
//// removed from the file and that any derivative work contains  ////
634
//// the original copyright notice and the associated disclaimer. ////
635
////                                                              ////
636
//// This source file is free software; you can redistribute it   ////
637
//// and/or modify it under the terms of the GNU Lesser General   ////
638
//// Public License as published by the Free Software Foundation; ////
639
//// either version 2.1 of the License, or (at your option) any   ////
640
//// later version.                                               ////
641
////                                                              ////
642
//// This source is distributed in the hope that it will be       ////
643
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
644
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
645
//// PURPOSE.  See the GNU Lesser General Public License for more ////
646
//// details.                                                     ////
647
////                                                              ////
648
//// You should have received a copy of the GNU Lesser General    ////
649
//// Public License along with this source; if not, download it   ////
650
//// from http://www.opencores.org/lgpl.shtml                     ////
651
////                                                              ////
652
//////////////////////////////////////////////////////////////////////
653 45 unneback
`timescale 1ns/1ns
654 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
655
parameter width = 1;
656 45 unneback
parameter reset_value = {width{1'b0}};
657
input  [width-1:0]  d_i;
658 44 unneback
output [width-1:0] o_pad;
659
input clk, rst;
660
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
661 45 unneback
reg  [width-1:0] o_pad_int;
662 44 unneback
assign d_i_int = d_i;
663
genvar i;
664 45 unneback
generate
665 44 unneback
for (i=0;i<width;i=i+1) begin
666
    always @ (posedge clk or posedge rst)
667
    if (rst)
668 45 unneback
        o_pad_int[i] <= reset_value[i];
669 44 unneback
    else
670 45 unneback
        o_pad_int[i] <= d_i_int[i];
671
    assign #1 o_pad[i] = o_pad_int[i];
672 44 unneback
end
673
endgenerate
674
endmodule
675 45 unneback
`timescale 1ns/1ns
676 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
677
parameter width = 1;
678
input  [width-1:0] d_o;
679
output reg [width-1:0] d_i;
680
input oe;
681
inout [width-1:0] io_pad;
682
input clk, rst;
683
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
684
reg [width-1:0] oe_q;
685
reg [width-1:0] d_o_q;
686
assign oe_d = {width{oe}};
687
genvar i;
688
generate
689
for (i=0;i<width;i=i+1) begin
690
    always @ (posedge clk or posedge rst)
691
    if (rst)
692
        oe_q[i] <= 1'b0;
693
    else
694
        oe_q[i] <= oe_d[i];
695
    always @ (posedge clk or posedge rst)
696
    if (rst)
697
        d_o_q[i] <= 1'b0;
698
    else
699
        d_o_q[i] <= d_o[i];
700
    always @ (posedge clk or posedge rst)
701
    if (rst)
702
        d_i[i] <= 1'b0;
703
    else
704
        d_i[i] <= io_pad[i];
705 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
706 44 unneback
end
707
endgenerate
708
endmodule
709
//////////////////////////////////////////////////////////////////////
710
////                                                              ////
711 6 unneback
////  Versatile counter                                           ////
712
////                                                              ////
713
////  Description                                                 ////
714
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
715
////  counter                                                     ////
716
////                                                              ////
717
////  To Do:                                                      ////
718
////   - add LFSR with more taps                                  ////
719
////                                                              ////
720
////  Author(s):                                                  ////
721
////      - Michael Unneback, unneback@opencores.org              ////
722
////        ORSoC AB                                              ////
723
////                                                              ////
724
//////////////////////////////////////////////////////////////////////
725
////                                                              ////
726
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
727
////                                                              ////
728
//// This source file may be used and distributed without         ////
729
//// restriction provided that this copyright statement is not    ////
730
//// removed from the file and that any derivative work contains  ////
731
//// the original copyright notice and the associated disclaimer. ////
732
////                                                              ////
733
//// This source file is free software; you can redistribute it   ////
734
//// and/or modify it under the terms of the GNU Lesser General   ////
735
//// Public License as published by the Free Software Foundation; ////
736
//// either version 2.1 of the License, or (at your option) any   ////
737
//// later version.                                               ////
738
////                                                              ////
739
//// This source is distributed in the hope that it will be       ////
740
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
741
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
742
//// PURPOSE.  See the GNU Lesser General Public License for more ////
743
//// details.                                                     ////
744
////                                                              ////
745
//// You should have received a copy of the GNU Lesser General    ////
746
//// Public License along with this source; if not, download it   ////
747
//// from http://www.opencores.org/lgpl.shtml                     ////
748
////                                                              ////
749
//////////////////////////////////////////////////////////////////////
750
// binary counter
751 40 unneback
module vl_cnt_bin_ce (
752
 cke, q, rst, clk);
753 22 unneback
   parameter length = 4;
754 6 unneback
   input cke;
755
   output [length:1] q;
756
   input rst;
757
   input clk;
758
   parameter clear_value = 0;
759
   parameter set_value = 1;
760
   parameter wrap_value = 0;
761
   parameter level1_value = 15;
762
   reg  [length:1] qi;
763
   wire [length:1] q_next;
764
   assign q_next = qi + {{length-1{1'b0}},1'b1};
765
   always @ (posedge clk or posedge rst)
766
     if (rst)
767
       qi <= {length{1'b0}};
768
     else
769
     if (cke)
770
       qi <= q_next;
771
   assign q = qi;
772
endmodule
773
//////////////////////////////////////////////////////////////////////
774
////                                                              ////
775
////  Versatile counter                                           ////
776
////                                                              ////
777
////  Description                                                 ////
778
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
779
////  counter                                                     ////
780
////                                                              ////
781
////  To Do:                                                      ////
782
////   - add LFSR with more taps                                  ////
783
////                                                              ////
784
////  Author(s):                                                  ////
785
////      - Michael Unneback, unneback@opencores.org              ////
786
////        ORSoC AB                                              ////
787
////                                                              ////
788
//////////////////////////////////////////////////////////////////////
789
////                                                              ////
790
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
791
////                                                              ////
792
//// This source file may be used and distributed without         ////
793
//// restriction provided that this copyright statement is not    ////
794
//// removed from the file and that any derivative work contains  ////
795
//// the original copyright notice and the associated disclaimer. ////
796
////                                                              ////
797
//// This source file is free software; you can redistribute it   ////
798
//// and/or modify it under the terms of the GNU Lesser General   ////
799
//// Public License as published by the Free Software Foundation; ////
800
//// either version 2.1 of the License, or (at your option) any   ////
801
//// later version.                                               ////
802
////                                                              ////
803
//// This source is distributed in the hope that it will be       ////
804
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
805
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
806
//// PURPOSE.  See the GNU Lesser General Public License for more ////
807
//// details.                                                     ////
808
////                                                              ////
809
//// You should have received a copy of the GNU Lesser General    ////
810
//// Public License along with this source; if not, download it   ////
811
//// from http://www.opencores.org/lgpl.shtml                     ////
812
////                                                              ////
813
//////////////////////////////////////////////////////////////////////
814
// binary counter
815 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
816
 cke, rew, zq, level1, rst, clk);
817 6 unneback
   parameter length = 4;
818
   input cke;
819
   input rew;
820 25 unneback
   output reg zq;
821
   output reg level1;
822
   input rst;
823
   input clk;
824
   parameter clear_value = 0;
825
   parameter set_value = 1;
826
   parameter wrap_value = 1;
827
   parameter level1_value = 15;
828 29 unneback
   wire clear;
829 30 unneback
   assign clear = 1'b0;
830 25 unneback
   reg  [length:1] qi;
831
   wire  [length:1] q_next, q_next_fw, q_next_rew;
832
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
833
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
834
   assign q_next = rew ? q_next_rew : q_next_fw;
835
   always @ (posedge clk or posedge rst)
836
     if (rst)
837
       qi <= {length{1'b0}};
838
     else
839
     if (cke)
840
       qi <= q_next;
841
   always @ (posedge clk or posedge rst)
842
     if (rst)
843
       zq <= 1'b1;
844
     else
845
     if (cke)
846
       zq <= q_next == {length{1'b0}};
847
    always @ (posedge clk or posedge rst)
848
    if (rst)
849
        level1 <= 1'b0;
850
    else
851
    if (cke)
852 29 unneback
    if (clear)
853
        level1 <= 1'b0;
854
    else if (q_next == level1_value)
855 25 unneback
        level1 <= 1'b1;
856
    else if (qi == level1_value & rew)
857
        level1 <= 1'b0;
858
endmodule
859
//////////////////////////////////////////////////////////////////////
860
////                                                              ////
861
////  Versatile counter                                           ////
862
////                                                              ////
863
////  Description                                                 ////
864
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
865
////  counter                                                     ////
866
////                                                              ////
867
////  To Do:                                                      ////
868
////   - add LFSR with more taps                                  ////
869
////                                                              ////
870
////  Author(s):                                                  ////
871
////      - Michael Unneback, unneback@opencores.org              ////
872
////        ORSoC AB                                              ////
873
////                                                              ////
874
//////////////////////////////////////////////////////////////////////
875
////                                                              ////
876
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
877
////                                                              ////
878
//// This source file may be used and distributed without         ////
879
//// restriction provided that this copyright statement is not    ////
880
//// removed from the file and that any derivative work contains  ////
881
//// the original copyright notice and the associated disclaimer. ////
882
////                                                              ////
883
//// This source file is free software; you can redistribute it   ////
884
//// and/or modify it under the terms of the GNU Lesser General   ////
885
//// Public License as published by the Free Software Foundation; ////
886
//// either version 2.1 of the License, or (at your option) any   ////
887
//// later version.                                               ////
888
////                                                              ////
889
//// This source is distributed in the hope that it will be       ////
890
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
891
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
892
//// PURPOSE.  See the GNU Lesser General Public License for more ////
893
//// details.                                                     ////
894
////                                                              ////
895
//// You should have received a copy of the GNU Lesser General    ////
896
//// Public License along with this source; if not, download it   ////
897
//// from http://www.opencores.org/lgpl.shtml                     ////
898
////                                                              ////
899
//////////////////////////////////////////////////////////////////////
900
// binary counter
901 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
902
 cke, rew, q, zq, level1, rst, clk);
903 25 unneback
   parameter length = 4;
904
   input cke;
905
   input rew;
906
   output [length:1] q;
907
   output reg zq;
908
   output reg level1;
909
   input rst;
910
   input clk;
911
   parameter clear_value = 0;
912
   parameter set_value = 1;
913
   parameter wrap_value = 1;
914
   parameter level1_value = 15;
915 29 unneback
   wire clear;
916 30 unneback
   assign clear = 1'b0;
917 25 unneback
   reg  [length:1] qi;
918
   wire  [length:1] q_next, q_next_fw, q_next_rew;
919
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
920
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
921
   assign q_next = rew ? q_next_rew : q_next_fw;
922
   always @ (posedge clk or posedge rst)
923
     if (rst)
924
       qi <= {length{1'b0}};
925
     else
926
     if (cke)
927
       qi <= q_next;
928
   assign q = qi;
929
   always @ (posedge clk or posedge rst)
930
     if (rst)
931
       zq <= 1'b1;
932
     else
933
     if (cke)
934
       zq <= q_next == {length{1'b0}};
935
    always @ (posedge clk or posedge rst)
936
    if (rst)
937
        level1 <= 1'b0;
938
    else
939
    if (cke)
940 29 unneback
    if (clear)
941
        level1 <= 1'b0;
942
    else if (q_next == level1_value)
943 25 unneback
        level1 <= 1'b1;
944
    else if (qi == level1_value & rew)
945
        level1 <= 1'b0;
946
endmodule
947
//////////////////////////////////////////////////////////////////////
948
////                                                              ////
949
////  Versatile counter                                           ////
950
////                                                              ////
951
////  Description                                                 ////
952
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
953
////  counter                                                     ////
954
////                                                              ////
955
////  To Do:                                                      ////
956
////   - add LFSR with more taps                                  ////
957
////                                                              ////
958
////  Author(s):                                                  ////
959
////      - Michael Unneback, unneback@opencores.org              ////
960
////        ORSoC AB                                              ////
961
////                                                              ////
962
//////////////////////////////////////////////////////////////////////
963
////                                                              ////
964
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
965
////                                                              ////
966
//// This source file may be used and distributed without         ////
967
//// restriction provided that this copyright statement is not    ////
968
//// removed from the file and that any derivative work contains  ////
969
//// the original copyright notice and the associated disclaimer. ////
970
////                                                              ////
971
//// This source file is free software; you can redistribute it   ////
972
//// and/or modify it under the terms of the GNU Lesser General   ////
973
//// Public License as published by the Free Software Foundation; ////
974
//// either version 2.1 of the License, or (at your option) any   ////
975
//// later version.                                               ////
976
////                                                              ////
977
//// This source is distributed in the hope that it will be       ////
978
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
979
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
980
//// PURPOSE.  See the GNU Lesser General Public License for more ////
981
//// details.                                                     ////
982
////                                                              ////
983
//// You should have received a copy of the GNU Lesser General    ////
984
//// Public License along with this source; if not, download it   ////
985
//// from http://www.opencores.org/lgpl.shtml                     ////
986
////                                                              ////
987
//////////////////////////////////////////////////////////////////////
988 75 unneback
// LFSR counter
989
module vl_cnt_lfsr_ce (
990
 cke, zq, rst, clk);
991
   parameter length = 4;
992
   input cke;
993
   output reg zq;
994
   input rst;
995
   input clk;
996
   parameter clear_value = 0;
997
   parameter set_value = 1;
998
   parameter wrap_value = 0;
999
   parameter level1_value = 15;
1000
   reg  [length:1] qi;
1001
   reg lfsr_fb;
1002
   wire [length:1] q_next;
1003
   reg [32:1] polynom;
1004
   integer i;
1005
   always @ (qi)
1006
   begin
1007
        case (length)
1008
         2: polynom = 32'b11;                               // 0x3
1009
         3: polynom = 32'b110;                              // 0x6
1010
         4: polynom = 32'b1100;                             // 0xC
1011
         5: polynom = 32'b10100;                            // 0x14
1012
         6: polynom = 32'b110000;                           // 0x30
1013
         7: polynom = 32'b1100000;                          // 0x60
1014
         8: polynom = 32'b10111000;                         // 0xb8
1015
         9: polynom = 32'b100010000;                        // 0x110
1016
        10: polynom = 32'b1001000000;                       // 0x240
1017
        11: polynom = 32'b10100000000;                      // 0x500
1018
        12: polynom = 32'b100000101001;                     // 0x829
1019
        13: polynom = 32'b1000000001100;                    // 0x100C
1020
        14: polynom = 32'b10000000010101;                   // 0x2015
1021
        15: polynom = 32'b110000000000000;                  // 0x6000
1022
        16: polynom = 32'b1101000000001000;                 // 0xD008
1023
        17: polynom = 32'b10010000000000000;                // 0x12000
1024
        18: polynom = 32'b100000010000000000;               // 0x20400
1025
        19: polynom = 32'b1000000000000100011;              // 0x40023
1026
        20: polynom = 32'b10010000000000000000;             // 0x90000
1027
        21: polynom = 32'b101000000000000000000;            // 0x140000
1028
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1029
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1030
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1031
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1032
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1033
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1034
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1035
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1036
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1037
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1038
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1039
        default: polynom = 32'b0;
1040
        endcase
1041
        lfsr_fb = qi[length];
1042
        for (i=length-1; i>=1; i=i-1) begin
1043
            if (polynom[i])
1044
                lfsr_fb = lfsr_fb  ~^ qi[i];
1045
        end
1046
    end
1047
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1048
   always @ (posedge clk or posedge rst)
1049
     if (rst)
1050
       qi <= {length{1'b0}};
1051
     else
1052
     if (cke)
1053
       qi <= q_next;
1054
   always @ (posedge clk or posedge rst)
1055
     if (rst)
1056
       zq <= 1'b1;
1057
     else
1058
     if (cke)
1059
       zq <= q_next == {length{1'b0}};
1060
endmodule
1061
//////////////////////////////////////////////////////////////////////
1062
////                                                              ////
1063
////  Versatile counter                                           ////
1064
////                                                              ////
1065
////  Description                                                 ////
1066
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1067
////  counter                                                     ////
1068
////                                                              ////
1069
////  To Do:                                                      ////
1070
////   - add LFSR with more taps                                  ////
1071
////                                                              ////
1072
////  Author(s):                                                  ////
1073
////      - Michael Unneback, unneback@opencores.org              ////
1074
////        ORSoC AB                                              ////
1075
////                                                              ////
1076
//////////////////////////////////////////////////////////////////////
1077
////                                                              ////
1078
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1079
////                                                              ////
1080
//// This source file may be used and distributed without         ////
1081
//// restriction provided that this copyright statement is not    ////
1082
//// removed from the file and that any derivative work contains  ////
1083
//// the original copyright notice and the associated disclaimer. ////
1084
////                                                              ////
1085
//// This source file is free software; you can redistribute it   ////
1086
//// and/or modify it under the terms of the GNU Lesser General   ////
1087
//// Public License as published by the Free Software Foundation; ////
1088
//// either version 2.1 of the License, or (at your option) any   ////
1089
//// later version.                                               ////
1090
////                                                              ////
1091
//// This source is distributed in the hope that it will be       ////
1092
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1093
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1094
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1095
//// details.                                                     ////
1096
////                                                              ////
1097
//// You should have received a copy of the GNU Lesser General    ////
1098
//// Public License along with this source; if not, download it   ////
1099
//// from http://www.opencores.org/lgpl.shtml                     ////
1100
////                                                              ////
1101
//////////////////////////////////////////////////////////////////////
1102 6 unneback
// GRAY counter
1103 40 unneback
module vl_cnt_gray_ce_bin (
1104
 cke, q, q_bin, rst, clk);
1105 6 unneback
   parameter length = 4;
1106
   input cke;
1107
   output reg [length:1] q;
1108
   output [length:1] q_bin;
1109
   input rst;
1110
   input clk;
1111
   parameter clear_value = 0;
1112
   parameter set_value = 1;
1113
   parameter wrap_value = 8;
1114
   parameter level1_value = 15;
1115
   reg  [length:1] qi;
1116
   wire [length:1] q_next;
1117
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1118
   always @ (posedge clk or posedge rst)
1119
     if (rst)
1120
       qi <= {length{1'b0}};
1121
     else
1122
     if (cke)
1123
       qi <= q_next;
1124
   always @ (posedge clk or posedge rst)
1125
     if (rst)
1126
       q <= {length{1'b0}};
1127
     else
1128
       if (cke)
1129
         q <= (q_next>>1) ^ q_next;
1130
   assign q_bin = qi;
1131
endmodule
1132
//////////////////////////////////////////////////////////////////////
1133
////                                                              ////
1134
////  Versatile library, counters                                 ////
1135
////                                                              ////
1136
////  Description                                                 ////
1137
////  counters                                                    ////
1138
////                                                              ////
1139
////                                                              ////
1140
////  To Do:                                                      ////
1141
////   - add more counters                                        ////
1142
////                                                              ////
1143
////  Author(s):                                                  ////
1144
////      - Michael Unneback, unneback@opencores.org              ////
1145
////        ORSoC AB                                              ////
1146
////                                                              ////
1147
//////////////////////////////////////////////////////////////////////
1148
////                                                              ////
1149
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1150
////                                                              ////
1151
//// This source file may be used and distributed without         ////
1152
//// restriction provided that this copyright statement is not    ////
1153
//// removed from the file and that any derivative work contains  ////
1154
//// the original copyright notice and the associated disclaimer. ////
1155
////                                                              ////
1156
//// This source file is free software; you can redistribute it   ////
1157
//// and/or modify it under the terms of the GNU Lesser General   ////
1158
//// Public License as published by the Free Software Foundation; ////
1159
//// either version 2.1 of the License, or (at your option) any   ////
1160
//// later version.                                               ////
1161
////                                                              ////
1162
//// This source is distributed in the hope that it will be       ////
1163
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1164
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1165
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1166
//// details.                                                     ////
1167
////                                                              ////
1168
//// You should have received a copy of the GNU Lesser General    ////
1169
//// Public License along with this source; if not, download it   ////
1170
//// from http://www.opencores.org/lgpl.shtml                     ////
1171
////                                                              ////
1172
//////////////////////////////////////////////////////////////////////
1173 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1174 6 unneback
   parameter length = 4;
1175
   output reg [0:length-1] q;
1176
   input rst;
1177
   input clk;
1178
    always @ (posedge clk or posedge rst)
1179
    if (rst)
1180
        q <= {1'b1,{length-1{1'b0}}};
1181
    else
1182
        q <= {q[length-1],q[0:length-2]};
1183
endmodule
1184 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1185 6 unneback
   parameter length = 4;
1186
   input cke;
1187
   output reg [0:length-1] q;
1188
   input rst;
1189
   input clk;
1190
    always @ (posedge clk or posedge rst)
1191
    if (rst)
1192
        q <= {1'b1,{length-1{1'b0}}};
1193
    else
1194
        if (cke)
1195
            q <= {q[length-1],q[0:length-2]};
1196
endmodule
1197 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1198 6 unneback
   parameter length = 4;
1199
   input cke, clear;
1200
   output reg [0:length-1] q;
1201
   input rst;
1202
   input clk;
1203
    always @ (posedge clk or posedge rst)
1204
    if (rst)
1205
        q <= {1'b1,{length-1{1'b0}}};
1206
    else
1207
        if (cke)
1208
            if (clear)
1209
                q <= {1'b1,{length-1{1'b0}}};
1210
            else
1211
                q <= q >> 1;
1212
endmodule
1213 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1214 6 unneback
   parameter length = 4;
1215
   input cke, clear;
1216
   output reg [0:length-1] q;
1217
   input rst;
1218
   input clk;
1219
    always @ (posedge clk or posedge rst)
1220
    if (rst)
1221
        q <= {1'b1,{length-1{1'b0}}};
1222
    else
1223
        if (cke)
1224
            if (clear)
1225
                q <= {1'b1,{length-1{1'b0}}};
1226
            else
1227
            q <= {q[length-1],q[0:length-2]};
1228
endmodule
1229
//////////////////////////////////////////////////////////////////////
1230
////                                                              ////
1231
////  Versatile library, memories                                 ////
1232
////                                                              ////
1233
////  Description                                                 ////
1234
////  memories                                                    ////
1235
////                                                              ////
1236
////                                                              ////
1237
////  To Do:                                                      ////
1238
////   - add more memory types                                    ////
1239
////                                                              ////
1240
////  Author(s):                                                  ////
1241
////      - Michael Unneback, unneback@opencores.org              ////
1242
////        ORSoC AB                                              ////
1243
////                                                              ////
1244
//////////////////////////////////////////////////////////////////////
1245
////                                                              ////
1246
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1247
////                                                              ////
1248
//// This source file may be used and distributed without         ////
1249
//// restriction provided that this copyright statement is not    ////
1250
//// removed from the file and that any derivative work contains  ////
1251
//// the original copyright notice and the associated disclaimer. ////
1252
////                                                              ////
1253
//// This source file is free software; you can redistribute it   ////
1254
//// and/or modify it under the terms of the GNU Lesser General   ////
1255
//// Public License as published by the Free Software Foundation; ////
1256
//// either version 2.1 of the License, or (at your option) any   ////
1257
//// later version.                                               ////
1258
////                                                              ////
1259
//// This source is distributed in the hope that it will be       ////
1260
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1261
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1262
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1263
//// details.                                                     ////
1264
////                                                              ////
1265
//// You should have received a copy of the GNU Lesser General    ////
1266
//// Public License along with this source; if not, download it   ////
1267
//// from http://www.opencores.org/lgpl.shtml                     ////
1268
////                                                              ////
1269
//////////////////////////////////////////////////////////////////////
1270
/// ROM
1271 7 unneback
module vl_rom_init ( adr, q, clk);
1272
   parameter data_width = 32;
1273
   parameter addr_width = 8;
1274 75 unneback
   parameter mem_size = 1<<addr_width;
1275 7 unneback
   input [(addr_width-1):0]       adr;
1276
   output reg [(data_width-1):0] q;
1277
   input                         clk;
1278 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1279 7 unneback
   parameter memory_file = "vl_rom.vmem";
1280
   initial
1281
     begin
1282
        $readmemh(memory_file, rom);
1283
     end
1284
   always @ (posedge clk)
1285
     q <= rom[adr];
1286
endmodule
1287 6 unneback
// Single port RAM
1288
module vl_ram ( d, adr, we, q, clk);
1289
   parameter data_width = 32;
1290
   parameter addr_width = 8;
1291 75 unneback
   parameter mem_size = 1<<addr_width;
1292 6 unneback
   input [(data_width-1):0]      d;
1293
   input [(addr_width-1):0]       adr;
1294
   input                         we;
1295 7 unneback
   output reg [(data_width-1):0] q;
1296 6 unneback
   input                         clk;
1297 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
1298 7 unneback
   parameter init = 0;
1299
   parameter memory_file = "vl_ram.vmem";
1300
   generate if (init) begin : init_mem
1301
   initial
1302
     begin
1303
        $readmemh(memory_file, ram);
1304
     end
1305
   end
1306
   endgenerate
1307 6 unneback
   always @ (posedge clk)
1308
   begin
1309
   if (we)
1310
     ram[adr] <= d;
1311
   q <= ram[adr];
1312
   end
1313
endmodule
1314 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1315 7 unneback
   parameter data_width = 32;
1316 72 unneback
   parameter addr_width = 6;
1317 75 unneback
   parameter mem_size = 1<<addr_width;
1318 7 unneback
   input [(data_width-1):0]      d;
1319
   input [(addr_width-1):0]       adr;
1320 73 unneback
   input [(data_width/8)-1:0]    be;
1321 7 unneback
   input                         we;
1322
   output reg [(data_width-1):0] q;
1323
   input                         clk;
1324 65 unneback
`ifdef SYSTEMVERILOG
1325 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
1326 65 unneback
`else
1327 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1328
    wire [data_width/8-1:0] cke;
1329 65 unneback
`endif
1330 60 unneback
   parameter memory_init = 0;
1331 7 unneback
   parameter memory_file = "vl_ram.vmem";
1332 60 unneback
   generate if (memory_init) begin : init_mem
1333 7 unneback
   initial
1334
     begin
1335
        $readmemh(memory_file, ram);
1336
     end
1337
   end
1338
   endgenerate
1339 60 unneback
`ifdef SYSTEMVERILOG
1340
// use a multi-dimensional packed array
1341
//to model individual bytes within the word
1342
always_ff@(posedge clk)
1343
begin
1344
    if(we) begin // note: we should have a for statement to support any bus width
1345 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1346
        if(be[2]) ram[adr][2] <= d[23:16];
1347
        if(be[1]) ram[adr][1] <= d[15:8];
1348
        if(be[0]) ram[adr][0] <= d[7:0];
1349 60 unneback
    end
1350 90 unneback
        q <= ram[adr];
1351 60 unneback
end
1352
`else
1353 85 unneback
assign cke = {data_width/8{we}} & be;
1354 7 unneback
   genvar i;
1355 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1356 7 unneback
      always @ (posedge clk)
1357 85 unneback
      if (cke[i])
1358 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1359
   end
1360
   endgenerate
1361
   always @ (posedge clk)
1362
      q <= ram[adr];
1363 60 unneback
`endif
1364 93 unneback
`ifdef verilator
1365 85 unneback
   // Function to access RAM (for use by Verilator).
1366
   function [31:0] get_mem;
1367
      // verilator public
1368 90 unneback
      input [addr_width-1:0]             addr;
1369 85 unneback
      get_mem = ram[addr];
1370
   endfunction // get_mem
1371
   // Function to write RAM (for use by Verilator).
1372
   function set_mem;
1373
      // verilator public
1374 90 unneback
      input [addr_width-1:0]             addr;
1375
      input [data_width-1:0]             data;
1376 85 unneback
      ram[addr] = data;
1377
   endfunction // set_mem
1378 93 unneback
`endif
1379 7 unneback
endmodule
1380 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
1381 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1382 6 unneback
   parameter data_width = 32;
1383
   parameter addr_width = 8;
1384 75 unneback
   parameter mem_size = 1<<addr_width;
1385 6 unneback
   input [(data_width-1):0]      d_a;
1386
   input [(addr_width-1):0]       adr_a;
1387
   input [(addr_width-1):0]       adr_b;
1388
   input                         we_a;
1389
   output [(data_width-1):0]      q_b;
1390
   input                         clk_a, clk_b;
1391
   reg [(addr_width-1):0]         adr_b_reg;
1392 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1393 7 unneback
   parameter init = 0;
1394
   parameter memory_file = "vl_ram.vmem";
1395
   generate if (init) begin : init_mem
1396
   initial
1397
     begin
1398
        $readmemh(memory_file, ram);
1399
     end
1400
   end
1401
   endgenerate
1402 6 unneback
   always @ (posedge clk_a)
1403
   if (we_a)
1404
     ram[adr_a] <= d_a;
1405
   always @ (posedge clk_b)
1406
   adr_b_reg <= adr_b;
1407
   assign q_b = ram[adr_b_reg];
1408
endmodule
1409 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1410 6 unneback
   parameter data_width = 32;
1411
   parameter addr_width = 8;
1412 75 unneback
   parameter mem_size = 1<<addr_width;
1413 6 unneback
   input [(data_width-1):0]      d_a;
1414
   input [(addr_width-1):0]       adr_a;
1415
   input [(addr_width-1):0]       adr_b;
1416
   input                         we_a;
1417
   output [(data_width-1):0]      q_b;
1418
   output reg [(data_width-1):0] q_a;
1419
   input                         clk_a, clk_b;
1420
   reg [(data_width-1):0]         q_b;
1421 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1422 7 unneback
   parameter init = 0;
1423
   parameter memory_file = "vl_ram.vmem";
1424
   generate if (init) begin : init_mem
1425
   initial
1426
     begin
1427
        $readmemh(memory_file, ram);
1428
     end
1429
   end
1430
   endgenerate
1431 6 unneback
   always @ (posedge clk_a)
1432
     begin
1433
        q_a <= ram[adr_a];
1434
        if (we_a)
1435
             ram[adr_a] <= d_a;
1436
     end
1437
   always @ (posedge clk_b)
1438
          q_b <= ram[adr_b];
1439
endmodule
1440 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1441 6 unneback
   parameter data_width = 32;
1442
   parameter addr_width = 8;
1443 75 unneback
   parameter mem_size = 1<<addr_width;
1444 6 unneback
   input [(data_width-1):0]      d_a;
1445
   input [(addr_width-1):0]       adr_a;
1446
   input [(addr_width-1):0]       adr_b;
1447
   input                         we_a;
1448
   output [(data_width-1):0]      q_b;
1449
   input [(data_width-1):0]       d_b;
1450
   output reg [(data_width-1):0] q_a;
1451
   input                         we_b;
1452
   input                         clk_a, clk_b;
1453
   reg [(data_width-1):0]         q_b;
1454 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1455 7 unneback
   parameter init = 0;
1456
   parameter memory_file = "vl_ram.vmem";
1457
   generate if (init) begin : init_mem
1458
   initial
1459
     begin
1460
        $readmemh(memory_file, ram);
1461
     end
1462
   end
1463
   endgenerate
1464 6 unneback
   always @ (posedge clk_a)
1465
     begin
1466
        q_a <= ram[adr_a];
1467
        if (we_a)
1468
             ram[adr_a] <= d_a;
1469
     end
1470
   always @ (posedge clk_b)
1471
     begin
1472
        q_b <= ram[adr_b];
1473
        if (we_b)
1474
          ram[adr_b] <= d_b;
1475
     end
1476
endmodule
1477 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
1478 75 unneback
   parameter a_data_width = 32;
1479
   parameter a_addr_width = 8;
1480 92 unneback
   parameter b_data_width = a_data_width;
1481 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1482
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
1483 75 unneback
   input [(a_data_width-1):0]      d_a;
1484 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1485
   input [(a_data_width/8-1):0]    be_a;
1486
   input                           we_a;
1487 75 unneback
   output reg [(a_data_width-1):0] q_a;
1488 91 unneback
   input [(b_data_width-1):0]       d_b;
1489
   input [(b_addr_width-1):0]       adr_b;
1490 92 unneback
   input [(b_data_width/8-1):0]    be_b;
1491
   input                           we_b;
1492
   output reg [(b_data_width-1):0]          q_b;
1493 91 unneback
   input                           clk_a, clk_b;
1494
`ifdef SYSTEMVERILOG
1495
// use a multi-dimensional packed array
1496
//to model individual bytes within the word
1497 75 unneback
generate
1498 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1499
   logic [3:0][7:0] ram [0:mem_size-1];
1500
    always_ff@(posedge clk_a)
1501
    begin
1502
        if(we_a) begin
1503
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1504
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1505
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1506
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1507
        end
1508
    end
1509 92 unneback
    always@(posedge clk_a)
1510
        q_a = ram[adr_a];
1511 91 unneback
    always_ff@(posedge clk_b)
1512 92 unneback
    begin
1513
        if(we_b) begin
1514
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1515
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1516
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1517
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1518
        end
1519
    end
1520
    always@(posedge clk_b)
1521
        q_b = ram[adr_b];
1522 75 unneback
end
1523
endgenerate
1524 91 unneback
`else
1525 92 unneback
    // This modules requires SystemVerilog
1526 91 unneback
`endif
1527 75 unneback
endmodule
1528 6 unneback
// FIFO
1529 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1530
    d, wr, fifo_full,
1531
    q, rd, fifo_empty,
1532
    fill_level,
1533
    clk, rst
1534
    );
1535
parameter data_width = 18;
1536
parameter addr_width = 4;
1537
// write side
1538
input  [data_width-1:0] d;
1539
input                   wr;
1540
output                  fifo_full;
1541
// read side
1542
output [data_width-1:0] q;
1543
input                   rd;
1544
output                  fifo_empty;
1545
// common
1546
output [addr_width:0]   fill_level;
1547
input rst, clk;
1548
wire [addr_width:1] wadr, radr;
1549
vl_cnt_bin_ce
1550
    # ( .length(addr_width))
1551
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1552
vl_cnt_bin_ce
1553
    # (.length(addr_width))
1554
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1555
vl_dpram_1r1w
1556
    # (.data_width(data_width), .addr_width(addr_width))
1557
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1558 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1559 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1560 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1561
endmodule
1562 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1563
// RAM is supposed to be larger than the two FIFOs
1564
// LFSR counters used adr pointers
1565
module vl_fifo_2r2w_sync_simplex (
1566
    // a side
1567
    a_d, a_wr, a_fifo_full,
1568
    a_q, a_rd, a_fifo_empty,
1569
    a_fill_level,
1570
    // b side
1571
    b_d, b_wr, b_fifo_full,
1572
    b_q, b_rd, b_fifo_empty,
1573
    b_fill_level,
1574
    // common
1575
    clk, rst
1576
    );
1577
parameter data_width = 8;
1578
parameter addr_width = 5;
1579
parameter fifo_full_level = (1<<addr_width)-1;
1580
// a side
1581
input  [data_width-1:0] a_d;
1582
input                   a_wr;
1583
output                  a_fifo_full;
1584
output [data_width-1:0] a_q;
1585
input                   a_rd;
1586
output                  a_fifo_empty;
1587
output [addr_width-1:0] a_fill_level;
1588
// b side
1589
input  [data_width-1:0] b_d;
1590
input                   b_wr;
1591
output                  b_fifo_full;
1592
output [data_width-1:0] b_q;
1593
input                   b_rd;
1594
output                  b_fifo_empty;
1595
output [addr_width-1:0] b_fill_level;
1596
input                   clk;
1597
input                   rst;
1598
// adr_gen
1599
wire [addr_width:1] a_wadr, a_radr;
1600
wire [addr_width:1] b_wadr, b_radr;
1601
// dpram
1602
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1603
vl_cnt_lfsr_ce
1604
    # ( .length(addr_width))
1605
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1606
vl_cnt_lfsr_ce
1607
    # (.length(addr_width))
1608
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1609
vl_cnt_lfsr_ce
1610
    # ( .length(addr_width))
1611
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1612
vl_cnt_lfsr_ce
1613
    # (.length(addr_width))
1614
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1615
// mux read or write adr to DPRAM
1616
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1617
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1618
vl_dpram_2r2w
1619
    # (.data_width(data_width), .addr_width(addr_width+1))
1620
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1621
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1622
vl_cnt_bin_ce_rew_zq_l1
1623 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1624 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1625
vl_cnt_bin_ce_rew_zq_l1
1626 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1627 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1628
endmodule
1629 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1630 11 unneback
   parameter addr_width = 4;
1631
   parameter N = addr_width-1;
1632 6 unneback
   parameter Q1 = 2'b00;
1633
   parameter Q2 = 2'b01;
1634
   parameter Q3 = 2'b11;
1635
   parameter Q4 = 2'b10;
1636
   parameter going_empty = 1'b0;
1637
   parameter going_full  = 1'b1;
1638
   input [N:0]  wptr, rptr;
1639 14 unneback
   output       fifo_empty;
1640 6 unneback
   output       fifo_full;
1641
   input        wclk, rclk, rst;
1642
   wire direction;
1643
   reg  direction_set, direction_clr;
1644
   wire async_empty, async_full;
1645
   wire fifo_full2;
1646 14 unneback
   wire fifo_empty2;
1647 6 unneback
   // direction_set
1648
   always @ (wptr[N:N-1] or rptr[N:N-1])
1649
     case ({wptr[N:N-1],rptr[N:N-1]})
1650
       {Q1,Q2} : direction_set <= 1'b1;
1651
       {Q2,Q3} : direction_set <= 1'b1;
1652
       {Q3,Q4} : direction_set <= 1'b1;
1653
       {Q4,Q1} : direction_set <= 1'b1;
1654
       default : direction_set <= 1'b0;
1655
     endcase
1656
   // direction_clear
1657
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1658
     if (rst)
1659
       direction_clr <= 1'b1;
1660
     else
1661
       case ({wptr[N:N-1],rptr[N:N-1]})
1662
         {Q2,Q1} : direction_clr <= 1'b1;
1663
         {Q3,Q2} : direction_clr <= 1'b1;
1664
         {Q4,Q3} : direction_clr <= 1'b1;
1665
         {Q1,Q4} : direction_clr <= 1'b1;
1666
         default : direction_clr <= 1'b0;
1667
       endcase
1668 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1669 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1670
   assign async_full  = (wptr == rptr) && (direction==going_full);
1671 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1672
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1673 6 unneback
/*
1674
   always @ (posedge wclk or posedge rst or posedge async_full)
1675
     if (rst)
1676
       {fifo_full, fifo_full2} <= 2'b00;
1677
     else if (async_full)
1678
       {fifo_full, fifo_full2} <= 2'b11;
1679
     else
1680
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1681
*/
1682 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1683 6 unneback
     if (async_empty)
1684
       {fifo_empty, fifo_empty2} <= 2'b11;
1685
     else
1686 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1687 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1688
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1689 27 unneback
endmodule // async_compb
1690 6 unneback
module vl_fifo_1r1w_async (
1691
    d, wr, fifo_full, wr_clk, wr_rst,
1692
    q, rd, fifo_empty, rd_clk, rd_rst
1693
    );
1694
parameter data_width = 18;
1695
parameter addr_width = 4;
1696
// write side
1697
input  [data_width-1:0] d;
1698
input                   wr;
1699
output                  fifo_full;
1700
input                   wr_clk;
1701
input                   wr_rst;
1702
// read side
1703
output [data_width-1:0] q;
1704
input                   rd;
1705
output                  fifo_empty;
1706
input                   rd_clk;
1707
input                   rd_rst;
1708
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1709 18 unneback
vl_cnt_gray_ce_bin
1710 6 unneback
    # ( .length(addr_width))
1711
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1712 18 unneback
vl_cnt_gray_ce_bin
1713 6 unneback
    # (.length(addr_width))
1714 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1715 7 unneback
vl_dpram_1r1w
1716 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1717
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1718
vl_fifo_cmp_async
1719
    # (.addr_width(addr_width))
1720
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1721
endmodule
1722 8 unneback
module vl_fifo_2r2w_async (
1723 6 unneback
    // a side
1724
    a_d, a_wr, a_fifo_full,
1725
    a_q, a_rd, a_fifo_empty,
1726
    a_clk, a_rst,
1727
    // b side
1728
    b_d, b_wr, b_fifo_full,
1729
    b_q, b_rd, b_fifo_empty,
1730
    b_clk, b_rst
1731
    );
1732
parameter data_width = 18;
1733
parameter addr_width = 4;
1734
// a side
1735
input  [data_width-1:0] a_d;
1736
input                   a_wr;
1737
output                  a_fifo_full;
1738
output [data_width-1:0] a_q;
1739
input                   a_rd;
1740
output                  a_fifo_empty;
1741
input                   a_clk;
1742
input                   a_rst;
1743
// b side
1744
input  [data_width-1:0] b_d;
1745
input                   b_wr;
1746
output                  b_fifo_full;
1747
output [data_width-1:0] b_q;
1748
input                   b_rd;
1749
output                  b_fifo_empty;
1750
input                   b_clk;
1751
input                   b_rst;
1752
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1753
vl_fifo_1r1w_async_a (
1754
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1755
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1756
    );
1757
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1758
vl_fifo_1r1w_async_b (
1759
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1760
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1761
    );
1762
endmodule
1763 8 unneback
module vl_fifo_2r2w_async_simplex (
1764 6 unneback
    // a side
1765
    a_d, a_wr, a_fifo_full,
1766
    a_q, a_rd, a_fifo_empty,
1767
    a_clk, a_rst,
1768
    // b side
1769
    b_d, b_wr, b_fifo_full,
1770
    b_q, b_rd, b_fifo_empty,
1771
    b_clk, b_rst
1772
    );
1773
parameter data_width = 18;
1774
parameter addr_width = 4;
1775
// a side
1776
input  [data_width-1:0] a_d;
1777
input                   a_wr;
1778
output                  a_fifo_full;
1779
output [data_width-1:0] a_q;
1780
input                   a_rd;
1781
output                  a_fifo_empty;
1782
input                   a_clk;
1783
input                   a_rst;
1784
// b side
1785
input  [data_width-1:0] b_d;
1786
input                   b_wr;
1787
output                  b_fifo_full;
1788
output [data_width-1:0] b_q;
1789
input                   b_rd;
1790
output                  b_fifo_empty;
1791
input                   b_clk;
1792
input                   b_rst;
1793
// adr_gen
1794
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1795
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1796
// dpram
1797
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1798 18 unneback
vl_cnt_gray_ce_bin
1799 6 unneback
    # ( .length(addr_width))
1800
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1801 18 unneback
vl_cnt_gray_ce_bin
1802 6 unneback
    # (.length(addr_width))
1803
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1804 18 unneback
vl_cnt_gray_ce_bin
1805 6 unneback
    # ( .length(addr_width))
1806
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1807 18 unneback
vl_cnt_gray_ce_bin
1808 6 unneback
    # (.length(addr_width))
1809
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1810
// mux read or write adr to DPRAM
1811
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1812
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1813 11 unneback
vl_dpram_2r2w
1814 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1815
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1816
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1817 11 unneback
vl_fifo_cmp_async
1818 6 unneback
    # (.addr_width(addr_width))
1819
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1820 11 unneback
vl_fifo_cmp_async
1821 6 unneback
    # (.addr_width(addr_width))
1822
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1823
endmodule
1824 48 unneback
module vl_reg_file (
1825
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1826
);
1827
parameter data_width = 32;
1828
parameter addr_width = 5;
1829
input [addr_width-1:0] a1, a2, a3;
1830
input [data_width-1:0] wd3;
1831
input we3;
1832
output [data_width-1:0] rd1, rd2;
1833
input clk;
1834
reg [data_width-1:0] wd3_reg;
1835
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
1836
reg we3_reg;
1837
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1838
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1839
always @ (posedge clk or posedge rst)
1840
if (rst)
1841
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
1842
else
1843
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
1844
    always @ (negedge clk)
1845
    if (we3_reg)
1846
        ram1[a3_reg] <= wd3;
1847
    always @ (posedge clk)
1848
        a1_reg <= a1;
1849
    assign rd1 = ram1[a1_reg];
1850
    always @ (negedge clk)
1851
    if (we3_reg)
1852
        ram2[a3_reg] <= wd3;
1853
    always @ (posedge clk)
1854
        a2_reg <= a2;
1855
    assign rd2 = ram2[a2_reg];
1856
endmodule
1857 12 unneback
//////////////////////////////////////////////////////////////////////
1858
////                                                              ////
1859
////  Versatile library, wishbone stuff                           ////
1860
////                                                              ////
1861
////  Description                                                 ////
1862
////  Wishbone compliant modules                                  ////
1863
////                                                              ////
1864
////                                                              ////
1865
////  To Do:                                                      ////
1866
////   -                                                          ////
1867
////                                                              ////
1868
////  Author(s):                                                  ////
1869
////      - Michael Unneback, unneback@opencores.org              ////
1870
////        ORSoC AB                                              ////
1871
////                                                              ////
1872
//////////////////////////////////////////////////////////////////////
1873
////                                                              ////
1874
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1875
////                                                              ////
1876
//// This source file may be used and distributed without         ////
1877
//// restriction provided that this copyright statement is not    ////
1878
//// removed from the file and that any derivative work contains  ////
1879
//// the original copyright notice and the associated disclaimer. ////
1880
////                                                              ////
1881
//// This source file is free software; you can redistribute it   ////
1882
//// and/or modify it under the terms of the GNU Lesser General   ////
1883
//// Public License as published by the Free Software Foundation; ////
1884
//// either version 2.1 of the License, or (at your option) any   ////
1885
//// later version.                                               ////
1886
////                                                              ////
1887
//// This source is distributed in the hope that it will be       ////
1888
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1889
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1890
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1891
//// details.                                                     ////
1892
////                                                              ////
1893
//// You should have received a copy of the GNU Lesser General    ////
1894
//// Public License along with this source; if not, download it   ////
1895
//// from http://www.opencores.org/lgpl.shtml                     ////
1896
////                                                              ////
1897
//////////////////////////////////////////////////////////////////////
1898
// async wb3 - wb3 bridge
1899
`timescale 1ns/1ns
1900 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
1901 83 unneback
parameter adr_width = 10;
1902
parameter max_burst_width = 4;
1903 85 unneback
input cyc_i, stb_i, we_i;
1904 83 unneback
input [2:0] cti_i;
1905
input [1:0] bte_i;
1906
input [adr_width-1:0] adr_i;
1907
output [adr_width-1:0] adr_o;
1908
output ack_o;
1909
input clk, rst;
1910
reg [adr_width-1:0] adr;
1911 90 unneback
wire [max_burst_width-1:0] to_adr;
1912 91 unneback
reg [max_burst_width-1:0] last_adr;
1913 92 unneback
reg last_cycle;
1914
localparam idle_or_eoc = 1'b0;
1915
localparam cyc_or_ws   = 1'b1;
1916 91 unneback
always @ (posedge clk or posedge rst)
1917
if (rst)
1918
    last_adr <= {max_burst_width{1'b0}};
1919
else
1920
    if (stb_i)
1921 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
1922 83 unneback
generate
1923
if (max_burst_width==0) begin : inst_0
1924
    reg ack_o;
1925
    assign adr_o = adr_i;
1926
    always @ (posedge clk or posedge rst)
1927
    if (rst)
1928
        ack_o <= 1'b0;
1929
    else
1930
        ack_o <= cyc_i & stb_i & !ack_o;
1931
end else begin
1932
    always @ (posedge clk or posedge rst)
1933
    if (rst)
1934 92 unneback
        last_cycle <= idle_or_eoc;
1935 83 unneback
    else
1936 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
1937
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
1938
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
1939
                      cyc_or_ws; // cyc
1940
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
1941 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
1942 91 unneback
                                        (!stb_i) ? last_adr :
1943 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
1944 85 unneback
                                        adr[max_burst_width-1:0];
1945 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
1946 83 unneback
end
1947
endgenerate
1948
generate
1949
if (max_burst_width==2) begin : inst_2
1950
    always @ (posedge clk or posedge rst)
1951
    if (rst)
1952
        adr <= 2'h0;
1953
    else
1954
        if (cyc_i & stb_i)
1955
            adr[1:0] <= to_adr[1:0] + 2'd1;
1956
        else
1957
            adr <= to_adr[1:0];
1958
end
1959
endgenerate
1960
generate
1961
if (max_burst_width==3) begin : inst_3
1962
    always @ (posedge clk or posedge rst)
1963
    if (rst)
1964
        adr <= 3'h0;
1965
    else
1966
        if (cyc_i & stb_i)
1967
            case (bte_i)
1968
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
1969
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
1970
            endcase
1971
        else
1972
            adr <= to_adr[2:0];
1973
end
1974
endgenerate
1975
generate
1976
if (max_burst_width==4) begin : inst_4
1977
    always @ (posedge clk or posedge rst)
1978
    if (rst)
1979
        adr <= 4'h0;
1980
    else
1981 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
1982 83 unneback
            case (bte_i)
1983
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
1984
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
1985
            default: adr[3:0] <= to_adr + 4'd1;
1986
            endcase
1987
        else
1988
            adr <= to_adr[3:0];
1989
end
1990
endgenerate
1991
generate
1992
if (adr_width > max_burst_width) begin : pass_through
1993
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
1994
end
1995
endgenerate
1996
endmodule
1997
// async wb3 - wb3 bridge
1998
`timescale 1ns/1ns
1999 18 unneback
module vl_wb3wb3_bridge (
2000 12 unneback
        // wishbone slave side
2001
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2002
        // wishbone master side
2003
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2004
input [31:0] wbs_dat_i;
2005
input [31:2] wbs_adr_i;
2006
input [3:0]  wbs_sel_i;
2007
input [1:0]  wbs_bte_i;
2008
input [2:0]  wbs_cti_i;
2009
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2010
output [31:0] wbs_dat_o;
2011 14 unneback
output wbs_ack_o;
2012 12 unneback
input wbs_clk, wbs_rst;
2013
output [31:0] wbm_dat_o;
2014
output reg [31:2] wbm_adr_o;
2015
output [3:0]  wbm_sel_o;
2016
output reg [1:0]  wbm_bte_o;
2017
output reg [2:0]  wbm_cti_o;
2018 14 unneback
output reg wbm_we_o;
2019
output wbm_cyc_o;
2020 12 unneback
output wbm_stb_o;
2021
input [31:0]  wbm_dat_i;
2022
input wbm_ack_i;
2023
input wbm_clk, wbm_rst;
2024
parameter addr_width = 4;
2025
// bte
2026
parameter linear       = 2'b00;
2027
parameter wrap4        = 2'b01;
2028
parameter wrap8        = 2'b10;
2029
parameter wrap16       = 2'b11;
2030
// cti
2031
parameter classic      = 3'b000;
2032
parameter incburst     = 3'b010;
2033
parameter endofburst   = 3'b111;
2034
parameter wbs_adr  = 1'b0;
2035
parameter wbs_data = 1'b1;
2036 33 unneback
parameter wbm_adr0      = 2'b00;
2037
parameter wbm_adr1      = 2'b01;
2038
parameter wbm_data      = 2'b10;
2039
parameter wbm_data_wait = 2'b11;
2040 12 unneback
reg [1:0] wbs_bte_reg;
2041
reg wbs;
2042
wire wbs_eoc_alert, wbm_eoc_alert;
2043
reg wbs_eoc, wbm_eoc;
2044
reg [1:0] wbm;
2045 14 unneback
wire [1:16] wbs_count, wbm_count;
2046 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2047
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2048
reg a_rd_reg;
2049
wire b_rd_adr, b_rd_data;
2050 14 unneback
wire b_rd_data_reg;
2051
wire [35:0] temp;
2052 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2053
always @ (posedge wbs_clk or posedge wbs_rst)
2054
if (wbs_rst)
2055
        wbs_eoc <= 1'b0;
2056
else
2057
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2058 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
2059 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
2060
                wbs_eoc <= 1'b1;
2061 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2062 12 unneback
    cnt0 (
2063
        .cke(wbs_ack_o),
2064
        .clear(wbs_eoc),
2065
        .q(wbs_count),
2066
        .rst(wbs_rst),
2067
        .clk(wbs_clk));
2068
always @ (posedge wbs_clk or posedge wbs_rst)
2069
if (wbs_rst)
2070
        wbs <= wbs_adr;
2071
else
2072 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
2073 12 unneback
                wbs <= wbs_data;
2074
        else if (wbs_eoc & wbs_ack_o)
2075
                wbs <= wbs_adr;
2076
// wbs FIFO
2077 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
2078
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
2079 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2080
              1'b0;
2081
assign a_rd = !a_fifo_empty;
2082
always @ (posedge wbs_clk or posedge wbs_rst)
2083
if (wbs_rst)
2084
        a_rd_reg <= 1'b0;
2085
else
2086
        a_rd_reg <= a_rd;
2087
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2088
assign wbs_dat_o = a_q[35:4];
2089
always @ (posedge wbs_clk or posedge wbs_rst)
2090
if (wbs_rst)
2091 13 unneback
        wbs_bte_reg <= 2'b00;
2092 12 unneback
else
2093 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2094 12 unneback
// wbm FIFO
2095
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2096
always @ (posedge wbm_clk or posedge wbm_rst)
2097
if (wbm_rst)
2098
        wbm_eoc <= 1'b0;
2099
else
2100
        if (wbm==wbm_adr0 & !b_fifo_empty)
2101
                wbm_eoc <= b_q[4:3] == linear;
2102
        else if (wbm_eoc_alert & wbm_ack_i)
2103
                wbm_eoc <= 1'b1;
2104
always @ (posedge wbm_clk or posedge wbm_rst)
2105
if (wbm_rst)
2106
        wbm <= wbm_adr0;
2107
else
2108 33 unneback
/*
2109 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2110
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2111
        (wbm==wbm_adr1 & !wbm_we_o) |
2112
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2113
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2114 33 unneback
*/
2115
    case (wbm)
2116
    wbm_adr0:
2117
        if (!b_fifo_empty)
2118
            wbm <= wbm_adr1;
2119
    wbm_adr1:
2120
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
2121
            wbm <= wbm_data;
2122
    wbm_data:
2123
        if (wbm_ack_i & wbm_eoc)
2124
            wbm <= wbm_adr0;
2125
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
2126
            wbm <= wbm_data_wait;
2127
    wbm_data_wait:
2128
        if (!b_fifo_empty)
2129
            wbm <= wbm_data;
2130
    endcase
2131 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
2132
assign b_wr = !wbm_we_o & wbm_ack_i;
2133
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2134
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2135
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2136 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
2137 12 unneback
                   1'b0;
2138
assign b_rd = b_rd_adr | b_rd_data;
2139 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2140
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2141 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2142 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2143 12 unneback
    cnt1 (
2144
        .cke(wbm_ack_i),
2145
        .clear(wbm_eoc),
2146
        .q(wbm_count),
2147
        .rst(wbm_rst),
2148
        .clk(wbm_clk));
2149 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
2150
assign wbm_stb_o = (wbm==wbm_data);
2151 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
2152
if (wbm_rst)
2153
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2154
else begin
2155
        if (wbm==wbm_adr0 & !b_fifo_empty)
2156
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2157
        else if (wbm_eoc_alert & wbm_ack_i)
2158
                wbm_cti_o <= endofburst;
2159
end
2160
//async_fifo_dw_simplex_top
2161
vl_fifo_2r2w_async_simplex
2162
# ( .data_width(36), .addr_width(addr_width))
2163
fifo (
2164
    // a side
2165
    .a_d(a_d),
2166
    .a_wr(a_wr),
2167
    .a_fifo_full(a_fifo_full),
2168
    .a_q(a_q),
2169
    .a_rd(a_rd),
2170
    .a_fifo_empty(a_fifo_empty),
2171
    .a_clk(wbs_clk),
2172
    .a_rst(wbs_rst),
2173
    // b side
2174
    .b_d(b_d),
2175
    .b_wr(b_wr),
2176
    .b_fifo_full(b_fifo_full),
2177
    .b_q(b_q),
2178
    .b_rd(b_rd),
2179
    .b_fifo_empty(b_fifo_empty),
2180
    .b_clk(wbm_clk),
2181
    .b_rst(wbm_rst)
2182
    );
2183
endmodule
2184 75 unneback
module vl_wb3avalon_bridge (
2185
        // wishbone slave side
2186
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2187 77 unneback
        // avalon master side
2188 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
2189 85 unneback
parameter linewrapburst = 1'b0;
2190 75 unneback
input [31:0] wbs_dat_i;
2191
input [31:2] wbs_adr_i;
2192
input [3:0]  wbs_sel_i;
2193
input [1:0]  wbs_bte_i;
2194
input [2:0]  wbs_cti_i;
2195 83 unneback
input wbs_we_i;
2196
input wbs_cyc_i;
2197
input wbs_stb_i;
2198 75 unneback
output [31:0] wbs_dat_o;
2199
output wbs_ack_o;
2200
input wbs_clk, wbs_rst;
2201
input [31:0] readdata;
2202
output [31:0] writedata;
2203
output [31:2] address;
2204
output [3:0]  be;
2205
output write;
2206 81 unneback
output read;
2207 75 unneback
output beginbursttransfer;
2208
output [3:0] burstcount;
2209
input readdatavalid;
2210
input waitrequest;
2211
input clk;
2212
input rst;
2213
wire [1:0] wbm_bte_o;
2214
wire [2:0] wbm_cti_o;
2215
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
2216
reg last_cyc;
2217 79 unneback
reg [3:0] counter;
2218 82 unneback
reg read_busy;
2219 75 unneback
always @ (posedge clk or posedge rst)
2220
if (rst)
2221
    last_cyc <= 1'b0;
2222
else
2223
    last_cyc <= wbm_cyc_o;
2224 79 unneback
always @ (posedge clk or posedge rst)
2225
if (rst)
2226 82 unneback
    read_busy <= 1'b0;
2227 79 unneback
else
2228 82 unneback
    if (read & !waitrequest)
2229
        read_busy <= 1'b1;
2230
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
2231
        read_busy <= 1'b0;
2232
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
2233 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
2234
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
2235
                    (wbm_bte_o==2'b10) ? 4'd8 :
2236 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
2237
                    4'd1;
2238 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
2239 79 unneback
always @ (posedge clk or posedge rst)
2240
if (rst) begin
2241
    counter <= 4'd0;
2242
end else
2243 80 unneback
    if (wbm_we_o) begin
2244
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
2245 85 unneback
            counter <= burstcount -4'd1;
2246 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
2247
            counter <= burstcount;
2248
        end else if (!waitrequest & wbm_stb_o) begin
2249
            counter <= counter - 4'd1;
2250
        end
2251 82 unneback
    end
2252 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
2253 77 unneback
vl_wb3wb3_bridge wbwb3inst (
2254 75 unneback
    // wishbone slave side
2255
    .wbs_dat_i(wbs_dat_i),
2256
    .wbs_adr_i(wbs_adr_i),
2257
    .wbs_sel_i(wbs_sel_i),
2258
    .wbs_bte_i(wbs_bte_i),
2259
    .wbs_cti_i(wbs_cti_i),
2260
    .wbs_we_i(wbs_we_i),
2261
    .wbs_cyc_i(wbs_cyc_i),
2262
    .wbs_stb_i(wbs_stb_i),
2263
    .wbs_dat_o(wbs_dat_o),
2264
    .wbs_ack_o(wbs_ack_o),
2265
    .wbs_clk(wbs_clk),
2266
    .wbs_rst(wbs_rst),
2267
    // wishbone master side
2268
    .wbm_dat_o(writedata),
2269 78 unneback
    .wbm_adr_o(address),
2270 75 unneback
    .wbm_sel_o(be),
2271
    .wbm_bte_o(wbm_bte_o),
2272
    .wbm_cti_o(wbm_cti_o),
2273
    .wbm_we_o(wbm_we_o),
2274
    .wbm_cyc_o(wbm_cyc_o),
2275
    .wbm_stb_o(wbm_stb_o),
2276
    .wbm_dat_i(readdata),
2277
    .wbm_ack_i(wbm_ack_i),
2278
    .wbm_clk(clk),
2279
    .wbm_rst(rst));
2280
endmodule
2281 39 unneback
module vl_wb3_arbiter_type1 (
2282
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
2283
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
2284
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
2285
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
2286
    wb_clk, wb_rst
2287
);
2288
parameter nr_of_ports = 3;
2289
parameter adr_size = 26;
2290
parameter adr_lo   = 2;
2291
parameter dat_size = 32;
2292
parameter sel_size = dat_size/8;
2293
localparam aw = (adr_size - adr_lo) * nr_of_ports;
2294
localparam dw = dat_size * nr_of_ports;
2295
localparam sw = sel_size * nr_of_ports;
2296
localparam cw = 3 * nr_of_ports;
2297
localparam bw = 2 * nr_of_ports;
2298
input  [dw-1:0] wbm_dat_o;
2299
input  [aw-1:0] wbm_adr_o;
2300
input  [sw-1:0] wbm_sel_o;
2301
input  [cw-1:0] wbm_cti_o;
2302
input  [bw-1:0] wbm_bte_o;
2303
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
2304
output [dw-1:0] wbm_dat_i;
2305
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
2306
output [dat_size-1:0] wbs_dat_i;
2307
output [adr_size-1:adr_lo] wbs_adr_i;
2308
output [sel_size-1:0] wbs_sel_i;
2309
output [2:0] wbs_cti_i;
2310
output [1:0] wbs_bte_i;
2311
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
2312
input  [dat_size-1:0] wbs_dat_o;
2313
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
2314
input wb_clk, wb_rst;
2315 44 unneback
reg  [nr_of_ports-1:0] select;
2316 39 unneback
wire [nr_of_ports-1:0] state;
2317
wire [nr_of_ports-1:0] eoc; // end-of-cycle
2318
wire [nr_of_ports-1:0] sel;
2319
wire idle;
2320
genvar i;
2321
assign idle = !(|state);
2322
generate
2323
if (nr_of_ports == 2) begin
2324
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
2325
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2326 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2327
    always @ (idle or wbm_cyc_o)
2328
    if (idle)
2329
        casex (wbm_cyc_o)
2330
        2'b1x : select = 2'b10;
2331
        2'b01 : select = 2'b01;
2332
        default : select = {nr_of_ports{1'b0}};
2333
        endcase
2334
    else
2335
        select = {nr_of_ports{1'b0}};
2336 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2337
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2338
end
2339
endgenerate
2340
generate
2341
if (nr_of_ports == 3) begin
2342
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2343
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2344 44 unneback
    always @ (idle or wbm_cyc_o)
2345
    if (idle)
2346
        casex (wbm_cyc_o)
2347
        3'b1xx : select = 3'b100;
2348
        3'b01x : select = 3'b010;
2349
        3'b001 : select = 3'b001;
2350
        default : select = {nr_of_ports{1'b0}};
2351
        endcase
2352
    else
2353
        select = {nr_of_ports{1'b0}};
2354
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2355 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2356
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2357
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2358
end
2359
endgenerate
2360
generate
2361 44 unneback
if (nr_of_ports == 4) begin
2362
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2363
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2364
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2365
    always @ (idle or wbm_cyc_o)
2366
    if (idle)
2367
        casex (wbm_cyc_o)
2368
        4'b1xxx : select = 4'b1000;
2369
        4'b01xx : select = 4'b0100;
2370
        4'b001x : select = 4'b0010;
2371
        4'b0001 : select = 4'b0001;
2372
        default : select = {nr_of_ports{1'b0}};
2373
        endcase
2374
    else
2375
        select = {nr_of_ports{1'b0}};
2376
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
2377
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2378
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o