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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Blame information for rev 98

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Line No. Rev Author Line
1 60 unneback
// default SYN_KEEP definition
2 98 unneback
    // ACTEL FPGA should not use logic to handle rw collision
3 97 unneback
// size to width
4 6 unneback
//////////////////////////////////////////////////////////////////////
5
////                                                              ////
6
////  Versatile library, clock and reset                          ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Logic related to clock and reset                            ////
10
////                                                              ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - add more different registers                             ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Michael Unneback, unneback@opencores.org              ////
17
////        ORSoC AB                                              ////
18
////                                                              ////
19
//////////////////////////////////////////////////////////////////////
20
////                                                              ////
21
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
22
////                                                              ////
23
//// This source file may be used and distributed without         ////
24
//// restriction provided that this copyright statement is not    ////
25
//// removed from the file and that any derivative work contains  ////
26
//// the original copyright notice and the associated disclaimer. ////
27
////                                                              ////
28
//// This source file is free software; you can redistribute it   ////
29
//// and/or modify it under the terms of the GNU Lesser General   ////
30
//// Public License as published by the Free Software Foundation; ////
31
//// either version 2.1 of the License, or (at your option) any   ////
32
//// later version.                                               ////
33
////                                                              ////
34
//// This source is distributed in the hope that it will be       ////
35
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
36
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
37
//// PURPOSE.  See the GNU Lesser General Public License for more ////
38
//// details.                                                     ////
39
////                                                              ////
40
//// You should have received a copy of the GNU Lesser General    ////
41
//// Public License along with this source; if not, download it   ////
42
//// from http://www.opencores.org/lgpl.shtml                     ////
43
////                                                              ////
44
//////////////////////////////////////////////////////////////////////
45 48 unneback
`timescale 1 ns/100 ps
46 6 unneback
// Global buffer
47
// usage:
48
// use to enable global buffers for high fan out signals such as clock and reset
49
// Version: 8.4 8.4.0.33
50
module gbuf(GL,CLK);
51
output GL;
52
input  CLK;
53
    wire GND;
54
    GND GND_1_net(.Y(GND));
55
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
56
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
57
endmodule
58
`timescale 1 ns/1 ns
59
module vl_gbuf ( i, o);
60
input i;
61
output o;
62
`ifdef SIM_GBUF
63
assign o=i;
64
`else
65
gbuf gbuf_i0 ( .CLK(i), .GL(o));
66
`endif
67
endmodule
68
 //ACTEL
69
// sync reset
70 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
71 6 unneback
// output active high global reset sync with two DFFs 
72
`timescale 1 ns/100 ps
73
module vl_sync_rst ( rst_n_i, rst_o, clk);
74
input rst_n_i, clk;
75
output rst_o;
76 18 unneback
reg [1:0] tmp;
77 6 unneback
always @ (posedge clk or negedge rst_n_i)
78
if (!rst_n_i)
79 17 unneback
        tmp <= 2'b11;
80 6 unneback
else
81 33 unneback
        tmp <= {1'b0,tmp[1]};
82 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
83 6 unneback
endmodule
84
// vl_pll
85 32 unneback
///////////////////////////////////////////////////////////////////////////////
86 17 unneback
`timescale 1 ps/1 ps
87 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
88
parameter index = 0;
89
parameter number_of_clk = 1;
90 17 unneback
parameter period_time_0 = 20000;
91
parameter period_time_1 = 20000;
92
parameter period_time_2 = 20000;
93
parameter lock_delay = 2000000;
94 6 unneback
input clk_i, rst_n_i;
95
output lock;
96
output reg [0:number_of_clk-1] clk_o;
97
output [0:number_of_clk-1] rst_o;
98
`ifdef SIM_PLL
99
always
100
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
101
generate if (number_of_clk > 1)
102
always
103
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
104
endgenerate
105
generate if (number_of_clk > 2)
106
always
107
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
108
endgenerate
109
genvar i;
110
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
111
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
112
end
113
endgenerate
114
assign #lock_delay lock = rst_n_i;
115
endmodule
116
`else
117
generate if (number_of_clk==1 & index==0) begin
118
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==0
121
generate if (number_of_clk==1 & index==1) begin
122
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==1
125
generate if (number_of_clk==1 & index==2) begin
126
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==2
129
generate if (number_of_clk==1 & index==3) begin
130
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==0) begin
134
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==0
137
generate if (number_of_clk==2 & index==1) begin
138
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==1
141
generate if (number_of_clk==2 & index==2) begin
142
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==2
145
generate if (number_of_clk==2 & index==3) begin
146
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==0) begin
150
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==0
153
generate if (number_of_clk==3 & index==1) begin
154
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==1
157
generate if (number_of_clk==3 & index==2) begin
158
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==2
161
generate if (number_of_clk==3 & index==3) begin
162
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
163
end
164
endgenerate // index==0
165
genvar i;
166
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
167 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
168 6 unneback
end
169
endgenerate
170
endmodule
171
`endif
172 32 unneback
///////////////////////////////////////////////////////////////////////////////
173 6 unneback
 //actel
174
//////////////////////////////////////////////////////////////////////
175
////                                                              ////
176
////  Versatile library, registers                                ////
177
////                                                              ////
178
////  Description                                                 ////
179
////  Different type of registers                                 ////
180
////                                                              ////
181
////                                                              ////
182
////  To Do:                                                      ////
183
////   - add more different registers                             ////
184
////                                                              ////
185
////  Author(s):                                                  ////
186
////      - Michael Unneback, unneback@opencores.org              ////
187
////        ORSoC AB                                              ////
188
////                                                              ////
189
//////////////////////////////////////////////////////////////////////
190
////                                                              ////
191
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
192
////                                                              ////
193
//// This source file may be used and distributed without         ////
194
//// restriction provided that this copyright statement is not    ////
195
//// removed from the file and that any derivative work contains  ////
196
//// the original copyright notice and the associated disclaimer. ////
197
////                                                              ////
198
//// This source file is free software; you can redistribute it   ////
199
//// and/or modify it under the terms of the GNU Lesser General   ////
200
//// Public License as published by the Free Software Foundation; ////
201
//// either version 2.1 of the License, or (at your option) any   ////
202
//// later version.                                               ////
203
////                                                              ////
204
//// This source is distributed in the hope that it will be       ////
205
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
206
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
207
//// PURPOSE.  See the GNU Lesser General Public License for more ////
208
//// details.                                                     ////
209
////                                                              ////
210
//// You should have received a copy of the GNU Lesser General    ////
211
//// Public License along with this source; if not, download it   ////
212
//// from http://www.opencores.org/lgpl.shtml                     ////
213
////                                                              ////
214
//////////////////////////////////////////////////////////////////////
215 18 unneback
module vl_dff ( d, q, clk, rst);
216 6 unneback
        parameter width = 1;
217
        parameter reset_value = 0;
218
        input [width-1:0] d;
219
        input clk, rst;
220
        output reg [width-1:0] q;
221
        always @ (posedge clk or posedge rst)
222
        if (rst)
223
                q <= reset_value;
224
        else
225
                q <= d;
226
endmodule
227 18 unneback
module vl_dff_array ( d, q, clk, rst);
228 6 unneback
        parameter width = 1;
229
        parameter depth = 2;
230
        parameter reset_value = 1'b0;
231
        input [width-1:0] d;
232
        input clk, rst;
233
        output [width-1:0] q;
234
        reg  [0:depth-1] q_tmp [width-1:0];
235
        integer i;
236
        always @ (posedge clk or posedge rst)
237
        if (rst) begin
238
            for (i=0;i<depth;i=i+1)
239
                q_tmp[i] <= {width{reset_value}};
240
        end else begin
241
            q_tmp[0] <= d;
242
            for (i=1;i<depth;i=i+1)
243
                q_tmp[i] <= q_tmp[i-1];
244
        end
245
    assign q = q_tmp[depth-1];
246
endmodule
247 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
248 6 unneback
        parameter width = 1;
249
        parameter reset_value = 0;
250
        input [width-1:0] d;
251
        input ce, clk, rst;
252
        output reg [width-1:0] q;
253
        always @ (posedge clk or posedge rst)
254
        if (rst)
255
                q <= reset_value;
256
        else
257
                if (ce)
258
                        q <= d;
259
endmodule
260 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
261 8 unneback
        parameter width = 1;
262
        parameter reset_value = 0;
263
        input [width-1:0] d;
264 10 unneback
        input ce, clear, clk, rst;
265 8 unneback
        output reg [width-1:0] q;
266
        always @ (posedge clk or posedge rst)
267
        if (rst)
268
            q <= reset_value;
269
        else
270
            if (ce)
271
                if (clear)
272
                    q <= {width{1'b0}};
273
                else
274
                    q <= d;
275
endmodule
276 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
277
        parameter width = 1;
278
        parameter reset_value = 0;
279
        input [width-1:0] d;
280
        input ce, set, clk, rst;
281
        output reg [width-1:0] q;
282
        always @ (posedge clk or posedge rst)
283
        if (rst)
284
            q <= reset_value;
285
        else
286
            if (ce)
287
                if (set)
288
                    q <= {width{1'b1}};
289
                else
290
                    q <= d;
291
endmodule
292 29 unneback
module vl_spr ( sp, r, q, clk, rst);
293 64 unneback
        //parameter width = 1;
294
        parameter reset_value = 1'b0;
295 29 unneback
        input sp, r;
296
        output reg q;
297
        input clk, rst;
298
        always @ (posedge clk or posedge rst)
299
        if (rst)
300
            q <= reset_value;
301
        else
302
            if (sp)
303
                q <= 1'b1;
304
            else if (r)
305
                q <= 1'b0;
306
endmodule
307
module vl_srp ( s, rp, q, clk, rst);
308
        parameter width = 1;
309
        parameter reset_value = 0;
310
        input s, rp;
311
        output reg q;
312
        input clk, rst;
313
        always @ (posedge clk or posedge rst)
314
        if (rst)
315
            q <= reset_value;
316
        else
317
            if (rp)
318
                q <= 1'b0;
319
            else if (s)
320
                q <= 1'b1;
321
endmodule
322 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
323 6 unneback
    input         aclr;
324
    input         aset;
325
    input         clock;
326
    input         data;
327
    output reg    q;
328
   always @ (posedge clock or posedge aclr or posedge aset)
329
     if (aclr)
330
       q <= 1'b0;
331
     else if (aset)
332
       q <= 1'b1;
333
     else
334
       q <= data;
335
endmodule
336
// LATCH
337
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
338 40 unneback
module vl_latch ( d, le, q, clk);
339 6 unneback
input d, le;
340 48 unneback
input clk;
341
always @ (le or d)
342 60 unneback
if (le)
343 48 unneback
    d <= q;
344 6 unneback
endmodule
345 18 unneback
module vl_shreg ( d, q, clk, rst);
346 17 unneback
parameter depth = 10;
347
input d;
348
output q;
349
input clk, rst;
350
reg [1:depth] dffs;
351
always @ (posedge clk or posedge rst)
352
if (rst)
353
    dffs <= {depth{1'b0}};
354
else
355
    dffs <= {d,dffs[1:depth-1]};
356
assign q = dffs[depth];
357
endmodule
358 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
359 17 unneback
parameter depth = 10;
360
input d, ce;
361
output q;
362
input clk, rst;
363
reg [1:depth] dffs;
364
always @ (posedge clk or posedge rst)
365
if (rst)
366
    dffs <= {depth{1'b0}};
367
else
368
    if (ce)
369
        dffs <= {d,dffs[1:depth-1]};
370
assign q = dffs[depth];
371
endmodule
372 18 unneback
module vl_delay ( d, q, clk, rst);
373 15 unneback
parameter depth = 10;
374
input d;
375
output q;
376
input clk, rst;
377
reg [1:depth] dffs;
378
always @ (posedge clk or posedge rst)
379
if (rst)
380
    dffs <= {depth{1'b0}};
381
else
382
    dffs <= {d,dffs[1:depth-1]};
383
assign q = dffs[depth];
384
endmodule
385 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
386 17 unneback
parameter depth = 10;
387
input d;
388
output q, emptyflag;
389
input clk, rst;
390
reg [1:depth] dffs;
391
always @ (posedge clk or posedge rst)
392
if (rst)
393
    dffs <= {depth{1'b0}};
394
else
395
    dffs <= {d,dffs[1:depth-1]};
396
assign q = dffs[depth];
397
assign emptyflag = !(|dffs);
398
endmodule
399 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
400 94 unneback
input pl;
401 98 unneback
output reg q;
402 94 unneback
input clk, rst;
403
always @ (posedge clk or posedge rst)
404
if (rst)
405
    q <= 1'b0;
406
else
407
    q <= pl ^ q;
408
endmodule
409 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
410 94 unneback
input d;
411
output pl;
412
input clk, rst;
413
reg dff;
414
always @ (posedge clk or posedge rst)
415
if (rst)
416
    dff <= 1'b0;
417
else
418
    dff <= d;
419 98 unneback
assign pl = d ^ dff;
420 94 unneback
endmodule
421
module vl_synchronizer (d, q, clk, rst);
422
input d;
423
output reg q;
424
output clk, rst;
425
reg dff;
426
always @ (posedge clk or posedge rst)
427
if (rst)
428
    {dff,q} <= 2'b00;
429
else
430
    {dff,q} <= {d,dff};
431
endmodule
432 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
433 94 unneback
input start_pl;
434
output take_it_pl;
435
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
436
output got_it_pl;
437
input clk_src, rst_src;
438
input clk_dst, rst_dst;
439
wire take_it_tg, take_it_tg_sync;
440
wire got_it_tg, got_it_tg_sync;
441
// src -> dst
442
vl_pulse2toggle p2t0 (
443
    .pl(start_pl),
444
    .q(take_it_tg),
445
    .clk(clk_src),
446
    .rst(rst_src));
447
vl_synchronizer sync0 (
448
    .d(take_it_tg),
449
    .q(take_it_tg_sync),
450
    .clk(clk_dst),
451
    .rst(rst_dst));
452
vl_toggle2pulse t2p0 (
453
    .d(take_it_sync),
454
    .pl(take_it_pl),
455
    .clk(clk_dst),
456
    .rst(rst_dst));
457
// dst -> src
458 98 unneback
vl_pulse2toggle p2t1 (
459 94 unneback
    .pl(take_it_grant_pl),
460
    .q(got_it_tg),
461
    .clk(clk_dst),
462
    .rst(rst_dst));
463
vl_synchronizer sync1 (
464
    .d(got_it_tg),
465
    .q(got_it_tg_sync),
466
    .clk(clk_src),
467
    .rst(rst_src));
468
vl_toggle2pulse t2p1 (
469
    .d(take_it_grant_tg_sync),
470
    .pl(got_it_pl),
471
    .clk(clk_src),
472
    .rst(rst_src));
473
endmodule
474 6 unneback
//////////////////////////////////////////////////////////////////////
475
////                                                              ////
476 18 unneback
////  Logic functions                                             ////
477
////                                                              ////
478
////  Description                                                 ////
479
////  Logic functions such as multiplexers                        ////
480
////                                                              ////
481
////                                                              ////
482
////  To Do:                                                      ////
483
////   -                                                          ////
484
////                                                              ////
485
////  Author(s):                                                  ////
486
////      - Michael Unneback, unneback@opencores.org              ////
487
////        ORSoC AB                                              ////
488
////                                                              ////
489
//////////////////////////////////////////////////////////////////////
490
////                                                              ////
491
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
492
////                                                              ////
493
//// This source file may be used and distributed without         ////
494
//// restriction provided that this copyright statement is not    ////
495
//// removed from the file and that any derivative work contains  ////
496
//// the original copyright notice and the associated disclaimer. ////
497
////                                                              ////
498
//// This source file is free software; you can redistribute it   ////
499
//// and/or modify it under the terms of the GNU Lesser General   ////
500
//// Public License as published by the Free Software Foundation; ////
501
//// either version 2.1 of the License, or (at your option) any   ////
502
//// later version.                                               ////
503
////                                                              ////
504
//// This source is distributed in the hope that it will be       ////
505
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
506
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
507
//// PURPOSE.  See the GNU Lesser General Public License for more ////
508
//// details.                                                     ////
509
////                                                              ////
510
//// You should have received a copy of the GNU Lesser General    ////
511
//// Public License along with this source; if not, download it   ////
512
//// from http://www.opencores.org/lgpl.shtml                     ////
513
////                                                              ////
514
//////////////////////////////////////////////////////////////////////
515 36 unneback
module vl_mux_andor ( a, sel, dout);
516
parameter width = 32;
517
parameter nr_of_ports = 4;
518
input [nr_of_ports*width-1:0] a;
519
input [nr_of_ports-1:0] sel;
520
output reg [width-1:0] dout;
521 38 unneback
integer i,j;
522 36 unneback
always @ (a, sel)
523
begin
524
    dout = a[width-1:0] & {width{sel[0]}};
525 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
526
        for (j=0;j<width;j=j+1)
527
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
528 36 unneback
end
529
endmodule
530 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
531
parameter width = 32;
532 35 unneback
localparam nr_of_ports = 2;
533 34 unneback
input [width-1:0] a1, a0;
534
input [nr_of_ports-1:0] sel;
535
output [width-1:0] dout;
536 36 unneback
vl_mux_andor
537 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
538 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
539 34 unneback
endmodule
540
module vl_mux3_andor ( a2, a1, a0, sel, dout);
541
parameter width = 32;
542 35 unneback
localparam nr_of_ports = 3;
543 34 unneback
input [width-1:0] a2, a1, a0;
544
input [nr_of_ports-1:0] sel;
545
output [width-1:0] dout;
546 36 unneback
vl_mux_andor
547 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
548 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
549 34 unneback
endmodule
550 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
551
parameter width = 32;
552 35 unneback
localparam nr_of_ports = 4;
553 18 unneback
input [width-1:0] a3, a2, a1, a0;
554
input [nr_of_ports-1:0] sel;
555 22 unneback
output [width-1:0] dout;
556 36 unneback
vl_mux_andor
557 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
558 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
559 18 unneback
endmodule
560
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
561
parameter width = 32;
562 35 unneback
localparam nr_of_ports = 5;
563 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
564
input [nr_of_ports-1:0] sel;
565 22 unneback
output [width-1:0] dout;
566 36 unneback
vl_mux_andor
567 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
568 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
569 18 unneback
endmodule
570
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
571
parameter width = 32;
572 35 unneback
localparam nr_of_ports = 6;
573 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
574
input [nr_of_ports-1:0] sel;
575 22 unneback
output [width-1:0] dout;
576 36 unneback
vl_mux_andor
577 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
578 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
579 18 unneback
endmodule
580 43 unneback
module vl_parity_generate (data, parity);
581
parameter word_size = 32;
582
parameter chunk_size = 8;
583
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
584
input [word_size-1:0] data;
585
output reg [word_size/chunk_size-1:0] parity;
586
integer i,j;
587
always @ (data)
588
for (i=0;i<word_size/chunk_size;i=i+1) begin
589
    parity[i] = parity_type;
590
    for (j=0;j<chunk_size;j=j+1) begin
591 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
592 43 unneback
    end
593
end
594
endmodule
595
module vl_parity_check( data, parity, parity_error);
596
parameter word_size = 32;
597
parameter chunk_size = 8;
598
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
599
input [word_size-1:0] data;
600
input [word_size/chunk_size-1:0] parity;
601
output parity_error;
602 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
603 43 unneback
integer i,j;
604
always @ (data or parity)
605
for (i=0;i<word_size/chunk_size;i=i+1) begin
606
    error_flag[i] = parity[i] ^ parity_type;
607
    for (j=0;j<chunk_size;j=j+1) begin
608 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
609 43 unneback
    end
610
end
611
assign parity_error = |error_flag;
612
endmodule
613 18 unneback
//////////////////////////////////////////////////////////////////////
614
////                                                              ////
615 44 unneback
////  IO functions                                                ////
616
////                                                              ////
617
////  Description                                                 ////
618
////  IO functions such as IOB flip-flops                         ////
619
////                                                              ////
620
////                                                              ////
621
////  To Do:                                                      ////
622
////   -                                                          ////
623
////                                                              ////
624
////  Author(s):                                                  ////
625
////      - Michael Unneback, unneback@opencores.org              ////
626
////        ORSoC AB                                              ////
627
////                                                              ////
628
//////////////////////////////////////////////////////////////////////
629
////                                                              ////
630
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
631
////                                                              ////
632
//// This source file may be used and distributed without         ////
633
//// restriction provided that this copyright statement is not    ////
634
//// removed from the file and that any derivative work contains  ////
635
//// the original copyright notice and the associated disclaimer. ////
636
////                                                              ////
637
//// This source file is free software; you can redistribute it   ////
638
//// and/or modify it under the terms of the GNU Lesser General   ////
639
//// Public License as published by the Free Software Foundation; ////
640
//// either version 2.1 of the License, or (at your option) any   ////
641
//// later version.                                               ////
642
////                                                              ////
643
//// This source is distributed in the hope that it will be       ////
644
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
645
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
646
//// PURPOSE.  See the GNU Lesser General Public License for more ////
647
//// details.                                                     ////
648
////                                                              ////
649
//// You should have received a copy of the GNU Lesser General    ////
650
//// Public License along with this source; if not, download it   ////
651
//// from http://www.opencores.org/lgpl.shtml                     ////
652
////                                                              ////
653
//////////////////////////////////////////////////////////////////////
654 45 unneback
`timescale 1ns/1ns
655 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
656
parameter width = 1;
657 45 unneback
parameter reset_value = {width{1'b0}};
658
input  [width-1:0]  d_i;
659 44 unneback
output [width-1:0] o_pad;
660
input clk, rst;
661
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
662 45 unneback
reg  [width-1:0] o_pad_int;
663 44 unneback
assign d_i_int = d_i;
664
genvar i;
665 45 unneback
generate
666 44 unneback
for (i=0;i<width;i=i+1) begin
667
    always @ (posedge clk or posedge rst)
668
    if (rst)
669 45 unneback
        o_pad_int[i] <= reset_value[i];
670 44 unneback
    else
671 45 unneback
        o_pad_int[i] <= d_i_int[i];
672
    assign #1 o_pad[i] = o_pad_int[i];
673 44 unneback
end
674
endgenerate
675
endmodule
676 45 unneback
`timescale 1ns/1ns
677 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
678
parameter width = 1;
679
input  [width-1:0] d_o;
680
output reg [width-1:0] d_i;
681
input oe;
682
inout [width-1:0] io_pad;
683
input clk, rst;
684
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
685
reg [width-1:0] oe_q;
686
reg [width-1:0] d_o_q;
687
assign oe_d = {width{oe}};
688
genvar i;
689
generate
690
for (i=0;i<width;i=i+1) begin
691
    always @ (posedge clk or posedge rst)
692
    if (rst)
693
        oe_q[i] <= 1'b0;
694
    else
695
        oe_q[i] <= oe_d[i];
696
    always @ (posedge clk or posedge rst)
697
    if (rst)
698
        d_o_q[i] <= 1'b0;
699
    else
700
        d_o_q[i] <= d_o[i];
701
    always @ (posedge clk or posedge rst)
702
    if (rst)
703
        d_i[i] <= 1'b0;
704
    else
705
        d_i[i] <= io_pad[i];
706 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
707 44 unneback
end
708
endgenerate
709
endmodule
710
//////////////////////////////////////////////////////////////////////
711
////                                                              ////
712 6 unneback
////  Versatile counter                                           ////
713
////                                                              ////
714
////  Description                                                 ////
715
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
716
////  counter                                                     ////
717
////                                                              ////
718
////  To Do:                                                      ////
719
////   - add LFSR with more taps                                  ////
720
////                                                              ////
721
////  Author(s):                                                  ////
722
////      - Michael Unneback, unneback@opencores.org              ////
723
////        ORSoC AB                                              ////
724
////                                                              ////
725
//////////////////////////////////////////////////////////////////////
726
////                                                              ////
727
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
728
////                                                              ////
729
//// This source file may be used and distributed without         ////
730
//// restriction provided that this copyright statement is not    ////
731
//// removed from the file and that any derivative work contains  ////
732
//// the original copyright notice and the associated disclaimer. ////
733
////                                                              ////
734
//// This source file is free software; you can redistribute it   ////
735
//// and/or modify it under the terms of the GNU Lesser General   ////
736
//// Public License as published by the Free Software Foundation; ////
737
//// either version 2.1 of the License, or (at your option) any   ////
738
//// later version.                                               ////
739
////                                                              ////
740
//// This source is distributed in the hope that it will be       ////
741
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
742
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
743
//// PURPOSE.  See the GNU Lesser General Public License for more ////
744
//// details.                                                     ////
745
////                                                              ////
746
//// You should have received a copy of the GNU Lesser General    ////
747
//// Public License along with this source; if not, download it   ////
748
//// from http://www.opencores.org/lgpl.shtml                     ////
749
////                                                              ////
750
//////////////////////////////////////////////////////////////////////
751
// binary counter
752 40 unneback
module vl_cnt_bin_ce (
753
 cke, q, rst, clk);
754 22 unneback
   parameter length = 4;
755 6 unneback
   input cke;
756
   output [length:1] q;
757
   input rst;
758
   input clk;
759
   parameter clear_value = 0;
760
   parameter set_value = 1;
761
   parameter wrap_value = 0;
762
   parameter level1_value = 15;
763
   reg  [length:1] qi;
764
   wire [length:1] q_next;
765
   assign q_next = qi + {{length-1{1'b0}},1'b1};
766
   always @ (posedge clk or posedge rst)
767
     if (rst)
768
       qi <= {length{1'b0}};
769
     else
770
     if (cke)
771
       qi <= q_next;
772
   assign q = qi;
773
endmodule
774
//////////////////////////////////////////////////////////////////////
775
////                                                              ////
776
////  Versatile counter                                           ////
777
////                                                              ////
778
////  Description                                                 ////
779
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
780
////  counter                                                     ////
781
////                                                              ////
782
////  To Do:                                                      ////
783
////   - add LFSR with more taps                                  ////
784
////                                                              ////
785
////  Author(s):                                                  ////
786
////      - Michael Unneback, unneback@opencores.org              ////
787
////        ORSoC AB                                              ////
788
////                                                              ////
789
//////////////////////////////////////////////////////////////////////
790
////                                                              ////
791
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
792
////                                                              ////
793
//// This source file may be used and distributed without         ////
794
//// restriction provided that this copyright statement is not    ////
795
//// removed from the file and that any derivative work contains  ////
796
//// the original copyright notice and the associated disclaimer. ////
797
////                                                              ////
798
//// This source file is free software; you can redistribute it   ////
799
//// and/or modify it under the terms of the GNU Lesser General   ////
800
//// Public License as published by the Free Software Foundation; ////
801
//// either version 2.1 of the License, or (at your option) any   ////
802
//// later version.                                               ////
803
////                                                              ////
804
//// This source is distributed in the hope that it will be       ////
805
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
806
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
807
//// PURPOSE.  See the GNU Lesser General Public License for more ////
808
//// details.                                                     ////
809
////                                                              ////
810
//// You should have received a copy of the GNU Lesser General    ////
811
//// Public License along with this source; if not, download it   ////
812
//// from http://www.opencores.org/lgpl.shtml                     ////
813
////                                                              ////
814
//////////////////////////////////////////////////////////////////////
815
// binary counter
816 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
817
 cke, rew, zq, level1, rst, clk);
818 6 unneback
   parameter length = 4;
819
   input cke;
820
   input rew;
821 25 unneback
   output reg zq;
822
   output reg level1;
823
   input rst;
824
   input clk;
825
   parameter clear_value = 0;
826
   parameter set_value = 1;
827
   parameter wrap_value = 1;
828
   parameter level1_value = 15;
829 29 unneback
   wire clear;
830 30 unneback
   assign clear = 1'b0;
831 25 unneback
   reg  [length:1] qi;
832
   wire  [length:1] q_next, q_next_fw, q_next_rew;
833
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
834
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
835
   assign q_next = rew ? q_next_rew : q_next_fw;
836
   always @ (posedge clk or posedge rst)
837
     if (rst)
838
       qi <= {length{1'b0}};
839
     else
840
     if (cke)
841
       qi <= q_next;
842
   always @ (posedge clk or posedge rst)
843
     if (rst)
844
       zq <= 1'b1;
845
     else
846
     if (cke)
847
       zq <= q_next == {length{1'b0}};
848
    always @ (posedge clk or posedge rst)
849
    if (rst)
850
        level1 <= 1'b0;
851
    else
852
    if (cke)
853 29 unneback
    if (clear)
854
        level1 <= 1'b0;
855
    else if (q_next == level1_value)
856 25 unneback
        level1 <= 1'b1;
857
    else if (qi == level1_value & rew)
858
        level1 <= 1'b0;
859
endmodule
860
//////////////////////////////////////////////////////////////////////
861
////                                                              ////
862
////  Versatile counter                                           ////
863
////                                                              ////
864
////  Description                                                 ////
865
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
866
////  counter                                                     ////
867
////                                                              ////
868
////  To Do:                                                      ////
869
////   - add LFSR with more taps                                  ////
870
////                                                              ////
871
////  Author(s):                                                  ////
872
////      - Michael Unneback, unneback@opencores.org              ////
873
////        ORSoC AB                                              ////
874
////                                                              ////
875
//////////////////////////////////////////////////////////////////////
876
////                                                              ////
877
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
878
////                                                              ////
879
//// This source file may be used and distributed without         ////
880
//// restriction provided that this copyright statement is not    ////
881
//// removed from the file and that any derivative work contains  ////
882
//// the original copyright notice and the associated disclaimer. ////
883
////                                                              ////
884
//// This source file is free software; you can redistribute it   ////
885
//// and/or modify it under the terms of the GNU Lesser General   ////
886
//// Public License as published by the Free Software Foundation; ////
887
//// either version 2.1 of the License, or (at your option) any   ////
888
//// later version.                                               ////
889
////                                                              ////
890
//// This source is distributed in the hope that it will be       ////
891
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
892
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
893
//// PURPOSE.  See the GNU Lesser General Public License for more ////
894
//// details.                                                     ////
895
////                                                              ////
896
//// You should have received a copy of the GNU Lesser General    ////
897
//// Public License along with this source; if not, download it   ////
898
//// from http://www.opencores.org/lgpl.shtml                     ////
899
////                                                              ////
900
//////////////////////////////////////////////////////////////////////
901
// binary counter
902 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
903
 cke, rew, q, zq, level1, rst, clk);
904 25 unneback
   parameter length = 4;
905
   input cke;
906
   input rew;
907
   output [length:1] q;
908
   output reg zq;
909
   output reg level1;
910
   input rst;
911
   input clk;
912
   parameter clear_value = 0;
913
   parameter set_value = 1;
914
   parameter wrap_value = 1;
915
   parameter level1_value = 15;
916 29 unneback
   wire clear;
917 30 unneback
   assign clear = 1'b0;
918 25 unneback
   reg  [length:1] qi;
919
   wire  [length:1] q_next, q_next_fw, q_next_rew;
920
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
921
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
922
   assign q_next = rew ? q_next_rew : q_next_fw;
923
   always @ (posedge clk or posedge rst)
924
     if (rst)
925
       qi <= {length{1'b0}};
926
     else
927
     if (cke)
928
       qi <= q_next;
929
   assign q = qi;
930
   always @ (posedge clk or posedge rst)
931
     if (rst)
932
       zq <= 1'b1;
933
     else
934
     if (cke)
935
       zq <= q_next == {length{1'b0}};
936
    always @ (posedge clk or posedge rst)
937
    if (rst)
938
        level1 <= 1'b0;
939
    else
940
    if (cke)
941 29 unneback
    if (clear)
942
        level1 <= 1'b0;
943
    else if (q_next == level1_value)
944 25 unneback
        level1 <= 1'b1;
945
    else if (qi == level1_value & rew)
946
        level1 <= 1'b0;
947
endmodule
948
//////////////////////////////////////////////////////////////////////
949
////                                                              ////
950
////  Versatile counter                                           ////
951
////                                                              ////
952
////  Description                                                 ////
953
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
954
////  counter                                                     ////
955
////                                                              ////
956
////  To Do:                                                      ////
957
////   - add LFSR with more taps                                  ////
958
////                                                              ////
959
////  Author(s):                                                  ////
960
////      - Michael Unneback, unneback@opencores.org              ////
961
////        ORSoC AB                                              ////
962
////                                                              ////
963
//////////////////////////////////////////////////////////////////////
964
////                                                              ////
965
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
966
////                                                              ////
967
//// This source file may be used and distributed without         ////
968
//// restriction provided that this copyright statement is not    ////
969
//// removed from the file and that any derivative work contains  ////
970
//// the original copyright notice and the associated disclaimer. ////
971
////                                                              ////
972
//// This source file is free software; you can redistribute it   ////
973
//// and/or modify it under the terms of the GNU Lesser General   ////
974
//// Public License as published by the Free Software Foundation; ////
975
//// either version 2.1 of the License, or (at your option) any   ////
976
//// later version.                                               ////
977
////                                                              ////
978
//// This source is distributed in the hope that it will be       ////
979
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
980
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
981
//// PURPOSE.  See the GNU Lesser General Public License for more ////
982
//// details.                                                     ////
983
////                                                              ////
984
//// You should have received a copy of the GNU Lesser General    ////
985
//// Public License along with this source; if not, download it   ////
986
//// from http://www.opencores.org/lgpl.shtml                     ////
987
////                                                              ////
988
//////////////////////////////////////////////////////////////////////
989 75 unneback
// LFSR counter
990
module vl_cnt_lfsr_ce (
991
 cke, zq, rst, clk);
992
   parameter length = 4;
993
   input cke;
994
   output reg zq;
995
   input rst;
996
   input clk;
997
   parameter clear_value = 0;
998
   parameter set_value = 1;
999
   parameter wrap_value = 0;
1000
   parameter level1_value = 15;
1001
   reg  [length:1] qi;
1002
   reg lfsr_fb;
1003
   wire [length:1] q_next;
1004
   reg [32:1] polynom;
1005
   integer i;
1006
   always @ (qi)
1007
   begin
1008
        case (length)
1009
         2: polynom = 32'b11;                               // 0x3
1010
         3: polynom = 32'b110;                              // 0x6
1011
         4: polynom = 32'b1100;                             // 0xC
1012
         5: polynom = 32'b10100;                            // 0x14
1013
         6: polynom = 32'b110000;                           // 0x30
1014
         7: polynom = 32'b1100000;                          // 0x60
1015
         8: polynom = 32'b10111000;                         // 0xb8
1016
         9: polynom = 32'b100010000;                        // 0x110
1017
        10: polynom = 32'b1001000000;                       // 0x240
1018
        11: polynom = 32'b10100000000;                      // 0x500
1019
        12: polynom = 32'b100000101001;                     // 0x829
1020
        13: polynom = 32'b1000000001100;                    // 0x100C
1021
        14: polynom = 32'b10000000010101;                   // 0x2015
1022
        15: polynom = 32'b110000000000000;                  // 0x6000
1023
        16: polynom = 32'b1101000000001000;                 // 0xD008
1024
        17: polynom = 32'b10010000000000000;                // 0x12000
1025
        18: polynom = 32'b100000010000000000;               // 0x20400
1026
        19: polynom = 32'b1000000000000100011;              // 0x40023
1027
        20: polynom = 32'b10010000000000000000;             // 0x90000
1028
        21: polynom = 32'b101000000000000000000;            // 0x140000
1029
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1030
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1031
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1032
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1033
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1034
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1035
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1036
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1037
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1038
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1039
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1040
        default: polynom = 32'b0;
1041
        endcase
1042
        lfsr_fb = qi[length];
1043
        for (i=length-1; i>=1; i=i-1) begin
1044
            if (polynom[i])
1045
                lfsr_fb = lfsr_fb  ~^ qi[i];
1046
        end
1047
    end
1048
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1049
   always @ (posedge clk or posedge rst)
1050
     if (rst)
1051
       qi <= {length{1'b0}};
1052
     else
1053
     if (cke)
1054
       qi <= q_next;
1055
   always @ (posedge clk or posedge rst)
1056
     if (rst)
1057
       zq <= 1'b1;
1058
     else
1059
     if (cke)
1060
       zq <= q_next == {length{1'b0}};
1061
endmodule
1062
//////////////////////////////////////////////////////////////////////
1063
////                                                              ////
1064
////  Versatile counter                                           ////
1065
////                                                              ////
1066
////  Description                                                 ////
1067
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1068
////  counter                                                     ////
1069
////                                                              ////
1070
////  To Do:                                                      ////
1071
////   - add LFSR with more taps                                  ////
1072
////                                                              ////
1073
////  Author(s):                                                  ////
1074
////      - Michael Unneback, unneback@opencores.org              ////
1075
////        ORSoC AB                                              ////
1076
////                                                              ////
1077
//////////////////////////////////////////////////////////////////////
1078
////                                                              ////
1079
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1080
////                                                              ////
1081
//// This source file may be used and distributed without         ////
1082
//// restriction provided that this copyright statement is not    ////
1083
//// removed from the file and that any derivative work contains  ////
1084
//// the original copyright notice and the associated disclaimer. ////
1085
////                                                              ////
1086
//// This source file is free software; you can redistribute it   ////
1087
//// and/or modify it under the terms of the GNU Lesser General   ////
1088
//// Public License as published by the Free Software Foundation; ////
1089
//// either version 2.1 of the License, or (at your option) any   ////
1090
//// later version.                                               ////
1091
////                                                              ////
1092
//// This source is distributed in the hope that it will be       ////
1093
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1094
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1095
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1096
//// details.                                                     ////
1097
////                                                              ////
1098
//// You should have received a copy of the GNU Lesser General    ////
1099
//// Public License along with this source; if not, download it   ////
1100
//// from http://www.opencores.org/lgpl.shtml                     ////
1101
////                                                              ////
1102
//////////////////////////////////////////////////////////////////////
1103 6 unneback
// GRAY counter
1104 40 unneback
module vl_cnt_gray_ce_bin (
1105
 cke, q, q_bin, rst, clk);
1106 6 unneback
   parameter length = 4;
1107
   input cke;
1108
   output reg [length:1] q;
1109
   output [length:1] q_bin;
1110
   input rst;
1111
   input clk;
1112
   parameter clear_value = 0;
1113
   parameter set_value = 1;
1114
   parameter wrap_value = 8;
1115
   parameter level1_value = 15;
1116
   reg  [length:1] qi;
1117
   wire [length:1] q_next;
1118
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1119
   always @ (posedge clk or posedge rst)
1120
     if (rst)
1121
       qi <= {length{1'b0}};
1122
     else
1123
     if (cke)
1124
       qi <= q_next;
1125
   always @ (posedge clk or posedge rst)
1126
     if (rst)
1127
       q <= {length{1'b0}};
1128
     else
1129
       if (cke)
1130
         q <= (q_next>>1) ^ q_next;
1131
   assign q_bin = qi;
1132
endmodule
1133
//////////////////////////////////////////////////////////////////////
1134
////                                                              ////
1135
////  Versatile library, counters                                 ////
1136
////                                                              ////
1137
////  Description                                                 ////
1138
////  counters                                                    ////
1139
////                                                              ////
1140
////                                                              ////
1141
////  To Do:                                                      ////
1142
////   - add more counters                                        ////
1143
////                                                              ////
1144
////  Author(s):                                                  ////
1145
////      - Michael Unneback, unneback@opencores.org              ////
1146
////        ORSoC AB                                              ////
1147
////                                                              ////
1148
//////////////////////////////////////////////////////////////////////
1149
////                                                              ////
1150
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1151
////                                                              ////
1152
//// This source file may be used and distributed without         ////
1153
//// restriction provided that this copyright statement is not    ////
1154
//// removed from the file and that any derivative work contains  ////
1155
//// the original copyright notice and the associated disclaimer. ////
1156
////                                                              ////
1157
//// This source file is free software; you can redistribute it   ////
1158
//// and/or modify it under the terms of the GNU Lesser General   ////
1159
//// Public License as published by the Free Software Foundation; ////
1160
//// either version 2.1 of the License, or (at your option) any   ////
1161
//// later version.                                               ////
1162
////                                                              ////
1163
//// This source is distributed in the hope that it will be       ////
1164
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1165
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1166
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1167
//// details.                                                     ////
1168
////                                                              ////
1169
//// You should have received a copy of the GNU Lesser General    ////
1170
//// Public License along with this source; if not, download it   ////
1171
//// from http://www.opencores.org/lgpl.shtml                     ////
1172
////                                                              ////
1173
//////////////////////////////////////////////////////////////////////
1174 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1175 6 unneback
   parameter length = 4;
1176
   output reg [0:length-1] q;
1177
   input rst;
1178
   input clk;
1179
    always @ (posedge clk or posedge rst)
1180
    if (rst)
1181
        q <= {1'b1,{length-1{1'b0}}};
1182
    else
1183
        q <= {q[length-1],q[0:length-2]};
1184
endmodule
1185 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1186 6 unneback
   parameter length = 4;
1187
   input cke;
1188
   output reg [0:length-1] q;
1189
   input rst;
1190
   input clk;
1191
    always @ (posedge clk or posedge rst)
1192
    if (rst)
1193
        q <= {1'b1,{length-1{1'b0}}};
1194
    else
1195
        if (cke)
1196
            q <= {q[length-1],q[0:length-2]};
1197
endmodule
1198 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1199 6 unneback
   parameter length = 4;
1200
   input cke, clear;
1201
   output reg [0:length-1] q;
1202
   input rst;
1203
   input clk;
1204
    always @ (posedge clk or posedge rst)
1205
    if (rst)
1206
        q <= {1'b1,{length-1{1'b0}}};
1207
    else
1208
        if (cke)
1209
            if (clear)
1210
                q <= {1'b1,{length-1{1'b0}}};
1211
            else
1212
                q <= q >> 1;
1213
endmodule
1214 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1215 6 unneback
   parameter length = 4;
1216
   input cke, clear;
1217
   output reg [0:length-1] q;
1218
   input rst;
1219
   input clk;
1220
    always @ (posedge clk or posedge rst)
1221
    if (rst)
1222
        q <= {1'b1,{length-1{1'b0}}};
1223
    else
1224
        if (cke)
1225
            if (clear)
1226
                q <= {1'b1,{length-1{1'b0}}};
1227
            else
1228
            q <= {q[length-1],q[0:length-2]};
1229
endmodule
1230
//////////////////////////////////////////////////////////////////////
1231
////                                                              ////
1232
////  Versatile library, memories                                 ////
1233
////                                                              ////
1234
////  Description                                                 ////
1235
////  memories                                                    ////
1236
////                                                              ////
1237
////                                                              ////
1238
////  To Do:                                                      ////
1239
////   - add more memory types                                    ////
1240
////                                                              ////
1241
////  Author(s):                                                  ////
1242
////      - Michael Unneback, unneback@opencores.org              ////
1243
////        ORSoC AB                                              ////
1244
////                                                              ////
1245
//////////////////////////////////////////////////////////////////////
1246
////                                                              ////
1247
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1248
////                                                              ////
1249
//// This source file may be used and distributed without         ////
1250
//// restriction provided that this copyright statement is not    ////
1251
//// removed from the file and that any derivative work contains  ////
1252
//// the original copyright notice and the associated disclaimer. ////
1253
////                                                              ////
1254
//// This source file is free software; you can redistribute it   ////
1255
//// and/or modify it under the terms of the GNU Lesser General   ////
1256
//// Public License as published by the Free Software Foundation; ////
1257
//// either version 2.1 of the License, or (at your option) any   ////
1258
//// later version.                                               ////
1259
////                                                              ////
1260
//// This source is distributed in the hope that it will be       ////
1261
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1262
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1263
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1264
//// details.                                                     ////
1265
////                                                              ////
1266
//// You should have received a copy of the GNU Lesser General    ////
1267
//// Public License along with this source; if not, download it   ////
1268
//// from http://www.opencores.org/lgpl.shtml                     ////
1269
////                                                              ////
1270
//////////////////////////////////////////////////////////////////////
1271
/// ROM
1272 7 unneback
module vl_rom_init ( adr, q, clk);
1273
   parameter data_width = 32;
1274
   parameter addr_width = 8;
1275 75 unneback
   parameter mem_size = 1<<addr_width;
1276 7 unneback
   input [(addr_width-1):0]       adr;
1277
   output reg [(data_width-1):0] q;
1278
   input                         clk;
1279 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1280 7 unneback
   parameter memory_file = "vl_rom.vmem";
1281
   initial
1282
     begin
1283
        $readmemh(memory_file, rom);
1284
     end
1285
   always @ (posedge clk)
1286
     q <= rom[adr];
1287
endmodule
1288 6 unneback
// Single port RAM
1289
module vl_ram ( d, adr, we, q, clk);
1290
   parameter data_width = 32;
1291
   parameter addr_width = 8;
1292 75 unneback
   parameter mem_size = 1<<addr_width;
1293 6 unneback
   input [(data_width-1):0]      d;
1294
   input [(addr_width-1):0]       adr;
1295
   input                         we;
1296 7 unneback
   output reg [(data_width-1):0] q;
1297 6 unneback
   input                         clk;
1298 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
1299 7 unneback
   parameter init = 0;
1300
   parameter memory_file = "vl_ram.vmem";
1301
   generate if (init) begin : init_mem
1302
   initial
1303
     begin
1304
        $readmemh(memory_file, ram);
1305
     end
1306
   end
1307
   endgenerate
1308 6 unneback
   always @ (posedge clk)
1309
   begin
1310
   if (we)
1311
     ram[adr] <= d;
1312
   q <= ram[adr];
1313
   end
1314
endmodule
1315 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1316 7 unneback
   parameter data_width = 32;
1317 72 unneback
   parameter addr_width = 6;
1318 75 unneback
   parameter mem_size = 1<<addr_width;
1319 7 unneback
   input [(data_width-1):0]      d;
1320
   input [(addr_width-1):0]       adr;
1321 73 unneback
   input [(data_width/8)-1:0]    be;
1322 7 unneback
   input                         we;
1323
   output reg [(data_width-1):0] q;
1324
   input                         clk;
1325 65 unneback
`ifdef SYSTEMVERILOG
1326 95 unneback
    // use a multi-dimensional packed array
1327
    //t o model individual bytes within the word
1328
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
1329 65 unneback
`else
1330 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1331
    wire [data_width/8-1:0] cke;
1332 65 unneback
`endif
1333 60 unneback
   parameter memory_init = 0;
1334 7 unneback
   parameter memory_file = "vl_ram.vmem";
1335 60 unneback
   generate if (memory_init) begin : init_mem
1336 7 unneback
   initial
1337
     begin
1338
        $readmemh(memory_file, ram);
1339
     end
1340
   end
1341
   endgenerate
1342 60 unneback
`ifdef SYSTEMVERILOG
1343
always_ff@(posedge clk)
1344
begin
1345 95 unneback
    if(we) begin
1346 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1347
        if(be[2]) ram[adr][2] <= d[23:16];
1348
        if(be[1]) ram[adr][1] <= d[15:8];
1349
        if(be[0]) ram[adr][0] <= d[7:0];
1350 60 unneback
    end
1351 90 unneback
        q <= ram[adr];
1352 60 unneback
end
1353
`else
1354 85 unneback
assign cke = {data_width/8{we}} & be;
1355 7 unneback
   genvar i;
1356 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1357 7 unneback
      always @ (posedge clk)
1358 85 unneback
      if (cke[i])
1359 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1360
   end
1361
   endgenerate
1362
   always @ (posedge clk)
1363
      q <= ram[adr];
1364 60 unneback
`endif
1365 93 unneback
`ifdef verilator
1366 85 unneback
   // Function to access RAM (for use by Verilator).
1367
   function [31:0] get_mem;
1368
      // verilator public
1369 90 unneback
      input [addr_width-1:0]             addr;
1370 85 unneback
      get_mem = ram[addr];
1371
   endfunction // get_mem
1372
   // Function to write RAM (for use by Verilator).
1373
   function set_mem;
1374
      // verilator public
1375 90 unneback
      input [addr_width-1:0]             addr;
1376
      input [data_width-1:0]             data;
1377 85 unneback
      ram[addr] = data;
1378
   endfunction // set_mem
1379 93 unneback
`endif
1380 7 unneback
endmodule
1381
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1382 6 unneback
   parameter data_width = 32;
1383
   parameter addr_width = 8;
1384 75 unneback
   parameter mem_size = 1<<addr_width;
1385 6 unneback
   input [(data_width-1):0]      d_a;
1386
   input [(addr_width-1):0]       adr_a;
1387
   input [(addr_width-1):0]       adr_b;
1388
   input                         we_a;
1389
   output [(data_width-1):0]      q_b;
1390
   input                         clk_a, clk_b;
1391
   reg [(addr_width-1):0]         adr_b_reg;
1392 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1393 7 unneback
   parameter init = 0;
1394
   parameter memory_file = "vl_ram.vmem";
1395
   generate if (init) begin : init_mem
1396
   initial
1397
     begin
1398
        $readmemh(memory_file, ram);
1399
     end
1400
   end
1401
   endgenerate
1402 6 unneback
   always @ (posedge clk_a)
1403
   if (we_a)
1404
     ram[adr_a] <= d_a;
1405
   always @ (posedge clk_b)
1406
   adr_b_reg <= adr_b;
1407
   assign q_b = ram[adr_b_reg];
1408
endmodule
1409 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1410 6 unneback
   parameter data_width = 32;
1411
   parameter addr_width = 8;
1412 75 unneback
   parameter mem_size = 1<<addr_width;
1413 6 unneback
   input [(data_width-1):0]      d_a;
1414
   input [(addr_width-1):0]       adr_a;
1415
   input [(addr_width-1):0]       adr_b;
1416
   input                         we_a;
1417
   output [(data_width-1):0]      q_b;
1418
   output reg [(data_width-1):0] q_a;
1419
   input                         clk_a, clk_b;
1420
   reg [(data_width-1):0]         q_b;
1421 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1422 7 unneback
   parameter init = 0;
1423
   parameter memory_file = "vl_ram.vmem";
1424
   generate if (init) begin : init_mem
1425
   initial
1426
     begin
1427
        $readmemh(memory_file, ram);
1428
     end
1429
   end
1430
   endgenerate
1431 6 unneback
   always @ (posedge clk_a)
1432
     begin
1433
        q_a <= ram[adr_a];
1434
        if (we_a)
1435
             ram[adr_a] <= d_a;
1436
     end
1437
   always @ (posedge clk_b)
1438
          q_b <= ram[adr_b];
1439
endmodule
1440 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1441 6 unneback
   parameter data_width = 32;
1442
   parameter addr_width = 8;
1443 75 unneback
   parameter mem_size = 1<<addr_width;
1444 6 unneback
   input [(data_width-1):0]      d_a;
1445
   input [(addr_width-1):0]       adr_a;
1446
   input [(addr_width-1):0]       adr_b;
1447
   input                         we_a;
1448
   output [(data_width-1):0]      q_b;
1449
   input [(data_width-1):0]       d_b;
1450
   output reg [(data_width-1):0] q_a;
1451
   input                         we_b;
1452
   input                         clk_a, clk_b;
1453
   reg [(data_width-1):0]         q_b;
1454 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1455 7 unneback
   parameter init = 0;
1456
   parameter memory_file = "vl_ram.vmem";
1457
   generate if (init) begin : init_mem
1458
   initial
1459
     begin
1460
        $readmemh(memory_file, ram);
1461
     end
1462
   end
1463
   endgenerate
1464 6 unneback
   always @ (posedge clk_a)
1465
     begin
1466
        q_a <= ram[adr_a];
1467
        if (we_a)
1468
             ram[adr_a] <= d_a;
1469
     end
1470
   always @ (posedge clk_b)
1471
     begin
1472
        q_b <= ram[adr_b];
1473
        if (we_b)
1474
          ram[adr_b] <= d_b;
1475
     end
1476
endmodule
1477 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
1478 75 unneback
   parameter a_data_width = 32;
1479
   parameter a_addr_width = 8;
1480 95 unneback
   parameter b_data_width = 64; //a_data_width;
1481 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1482 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
1483
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
1484
   parameter init = 0;
1485
   parameter memory_file = "vl_ram.vmem";
1486 75 unneback
   input [(a_data_width-1):0]      d_a;
1487 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1488
   input [(a_data_width/8-1):0]    be_a;
1489
   input                           we_a;
1490 75 unneback
   output reg [(a_data_width-1):0] q_a;
1491 91 unneback
   input [(b_data_width-1):0]       d_b;
1492
   input [(b_addr_width-1):0]       adr_b;
1493 92 unneback
   input [(b_data_width/8-1):0]    be_b;
1494
   input                           we_b;
1495
   output reg [(b_data_width-1):0]          q_b;
1496 91 unneback
   input                           clk_a, clk_b;
1497
`ifdef SYSTEMVERILOG
1498
// use a multi-dimensional packed array
1499
//to model individual bytes within the word
1500 75 unneback
generate
1501 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1502 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1503 95 unneback
    initial
1504
        if (init)
1505
            $readmemh(memory_file, ram);
1506 91 unneback
    always_ff@(posedge clk_a)
1507
    begin
1508
        if(we_a) begin
1509
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1510
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1511
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1512
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1513
        end
1514
    end
1515 92 unneback
    always@(posedge clk_a)
1516
        q_a = ram[adr_a];
1517 91 unneback
    always_ff@(posedge clk_b)
1518 92 unneback
    begin
1519
        if(we_b) begin
1520
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1521
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1522
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1523
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1524
        end
1525
    end
1526
    always@(posedge clk_b)
1527
        q_b = ram[adr_b];
1528 75 unneback
end
1529
endgenerate
1530 95 unneback
generate
1531
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
1532 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1533 95 unneback
    initial
1534
        if (init)
1535
            $readmemh(memory_file, ram);
1536
    always_ff@(posedge clk_a)
1537
    begin
1538
        if(we_a) begin
1539
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
1540
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
1541
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
1542
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
1543
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1544
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1545
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1546
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1547
        end
1548
    end
1549
    always@(posedge clk_a)
1550
        q_a = ram[adr_a];
1551
    always_ff@(posedge clk_b)
1552
    begin
1553
        if(we_b) begin
1554
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
1555
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
1556
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
1557
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
1558
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1559
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1560
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1561
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1562
        end
1563
    end
1564
    always@(posedge clk_b)
1565
        q_b = ram[adr_b];
1566
end
1567
endgenerate
1568
generate
1569
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
1570
logic [31:0] temp;
1571
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
1572
dpram6464 (
1573
    .d_a(d_a),
1574
    .q_a(q_a),
1575
    .adr_a(adr_a),
1576
    .be_a(be_a),
1577
    .we_a(we_a),
1578
    .clk_a(clk_a),
1579
    .d_b({d_b,d_b}),
1580
    .q_b(temp),
1581
    .adr_b(adr_b),
1582
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
1583
    .we_b(we_b),
1584
    .clk_b(clk_b)
1585
);
1586
always_comb
1587
    if (adr_b[0])
1588
        q_b = temp[31:16];
1589
    else
1590
        q_b = temp[15:0];
1591
end
1592
endgenerate
1593
generate
1594
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
1595
logic [63:0] temp;
1596
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
1597
dpram6464 (
1598
    .d_a({d_a,d_a}),
1599
    .q_a(temp),
1600
    .adr_a(adr_a[a_addr_width-1:1]),
1601
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
1602
    .we_a(we_a),
1603
    .clk_a(clk_a),
1604
    .d_b(d_b),
1605
    .q_b(q_b),
1606
    .adr_b(adr_b),
1607
    .be_b(be_b),
1608
    .we_b(we_b),
1609
    .clk_b(clk_b)
1610
);
1611
always_comb
1612
    if (adr_a[0])
1613
        q_a = temp[63:32];
1614
    else
1615
        q_a = temp[31:0];
1616
end
1617
endgenerate
1618 91 unneback
`else
1619 92 unneback
    // This modules requires SystemVerilog
1620 98 unneback
    // at this point anyway
1621 91 unneback
`endif
1622 75 unneback
endmodule
1623 6 unneback
// FIFO
1624 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1625
    d, wr, fifo_full,
1626
    q, rd, fifo_empty,
1627
    fill_level,
1628
    clk, rst
1629
    );
1630
parameter data_width = 18;
1631
parameter addr_width = 4;
1632
// write side
1633
input  [data_width-1:0] d;
1634
input                   wr;
1635
output                  fifo_full;
1636
// read side
1637
output [data_width-1:0] q;
1638
input                   rd;
1639
output                  fifo_empty;
1640
// common
1641
output [addr_width:0]   fill_level;
1642
input rst, clk;
1643
wire [addr_width:1] wadr, radr;
1644
vl_cnt_bin_ce
1645
    # ( .length(addr_width))
1646
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1647
vl_cnt_bin_ce
1648
    # (.length(addr_width))
1649
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1650
vl_dpram_1r1w
1651
    # (.data_width(data_width), .addr_width(addr_width))
1652
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1653 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1654 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1655 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1656
endmodule
1657 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1658
// RAM is supposed to be larger than the two FIFOs
1659
// LFSR counters used adr pointers
1660
module vl_fifo_2r2w_sync_simplex (
1661
    // a side
1662
    a_d, a_wr, a_fifo_full,
1663
    a_q, a_rd, a_fifo_empty,
1664
    a_fill_level,
1665
    // b side
1666
    b_d, b_wr, b_fifo_full,
1667
    b_q, b_rd, b_fifo_empty,
1668
    b_fill_level,
1669
    // common
1670
    clk, rst
1671
    );
1672
parameter data_width = 8;
1673
parameter addr_width = 5;
1674
parameter fifo_full_level = (1<<addr_width)-1;
1675
// a side
1676
input  [data_width-1:0] a_d;
1677
input                   a_wr;
1678
output                  a_fifo_full;
1679
output [data_width-1:0] a_q;
1680
input                   a_rd;
1681
output                  a_fifo_empty;
1682
output [addr_width-1:0] a_fill_level;
1683
// b side
1684
input  [data_width-1:0] b_d;
1685
input                   b_wr;
1686
output                  b_fifo_full;
1687
output [data_width-1:0] b_q;
1688
input                   b_rd;
1689
output                  b_fifo_empty;
1690
output [addr_width-1:0] b_fill_level;
1691
input                   clk;
1692
input                   rst;
1693
// adr_gen
1694
wire [addr_width:1] a_wadr, a_radr;
1695
wire [addr_width:1] b_wadr, b_radr;
1696
// dpram
1697
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1698
vl_cnt_lfsr_ce
1699
    # ( .length(addr_width))
1700
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1701
vl_cnt_lfsr_ce
1702
    # (.length(addr_width))
1703
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1704
vl_cnt_lfsr_ce
1705
    # ( .length(addr_width))
1706
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1707
vl_cnt_lfsr_ce
1708
    # (.length(addr_width))
1709
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1710
// mux read or write adr to DPRAM
1711
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1712
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1713
vl_dpram_2r2w
1714
    # (.data_width(data_width), .addr_width(addr_width+1))
1715
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1716
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1717
vl_cnt_bin_ce_rew_zq_l1
1718 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1719 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1720
vl_cnt_bin_ce_rew_zq_l1
1721 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1722 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1723
endmodule
1724 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1725 11 unneback
   parameter addr_width = 4;
1726
   parameter N = addr_width-1;
1727 6 unneback
   parameter Q1 = 2'b00;
1728
   parameter Q2 = 2'b01;
1729
   parameter Q3 = 2'b11;
1730
   parameter Q4 = 2'b10;
1731
   parameter going_empty = 1'b0;
1732
   parameter going_full  = 1'b1;
1733
   input [N:0]  wptr, rptr;
1734 14 unneback
   output       fifo_empty;
1735 6 unneback
   output       fifo_full;
1736
   input        wclk, rclk, rst;
1737
   wire direction;
1738
   reg  direction_set, direction_clr;
1739
   wire async_empty, async_full;
1740
   wire fifo_full2;
1741 14 unneback
   wire fifo_empty2;
1742 6 unneback
   // direction_set
1743
   always @ (wptr[N:N-1] or rptr[N:N-1])
1744
     case ({wptr[N:N-1],rptr[N:N-1]})
1745
       {Q1,Q2} : direction_set <= 1'b1;
1746
       {Q2,Q3} : direction_set <= 1'b1;
1747
       {Q3,Q4} : direction_set <= 1'b1;
1748
       {Q4,Q1} : direction_set <= 1'b1;
1749
       default : direction_set <= 1'b0;
1750
     endcase
1751
   // direction_clear
1752
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1753
     if (rst)
1754
       direction_clr <= 1'b1;
1755
     else
1756
       case ({wptr[N:N-1],rptr[N:N-1]})
1757
         {Q2,Q1} : direction_clr <= 1'b1;
1758
         {Q3,Q2} : direction_clr <= 1'b1;
1759
         {Q4,Q3} : direction_clr <= 1'b1;
1760
         {Q1,Q4} : direction_clr <= 1'b1;
1761
         default : direction_clr <= 1'b0;
1762
       endcase
1763 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1764 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1765
   assign async_full  = (wptr == rptr) && (direction==going_full);
1766 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1767
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1768 6 unneback
/*
1769
   always @ (posedge wclk or posedge rst or posedge async_full)
1770
     if (rst)
1771
       {fifo_full, fifo_full2} <= 2'b00;
1772
     else if (async_full)
1773
       {fifo_full, fifo_full2} <= 2'b11;
1774
     else
1775
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1776
*/
1777 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1778 6 unneback
     if (async_empty)
1779
       {fifo_empty, fifo_empty2} <= 2'b11;
1780
     else
1781 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1782 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1783
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1784 27 unneback
endmodule // async_compb
1785 6 unneback
module vl_fifo_1r1w_async (
1786
    d, wr, fifo_full, wr_clk, wr_rst,
1787
    q, rd, fifo_empty, rd_clk, rd_rst
1788
    );
1789
parameter data_width = 18;
1790
parameter addr_width = 4;
1791
// write side
1792
input  [data_width-1:0] d;
1793
input                   wr;
1794
output                  fifo_full;
1795
input                   wr_clk;
1796
input                   wr_rst;
1797
// read side
1798
output [data_width-1:0] q;
1799
input                   rd;
1800
output                  fifo_empty;
1801
input                   rd_clk;
1802
input                   rd_rst;
1803
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1804 18 unneback
vl_cnt_gray_ce_bin
1805 6 unneback
    # ( .length(addr_width))
1806
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1807 18 unneback
vl_cnt_gray_ce_bin
1808 6 unneback
    # (.length(addr_width))
1809 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1810 7 unneback
vl_dpram_1r1w
1811 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1812
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1813
vl_fifo_cmp_async
1814
    # (.addr_width(addr_width))
1815
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1816
endmodule
1817 8 unneback
module vl_fifo_2r2w_async (
1818 6 unneback
    // a side
1819
    a_d, a_wr, a_fifo_full,
1820
    a_q, a_rd, a_fifo_empty,
1821
    a_clk, a_rst,
1822
    // b side
1823
    b_d, b_wr, b_fifo_full,
1824
    b_q, b_rd, b_fifo_empty,
1825
    b_clk, b_rst
1826
    );
1827
parameter data_width = 18;
1828
parameter addr_width = 4;
1829
// a side
1830
input  [data_width-1:0] a_d;
1831
input                   a_wr;
1832
output                  a_fifo_full;
1833
output [data_width-1:0] a_q;
1834
input                   a_rd;
1835
output                  a_fifo_empty;
1836
input                   a_clk;
1837
input                   a_rst;
1838
// b side
1839
input  [data_width-1:0] b_d;
1840
input                   b_wr;
1841
output                  b_fifo_full;
1842
output [data_width-1:0] b_q;
1843
input                   b_rd;
1844
output                  b_fifo_empty;
1845
input                   b_clk;
1846
input                   b_rst;
1847
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1848
vl_fifo_1r1w_async_a (
1849
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1850
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1851
    );
1852
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1853
vl_fifo_1r1w_async_b (
1854
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1855
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1856
    );
1857
endmodule
1858 8 unneback
module vl_fifo_2r2w_async_simplex (
1859 6 unneback
    // a side
1860
    a_d, a_wr, a_fifo_full,
1861
    a_q, a_rd, a_fifo_empty,
1862
    a_clk, a_rst,
1863
    // b side
1864
    b_d, b_wr, b_fifo_full,
1865
    b_q, b_rd, b_fifo_empty,
1866
    b_clk, b_rst
1867
    );
1868
parameter data_width = 18;
1869
parameter addr_width = 4;
1870
// a side
1871
input  [data_width-1:0] a_d;
1872
input                   a_wr;
1873
output                  a_fifo_full;
1874
output [data_width-1:0] a_q;
1875
input                   a_rd;
1876
output                  a_fifo_empty;
1877
input                   a_clk;
1878
input                   a_rst;
1879
// b side
1880
input  [data_width-1:0] b_d;
1881
input                   b_wr;
1882
output                  b_fifo_full;
1883
output [data_width-1:0] b_q;
1884
input                   b_rd;
1885
output                  b_fifo_empty;
1886
input                   b_clk;
1887
input                   b_rst;
1888
// adr_gen
1889
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1890
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1891
// dpram
1892
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1893 18 unneback
vl_cnt_gray_ce_bin
1894 6 unneback
    # ( .length(addr_width))
1895
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1896 18 unneback
vl_cnt_gray_ce_bin
1897 6 unneback
    # (.length(addr_width))
1898
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1899 18 unneback
vl_cnt_gray_ce_bin
1900 6 unneback
    # ( .length(addr_width))
1901
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1902 18 unneback
vl_cnt_gray_ce_bin
1903 6 unneback
    # (.length(addr_width))
1904
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1905
// mux read or write adr to DPRAM
1906
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1907
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1908 11 unneback
vl_dpram_2r2w
1909 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1910
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1911
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1912 11 unneback
vl_fifo_cmp_async
1913 6 unneback
    # (.addr_width(addr_width))
1914
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1915 11 unneback
vl_fifo_cmp_async
1916 6 unneback
    # (.addr_width(addr_width))
1917
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1918
endmodule
1919 48 unneback
module vl_reg_file (
1920
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1921
);
1922
parameter data_width = 32;
1923
parameter addr_width = 5;
1924
input [addr_width-1:0] a1, a2, a3;
1925
input [data_width-1:0] wd3;
1926
input we3;
1927
output [data_width-1:0] rd1, rd2;
1928
input clk;
1929
reg [data_width-1:0] wd3_reg;
1930
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
1931
reg we3_reg;
1932
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1933
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1934
always @ (posedge clk or posedge rst)
1935
if (rst)
1936
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
1937
else
1938
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
1939
    always @ (negedge clk)
1940
    if (we3_reg)
1941
        ram1[a3_reg] <= wd3;
1942
    always @ (posedge clk)
1943
        a1_reg <= a1;
1944
    assign rd1 = ram1[a1_reg];
1945
    always @ (negedge clk)
1946
    if (we3_reg)
1947
        ram2[a3_reg] <= wd3;
1948
    always @ (posedge clk)
1949
        a2_reg <= a2;
1950
    assign rd2 = ram2[a2_reg];
1951
endmodule
1952 12 unneback
//////////////////////////////////////////////////////////////////////
1953
////                                                              ////
1954
////  Versatile library, wishbone stuff                           ////
1955
////                                                              ////
1956
////  Description                                                 ////
1957
////  Wishbone compliant modules                                  ////
1958
////                                                              ////
1959
////                                                              ////
1960
////  To Do:                                                      ////
1961
////   -                                                          ////
1962
////                                                              ////
1963
////  Author(s):                                                  ////
1964
////      - Michael Unneback, unneback@opencores.org              ////
1965
////        ORSoC AB                                              ////
1966
////                                                              ////
1967
//////////////////////////////////////////////////////////////////////
1968
////                                                              ////
1969
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1970
////                                                              ////
1971
//// This source file may be used and distributed without         ////
1972
//// restriction provided that this copyright statement is not    ////
1973
//// removed from the file and that any derivative work contains  ////
1974
//// the original copyright notice and the associated disclaimer. ////
1975
////                                                              ////
1976
//// This source file is free software; you can redistribute it   ////
1977
//// and/or modify it under the terms of the GNU Lesser General   ////
1978
//// Public License as published by the Free Software Foundation; ////
1979
//// either version 2.1 of the License, or (at your option) any   ////
1980
//// later version.                                               ////
1981
////                                                              ////
1982
//// This source is distributed in the hope that it will be       ////
1983
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1984
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1985
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1986
//// details.                                                     ////
1987
////                                                              ////
1988
//// You should have received a copy of the GNU Lesser General    ////
1989
//// Public License along with this source; if not, download it   ////
1990
//// from http://www.opencores.org/lgpl.shtml                     ////
1991
////                                                              ////
1992
//////////////////////////////////////////////////////////////////////
1993
// async wb3 - wb3 bridge
1994
`timescale 1ns/1ns
1995 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
1996 83 unneback
parameter adr_width = 10;
1997
parameter max_burst_width = 4;
1998 85 unneback
input cyc_i, stb_i, we_i;
1999 83 unneback
input [2:0] cti_i;
2000
input [1:0] bte_i;
2001
input [adr_width-1:0] adr_i;
2002
output [adr_width-1:0] adr_o;
2003
output ack_o;
2004
input clk, rst;
2005
reg [adr_width-1:0] adr;
2006 90 unneback
wire [max_burst_width-1:0] to_adr;
2007 91 unneback
reg [max_burst_width-1:0] last_adr;
2008 92 unneback
reg last_cycle;
2009
localparam idle_or_eoc = 1'b0;
2010
localparam cyc_or_ws   = 1'b1;
2011 91 unneback
always @ (posedge clk or posedge rst)
2012
if (rst)
2013
    last_adr <= {max_burst_width{1'b0}};
2014
else
2015
    if (stb_i)
2016 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
2017 83 unneback
generate
2018
if (max_burst_width==0) begin : inst_0
2019 97 unneback
        reg ack_o;
2020
        assign adr_o = adr_i;
2021
        always @ (posedge clk or posedge rst)
2022
        if (rst)
2023
            ack_o <= 1'b0;
2024
        else
2025
            ack_o <= cyc_i & stb_i & !ack_o;
2026 83 unneback
end else begin
2027
    always @ (posedge clk or posedge rst)
2028
    if (rst)
2029 92 unneback
        last_cycle <= idle_or_eoc;
2030 83 unneback
    else
2031 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
2032
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
2033
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
2034
                      cyc_or_ws; // cyc
2035
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
2036 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
2037 91 unneback
                                        (!stb_i) ? last_adr :
2038 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
2039 85 unneback
                                        adr[max_burst_width-1:0];
2040 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
2041 83 unneback
end
2042
endgenerate
2043
generate
2044
if (max_burst_width==2) begin : inst_2
2045
    always @ (posedge clk or posedge rst)
2046
    if (rst)
2047
        adr <= 2'h0;
2048
    else
2049
        if (cyc_i & stb_i)
2050
            adr[1:0] <= to_adr[1:0] + 2'd1;
2051
        else
2052
            adr <= to_adr[1:0];
2053
end
2054
endgenerate
2055
generate
2056
if (max_burst_width==3) begin : inst_3
2057
    always @ (posedge clk or posedge rst)
2058
    if (rst)
2059
        adr <= 3'h0;
2060
    else
2061
        if (cyc_i & stb_i)
2062
            case (bte_i)
2063
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
2064
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
2065
            endcase
2066
        else
2067
            adr <= to_adr[2:0];
2068
end
2069
endgenerate
2070
generate
2071
if (max_burst_width==4) begin : inst_4
2072
    always @ (posedge clk or posedge rst)
2073
    if (rst)
2074
        adr <= 4'h0;
2075
    else
2076 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
2077 83 unneback
            case (bte_i)
2078
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
2079
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
2080
            default: adr[3:0] <= to_adr + 4'd1;
2081
            endcase
2082
        else
2083
            adr <= to_adr[3:0];
2084
end
2085
endgenerate
2086
generate
2087
if (adr_width > max_burst_width) begin : pass_through
2088
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
2089
end
2090
endgenerate
2091
endmodule
2092
// async wb3 - wb3 bridge
2093
`timescale 1ns/1ns
2094 18 unneback
module vl_wb3wb3_bridge (
2095 12 unneback
        // wishbone slave side
2096
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2097
        // wishbone master side
2098
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2099 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
2100
parameter addr_width = 4;
2101 12 unneback
input [31:0] wbs_dat_i;
2102
input [31:2] wbs_adr_i;
2103
input [3:0]  wbs_sel_i;
2104
input [1:0]  wbs_bte_i;
2105
input [2:0]  wbs_cti_i;
2106
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2107
output [31:0] wbs_dat_o;
2108 14 unneback
output wbs_ack_o;
2109 12 unneback
input wbs_clk, wbs_rst;
2110
output [31:0] wbm_dat_o;
2111
output reg [31:2] wbm_adr_o;
2112
output [3:0]  wbm_sel_o;
2113
output reg [1:0]  wbm_bte_o;
2114
output reg [2:0]  wbm_cti_o;
2115 14 unneback
output reg wbm_we_o;
2116
output wbm_cyc_o;
2117 12 unneback
output wbm_stb_o;
2118
input [31:0]  wbm_dat_i;
2119
input wbm_ack_i;
2120
input wbm_clk, wbm_rst;
2121
// bte
2122
parameter linear       = 2'b00;
2123
parameter wrap4        = 2'b01;
2124
parameter wrap8        = 2'b10;
2125
parameter wrap16       = 2'b11;
2126
// cti
2127
parameter classic      = 3'b000;
2128
parameter incburst     = 3'b010;
2129
parameter endofburst   = 3'b111;
2130 95 unneback
localparam wbs_adr  = 1'b0;
2131
localparam wbs_data = 1'b1;
2132
localparam wbm_adr0      = 2'b00;
2133
localparam wbm_adr1      = 2'b01;
2134
localparam wbm_data      = 2'b10;
2135
localparam wbm_data_wait = 2'b11;
2136 12 unneback
reg [1:0] wbs_bte_reg;
2137
reg wbs;
2138
wire wbs_eoc_alert, wbm_eoc_alert;
2139
reg wbs_eoc, wbm_eoc;
2140
reg [1:0] wbm;
2141 14 unneback
wire [1:16] wbs_count, wbm_count;
2142 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2143
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2144
reg a_rd_reg;
2145
wire b_rd_adr, b_rd_data;
2146 14 unneback
wire b_rd_data_reg;
2147
wire [35:0] temp;
2148 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2149
always @ (posedge wbs_clk or posedge wbs_rst)
2150
if (wbs_rst)
2151
        wbs_eoc <= 1'b0;
2152
else
2153
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2154 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
2155 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
2156
                wbs_eoc <= 1'b1;
2157 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2158 12 unneback
    cnt0 (
2159
        .cke(wbs_ack_o),
2160
        .clear(wbs_eoc),
2161
        .q(wbs_count),
2162
        .rst(wbs_rst),
2163
        .clk(wbs_clk));
2164
always @ (posedge wbs_clk or posedge wbs_rst)
2165
if (wbs_rst)
2166
        wbs <= wbs_adr;
2167
else
2168 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
2169 12 unneback
                wbs <= wbs_data;
2170
        else if (wbs_eoc & wbs_ack_o)
2171
                wbs <= wbs_adr;
2172
// wbs FIFO
2173 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
2174
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
2175 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2176
              1'b0;
2177
assign a_rd = !a_fifo_empty;
2178
always @ (posedge wbs_clk or posedge wbs_rst)
2179
if (wbs_rst)
2180
        a_rd_reg <= 1'b0;
2181
else
2182
        a_rd_reg <= a_rd;
2183
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2184
assign wbs_dat_o = a_q[35:4];
2185
always @ (posedge wbs_clk or posedge wbs_rst)
2186
if (wbs_rst)
2187 13 unneback
        wbs_bte_reg <= 2'b00;
2188 12 unneback
else
2189 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2190 12 unneback
// wbm FIFO
2191
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2192
always @ (posedge wbm_clk or posedge wbm_rst)
2193
if (wbm_rst)
2194
        wbm_eoc <= 1'b0;
2195
else
2196
        if (wbm==wbm_adr0 & !b_fifo_empty)
2197
                wbm_eoc <= b_q[4:3] == linear;
2198
        else if (wbm_eoc_alert & wbm_ack_i)
2199
                wbm_eoc <= 1'b1;
2200
always @ (posedge wbm_clk or posedge wbm_rst)
2201
if (wbm_rst)
2202
        wbm <= wbm_adr0;
2203
else
2204 33 unneback
/*
2205 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2206
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2207
        (wbm==wbm_adr1 & !wbm_we_o) |
2208
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2209
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2210 33 unneback
*/
2211
    case (wbm)
2212
    wbm_adr0:
2213
        if (!b_fifo_empty)
2214
            wbm <= wbm_adr1;
2215
    wbm_adr1:
2216
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
2217
            wbm <= wbm_data;
2218
    wbm_data:
2219
        if (wbm_ack_i & wbm_eoc)
2220
            wbm <= wbm_adr0;
2221
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
2222
            wbm <= wbm_data_wait;
2223
    wbm_data_wait:
2224
        if (!b_fifo_empty)
2225
            wbm <= wbm_data;
2226
    endcase
2227 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
2228
assign b_wr = !wbm_we_o & wbm_ack_i;
2229
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2230
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2231
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2232 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
2233 12 unneback
                   1'b0;
2234
assign b_rd = b_rd_adr | b_rd_data;
2235 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2236
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2237 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2238 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2239 12 unneback
    cnt1 (
2240
        .cke(wbm_ack_i),
2241
        .clear(wbm_eoc),
2242
        .q(wbm_count),
2243
        .rst(wbm_rst),
2244
        .clk(wbm_clk));
2245 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
2246
assign wbm_stb_o = (wbm==wbm_data);
2247 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
2248
if (wbm_rst)
2249
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2250
else begin
2251
        if (wbm==wbm_adr0 & !b_fifo_empty)
2252
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2253
        else if (wbm_eoc_alert & wbm_ack_i)
2254
                wbm_cti_o <= endofburst;
2255
end
2256
//async_fifo_dw_simplex_top
2257
vl_fifo_2r2w_async_simplex
2258
# ( .data_width(36), .addr_width(addr_width))
2259
fifo (
2260
    // a side
2261
    .a_d(a_d),
2262
    .a_wr(a_wr),
2263
    .a_fifo_full(a_fifo_full),
2264
    .a_q(a_q),
2265
    .a_rd(a_rd),
2266
    .a_fifo_empty(a_fifo_empty),
2267
    .a_clk(wbs_clk),
2268
    .a_rst(wbs_rst),
2269
    // b side
2270
    .b_d(b_d),
2271
    .b_wr(b_wr),
2272
    .b_fifo_full(b_fifo_full),
2273
    .b_q(b_q),
2274
    .b_rd(b_rd),
2275
    .b_fifo_empty(b_fifo_empty),
2276
    .b_clk(wbm_clk),
2277
    .b_rst(wbm_rst)
2278
    );
2279
endmodule
2280 75 unneback
module vl_wb3avalon_bridge (
2281
        // wishbone slave side
2282
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2283 77 unneback
        // avalon master side
2284 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
2285 85 unneback
parameter linewrapburst = 1'b0;
2286 75 unneback
input [31:0] wbs_dat_i;
2287
input [31:2] wbs_adr_i;
2288
input [3:0]  wbs_sel_i;
2289
input [1:0]  wbs_bte_i;
2290
input [2:0]  wbs_cti_i;
2291 83 unneback
input wbs_we_i;
2292
input wbs_cyc_i;
2293
input wbs_stb_i;
2294 75 unneback
output [31:0] wbs_dat_o;
2295
output wbs_ack_o;
2296
input wbs_clk, wbs_rst;
2297
input [31:0] readdata;
2298
output [31:0] writedata;
2299
output [31:2] address;
2300
output [3:0]  be;
2301
output write;
2302 81 unneback
output read;
2303 75 unneback
output beginbursttransfer;
2304
output [3:0] burstcount;
2305
input readdatavalid;
2306
input waitrequest;
2307
input clk;
2308
input rst;
2309
wire [1:0] wbm_bte_o;
2310
wire [2:0] wbm_cti_o;
2311
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
2312
reg last_cyc;
2313 79 unneback
reg [3:0] counter;
2314 82 unneback
reg read_busy;
2315 75 unneback
always @ (posedge clk or posedge rst)
2316
if (rst)
2317
    last_cyc <= 1'b0;
2318
else
2319
    last_cyc <= wbm_cyc_o;
2320 79 unneback
always @ (posedge clk or posedge rst)
2321
if (rst)
2322 82 unneback
    read_busy <= 1'b0;
2323 79 unneback
else
2324 82 unneback
    if (read & !waitrequest)
2325
        read_busy <= 1'b1;
2326
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
2327
        read_busy <= 1'b0;
2328
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
2329 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
2330
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
2331
                    (wbm_bte_o==2'b10) ? 4'd8 :
2332 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
2333
                    4'd1;
2334 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
2335 79 unneback
always @ (posedge clk or posedge rst)
2336
if (rst) begin
2337
    counter <= 4'd0;
2338
end else
2339 80 unneback
    if (wbm_we_o) begin
2340
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
2341 85 unneback
            counter <= burstcount -4'd1;
2342 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
2343
            counter <= burstcount;
2344
        end else if (!waitrequest & wbm_stb_o) begin
2345
            counter <= counter - 4'd1;
2346
        end
2347 82 unneback
    end
2348 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
2349 77 unneback
vl_wb3wb3_bridge wbwb3inst (
2350 75 unneback
    // wishbone slave side
2351
    .wbs_dat_i(wbs_dat_i),
2352
    .wbs_adr_i(wbs_adr_i),
2353
    .wbs_sel_i(wbs_sel_i),
2354
    .wbs_bte_i(wbs_bte_i),
2355
    .wbs_cti_i(wbs_cti_i),
2356
    .wbs_we_i(wbs_we_i),
2357
    .wbs_cyc_i(wbs_cyc_i),
2358
    .wbs_stb_i(wbs_stb_i),
2359
    .wbs_dat_o(wbs_dat_o),
2360
    .wbs_ack_o(wbs_ack_o),
2361
    .wbs_clk(wbs_clk),
2362
    .wbs_rst(wbs_rst),
2363
    // wishbone master side
2364
    .wbm_dat_o(writedata),
2365 78 unneback
    .wbm_adr_o(address),
2366 75 unneback
    .wbm_sel_o(be),
2367
    .wbm_bte_o(wbm_bte_o),
2368
    .wbm_cti_o(wbm_cti_o),
2369
    .wbm_we_o(wbm_we_o),
2370
    .wbm_cyc_o(wbm_cyc_o),
2371
    .wbm_stb_o(wbm_stb_o),
2372
    .wbm_dat_i(readdata),
2373
    .wbm_ack_i(wbm_ack_i),
2374
    .wbm_clk(clk),
2375
    .wbm_rst(rst));
2376
endmodule
2377 39 unneback
module vl_wb3_arbiter_