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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
altera
46
 // ALTERA
47
 //ACTEL
48
// sync reset
49
// input active lo async reset, normally from external reset generetaor and/or switch
50
// output active high global reset sync with two DFFs 
51
`timescale 1 ns/100 ps
52
module vl_sync_rst ( rst_n_i, rst_o, clk);
53
input rst_n_i, clk;
54
output rst_o;
55
reg [0:1] tmp;
56
always @ (posedge clk or negedge rst_n_i)
57
if (!rst_n_i)
58
        tmp <= 2'b00;
59
else
60
        tmp <= {1'b1,tmp[0]};
61
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
62
endmodule
63
// vl_pll
64
 //altera
65
 //actel
66
//////////////////////////////////////////////////////////////////////
67
////                                                              ////
68
////  Versatile library, registers                                ////
69
////                                                              ////
70
////  Description                                                 ////
71
////  Different type of registers                                 ////
72
////                                                              ////
73
////                                                              ////
74
////  To Do:                                                      ////
75
////   - add more different registers                             ////
76
////                                                              ////
77
////  Author(s):                                                  ////
78
////      - Michael Unneback, unneback@opencores.org              ////
79
////        ORSoC AB                                              ////
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////                                                              ////
81
//////////////////////////////////////////////////////////////////////
82
////                                                              ////
83
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84
////                                                              ////
85
//// This source file may be used and distributed without         ////
86
//// restriction provided that this copyright statement is not    ////
87
//// removed from the file and that any derivative work contains  ////
88
//// the original copyright notice and the associated disclaimer. ////
89
////                                                              ////
90
//// This source file is free software; you can redistribute it   ////
91
//// and/or modify it under the terms of the GNU Lesser General   ////
92
//// Public License as published by the Free Software Foundation; ////
93
//// either version 2.1 of the License, or (at your option) any   ////
94
//// later version.                                               ////
95
////                                                              ////
96
//// This source is distributed in the hope that it will be       ////
97
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100
//// details.                                                     ////
101
////                                                              ////
102
//// You should have received a copy of the GNU Lesser General    ////
103
//// Public License along with this source; if not, download it   ////
104
//// from http://www.opencores.org/lgpl.shtml                     ////
105
////                                                              ////
106
//////////////////////////////////////////////////////////////////////
107
module dff ( d, q, clk, rst);
108
        parameter width = 1;
109
        parameter reset_value = 0;
110
        input [width-1:0] d;
111
        input clk, rst;
112
        output reg [width-1:0] q;
113
        always @ (posedge clk or posedge rst)
114
        if (rst)
115
                q <= reset_value;
116
        else
117
                q <= d;
118
endmodule
119
module dff_array ( d, q, clk, rst);
120
        parameter width = 1;
121
        parameter depth = 2;
122
        parameter reset_value = 1'b0;
123
        input [width-1:0] d;
124
        input clk, rst;
125
        output [width-1:0] q;
126
        reg  [0:depth-1] q_tmp [width-1:0];
127
        integer i;
128
        always @ (posedge clk or posedge rst)
129
        if (rst) begin
130
            for (i=0;i<depth;i=i+1)
131
                q_tmp[i] <= {width{reset_value}};
132
        end else begin
133
            q_tmp[0] <= d;
134
            for (i=1;i<depth;i=i+1)
135
                q_tmp[i] <= q_tmp[i-1];
136
        end
137
    assign q = q_tmp[depth-1];
138
endmodule
139
module dff_ce ( d, ce, q, clk, rst);
140
        parameter width = 1;
141
        parameter reset_value = 0;
142
        input [width-1:0] d;
143
        input ce, clk, rst;
144
        output reg [width-1:0] q;
145
        always @ (posedge clk or posedge rst)
146
        if (rst)
147
                q <= reset_value;
148
        else
149
                if (ce)
150
                        q <= d;
151
endmodule
152 8 unneback
module dff_ce_clear ( d, ce, clear, q, clk, rst);
153
        parameter width = 1;
154
        parameter reset_value = 0;
155
        input [width-1:0] d;
156 10 unneback
        input ce, clear, clk, rst;
157 8 unneback
        output reg [width-1:0] q;
158
        always @ (posedge clk or posedge rst)
159
        if (rst)
160
            q <= reset_value;
161
        else
162
            if (ce)
163
                if (clear)
164
                    q <= {width{1'b0}};
165
                else
166
                    q <= d;
167
endmodule
168 6 unneback
// megafunction wizard: %LPM_FF%
169
// GENERATION: STANDARD
170
// VERSION: WM1.0
171
// MODULE: lpm_ff 
172
// ============================================================
173
// File Name: dff_sr.v
174
// Megafunction Name(s):
175
//                      lpm_ff
176
//
177
// Simulation Library Files(s):
178
//                      lpm
179
// ============================================================
180
// ************************************************************
181
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
182
//
183
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
184
// ************************************************************
185
//Copyright (C) 1991-2010 Altera Corporation
186
//Your use of Altera Corporation's design tools, logic functions 
187
//and other software and tools, and its AMPP partner logic 
188
//functions, and any output files from any of the foregoing 
189
//(including device programming or simulation files), and any 
190
//associated documentation or information are expressly subject 
191
//to the terms and conditions of the Altera Program License 
192
//Subscription Agreement, Altera MegaCore Function License 
193
//Agreement, or other applicable license agreement, including, 
194
//without limitation, that your use is for the sole purpose of 
195
//programming logic devices manufactured by Altera and sold by 
196
//Altera or its authorized distributors.  Please refer to the 
197
//applicable agreement for further details.
198
// synopsys translate_off
199
`timescale 1 ps / 1 ps
200
// synopsys translate_on
201
module dff_sr (
202
        aclr,
203
        aset,
204
        clock,
205
        data,
206
        q);
207
        input     aclr;
208
        input     aset;
209
        input     clock;
210
        input     data;
211
        output    q;
212
        wire [0:0] sub_wire0;
213
        wire [0:0] sub_wire1 = sub_wire0[0:0];
214
        wire  q = sub_wire1;
215
        wire  sub_wire2 = data;
216
        wire  sub_wire3 = sub_wire2;
217
        lpm_ff  lpm_ff_component (
218
                                .aclr (aclr),
219
                                .clock (clock),
220
                                .data (sub_wire3),
221
                                .aset (aset),
222
                                .q (sub_wire0)
223
                                // synopsys translate_off
224
                                ,
225
                                .aload (),
226
                                .enable (),
227
                                .sclr (),
228
                                .sload (),
229
                                .sset ()
230
                                // synopsys translate_on
231
                                );
232
        defparam
233
                lpm_ff_component.lpm_fftype = "DFF",
234
                lpm_ff_component.lpm_type = "LPM_FF",
235
                lpm_ff_component.lpm_width = 1;
236
endmodule
237
// ============================================================
238
// CNX file retrieval info
239
// ============================================================
240
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
241
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
242
// Retrieval info: PRIVATE: ASET NUMERIC "1"
243
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
244
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
245
// Retrieval info: PRIVATE: DFF NUMERIC "1"
246
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
247
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
248
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
249
// Retrieval info: PRIVATE: SSET NUMERIC "0"
250
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
251
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
252
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
253
// Retrieval info: PRIVATE: nBit NUMERIC "1"
254
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
255
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
256
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
257
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
258
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
259
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
260
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
261
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
262
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
263
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
264
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
265
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
266
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
267
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
268
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
269
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
270
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
271
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
272
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
273
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
274
// Retrieval info: LIB_FILE: lpm
275
// LATCH
276
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
277
module latch ( d, le, q, clk);
278
input d, le;
279
output q;
280
input clk;
281
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
282
endmodule
283
//////////////////////////////////////////////////////////////////////
284
////                                                              ////
285
////  Versatile counter                                           ////
286
////                                                              ////
287
////  Description                                                 ////
288
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
289
////  counter                                                     ////
290
////                                                              ////
291
////  To Do:                                                      ////
292
////   - add LFSR with more taps                                  ////
293
////                                                              ////
294
////  Author(s):                                                  ////
295
////      - Michael Unneback, unneback@opencores.org              ////
296
////        ORSoC AB                                              ////
297
////                                                              ////
298
//////////////////////////////////////////////////////////////////////
299
////                                                              ////
300
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
301
////                                                              ////
302
//// This source file may be used and distributed without         ////
303
//// restriction provided that this copyright statement is not    ////
304
//// removed from the file and that any derivative work contains  ////
305
//// the original copyright notice and the associated disclaimer. ////
306
////                                                              ////
307
//// This source file is free software; you can redistribute it   ////
308
//// and/or modify it under the terms of the GNU Lesser General   ////
309
//// Public License as published by the Free Software Foundation; ////
310
//// either version 2.1 of the License, or (at your option) any   ////
311
//// later version.                                               ////
312
////                                                              ////
313
//// This source is distributed in the hope that it will be       ////
314
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
315
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
316
//// PURPOSE.  See the GNU Lesser General Public License for more ////
317
//// details.                                                     ////
318
////                                                              ////
319
//// You should have received a copy of the GNU Lesser General    ////
320
//// Public License along with this source; if not, download it   ////
321
//// from http://www.opencores.org/lgpl.shtml                     ////
322
////                                                              ////
323
//////////////////////////////////////////////////////////////////////
324
// binary counter
325
module cnt_bin_ce ( cke, q, rst, clk);
326
   parameter length = 4;
327
   input cke;
328
   output [length:1] q;
329
   input rst;
330
   input clk;
331
   parameter clear_value = 0;
332
   parameter set_value = 1;
333
   parameter wrap_value = 0;
334
   parameter level1_value = 15;
335
   reg  [length:1] qi;
336
   wire [length:1] q_next;
337
   assign q_next = qi + {{length-1{1'b0}},1'b1};
338
   always @ (posedge clk or posedge rst)
339
     if (rst)
340
       qi <= {length{1'b0}};
341
     else
342
     if (cke)
343
       qi <= q_next;
344
   assign q = qi;
345
endmodule
346
//////////////////////////////////////////////////////////////////////
347
////                                                              ////
348
////  Versatile counter                                           ////
349
////                                                              ////
350
////  Description                                                 ////
351
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
352
////  counter                                                     ////
353
////                                                              ////
354
////  To Do:                                                      ////
355
////   - add LFSR with more taps                                  ////
356
////                                                              ////
357
////  Author(s):                                                  ////
358
////      - Michael Unneback, unneback@opencores.org              ////
359
////        ORSoC AB                                              ////
360
////                                                              ////
361
//////////////////////////////////////////////////////////////////////
362
////                                                              ////
363
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
364
////                                                              ////
365
//// This source file may be used and distributed without         ////
366
//// restriction provided that this copyright statement is not    ////
367
//// removed from the file and that any derivative work contains  ////
368
//// the original copyright notice and the associated disclaimer. ////
369
////                                                              ////
370
//// This source file is free software; you can redistribute it   ////
371
//// and/or modify it under the terms of the GNU Lesser General   ////
372
//// Public License as published by the Free Software Foundation; ////
373
//// either version 2.1 of the License, or (at your option) any   ////
374
//// later version.                                               ////
375
////                                                              ////
376
//// This source is distributed in the hope that it will be       ////
377
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
378
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
379
//// PURPOSE.  See the GNU Lesser General Public License for more ////
380
//// details.                                                     ////
381
////                                                              ////
382
//// You should have received a copy of the GNU Lesser General    ////
383
//// Public License along with this source; if not, download it   ////
384
//// from http://www.opencores.org/lgpl.shtml                     ////
385
////                                                              ////
386
//////////////////////////////////////////////////////////////////////
387
// binary counter
388
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
389
   parameter length = 4;
390
   input clear;
391
   input cke;
392
   output [length:1] q;
393
   input rst;
394
   input clk;
395
   parameter clear_value = 0;
396
   parameter set_value = 1;
397
   parameter wrap_value = 0;
398
   parameter level1_value = 15;
399
   reg  [length:1] qi;
400
   wire [length:1] q_next;
401
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
402
   always @ (posedge clk or posedge rst)
403
     if (rst)
404
       qi <= {length{1'b0}};
405
     else
406
     if (cke)
407
       qi <= q_next;
408
   assign q = qi;
409
endmodule
410
//////////////////////////////////////////////////////////////////////
411
////                                                              ////
412
////  Versatile counter                                           ////
413
////                                                              ////
414
////  Description                                                 ////
415
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
416
////  counter                                                     ////
417
////                                                              ////
418
////  To Do:                                                      ////
419
////   - add LFSR with more taps                                  ////
420
////                                                              ////
421
////  Author(s):                                                  ////
422
////      - Michael Unneback, unneback@opencores.org              ////
423
////        ORSoC AB                                              ////
424
////                                                              ////
425
//////////////////////////////////////////////////////////////////////
426
////                                                              ////
427
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
428
////                                                              ////
429
//// This source file may be used and distributed without         ////
430
//// restriction provided that this copyright statement is not    ////
431
//// removed from the file and that any derivative work contains  ////
432
//// the original copyright notice and the associated disclaimer. ////
433
////                                                              ////
434
//// This source file is free software; you can redistribute it   ////
435
//// and/or modify it under the terms of the GNU Lesser General   ////
436
//// Public License as published by the Free Software Foundation; ////
437
//// either version 2.1 of the License, or (at your option) any   ////
438
//// later version.                                               ////
439
////                                                              ////
440
//// This source is distributed in the hope that it will be       ////
441
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
442
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
443
//// PURPOSE.  See the GNU Lesser General Public License for more ////
444
//// details.                                                     ////
445
////                                                              ////
446
//// You should have received a copy of the GNU Lesser General    ////
447
//// Public License along with this source; if not, download it   ////
448
//// from http://www.opencores.org/lgpl.shtml                     ////
449
////                                                              ////
450
//////////////////////////////////////////////////////////////////////
451
// binary counter
452
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
453
   parameter length = 4;
454
   input clear;
455
   input set;
456
   input cke;
457
   input rew;
458
   output [length:1] q;
459
   input rst;
460
   input clk;
461
   parameter clear_value = 0;
462
   parameter set_value = 1;
463
   parameter wrap_value = 0;
464
   parameter level1_value = 15;
465
   reg  [length:1] qi;
466
   wire  [length:1] q_next, q_next_fw, q_next_rew;
467
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
468
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
469
   assign q_next = rew ? q_next_rew : q_next_fw;
470
   always @ (posedge clk or posedge rst)
471
     if (rst)
472
       qi <= {length{1'b0}};
473
     else
474
     if (cke)
475
       qi <= q_next;
476
   assign q = qi;
477
endmodule
478
//////////////////////////////////////////////////////////////////////
479
////                                                              ////
480
////  Versatile counter                                           ////
481
////                                                              ////
482
////  Description                                                 ////
483
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
484
////  counter                                                     ////
485
////                                                              ////
486
////  To Do:                                                      ////
487
////   - add LFSR with more taps                                  ////
488
////                                                              ////
489
////  Author(s):                                                  ////
490
////      - Michael Unneback, unneback@opencores.org              ////
491
////        ORSoC AB                                              ////
492
////                                                              ////
493
//////////////////////////////////////////////////////////////////////
494
////                                                              ////
495
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
496
////                                                              ////
497
//// This source file may be used and distributed without         ////
498
//// restriction provided that this copyright statement is not    ////
499
//// removed from the file and that any derivative work contains  ////
500
//// the original copyright notice and the associated disclaimer. ////
501
////                                                              ////
502
//// This source file is free software; you can redistribute it   ////
503
//// and/or modify it under the terms of the GNU Lesser General   ////
504
//// Public License as published by the Free Software Foundation; ////
505
//// either version 2.1 of the License, or (at your option) any   ////
506
//// later version.                                               ////
507
////                                                              ////
508
//// This source is distributed in the hope that it will be       ////
509
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
510
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
511
//// PURPOSE.  See the GNU Lesser General Public License for more ////
512
//// details.                                                     ////
513
////                                                              ////
514
//// You should have received a copy of the GNU Lesser General    ////
515
//// Public License along with this source; if not, download it   ////
516
//// from http://www.opencores.org/lgpl.shtml                     ////
517
////                                                              ////
518
//////////////////////////////////////////////////////////////////////
519
// binary counter
520
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
521
   parameter length = 4;
522
   input cke;
523
   input rew;
524
   output reg level1;
525
   input rst;
526
   input clk;
527
   parameter clear_value = 0;
528
   parameter set_value = 1;
529
   parameter wrap_value = 1;
530
   parameter level1_value = 15;
531
   reg  [length:1] qi;
532
   wire  [length:1] q_next, q_next_fw, q_next_rew;
533
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
534
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
535
   assign q_next = rew ? q_next_rew : q_next_fw;
536
   always @ (posedge clk or posedge rst)
537
     if (rst)
538
       qi <= {length{1'b0}};
539
     else
540
     if (cke)
541
       qi <= q_next;
542
    always @ (posedge clk or posedge rst)
543
    if (rst)
544
        level1 <= 1'b0;
545
    else
546
    if (cke)
547
    if (q_next == level1_value)
548
        level1 <= 1'b1;
549
    else if (qi == level1_value & rew)
550
        level1 <= 1'b0;
551
endmodule
552
//////////////////////////////////////////////////////////////////////
553
////                                                              ////
554
////  Versatile counter                                           ////
555
////                                                              ////
556
////  Description                                                 ////
557
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
558
////  counter                                                     ////
559
////                                                              ////
560
////  To Do:                                                      ////
561
////   - add LFSR with more taps                                  ////
562
////                                                              ////
563
////  Author(s):                                                  ////
564
////      - Michael Unneback, unneback@opencores.org              ////
565
////        ORSoC AB                                              ////
566
////                                                              ////
567
//////////////////////////////////////////////////////////////////////
568
////                                                              ////
569
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
570
////                                                              ////
571
//// This source file may be used and distributed without         ////
572
//// restriction provided that this copyright statement is not    ////
573
//// removed from the file and that any derivative work contains  ////
574
//// the original copyright notice and the associated disclaimer. ////
575
////                                                              ////
576
//// This source file is free software; you can redistribute it   ////
577
//// and/or modify it under the terms of the GNU Lesser General   ////
578
//// Public License as published by the Free Software Foundation; ////
579
//// either version 2.1 of the License, or (at your option) any   ////
580
//// later version.                                               ////
581
////                                                              ////
582
//// This source is distributed in the hope that it will be       ////
583
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
584
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
585
//// PURPOSE.  See the GNU Lesser General Public License for more ////
586
//// details.                                                     ////
587
////                                                              ////
588
//// You should have received a copy of the GNU Lesser General    ////
589
//// Public License along with this source; if not, download it   ////
590
//// from http://www.opencores.org/lgpl.shtml                     ////
591
////                                                              ////
592
//////////////////////////////////////////////////////////////////////
593
// LFSR counter
594
module cnt_lfsr_zq ( zq, rst, clk);
595
   parameter length = 4;
596
   output reg zq;
597
   input rst;
598
   input clk;
599
   parameter clear_value = 0;
600
   parameter set_value = 1;
601
   parameter wrap_value = 8;
602
   parameter level1_value = 15;
603
   reg  [length:1] qi;
604
   reg lfsr_fb;
605
   wire [length:1] q_next;
606
   reg [32:1] polynom;
607
   integer i;
608
   always @ (qi)
609
   begin
610
        case (length)
611
         2: polynom = 32'b11;                               // 0x3
612
         3: polynom = 32'b110;                              // 0x6
613
         4: polynom = 32'b1100;                             // 0xC
614
         5: polynom = 32'b10100;                            // 0x14
615
         6: polynom = 32'b110000;                           // 0x30
616
         7: polynom = 32'b1100000;                          // 0x60
617
         8: polynom = 32'b10111000;                         // 0xb8
618
         9: polynom = 32'b100010000;                        // 0x110
619
        10: polynom = 32'b1001000000;                       // 0x240
620
        11: polynom = 32'b10100000000;                      // 0x500
621
        12: polynom = 32'b100000101001;                     // 0x829
622
        13: polynom = 32'b1000000001100;                    // 0x100C
623
        14: polynom = 32'b10000000010101;                   // 0x2015
624
        15: polynom = 32'b110000000000000;                  // 0x6000
625
        16: polynom = 32'b1101000000001000;                 // 0xD008
626
        17: polynom = 32'b10010000000000000;                // 0x12000
627
        18: polynom = 32'b100000010000000000;               // 0x20400
628
        19: polynom = 32'b1000000000000100011;              // 0x40023
629
        20: polynom = 32'b10000010000000000000;             // 0x82000
630
        21: polynom = 32'b101000000000000000000;            // 0x140000
631
        22: polynom = 32'b1100000000000000000000;           // 0x300000
632
        23: polynom = 32'b10000100000000000000000;          // 0x420000
633
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
634
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
635
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
636
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
637
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
638
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
639
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
640
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
641
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
642
        default: polynom = 32'b0;
643
        endcase
644
        lfsr_fb = qi[length];
645
        for (i=length-1; i>=1; i=i-1) begin
646
            if (polynom[i])
647
                lfsr_fb = lfsr_fb  ~^ qi[i];
648
        end
649
    end
650
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
651
   always @ (posedge clk or posedge rst)
652
     if (rst)
653
       qi <= {length{1'b0}};
654
     else
655
       qi <= q_next;
656
   always @ (posedge clk or posedge rst)
657
     if (rst)
658
       zq <= 1'b1;
659
     else
660
       zq <= q_next == {length{1'b0}};
661
endmodule
662
//////////////////////////////////////////////////////////////////////
663
////                                                              ////
664
////  Versatile counter                                           ////
665
////                                                              ////
666
////  Description                                                 ////
667
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
668
////  counter                                                     ////
669
////                                                              ////
670
////  To Do:                                                      ////
671
////   - add LFSR with more taps                                  ////
672
////                                                              ////
673
////  Author(s):                                                  ////
674
////      - Michael Unneback, unneback@opencores.org              ////
675
////        ORSoC AB                                              ////
676
////                                                              ////
677
//////////////////////////////////////////////////////////////////////
678
////                                                              ////
679
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
680
////                                                              ////
681
//// This source file may be used and distributed without         ////
682
//// restriction provided that this copyright statement is not    ////
683
//// removed from the file and that any derivative work contains  ////
684
//// the original copyright notice and the associated disclaimer. ////
685
////                                                              ////
686
//// This source file is free software; you can redistribute it   ////
687
//// and/or modify it under the terms of the GNU Lesser General   ////
688
//// Public License as published by the Free Software Foundation; ////
689
//// either version 2.1 of the License, or (at your option) any   ////
690
//// later version.                                               ////
691
////                                                              ////
692
//// This source is distributed in the hope that it will be       ////
693
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
694
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
695
//// PURPOSE.  See the GNU Lesser General Public License for more ////
696
//// details.                                                     ////
697
////                                                              ////
698
//// You should have received a copy of the GNU Lesser General    ////
699
//// Public License along with this source; if not, download it   ////
700
//// from http://www.opencores.org/lgpl.shtml                     ////
701
////                                                              ////
702
//////////////////////////////////////////////////////////////////////
703
// LFSR counter
704
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
705
   parameter length = 4;
706
   input cke;
707
   output reg zq;
708
   input rst;
709
   input clk;
710
   parameter clear_value = 0;
711
   parameter set_value = 1;
712
   parameter wrap_value = 8;
713
   parameter level1_value = 15;
714
   reg  [length:1] qi;
715
   reg lfsr_fb;
716
   wire [length:1] q_next;
717
   reg [32:1] polynom;
718
   integer i;
719
   always @ (qi)
720
   begin
721
        case (length)
722
         2: polynom = 32'b11;                               // 0x3
723
         3: polynom = 32'b110;                              // 0x6
724
         4: polynom = 32'b1100;                             // 0xC
725
         5: polynom = 32'b10100;                            // 0x14
726
         6: polynom = 32'b110000;                           // 0x30
727
         7: polynom = 32'b1100000;                          // 0x60
728
         8: polynom = 32'b10111000;                         // 0xb8
729
         9: polynom = 32'b100010000;                        // 0x110
730
        10: polynom = 32'b1001000000;                       // 0x240
731
        11: polynom = 32'b10100000000;                      // 0x500
732
        12: polynom = 32'b100000101001;                     // 0x829
733
        13: polynom = 32'b1000000001100;                    // 0x100C
734
        14: polynom = 32'b10000000010101;                   // 0x2015
735
        15: polynom = 32'b110000000000000;                  // 0x6000
736
        16: polynom = 32'b1101000000001000;                 // 0xD008
737
        17: polynom = 32'b10010000000000000;                // 0x12000
738
        18: polynom = 32'b100000010000000000;               // 0x20400
739
        19: polynom = 32'b1000000000000100011;              // 0x40023
740
        20: polynom = 32'b10000010000000000000;             // 0x82000
741
        21: polynom = 32'b101000000000000000000;            // 0x140000
742
        22: polynom = 32'b1100000000000000000000;           // 0x300000
743
        23: polynom = 32'b10000100000000000000000;          // 0x420000
744
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
745
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
746
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
747
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
748
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
749
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
750
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
751
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
752
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
753
        default: polynom = 32'b0;
754
        endcase
755
        lfsr_fb = qi[length];
756
        for (i=length-1; i>=1; i=i-1) begin
757
            if (polynom[i])
758
                lfsr_fb = lfsr_fb  ~^ qi[i];
759
        end
760
    end
761
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
762
   always @ (posedge clk or posedge rst)
763
     if (rst)
764
       qi <= {length{1'b0}};
765
     else
766
     if (cke)
767
       qi <= q_next;
768
   always @ (posedge clk or posedge rst)
769
     if (rst)
770
       zq <= 1'b1;
771
     else
772
     if (cke)
773
       zq <= q_next == {length{1'b0}};
774
endmodule
775
//////////////////////////////////////////////////////////////////////
776
////                                                              ////
777
////  Versatile counter                                           ////
778
////                                                              ////
779
////  Description                                                 ////
780
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
781
////  counter                                                     ////
782
////                                                              ////
783
////  To Do:                                                      ////
784
////   - add LFSR with more taps                                  ////
785
////                                                              ////
786
////  Author(s):                                                  ////
787
////      - Michael Unneback, unneback@opencores.org              ////
788
////        ORSoC AB                                              ////
789
////                                                              ////
790
//////////////////////////////////////////////////////////////////////
791
////                                                              ////
792
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
793
////                                                              ////
794
//// This source file may be used and distributed without         ////
795
//// restriction provided that this copyright statement is not    ////
796
//// removed from the file and that any derivative work contains  ////
797
//// the original copyright notice and the associated disclaimer. ////
798
////                                                              ////
799
//// This source file is free software; you can redistribute it   ////
800
//// and/or modify it under the terms of the GNU Lesser General   ////
801
//// Public License as published by the Free Software Foundation; ////
802
//// either version 2.1 of the License, or (at your option) any   ////
803
//// later version.                                               ////
804
////                                                              ////
805
//// This source is distributed in the hope that it will be       ////
806
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
807
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
808
//// PURPOSE.  See the GNU Lesser General Public License for more ////
809
//// details.                                                     ////
810
////                                                              ////
811
//// You should have received a copy of the GNU Lesser General    ////
812
//// Public License along with this source; if not, download it   ////
813
//// from http://www.opencores.org/lgpl.shtml                     ////
814
////                                                              ////
815
//////////////////////////////////////////////////////////////////////
816
// LFSR counter
817
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
818
   parameter length = 4;
819
   input cke;
820
   input rew;
821
   output reg level1;
822
   input rst;
823
   input clk;
824
   parameter clear_value = 0;
825
   parameter set_value = 1;
826
   parameter wrap_value = 8;
827
   parameter level1_value = 15;
828
   reg  [length:1] qi;
829
   reg lfsr_fb, lfsr_fb_rew;
830
   wire  [length:1] q_next, q_next_fw, q_next_rew;
831
   reg [32:1] polynom_rew;
832
   integer j;
833
   reg [32:1] polynom;
834
   integer i;
835
   always @ (qi)
836
   begin
837
        case (length)
838
         2: polynom = 32'b11;                               // 0x3
839
         3: polynom = 32'b110;                              // 0x6
840
         4: polynom = 32'b1100;                             // 0xC
841
         5: polynom = 32'b10100;                            // 0x14
842
         6: polynom = 32'b110000;                           // 0x30
843
         7: polynom = 32'b1100000;                          // 0x60
844
         8: polynom = 32'b10111000;                         // 0xb8
845
         9: polynom = 32'b100010000;                        // 0x110
846
        10: polynom = 32'b1001000000;                       // 0x240
847
        11: polynom = 32'b10100000000;                      // 0x500
848
        12: polynom = 32'b100000101001;                     // 0x829
849
        13: polynom = 32'b1000000001100;                    // 0x100C
850
        14: polynom = 32'b10000000010101;                   // 0x2015
851
        15: polynom = 32'b110000000000000;                  // 0x6000
852
        16: polynom = 32'b1101000000001000;                 // 0xD008
853
        17: polynom = 32'b10010000000000000;                // 0x12000
854
        18: polynom = 32'b100000010000000000;               // 0x20400
855
        19: polynom = 32'b1000000000000100011;              // 0x40023
856
        20: polynom = 32'b10000010000000000000;             // 0x82000
857
        21: polynom = 32'b101000000000000000000;            // 0x140000
858
        22: polynom = 32'b1100000000000000000000;           // 0x300000
859
        23: polynom = 32'b10000100000000000000000;          // 0x420000
860
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
861
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
862
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
863
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
864
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
865
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
866
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
867
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
868
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
869
        default: polynom = 32'b0;
870
        endcase
871
        lfsr_fb = qi[length];
872
        for (i=length-1; i>=1; i=i-1) begin
873
            if (polynom[i])
874
                lfsr_fb = lfsr_fb  ~^ qi[i];
875
        end
876
    end
877
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
878
   always @ (qi)
879
   begin
880
        case (length)
881
         2: polynom_rew = 32'b11;
882
         3: polynom_rew = 32'b110;
883
         4: polynom_rew = 32'b1100;
884
         5: polynom_rew = 32'b10100;
885
         6: polynom_rew = 32'b110000;
886
         7: polynom_rew = 32'b1100000;
887
         8: polynom_rew = 32'b10111000;
888
         9: polynom_rew = 32'b100010000;
889
        10: polynom_rew = 32'b1001000000;
890
        11: polynom_rew = 32'b10100000000;
891
        12: polynom_rew = 32'b100000101001;
892
        13: polynom_rew = 32'b1000000001100;
893
        14: polynom_rew = 32'b10000000010101;
894
        15: polynom_rew = 32'b110000000000000;
895
        16: polynom_rew = 32'b1101000000001000;
896
        17: polynom_rew = 32'b10010000000000000;
897
        18: polynom_rew = 32'b100000010000000000;
898
        19: polynom_rew = 32'b1000000000000100011;
899
        20: polynom_rew = 32'b10000010000000000000;
900
        21: polynom_rew = 32'b101000000000000000000;
901
        22: polynom_rew = 32'b1100000000000000000000;
902
        23: polynom_rew = 32'b10000100000000000000000;
903
        24: polynom_rew = 32'b111000010000000000000000;
904
        25: polynom_rew = 32'b1001000000000000000000000;
905
        26: polynom_rew = 32'b10000000000000000000100011;
906
        27: polynom_rew = 32'b100000000000000000000010011;
907
        28: polynom_rew = 32'b1100100000000000000000000000;
908
        29: polynom_rew = 32'b10100000000000000000000000000;
909
        30: polynom_rew = 32'b100000000000000000000000101001;
910
        31: polynom_rew = 32'b1001000000000000000000000000000;
911
        32: polynom_rew = 32'b10000000001000000000000000000011;
912
        default: polynom_rew = 32'b0;
913
        endcase
914
        // rotate left
915
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
916
        lfsr_fb_rew = qi[length];
917
        for (i=length-1; i>=1; i=i-1) begin
918
            if (polynom_rew[i])
919
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
920
        end
921
    end
922
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
923
   assign q_next = rew ? q_next_rew : q_next_fw;
924
   always @ (posedge clk or posedge rst)
925
     if (rst)
926
       qi <= {length{1'b0}};
927
     else
928
     if (cke)
929
       qi <= q_next;
930
    always @ (posedge clk or posedge rst)
931
    if (rst)
932
        level1 <= 1'b0;
933
    else
934
    if (cke)
935
    if (q_next == level1_value)
936
        level1 <= 1'b1;
937
    else if (qi == level1_value & rew)
938
        level1 <= 1'b0;
939
endmodule
940
//////////////////////////////////////////////////////////////////////
941
////                                                              ////
942
////  Versatile counter                                           ////
943
////                                                              ////
944
////  Description                                                 ////
945
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
946
////  counter                                                     ////
947
////                                                              ////
948
////  To Do:                                                      ////
949
////   - add LFSR with more taps                                  ////
950
////                                                              ////
951
////  Author(s):                                                  ////
952
////      - Michael Unneback, unneback@opencores.org              ////
953
////        ORSoC AB                                              ////
954
////                                                              ////
955
//////////////////////////////////////////////////////////////////////
956
////                                                              ////
957
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
958
////                                                              ////
959
//// This source file may be used and distributed without         ////
960
//// restriction provided that this copyright statement is not    ////
961
//// removed from the file and that any derivative work contains  ////
962
//// the original copyright notice and the associated disclaimer. ////
963
////                                                              ////
964
//// This source file is free software; you can redistribute it   ////
965
//// and/or modify it under the terms of the GNU Lesser General   ////
966
//// Public License as published by the Free Software Foundation; ////
967
//// either version 2.1 of the License, or (at your option) any   ////
968
//// later version.                                               ////
969
////                                                              ////
970
//// This source is distributed in the hope that it will be       ////
971
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
972
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
973
//// PURPOSE.  See the GNU Lesser General Public License for more ////
974
//// details.                                                     ////
975
////                                                              ////
976
//// You should have received a copy of the GNU Lesser General    ////
977
//// Public License along with this source; if not, download it   ////
978
//// from http://www.opencores.org/lgpl.shtml                     ////
979
////                                                              ////
980
//////////////////////////////////////////////////////////////////////
981
// GRAY counter
982
module cnt_gray ( q, rst, clk);
983
   parameter length = 4;
984
   output reg [length:1] q;
985
   input rst;
986
   input clk;
987
   parameter clear_value = 0;
988
   parameter set_value = 1;
989
   parameter wrap_value = 8;
990
   parameter level1_value = 15;
991
   reg  [length:1] qi;
992
   wire [length:1] q_next;
993
   assign q_next = qi + {{length-1{1'b0}},1'b1};
994
   always @ (posedge clk or posedge rst)
995
     if (rst)
996
       qi <= {length{1'b0}};
997
     else
998
       qi <= q_next;
999
   always @ (posedge clk or posedge rst)
1000
     if (rst)
1001
       q <= {length{1'b0}};
1002
     else
1003
         q <= (q_next>>1) ^ q_next;
1004
endmodule
1005
//////////////////////////////////////////////////////////////////////
1006
////                                                              ////
1007
////  Versatile counter                                           ////
1008
////                                                              ////
1009
////  Description                                                 ////
1010
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1011
////  counter                                                     ////
1012
////                                                              ////
1013
////  To Do:                                                      ////
1014
////   - add LFSR with more taps                                  ////
1015
////                                                              ////
1016
////  Author(s):                                                  ////
1017
////      - Michael Unneback, unneback@opencores.org              ////
1018
////        ORSoC AB                                              ////
1019
////                                                              ////
1020
//////////////////////////////////////////////////////////////////////
1021
////                                                              ////
1022
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1023
////                                                              ////
1024
//// This source file may be used and distributed without         ////
1025
//// restriction provided that this copyright statement is not    ////
1026
//// removed from the file and that any derivative work contains  ////
1027
//// the original copyright notice and the associated disclaimer. ////
1028
////                                                              ////
1029
//// This source file is free software; you can redistribute it   ////
1030
//// and/or modify it under the terms of the GNU Lesser General   ////
1031
//// Public License as published by the Free Software Foundation; ////
1032
//// either version 2.1 of the License, or (at your option) any   ////
1033
//// later version.                                               ////
1034
////                                                              ////
1035
//// This source is distributed in the hope that it will be       ////
1036
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1037
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1038
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1039
//// details.                                                     ////
1040
////                                                              ////
1041
//// You should have received a copy of the GNU Lesser General    ////
1042
//// Public License along with this source; if not, download it   ////
1043
//// from http://www.opencores.org/lgpl.shtml                     ////
1044
////                                                              ////
1045
//////////////////////////////////////////////////////////////////////
1046
// GRAY counter
1047
module cnt_gray_ce ( cke, q, rst, clk);
1048
   parameter length = 4;
1049
   input cke;
1050
   output reg [length:1] q;
1051
   input rst;
1052
   input clk;
1053
   parameter clear_value = 0;
1054
   parameter set_value = 1;
1055
   parameter wrap_value = 8;
1056
   parameter level1_value = 15;
1057
   reg  [length:1] qi;
1058
   wire [length:1] q_next;
1059
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1060
   always @ (posedge clk or posedge rst)
1061
     if (rst)
1062
       qi <= {length{1'b0}};
1063
     else
1064
     if (cke)
1065
       qi <= q_next;
1066
   always @ (posedge clk or posedge rst)
1067
     if (rst)
1068
       q <= {length{1'b0}};
1069
     else
1070
       if (cke)
1071
         q <= (q_next>>1) ^ q_next;
1072
endmodule
1073
//////////////////////////////////////////////////////////////////////
1074
////                                                              ////
1075
////  Versatile counter                                           ////
1076
////                                                              ////
1077
////  Description                                                 ////
1078
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1079
////  counter                                                     ////
1080
////                                                              ////
1081
////  To Do:                                                      ////
1082
////   - add LFSR with more taps                                  ////
1083
////                                                              ////
1084
////  Author(s):                                                  ////
1085
////      - Michael Unneback, unneback@opencores.org              ////
1086
////        ORSoC AB                                              ////
1087
////                                                              ////
1088
//////////////////////////////////////////////////////////////////////
1089
////                                                              ////
1090
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1091
////                                                              ////
1092
//// This source file may be used and distributed without         ////
1093
//// restriction provided that this copyright statement is not    ////
1094
//// removed from the file and that any derivative work contains  ////
1095
//// the original copyright notice and the associated disclaimer. ////
1096
////                                                              ////
1097
//// This source file is free software; you can redistribute it   ////
1098
//// and/or modify it under the terms of the GNU Lesser General   ////
1099
//// Public License as published by the Free Software Foundation; ////
1100
//// either version 2.1 of the License, or (at your option) any   ////
1101
//// later version.                                               ////
1102
////                                                              ////
1103
//// This source is distributed in the hope that it will be       ////
1104
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1105
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1106
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1107
//// details.                                                     ////
1108
////                                                              ////
1109
//// You should have received a copy of the GNU Lesser General    ////
1110
//// Public License along with this source; if not, download it   ////
1111
//// from http://www.opencores.org/lgpl.shtml                     ////
1112
////                                                              ////
1113
//////////////////////////////////////////////////////////////////////
1114
// GRAY counter
1115
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1116
   parameter length = 4;
1117
   input cke;
1118
   output reg [length:1] q;
1119
   output [length:1] q_bin;
1120
   input rst;
1121
   input clk;
1122
   parameter clear_value = 0;
1123
   parameter set_value = 1;
1124
   parameter wrap_value = 8;
1125
   parameter level1_value = 15;
1126
   reg  [length:1] qi;
1127
   wire [length:1] q_next;
1128
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1129
   always @ (posedge clk or posedge rst)
1130
     if (rst)
1131
       qi <= {length{1'b0}};
1132
     else
1133
     if (cke)
1134
       qi <= q_next;
1135
   always @ (posedge clk or posedge rst)
1136
     if (rst)
1137
       q <= {length{1'b0}};
1138
     else
1139
       if (cke)
1140
         q <= (q_next>>1) ^ q_next;
1141
   assign q_bin = qi;
1142
endmodule
1143
//////////////////////////////////////////////////////////////////////
1144
////                                                              ////
1145
////  Versatile library, counters                                 ////
1146
////                                                              ////
1147
////  Description                                                 ////
1148
////  counters                                                    ////
1149
////                                                              ////
1150
////                                                              ////
1151
////  To Do:                                                      ////
1152
////   - add more counters                                        ////
1153
////                                                              ////
1154
////  Author(s):                                                  ////
1155
////      - Michael Unneback, unneback@opencores.org              ////
1156
////        ORSoC AB                                              ////
1157
////                                                              ////
1158
//////////////////////////////////////////////////////////////////////
1159
////                                                              ////
1160
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1161
////                                                              ////
1162
//// This source file may be used and distributed without         ////
1163
//// restriction provided that this copyright statement is not    ////
1164
//// removed from the file and that any derivative work contains  ////
1165
//// the original copyright notice and the associated disclaimer. ////
1166
////                                                              ////
1167
//// This source file is free software; you can redistribute it   ////
1168
//// and/or modify it under the terms of the GNU Lesser General   ////
1169
//// Public License as published by the Free Software Foundation; ////
1170
//// either version 2.1 of the License, or (at your option) any   ////
1171
//// later version.                                               ////
1172
////                                                              ////
1173
//// This source is distributed in the hope that it will be       ////
1174
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1175
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1176
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1177
//// details.                                                     ////
1178
////                                                              ////
1179
//// You should have received a copy of the GNU Lesser General    ////
1180
//// Public License along with this source; if not, download it   ////
1181
//// from http://www.opencores.org/lgpl.shtml                     ////
1182
////                                                              ////
1183
//////////////////////////////////////////////////////////////////////
1184
module cnt_shreg_wrap ( q, rst, clk);
1185
   parameter length = 4;
1186
   output reg [0:length-1] q;
1187
   input rst;
1188
   input clk;
1189
    always @ (posedge clk or posedge rst)
1190
    if (rst)
1191
        q <= {1'b1,{length-1{1'b0}}};
1192
    else
1193
        q <= {q[length-1],q[0:length-2]};
1194
endmodule
1195
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1196
   parameter length = 4;
1197
   input cke;
1198
   output reg [0:length-1] q;
1199
   input rst;
1200
   input clk;
1201
    always @ (posedge clk or posedge rst)
1202
    if (rst)
1203
        q <= {1'b1,{length-1{1'b0}}};
1204
    else
1205
        if (cke)
1206
            q <= {q[length-1],q[0:length-2]};
1207
endmodule
1208
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1209
   parameter length = 4;
1210
   input cke, clear;
1211
   output reg [0:length-1] q;
1212
   input rst;
1213
   input clk;
1214
    always @ (posedge clk or posedge rst)
1215
    if (rst)
1216
        q <= {1'b1,{length-1{1'b0}}};
1217
    else
1218
        if (cke)
1219
            if (clear)
1220
                q <= {1'b1,{length-1{1'b0}}};
1221
            else
1222
                q <= q >> 1;
1223
endmodule
1224
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1225
   parameter length = 4;
1226
   input cke, clear;
1227
   output reg [0:length-1] q;
1228
   input rst;
1229
   input clk;
1230
    always @ (posedge clk or posedge rst)
1231
    if (rst)
1232
        q <= {1'b1,{length-1{1'b0}}};
1233
    else
1234
        if (cke)
1235
            if (clear)
1236
                q <= {1'b1,{length-1{1'b0}}};
1237
            else
1238
            q <= {q[length-1],q[0:length-2]};
1239
endmodule
1240
//////////////////////////////////////////////////////////////////////
1241
////                                                              ////
1242
////  Versatile library, memories                                 ////
1243
////                                                              ////
1244
////  Description                                                 ////
1245
////  memories                                                    ////
1246
////                                                              ////
1247
////                                                              ////
1248
////  To Do:                                                      ////
1249
////   - add more memory types                                    ////
1250
////                                                              ////
1251
////  Author(s):                                                  ////
1252
////      - Michael Unneback, unneback@opencores.org              ////
1253
////        ORSoC AB                                              ////
1254
////                                                              ////
1255
//////////////////////////////////////////////////////////////////////
1256
////                                                              ////
1257
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1258
////                                                              ////
1259
//// This source file may be used and distributed without         ////
1260
//// restriction provided that this copyright statement is not    ////
1261
//// removed from the file and that any derivative work contains  ////
1262
//// the original copyright notice and the associated disclaimer. ////
1263
////                                                              ////
1264
//// This source file is free software; you can redistribute it   ////
1265
//// and/or modify it under the terms of the GNU Lesser General   ////
1266
//// Public License as published by the Free Software Foundation; ////
1267
//// either version 2.1 of the License, or (at your option) any   ////
1268
//// later version.                                               ////
1269
////                                                              ////
1270
//// This source is distributed in the hope that it will be       ////
1271
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1272
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1273
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1274
//// details.                                                     ////
1275
////                                                              ////
1276
//// You should have received a copy of the GNU Lesser General    ////
1277
//// Public License along with this source; if not, download it   ////
1278
//// from http://www.opencores.org/lgpl.shtml                     ////
1279
////                                                              ////
1280
//////////////////////////////////////////////////////////////////////
1281
/// ROM
1282 7 unneback
module vl_rom_init ( adr, q, clk);
1283
   parameter data_width = 32;
1284
   parameter addr_width = 8;
1285
   input [(addr_width-1):0]       adr;
1286
   output reg [(data_width-1):0] q;
1287
   input                         clk;
1288
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1289
   parameter memory_file = "vl_rom.vmem";
1290
   initial
1291
     begin
1292
        $readmemh(memory_file, rom);
1293
     end
1294
   always @ (posedge clk)
1295
     q <= rom[adr];
1296
endmodule
1297
module vl_rom ( adr, q, clk);
1298 6 unneback
parameter data_width = 32;
1299
parameter addr_width = 4;
1300
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1301
    {32'h18000000},
1302
    {32'hA8200000},
1303
    {32'hA8200000},
1304
    {32'hA8200000},
1305
    {32'h44003000},
1306
    {32'h15000000},
1307
    {32'h15000000},
1308
    {32'h15000000},
1309
    {32'h15000000},
1310
    {32'h15000000},
1311
    {32'h15000000},
1312
    {32'h15000000},
1313
    {32'h15000000},
1314
    {32'h15000000},
1315
    {32'h15000000},
1316
    {32'h15000000}};
1317 7 unneback
input [addr_width-1:0] adr;
1318 6 unneback
output reg [data_width-1:0] q;
1319
input clk;
1320
always @ (posedge clk)
1321 7 unneback
    q <= data[adr];
1322 6 unneback
endmodule
1323
// Single port RAM
1324
module vl_ram ( d, adr, we, q, clk);
1325
   parameter data_width = 32;
1326
   parameter addr_width = 8;
1327
   input [(data_width-1):0]      d;
1328
   input [(addr_width-1):0]       adr;
1329
   input                         we;
1330 7 unneback
   output reg [(data_width-1):0] q;
1331 6 unneback
   input                         clk;
1332
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1333 7 unneback
   parameter init = 0;
1334
   parameter memory_file = "vl_ram.vmem";
1335
   generate if (init) begin : init_mem
1336
   initial
1337
     begin
1338
        $readmemh(memory_file, ram);
1339
     end
1340
   end
1341
   endgenerate
1342 6 unneback
   always @ (posedge clk)
1343
   begin
1344
   if (we)
1345
     ram[adr] <= d;
1346
   q <= ram[adr];
1347
   end
1348
endmodule
1349 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1350
   parameter data_width = 32;
1351
   parameter addr_width = 8;
1352
   input [(data_width-1):0]      d;
1353
   input [(addr_width-1):0]       adr;
1354
   input [(addr_width/4)-1:0]    be;
1355
   input                         we;
1356
   output reg [(data_width-1):0] q;
1357
   input                         clk;
1358
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1359
   parameter init = 0;
1360
   parameter memory_file = "vl_ram.vmem";
1361
   generate if (init) begin : init_mem
1362
   initial
1363
     begin
1364
        $readmemh(memory_file, ram);
1365
     end
1366
   end
1367
   endgenerate
1368
   genvar i;
1369
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1370
      always @ (posedge clk)
1371
      if (we & be[i])
1372
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1373
   end
1374
   endgenerate
1375
   always @ (posedge clk)
1376
      q <= ram[adr];
1377
endmodule
1378 6 unneback
// Dual port RAM
1379
// ACTEL FPGA should not use logic to handle rw collision
1380 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1381 6 unneback
   parameter data_width = 32;
1382
   parameter addr_width = 8;
1383
   input [(data_width-1):0]      d_a;
1384
   input [(addr_width-1):0]       adr_a;
1385
   input [(addr_width-1):0]       adr_b;
1386
   input                         we_a;
1387
   output [(data_width-1):0]      q_b;
1388
   input                         clk_a, clk_b;
1389
   reg [(addr_width-1):0]         adr_b_reg;
1390
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1391 7 unneback
   parameter init = 0;
1392
   parameter memory_file = "vl_ram.vmem";
1393
   generate if (init) begin : init_mem
1394
   initial
1395
     begin
1396
        $readmemh(memory_file, ram);
1397
     end
1398
   end
1399
   endgenerate
1400 6 unneback
   always @ (posedge clk_a)
1401
   if (we_a)
1402
     ram[adr_a] <= d_a;
1403
   always @ (posedge clk_b)
1404
   adr_b_reg <= adr_b;
1405
   assign q_b = ram[adr_b_reg];
1406
endmodule
1407 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1408 6 unneback
   parameter data_width = 32;
1409
   parameter addr_width = 8;
1410
   input [(data_width-1):0]      d_a;
1411
   input [(addr_width-1):0]       adr_a;
1412
   input [(addr_width-1):0]       adr_b;
1413
   input                         we_a;
1414
   output [(data_width-1):0]      q_b;
1415
   output reg [(data_width-1):0] q_a;
1416
   input                         clk_a, clk_b;
1417
   reg [(data_width-1):0]         q_b;
1418
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1419 7 unneback
   parameter init = 0;
1420
   parameter memory_file = "vl_ram.vmem";
1421
   generate if (init) begin : init_mem
1422
   initial
1423
     begin
1424
        $readmemh(memory_file, ram);
1425
     end
1426
   end
1427
   endgenerate
1428 6 unneback
   always @ (posedge clk_a)
1429
     begin
1430
        q_a <= ram[adr_a];
1431
        if (we_a)
1432
             ram[adr_a] <= d_a;
1433
     end
1434
   always @ (posedge clk_b)
1435
          q_b <= ram[adr_b];
1436
endmodule
1437 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1438 6 unneback
   parameter data_width = 32;
1439
   parameter addr_width = 8;
1440
   input [(data_width-1):0]      d_a;
1441
   input [(addr_width-1):0]       adr_a;
1442
   input [(addr_width-1):0]       adr_b;
1443
   input                         we_a;
1444
   output [(data_width-1):0]      q_b;
1445
   input [(data_width-1):0]       d_b;
1446
   output reg [(data_width-1):0] q_a;
1447
   input                         we_b;
1448
   input                         clk_a, clk_b;
1449
   reg [(data_width-1):0]         q_b;
1450
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1451 7 unneback
   parameter init = 0;
1452
   parameter memory_file = "vl_ram.vmem";
1453
   generate if (init) begin : init_mem
1454
   initial
1455
     begin
1456
        $readmemh(memory_file, ram);
1457
     end
1458
   end
1459
   endgenerate
1460 6 unneback
   always @ (posedge clk_a)
1461
     begin
1462
        q_a <= ram[adr_a];
1463
        if (we_a)
1464
             ram[adr_a] <= d_a;
1465
     end
1466
   always @ (posedge clk_b)
1467
     begin
1468
        q_b <= ram[adr_b];
1469
        if (we_b)
1470
          ram[adr_b] <= d_b;
1471
     end
1472
endmodule
1473
// Content addresable memory, CAM
1474
// FIFO
1475
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1476 11 unneback
   parameter addr_width = 4;
1477
   parameter N = addr_width-1;
1478 6 unneback
   parameter Q1 = 2'b00;
1479
   parameter Q2 = 2'b01;
1480
   parameter Q3 = 2'b11;
1481
   parameter Q4 = 2'b10;
1482
   parameter going_empty = 1'b0;
1483
   parameter going_full  = 1'b1;
1484
   input [N:0]  wptr, rptr;
1485
   output reg   fifo_empty;
1486
   output       fifo_full;
1487
   input        wclk, rclk, rst;
1488
   wire direction;
1489
   reg  direction_set, direction_clr;
1490
   wire async_empty, async_full;
1491
   wire fifo_full2;
1492
   reg  fifo_empty2;
1493
   // direction_set
1494
   always @ (wptr[N:N-1] or rptr[N:N-1])
1495
     case ({wptr[N:N-1],rptr[N:N-1]})
1496
       {Q1,Q2} : direction_set <= 1'b1;
1497
       {Q2,Q3} : direction_set <= 1'b1;
1498
       {Q3,Q4} : direction_set <= 1'b1;
1499
       {Q4,Q1} : direction_set <= 1'b1;
1500
       default : direction_set <= 1'b0;
1501
     endcase
1502
   // direction_clear
1503
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1504
     if (rst)
1505
       direction_clr <= 1'b1;
1506
     else
1507
       case ({wptr[N:N-1],rptr[N:N-1]})
1508
         {Q2,Q1} : direction_clr <= 1'b1;
1509
         {Q3,Q2} : direction_clr <= 1'b1;
1510
         {Q4,Q3} : direction_clr <= 1'b1;
1511
         {Q1,Q4} : direction_clr <= 1'b1;
1512
         default : direction_clr <= 1'b0;
1513
       endcase
1514
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1515
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1516
   assign async_full  = (wptr == rptr) && (direction==going_full);
1517
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1518
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1519
/*
1520
   always @ (posedge wclk or posedge rst or posedge async_full)
1521
     if (rst)
1522
       {fifo_full, fifo_full2} <= 2'b00;
1523
     else if (async_full)
1524
       {fifo_full, fifo_full2} <= 2'b11;
1525
     else
1526
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1527
*/
1528
   always @ (posedge rclk or posedge async_empty)
1529
     if (async_empty)
1530
       {fifo_empty, fifo_empty2} <= 2'b11;
1531
     else
1532
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
1533
endmodule // async_comp
1534
module vl_fifo_1r1w_async (
1535
    d, wr, fifo_full, wr_clk, wr_rst,
1536
    q, rd, fifo_empty, rd_clk, rd_rst
1537
    );
1538
parameter data_width = 18;
1539
parameter addr_width = 4;
1540
// write side
1541
input  [data_width-1:0] d;
1542
input                   wr;
1543
output                  fifo_full;
1544
input                   wr_clk;
1545
input                   wr_rst;
1546
// read side
1547
output [data_width-1:0] q;
1548
input                   rd;
1549
output                  fifo_empty;
1550
input                   rd_clk;
1551
input                   rd_rst;
1552
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1553
vl_fifo_1r1w_async (
1554
    d, wr, fifo_full, wr_clk, wr_rst,
1555
    q, rd, fifo_empty, rd_clk, rd_rst
1556
    );
1557 7 unneback
cnt_gray_ce_bin
1558 6 unneback
    # ( .length(addr_width))
1559
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1560 7 unneback
cnt_gray_ce_bin
1561 6 unneback
    # (.length(addr_width))
1562
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1563 7 unneback
vl_dpram_1r1w
1564 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1565
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1566
vl_fifo_cmp_async
1567
    # (.addr_width(addr_width))
1568
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1569
endmodule
1570 8 unneback
module vl_fifo_2r2w_async (
1571 6 unneback
    // a side
1572
    a_d, a_wr, a_fifo_full,
1573
    a_q, a_rd, a_fifo_empty,
1574
    a_clk, a_rst,
1575
    // b side
1576
    b_d, b_wr, b_fifo_full,
1577
    b_q, b_rd, b_fifo_empty,
1578
    b_clk, b_rst
1579
    );
1580
parameter data_width = 18;
1581
parameter addr_width = 4;
1582
// a side
1583
input  [data_width-1:0] a_d;
1584
input                   a_wr;
1585
output                  a_fifo_full;
1586
output [data_width-1:0] a_q;
1587
input                   a_rd;
1588
output                  a_fifo_empty;
1589
input                   a_clk;
1590
input                   a_rst;
1591
// b side
1592
input  [data_width-1:0] b_d;
1593
input                   b_wr;
1594
output                  b_fifo_full;
1595
output [data_width-1:0] b_q;
1596
input                   b_rd;
1597
output                  b_fifo_empty;
1598
input                   b_clk;
1599
input                   b_rst;
1600
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1601
vl_fifo_1r1w_async_a (
1602
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1603
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1604
    );
1605
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1606
vl_fifo_1r1w_async_b (
1607
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1608
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1609
    );
1610
endmodule
1611 8 unneback
module vl_fifo_2r2w_async_simplex (
1612 6 unneback
    // a side
1613
    a_d, a_wr, a_fifo_full,
1614
    a_q, a_rd, a_fifo_empty,
1615
    a_clk, a_rst,
1616
    // b side
1617
    b_d, b_wr, b_fifo_full,
1618
    b_q, b_rd, b_fifo_empty,
1619
    b_clk, b_rst
1620
    );
1621
parameter data_width = 18;
1622
parameter addr_width = 4;
1623
// a side
1624
input  [data_width-1:0] a_d;
1625
input                   a_wr;
1626
output                  a_fifo_full;
1627
output [data_width-1:0] a_q;
1628
input                   a_rd;
1629
output                  a_fifo_empty;
1630
input                   a_clk;
1631
input                   a_rst;
1632
// b side
1633
input  [data_width-1:0] b_d;
1634
input                   b_wr;
1635
output                  b_fifo_full;
1636
output [data_width-1:0] b_q;
1637
input                   b_rd;
1638
output                  b_fifo_empty;
1639
input                   b_clk;
1640
input                   b_rst;
1641
// adr_gen
1642
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1643
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1644
// dpram
1645
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1646 7 unneback
cnt_gray_ce_bin
1647 6 unneback
    # ( .length(addr_width))
1648
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1649 7 unneback
cnt_gray_ce_bin
1650 6 unneback
    # (.length(addr_width))
1651
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1652 7 unneback
cnt_gray_ce_bin
1653 6 unneback
    # ( .length(addr_width))
1654
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1655 7 unneback
cnt_gray_ce_bin
1656 6 unneback
    # (.length(addr_width))
1657
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1658
// mux read or write adr to DPRAM
1659
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1660
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1661 11 unneback
vl_dpram_2r2w
1662 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1663
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1664
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1665 11 unneback
vl_fifo_cmp_async
1666 6 unneback
    # (.addr_width(addr_width))
1667
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1668 11 unneback
vl_fifo_cmp_async
1669 6 unneback
    # (.addr_width(addr_width))
1670
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1671
endmodule

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