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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 133

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1 60 unneback
// default SYN_KEEP definition
2 97 unneback
// size to width
3 6 unneback
//////////////////////////////////////////////////////////////////////
4
////                                                              ////
5
////  Versatile library, clock and reset                          ////
6
////                                                              ////
7
////  Description                                                 ////
8
////  Logic related to clock and reset                            ////
9
////                                                              ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add more different registers                             ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Michael Unneback, unneback@opencores.org              ////
16
////        ORSoC AB                                              ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44 21 unneback
//altera
45 33 unneback
module vl_gbuf ( i, o);
46
input i;
47
output o;
48
assign o = i;
49
endmodule
50 6 unneback
 // ALTERA
51
 //ACTEL
52
// sync reset
53 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
54 6 unneback
// output active high global reset sync with two DFFs 
55
`timescale 1 ns/100 ps
56
module vl_sync_rst ( rst_n_i, rst_o, clk);
57
input rst_n_i, clk;
58
output rst_o;
59 18 unneback
reg [1:0] tmp;
60 6 unneback
always @ (posedge clk or negedge rst_n_i)
61
if (!rst_n_i)
62 17 unneback
        tmp <= 2'b11;
63 6 unneback
else
64 33 unneback
        tmp <= {1'b0,tmp[1]};
65 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
66 6 unneback
endmodule
67
// vl_pll
68 32 unneback
///////////////////////////////////////////////////////////////////////////////
69
`timescale 1 ps/1 ps
70
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
71
parameter index = 0;
72
parameter number_of_clk = 1;
73
parameter period_time_0 = 20000;
74
parameter period_time_1 = 20000;
75
parameter period_time_2 = 20000;
76
parameter period_time_3 = 20000;
77
parameter period_time_4 = 20000;
78
parameter lock_delay = 2000000;
79
input clk_i, rst_n_i;
80
output lock;
81
output reg [0:number_of_clk-1] clk_o;
82
output [0:number_of_clk-1] rst_o;
83 33 unneback
`ifdef SIM_PLL
84 32 unneback
always
85
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
86
generate if (number_of_clk > 1)
87
always
88
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
89
endgenerate
90
generate if (number_of_clk > 2)
91
always
92
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
93
endgenerate
94 33 unneback
generate if (number_of_clk > 3)
95 32 unneback
always
96
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
97
endgenerate
98 33 unneback
generate if (number_of_clk > 4)
99 32 unneback
always
100
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
101
endgenerate
102
genvar i;
103
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
104
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
105
end
106
endgenerate
107 33 unneback
//assign #lock_delay lock = rst_n_i;
108
assign lock = rst_n_i;
109 32 unneback
endmodule
110 33 unneback
`else
111
`ifdef VL_PLL0
112
`ifdef VL_PLL0_CLK1
113
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
114
`endif
115
`ifdef VL_PLL0_CLK2
116
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
117
`endif
118
`ifdef VL_PLL0_CLK3
119
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
120
`endif
121
`ifdef VL_PLL0_CLK4
122
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
123
`endif
124
`ifdef VL_PLL0_CLK5
125
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
126
`endif
127
`endif
128
`ifdef VL_PLL1
129
`ifdef VL_PLL1_CLK1
130
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
131
`endif
132
`ifdef VL_PLL1_CLK2
133
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
134
`endif
135
`ifdef VL_PLL1_CLK3
136
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
137
`endif
138
`ifdef VL_PLL1_CLK4
139
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
140
`endif
141
`ifdef VL_PLL1_CLK5
142
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
143
`endif
144
`endif
145
`ifdef VL_PLL2
146
`ifdef VL_PLL2_CLK1
147
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
148
`endif
149
`ifdef VL_PLL2_CLK2
150
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
151
`endif
152
`ifdef VL_PLL2_CLK3
153
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
154
`endif
155
`ifdef VL_PLL2_CLK4
156
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
157
`endif
158
`ifdef VL_PLL2_CLK5
159
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
160
`endif
161
`endif
162
`ifdef VL_PLL3
163
`ifdef VL_PLL3_CLK1
164
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
165
`endif
166
`ifdef VL_PLL3_CLK2
167
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
168
`endif
169
`ifdef VL_PLL3_CLK3
170
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
171
`endif
172
`ifdef VL_PLL3_CLK4
173
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
174
`endif
175
`ifdef VL_PLL3_CLK5
176
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
177
`endif
178
`endif
179 32 unneback
genvar i;
180
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
181 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
182 32 unneback
end
183
endgenerate
184
endmodule
185 33 unneback
`endif
186 32 unneback
///////////////////////////////////////////////////////////////////////////////
187 6 unneback
 //altera
188
 //actel
189
//////////////////////////////////////////////////////////////////////
190
////                                                              ////
191
////  Versatile library, registers                                ////
192
////                                                              ////
193
////  Description                                                 ////
194
////  Different type of registers                                 ////
195
////                                                              ////
196
////                                                              ////
197
////  To Do:                                                      ////
198
////   - add more different registers                             ////
199
////                                                              ////
200
////  Author(s):                                                  ////
201
////      - Michael Unneback, unneback@opencores.org              ////
202
////        ORSoC AB                                              ////
203
////                                                              ////
204
//////////////////////////////////////////////////////////////////////
205
////                                                              ////
206
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
207
////                                                              ////
208
//// This source file may be used and distributed without         ////
209
//// restriction provided that this copyright statement is not    ////
210
//// removed from the file and that any derivative work contains  ////
211
//// the original copyright notice and the associated disclaimer. ////
212
////                                                              ////
213
//// This source file is free software; you can redistribute it   ////
214
//// and/or modify it under the terms of the GNU Lesser General   ////
215
//// Public License as published by the Free Software Foundation; ////
216
//// either version 2.1 of the License, or (at your option) any   ////
217
//// later version.                                               ////
218
////                                                              ////
219
//// This source is distributed in the hope that it will be       ////
220
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
221
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
222
//// PURPOSE.  See the GNU Lesser General Public License for more ////
223
//// details.                                                     ////
224
////                                                              ////
225
//// You should have received a copy of the GNU Lesser General    ////
226
//// Public License along with this source; if not, download it   ////
227
//// from http://www.opencores.org/lgpl.shtml                     ////
228
////                                                              ////
229
//////////////////////////////////////////////////////////////////////
230 18 unneback
module vl_dff ( d, q, clk, rst);
231 6 unneback
        parameter width = 1;
232
        parameter reset_value = 0;
233
        input [width-1:0] d;
234
        input clk, rst;
235
        output reg [width-1:0] q;
236
        always @ (posedge clk or posedge rst)
237
        if (rst)
238
                q <= reset_value;
239
        else
240
                q <= d;
241
endmodule
242 18 unneback
module vl_dff_array ( d, q, clk, rst);
243 6 unneback
        parameter width = 1;
244
        parameter depth = 2;
245
        parameter reset_value = 1'b0;
246
        input [width-1:0] d;
247
        input clk, rst;
248
        output [width-1:0] q;
249
        reg  [0:depth-1] q_tmp [width-1:0];
250
        integer i;
251
        always @ (posedge clk or posedge rst)
252
        if (rst) begin
253
            for (i=0;i<depth;i=i+1)
254
                q_tmp[i] <= {width{reset_value}};
255
        end else begin
256
            q_tmp[0] <= d;
257
            for (i=1;i<depth;i=i+1)
258
                q_tmp[i] <= q_tmp[i-1];
259
        end
260
    assign q = q_tmp[depth-1];
261
endmodule
262 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
263 6 unneback
        parameter width = 1;
264
        parameter reset_value = 0;
265
        input [width-1:0] d;
266
        input ce, clk, rst;
267
        output reg [width-1:0] q;
268
        always @ (posedge clk or posedge rst)
269
        if (rst)
270
                q <= reset_value;
271
        else
272
                if (ce)
273
                        q <= d;
274
endmodule
275 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
276 8 unneback
        parameter width = 1;
277
        parameter reset_value = 0;
278
        input [width-1:0] d;
279 10 unneback
        input ce, clear, clk, rst;
280 8 unneback
        output reg [width-1:0] q;
281
        always @ (posedge clk or posedge rst)
282
        if (rst)
283
            q <= reset_value;
284
        else
285
            if (ce)
286
                if (clear)
287
                    q <= {width{1'b0}};
288
                else
289
                    q <= d;
290
endmodule
291 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
292
        parameter width = 1;
293
        parameter reset_value = 0;
294
        input [width-1:0] d;
295
        input ce, set, clk, rst;
296
        output reg [width-1:0] q;
297
        always @ (posedge clk or posedge rst)
298
        if (rst)
299
            q <= reset_value;
300
        else
301
            if (ce)
302
                if (set)
303
                    q <= {width{1'b1}};
304
                else
305
                    q <= d;
306
endmodule
307 29 unneback
module vl_spr ( sp, r, q, clk, rst);
308 64 unneback
        //parameter width = 1;
309
        parameter reset_value = 1'b0;
310 29 unneback
        input sp, r;
311
        output reg q;
312
        input clk, rst;
313
        always @ (posedge clk or posedge rst)
314
        if (rst)
315
            q <= reset_value;
316
        else
317
            if (sp)
318
                q <= 1'b1;
319
            else if (r)
320
                q <= 1'b0;
321
endmodule
322
module vl_srp ( s, rp, q, clk, rst);
323
        parameter width = 1;
324
        parameter reset_value = 0;
325
        input s, rp;
326
        output reg q;
327
        input clk, rst;
328
        always @ (posedge clk or posedge rst)
329
        if (rst)
330
            q <= reset_value;
331
        else
332
            if (rp)
333
                q <= 1'b0;
334
            else if (s)
335
                q <= 1'b1;
336
endmodule
337 6 unneback
// megafunction wizard: %LPM_FF%
338
// GENERATION: STANDARD
339
// VERSION: WM1.0
340
// MODULE: lpm_ff 
341
// ============================================================
342
// File Name: dff_sr.v
343
// Megafunction Name(s):
344
//                      lpm_ff
345
//
346
// Simulation Library Files(s):
347
//                      lpm
348
// ============================================================
349
// ************************************************************
350
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
351
//
352
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
353
// ************************************************************
354
//Copyright (C) 1991-2010 Altera Corporation
355
//Your use of Altera Corporation's design tools, logic functions 
356
//and other software and tools, and its AMPP partner logic 
357
//functions, and any output files from any of the foregoing 
358
//(including device programming or simulation files), and any 
359
//associated documentation or information are expressly subject 
360
//to the terms and conditions of the Altera Program License 
361
//Subscription Agreement, Altera MegaCore Function License 
362
//Agreement, or other applicable license agreement, including, 
363
//without limitation, that your use is for the sole purpose of 
364
//programming logic devices manufactured by Altera and sold by 
365
//Altera or its authorized distributors.  Please refer to the 
366
//applicable agreement for further details.
367
// synopsys translate_off
368
`timescale 1 ps / 1 ps
369
// synopsys translate_on
370 18 unneback
module vl_dff_sr (
371 6 unneback
        aclr,
372
        aset,
373
        clock,
374
        data,
375
        q);
376
        input     aclr;
377
        input     aset;
378
        input     clock;
379
        input     data;
380
        output    q;
381
        wire [0:0] sub_wire0;
382
        wire [0:0] sub_wire1 = sub_wire0[0:0];
383
        wire  q = sub_wire1;
384
        wire  sub_wire2 = data;
385
        wire  sub_wire3 = sub_wire2;
386
        lpm_ff  lpm_ff_component (
387
                                .aclr (aclr),
388
                                .clock (clock),
389
                                .data (sub_wire3),
390
                                .aset (aset),
391
                                .q (sub_wire0)
392
                                // synopsys translate_off
393
                                ,
394
                                .aload (),
395
                                .enable (),
396
                                .sclr (),
397
                                .sload (),
398
                                .sset ()
399
                                // synopsys translate_on
400
                                );
401
        defparam
402
                lpm_ff_component.lpm_fftype = "DFF",
403
                lpm_ff_component.lpm_type = "LPM_FF",
404
                lpm_ff_component.lpm_width = 1;
405
endmodule
406
// ============================================================
407
// CNX file retrieval info
408
// ============================================================
409
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
410
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
411
// Retrieval info: PRIVATE: ASET NUMERIC "1"
412
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
413
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
414
// Retrieval info: PRIVATE: DFF NUMERIC "1"
415
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
416
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
417
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
418
// Retrieval info: PRIVATE: SSET NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
420
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
421
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
422
// Retrieval info: PRIVATE: nBit NUMERIC "1"
423
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
424
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
425
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
426
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
427
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
428
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
429
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
430
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
431
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
432
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
433
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
434
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
435
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
436
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
437
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
443
// Retrieval info: LIB_FILE: lpm
444
// LATCH
445
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
446 18 unneback
module vl_latch ( d, le, q, clk);
447 6 unneback
input d, le;
448
output q;
449
input clk;
450
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
451
endmodule
452 18 unneback
module vl_shreg ( d, q, clk, rst);
453 17 unneback
parameter depth = 10;
454
input d;
455
output q;
456
input clk, rst;
457
reg [1:depth] dffs;
458
always @ (posedge clk or posedge rst)
459
if (rst)
460
    dffs <= {depth{1'b0}};
461
else
462
    dffs <= {d,dffs[1:depth-1]};
463
assign q = dffs[depth];
464
endmodule
465 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
466 17 unneback
parameter depth = 10;
467
input d, ce;
468
output q;
469
input clk, rst;
470
reg [1:depth] dffs;
471
always @ (posedge clk or posedge rst)
472
if (rst)
473
    dffs <= {depth{1'b0}};
474
else
475
    if (ce)
476
        dffs <= {d,dffs[1:depth-1]};
477
assign q = dffs[depth];
478
endmodule
479 18 unneback
module vl_delay ( d, q, clk, rst);
480 15 unneback
parameter depth = 10;
481
input d;
482
output q;
483
input clk, rst;
484
reg [1:depth] dffs;
485
always @ (posedge clk or posedge rst)
486
if (rst)
487
    dffs <= {depth{1'b0}};
488
else
489
    dffs <= {d,dffs[1:depth-1]};
490
assign q = dffs[depth];
491
endmodule
492 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
493 17 unneback
parameter depth = 10;
494
input d;
495
output q, emptyflag;
496
input clk, rst;
497
reg [1:depth] dffs;
498
always @ (posedge clk or posedge rst)
499
if (rst)
500
    dffs <= {depth{1'b0}};
501
else
502
    dffs <= {d,dffs[1:depth-1]};
503
assign q = dffs[depth];
504
assign emptyflag = !(|dffs);
505
endmodule
506 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
507 94 unneback
input pl;
508 98 unneback
output reg q;
509 94 unneback
input clk, rst;
510
always @ (posedge clk or posedge rst)
511
if (rst)
512
    q <= 1'b0;
513
else
514
    q <= pl ^ q;
515
endmodule
516 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
517 94 unneback
input d;
518
output pl;
519
input clk, rst;
520
reg dff;
521
always @ (posedge clk or posedge rst)
522
if (rst)
523
    dff <= 1'b0;
524
else
525
    dff <= d;
526 98 unneback
assign pl = d ^ dff;
527 94 unneback
endmodule
528
module vl_synchronizer (d, q, clk, rst);
529
input d;
530
output reg q;
531 116 unneback
input clk, rst;
532 94 unneback
reg dff;
533
always @ (posedge clk or posedge rst)
534
if (rst)
535 100 unneback
    {q,dff} <= 2'b00;
536 94 unneback
else
537 100 unneback
    {q,dff} <= {dff,d};
538 94 unneback
endmodule
539 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
540 94 unneback
input start_pl;
541
output take_it_pl;
542
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
543
output got_it_pl;
544
input clk_src, rst_src;
545
input clk_dst, rst_dst;
546
wire take_it_tg, take_it_tg_sync;
547
wire got_it_tg, got_it_tg_sync;
548
// src -> dst
549
vl_pulse2toggle p2t0 (
550
    .pl(start_pl),
551
    .q(take_it_tg),
552
    .clk(clk_src),
553
    .rst(rst_src));
554
vl_synchronizer sync0 (
555
    .d(take_it_tg),
556
    .q(take_it_tg_sync),
557
    .clk(clk_dst),
558
    .rst(rst_dst));
559
vl_toggle2pulse t2p0 (
560 100 unneback
    .d(take_it_tg_sync),
561 94 unneback
    .pl(take_it_pl),
562
    .clk(clk_dst),
563
    .rst(rst_dst));
564
// dst -> src
565 98 unneback
vl_pulse2toggle p2t1 (
566 94 unneback
    .pl(take_it_grant_pl),
567
    .q(got_it_tg),
568
    .clk(clk_dst),
569
    .rst(rst_dst));
570
vl_synchronizer sync1 (
571
    .d(got_it_tg),
572
    .q(got_it_tg_sync),
573
    .clk(clk_src),
574
    .rst(rst_src));
575
vl_toggle2pulse t2p1 (
576 100 unneback
    .d(got_it_tg_sync),
577 94 unneback
    .pl(got_it_pl),
578
    .clk(clk_src),
579
    .rst(rst_src));
580
endmodule
581 6 unneback
//////////////////////////////////////////////////////////////////////
582
////                                                              ////
583 18 unneback
////  Logic functions                                             ////
584
////                                                              ////
585
////  Description                                                 ////
586
////  Logic functions such as multiplexers                        ////
587
////                                                              ////
588
////                                                              ////
589
////  To Do:                                                      ////
590
////   -                                                          ////
591
////                                                              ////
592
////  Author(s):                                                  ////
593
////      - Michael Unneback, unneback@opencores.org              ////
594
////        ORSoC AB                                              ////
595
////                                                              ////
596
//////////////////////////////////////////////////////////////////////
597
////                                                              ////
598
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
599
////                                                              ////
600
//// This source file may be used and distributed without         ////
601
//// restriction provided that this copyright statement is not    ////
602
//// removed from the file and that any derivative work contains  ////
603
//// the original copyright notice and the associated disclaimer. ////
604
////                                                              ////
605
//// This source file is free software; you can redistribute it   ////
606
//// and/or modify it under the terms of the GNU Lesser General   ////
607
//// Public License as published by the Free Software Foundation; ////
608
//// either version 2.1 of the License, or (at your option) any   ////
609
//// later version.                                               ////
610
////                                                              ////
611
//// This source is distributed in the hope that it will be       ////
612
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
613
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
614
//// PURPOSE.  See the GNU Lesser General Public License for more ////
615
//// details.                                                     ////
616
////                                                              ////
617
//// You should have received a copy of the GNU Lesser General    ////
618
//// Public License along with this source; if not, download it   ////
619
//// from http://www.opencores.org/lgpl.shtml                     ////
620
////                                                              ////
621
//////////////////////////////////////////////////////////////////////
622 36 unneback
module vl_mux_andor ( a, sel, dout);
623
parameter width = 32;
624
parameter nr_of_ports = 4;
625
input [nr_of_ports*width-1:0] a;
626
input [nr_of_ports-1:0] sel;
627
output reg [width-1:0] dout;
628 38 unneback
integer i,j;
629 36 unneback
always @ (a, sel)
630
begin
631
    dout = a[width-1:0] & {width{sel[0]}};
632 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
633
        for (j=0;j<width;j=j+1)
634
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
635 36 unneback
end
636
endmodule
637 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
638
parameter width = 32;
639 35 unneback
localparam nr_of_ports = 2;
640 34 unneback
input [width-1:0] a1, a0;
641
input [nr_of_ports-1:0] sel;
642
output [width-1:0] dout;
643 36 unneback
vl_mux_andor
644 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
645 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
646 34 unneback
endmodule
647
module vl_mux3_andor ( a2, a1, a0, sel, dout);
648
parameter width = 32;
649 35 unneback
localparam nr_of_ports = 3;
650 34 unneback
input [width-1:0] a2, a1, a0;
651
input [nr_of_ports-1:0] sel;
652
output [width-1:0] dout;
653 36 unneback
vl_mux_andor
654 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
655 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
656 34 unneback
endmodule
657 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
658
parameter width = 32;
659 35 unneback
localparam nr_of_ports = 4;
660 18 unneback
input [width-1:0] a3, a2, a1, a0;
661
input [nr_of_ports-1:0] sel;
662 22 unneback
output [width-1:0] dout;
663 36 unneback
vl_mux_andor
664 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
665 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
666 18 unneback
endmodule
667
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
668
parameter width = 32;
669 35 unneback
localparam nr_of_ports = 5;
670 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
671
input [nr_of_ports-1:0] sel;
672 22 unneback
output [width-1:0] dout;
673 36 unneback
vl_mux_andor
674 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
675 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
676 18 unneback
endmodule
677
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
678
parameter width = 32;
679 35 unneback
localparam nr_of_ports = 6;
680 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
681
input [nr_of_ports-1:0] sel;
682 22 unneback
output [width-1:0] dout;
683 36 unneback
vl_mux_andor
684 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
685 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
686 18 unneback
endmodule
687 43 unneback
module vl_parity_generate (data, parity);
688
parameter word_size = 32;
689
parameter chunk_size = 8;
690
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
691
input [word_size-1:0] data;
692
output reg [word_size/chunk_size-1:0] parity;
693
integer i,j;
694
always @ (data)
695
for (i=0;i<word_size/chunk_size;i=i+1) begin
696
    parity[i] = parity_type;
697
    for (j=0;j<chunk_size;j=j+1) begin
698 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
699 43 unneback
    end
700
end
701
endmodule
702
module vl_parity_check( data, parity, parity_error);
703
parameter word_size = 32;
704
parameter chunk_size = 8;
705
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
706
input [word_size-1:0] data;
707
input [word_size/chunk_size-1:0] parity;
708
output parity_error;
709 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
710 43 unneback
integer i,j;
711
always @ (data or parity)
712
for (i=0;i<word_size/chunk_size;i=i+1) begin
713
    error_flag[i] = parity[i] ^ parity_type;
714
    for (j=0;j<chunk_size;j=j+1) begin
715 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
716 43 unneback
    end
717
end
718
assign parity_error = |error_flag;
719
endmodule
720 18 unneback
//////////////////////////////////////////////////////////////////////
721
////                                                              ////
722 44 unneback
////  IO functions                                                ////
723
////                                                              ////
724
////  Description                                                 ////
725
////  IO functions such as IOB flip-flops                         ////
726
////                                                              ////
727
////                                                              ////
728
////  To Do:                                                      ////
729
////   -                                                          ////
730
////                                                              ////
731
////  Author(s):                                                  ////
732
////      - Michael Unneback, unneback@opencores.org              ////
733
////        ORSoC AB                                              ////
734
////                                                              ////
735
//////////////////////////////////////////////////////////////////////
736
////                                                              ////
737
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
738
////                                                              ////
739
//// This source file may be used and distributed without         ////
740
//// restriction provided that this copyright statement is not    ////
741
//// removed from the file and that any derivative work contains  ////
742
//// the original copyright notice and the associated disclaimer. ////
743
////                                                              ////
744
//// This source file is free software; you can redistribute it   ////
745
//// and/or modify it under the terms of the GNU Lesser General   ////
746
//// Public License as published by the Free Software Foundation; ////
747
//// either version 2.1 of the License, or (at your option) any   ////
748
//// later version.                                               ////
749
////                                                              ////
750
//// This source is distributed in the hope that it will be       ////
751
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
752
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
753
//// PURPOSE.  See the GNU Lesser General Public License for more ////
754
//// details.                                                     ////
755
////                                                              ////
756
//// You should have received a copy of the GNU Lesser General    ////
757
//// Public License along with this source; if not, download it   ////
758
//// from http://www.opencores.org/lgpl.shtml                     ////
759
////                                                              ////
760
//////////////////////////////////////////////////////////////////////
761 45 unneback
`timescale 1ns/1ns
762 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
763
parameter width = 1;
764 45 unneback
parameter reset_value = {width{1'b0}};
765
input  [width-1:0]  d_i;
766 44 unneback
output [width-1:0] o_pad;
767
input clk, rst;
768 60 unneback
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
769 45 unneback
reg  [width-1:0] o_pad_int;
770 44 unneback
assign d_i_int = d_i;
771
genvar i;
772 45 unneback
generate
773 44 unneback
for (i=0;i<width;i=i+1) begin
774
    always @ (posedge clk or posedge rst)
775
    if (rst)
776 45 unneback
        o_pad_int[i] <= reset_value[i];
777 44 unneback
    else
778 45 unneback
        o_pad_int[i] <= d_i_int[i];
779
    assign #1 o_pad[i] = o_pad_int[i];
780 44 unneback
end
781
endgenerate
782
endmodule
783 45 unneback
`timescale 1ns/1ns
784 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
785
parameter width = 1;
786
input  [width-1:0] d_o;
787
output reg [width-1:0] d_i;
788
input oe;
789
inout [width-1:0] io_pad;
790
input clk, rst;
791 60 unneback
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
792 44 unneback
reg [width-1:0] oe_q;
793
reg [width-1:0] d_o_q;
794
assign oe_d = {width{oe}};
795
genvar i;
796
generate
797
for (i=0;i<width;i=i+1) begin
798
    always @ (posedge clk or posedge rst)
799
    if (rst)
800
        oe_q[i] <= 1'b0;
801
    else
802
        oe_q[i] <= oe_d[i];
803
    always @ (posedge clk or posedge rst)
804
    if (rst)
805
        d_o_q[i] <= 1'b0;
806
    else
807
        d_o_q[i] <= d_o[i];
808
    always @ (posedge clk or posedge rst)
809
    if (rst)
810
        d_i[i] <= 1'b0;
811
    else
812
        d_i[i] <= io_pad[i];
813 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
814 44 unneback
end
815
endgenerate
816
endmodule
817
//////////////////////////////////////////////////////////////////////
818
////                                                              ////
819 6 unneback
////  Versatile counter                                           ////
820
////                                                              ////
821
////  Description                                                 ////
822
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
823
////  counter                                                     ////
824
////                                                              ////
825
////  To Do:                                                      ////
826
////   - add LFSR with more taps                                  ////
827
////                                                              ////
828
////  Author(s):                                                  ////
829
////      - Michael Unneback, unneback@opencores.org              ////
830
////        ORSoC AB                                              ////
831
////                                                              ////
832
//////////////////////////////////////////////////////////////////////
833
////                                                              ////
834
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
835
////                                                              ////
836
//// This source file may be used and distributed without         ////
837
//// restriction provided that this copyright statement is not    ////
838
//// removed from the file and that any derivative work contains  ////
839
//// the original copyright notice and the associated disclaimer. ////
840
////                                                              ////
841
//// This source file is free software; you can redistribute it   ////
842
//// and/or modify it under the terms of the GNU Lesser General   ////
843
//// Public License as published by the Free Software Foundation; ////
844
//// either version 2.1 of the License, or (at your option) any   ////
845
//// later version.                                               ////
846
////                                                              ////
847
//// This source is distributed in the hope that it will be       ////
848
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
849
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
850
//// PURPOSE.  See the GNU Lesser General Public License for more ////
851
//// details.                                                     ////
852
////                                                              ////
853
//// You should have received a copy of the GNU Lesser General    ////
854
//// Public License along with this source; if not, download it   ////
855
//// from http://www.opencores.org/lgpl.shtml                     ////
856
////                                                              ////
857
//////////////////////////////////////////////////////////////////////
858
// binary counter
859 40 unneback
module vl_cnt_bin_ce (
860
 cke, q, rst, clk);
861 22 unneback
   parameter length = 4;
862 6 unneback
   input cke;
863
   output [length:1] q;
864
   input rst;
865
   input clk;
866
   parameter clear_value = 0;
867
   parameter set_value = 1;
868
   parameter wrap_value = 0;
869
   parameter level1_value = 15;
870
   reg  [length:1] qi;
871
   wire [length:1] q_next;
872
   assign q_next = qi + {{length-1{1'b0}},1'b1};
873
   always @ (posedge clk or posedge rst)
874
     if (rst)
875
       qi <= {length{1'b0}};
876
     else
877
     if (cke)
878
       qi <= q_next;
879
   assign q = qi;
880
endmodule
881
//////////////////////////////////////////////////////////////////////
882
////                                                              ////
883
////  Versatile counter                                           ////
884
////                                                              ////
885
////  Description                                                 ////
886
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
887
////  counter                                                     ////
888
////                                                              ////
889
////  To Do:                                                      ////
890
////   - add LFSR with more taps                                  ////
891
////                                                              ////
892
////  Author(s):                                                  ////
893
////      - Michael Unneback, unneback@opencores.org              ////
894
////        ORSoC AB                                              ////
895
////                                                              ////
896
//////////////////////////////////////////////////////////////////////
897
////                                                              ////
898
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
899
////                                                              ////
900
//// This source file may be used and distributed without         ////
901
//// restriction provided that this copyright statement is not    ////
902
//// removed from the file and that any derivative work contains  ////
903
//// the original copyright notice and the associated disclaimer. ////
904
////                                                              ////
905
//// This source file is free software; you can redistribute it   ////
906
//// and/or modify it under the terms of the GNU Lesser General   ////
907
//// Public License as published by the Free Software Foundation; ////
908
//// either version 2.1 of the License, or (at your option) any   ////
909
//// later version.                                               ////
910
////                                                              ////
911
//// This source is distributed in the hope that it will be       ////
912
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
913
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
914
//// PURPOSE.  See the GNU Lesser General Public License for more ////
915
//// details.                                                     ////
916
////                                                              ////
917
//// You should have received a copy of the GNU Lesser General    ////
918
//// Public License along with this source; if not, download it   ////
919
//// from http://www.opencores.org/lgpl.shtml                     ////
920
////                                                              ////
921
//////////////////////////////////////////////////////////////////////
922
// binary counter
923 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
924
 cke, rew, zq, level1, rst, clk);
925 6 unneback
   parameter length = 4;
926
   input cke;
927
   input rew;
928 25 unneback
   output reg zq;
929
   output reg level1;
930
   input rst;
931
   input clk;
932
   parameter clear_value = 0;
933
   parameter set_value = 1;
934
   parameter wrap_value = 1;
935
   parameter level1_value = 15;
936 29 unneback
   wire clear;
937 30 unneback
   assign clear = 1'b0;
938 25 unneback
   reg  [length:1] qi;
939
   wire  [length:1] q_next, q_next_fw, q_next_rew;
940
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
941
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
942
   assign q_next = rew ? q_next_rew : q_next_fw;
943
   always @ (posedge clk or posedge rst)
944
     if (rst)
945
       qi <= {length{1'b0}};
946
     else
947
     if (cke)
948
       qi <= q_next;
949
   always @ (posedge clk or posedge rst)
950
     if (rst)
951
       zq <= 1'b1;
952
     else
953
     if (cke)
954
       zq <= q_next == {length{1'b0}};
955
    always @ (posedge clk or posedge rst)
956
    if (rst)
957
        level1 <= 1'b0;
958
    else
959
    if (cke)
960 29 unneback
    if (clear)
961
        level1 <= 1'b0;
962
    else if (q_next == level1_value)
963 25 unneback
        level1 <= 1'b1;
964
    else if (qi == level1_value & rew)
965
        level1 <= 1'b0;
966
endmodule
967
//////////////////////////////////////////////////////////////////////
968
////                                                              ////
969
////  Versatile counter                                           ////
970
////                                                              ////
971
////  Description                                                 ////
972
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
973
////  counter                                                     ////
974
////                                                              ////
975
////  To Do:                                                      ////
976
////   - add LFSR with more taps                                  ////
977
////                                                              ////
978
////  Author(s):                                                  ////
979
////      - Michael Unneback, unneback@opencores.org              ////
980
////        ORSoC AB                                              ////
981
////                                                              ////
982
//////////////////////////////////////////////////////////////////////
983
////                                                              ////
984
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
985
////                                                              ////
986
//// This source file may be used and distributed without         ////
987
//// restriction provided that this copyright statement is not    ////
988
//// removed from the file and that any derivative work contains  ////
989
//// the original copyright notice and the associated disclaimer. ////
990
////                                                              ////
991
//// This source file is free software; you can redistribute it   ////
992
//// and/or modify it under the terms of the GNU Lesser General   ////
993
//// Public License as published by the Free Software Foundation; ////
994
//// either version 2.1 of the License, or (at your option) any   ////
995
//// later version.                                               ////
996
////                                                              ////
997
//// This source is distributed in the hope that it will be       ////
998
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
999
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1000
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1001
//// details.                                                     ////
1002
////                                                              ////
1003
//// You should have received a copy of the GNU Lesser General    ////
1004
//// Public License along with this source; if not, download it   ////
1005
//// from http://www.opencores.org/lgpl.shtml                     ////
1006
////                                                              ////
1007
//////////////////////////////////////////////////////////////////////
1008
// binary counter
1009 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
1010
 cke, rew, q, zq, level1, rst, clk);
1011 25 unneback
   parameter length = 4;
1012
   input cke;
1013
   input rew;
1014
   output [length:1] q;
1015
   output reg zq;
1016
   output reg level1;
1017
   input rst;
1018
   input clk;
1019
   parameter clear_value = 0;
1020
   parameter set_value = 1;
1021
   parameter wrap_value = 1;
1022
   parameter level1_value = 15;
1023 29 unneback
   wire clear;
1024 30 unneback
   assign clear = 1'b0;
1025 25 unneback
   reg  [length:1] qi;
1026
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1027
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1028
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1029
   assign q_next = rew ? q_next_rew : q_next_fw;
1030
   always @ (posedge clk or posedge rst)
1031
     if (rst)
1032
       qi <= {length{1'b0}};
1033
     else
1034
     if (cke)
1035
       qi <= q_next;
1036
   assign q = qi;
1037
   always @ (posedge clk or posedge rst)
1038
     if (rst)
1039
       zq <= 1'b1;
1040
     else
1041
     if (cke)
1042
       zq <= q_next == {length{1'b0}};
1043
    always @ (posedge clk or posedge rst)
1044
    if (rst)
1045
        level1 <= 1'b0;
1046
    else
1047
    if (cke)
1048 29 unneback
    if (clear)
1049
        level1 <= 1'b0;
1050
    else if (q_next == level1_value)
1051 25 unneback
        level1 <= 1'b1;
1052
    else if (qi == level1_value & rew)
1053
        level1 <= 1'b0;
1054
endmodule
1055
//////////////////////////////////////////////////////////////////////
1056
////                                                              ////
1057
////  Versatile counter                                           ////
1058
////                                                              ////
1059
////  Description                                                 ////
1060
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1061
////  counter                                                     ////
1062
////                                                              ////
1063
////  To Do:                                                      ////
1064
////   - add LFSR with more taps                                  ////
1065
////                                                              ////
1066
////  Author(s):                                                  ////
1067
////      - Michael Unneback, unneback@opencores.org              ////
1068
////        ORSoC AB                                              ////
1069
////                                                              ////
1070
//////////////////////////////////////////////////////////////////////
1071
////                                                              ////
1072
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1073
////                                                              ////
1074
//// This source file may be used and distributed without         ////
1075
//// restriction provided that this copyright statement is not    ////
1076
//// removed from the file and that any derivative work contains  ////
1077
//// the original copyright notice and the associated disclaimer. ////
1078
////                                                              ////
1079
//// This source file is free software; you can redistribute it   ////
1080
//// and/or modify it under the terms of the GNU Lesser General   ////
1081
//// Public License as published by the Free Software Foundation; ////
1082
//// either version 2.1 of the License, or (at your option) any   ////
1083
//// later version.                                               ////
1084
////                                                              ////
1085
//// This source is distributed in the hope that it will be       ////
1086
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1087
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1088
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1089
//// details.                                                     ////
1090
////                                                              ////
1091
//// You should have received a copy of the GNU Lesser General    ////
1092
//// Public License along with this source; if not, download it   ////
1093
//// from http://www.opencores.org/lgpl.shtml                     ////
1094
////                                                              ////
1095
//////////////////////////////////////////////////////////////////////
1096 75 unneback
// LFSR counter
1097
module vl_cnt_lfsr_ce (
1098
 cke, zq, rst, clk);
1099
   parameter length = 4;
1100
   input cke;
1101
   output reg zq;
1102
   input rst;
1103
   input clk;
1104
   parameter clear_value = 0;
1105
   parameter set_value = 1;
1106
   parameter wrap_value = 0;
1107
   parameter level1_value = 15;
1108
   reg  [length:1] qi;
1109
   reg lfsr_fb;
1110
   wire [length:1] q_next;
1111
   reg [32:1] polynom;
1112
   integer i;
1113
   always @ (qi)
1114
   begin
1115
        case (length)
1116
         2: polynom = 32'b11;                               // 0x3
1117
         3: polynom = 32'b110;                              // 0x6
1118
         4: polynom = 32'b1100;                             // 0xC
1119
         5: polynom = 32'b10100;                            // 0x14
1120
         6: polynom = 32'b110000;                           // 0x30
1121
         7: polynom = 32'b1100000;                          // 0x60
1122
         8: polynom = 32'b10111000;                         // 0xb8
1123
         9: polynom = 32'b100010000;                        // 0x110
1124
        10: polynom = 32'b1001000000;                       // 0x240
1125
        11: polynom = 32'b10100000000;                      // 0x500
1126
        12: polynom = 32'b100000101001;                     // 0x829
1127
        13: polynom = 32'b1000000001100;                    // 0x100C
1128
        14: polynom = 32'b10000000010101;                   // 0x2015
1129
        15: polynom = 32'b110000000000000;                  // 0x6000
1130
        16: polynom = 32'b1101000000001000;                 // 0xD008
1131
        17: polynom = 32'b10010000000000000;                // 0x12000
1132
        18: polynom = 32'b100000010000000000;               // 0x20400
1133
        19: polynom = 32'b1000000000000100011;              // 0x40023
1134
        20: polynom = 32'b10010000000000000000;             // 0x90000
1135
        21: polynom = 32'b101000000000000000000;            // 0x140000
1136
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1137
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1138
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1139
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1140
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1141
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1142
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1143
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1144
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1145
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1146
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1147
        default: polynom = 32'b0;
1148
        endcase
1149
        lfsr_fb = qi[length];
1150
        for (i=length-1; i>=1; i=i-1) begin
1151
            if (polynom[i])
1152
                lfsr_fb = lfsr_fb  ~^ qi[i];
1153
        end
1154
    end
1155
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1156
   always @ (posedge clk or posedge rst)
1157
     if (rst)
1158
       qi <= {length{1'b0}};
1159
     else
1160
     if (cke)
1161
       qi <= q_next;
1162
   always @ (posedge clk or posedge rst)
1163
     if (rst)
1164
       zq <= 1'b1;
1165
     else
1166
     if (cke)
1167
       zq <= q_next == {length{1'b0}};
1168
endmodule
1169
//////////////////////////////////////////////////////////////////////
1170
////                                                              ////
1171
////  Versatile counter                                           ////
1172
////                                                              ////
1173
////  Description                                                 ////
1174
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1175
////  counter                                                     ////
1176
////                                                              ////
1177
////  To Do:                                                      ////
1178
////   - add LFSR with more taps                                  ////
1179
////                                                              ////
1180
////  Author(s):                                                  ////
1181
////      - Michael Unneback, unneback@opencores.org              ////
1182
////        ORSoC AB                                              ////
1183
////                                                              ////
1184
//////////////////////////////////////////////////////////////////////
1185
////                                                              ////
1186
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1187
////                                                              ////
1188
//// This source file may be used and distributed without         ////
1189
//// restriction provided that this copyright statement is not    ////
1190
//// removed from the file and that any derivative work contains  ////
1191
//// the original copyright notice and the associated disclaimer. ////
1192
////                                                              ////
1193
//// This source file is free software; you can redistribute it   ////
1194
//// and/or modify it under the terms of the GNU Lesser General   ////
1195
//// Public License as published by the Free Software Foundation; ////
1196
//// either version 2.1 of the License, or (at your option) any   ////
1197
//// later version.                                               ////
1198
////                                                              ////
1199
//// This source is distributed in the hope that it will be       ////
1200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1203
//// details.                                                     ////
1204
////                                                              ////
1205
//// You should have received a copy of the GNU Lesser General    ////
1206
//// Public License along with this source; if not, download it   ////
1207
//// from http://www.opencores.org/lgpl.shtml                     ////
1208
////                                                              ////
1209
//////////////////////////////////////////////////////////////////////
1210 6 unneback
// GRAY counter
1211 40 unneback
module vl_cnt_gray_ce_bin (
1212
 cke, q, q_bin, rst, clk);
1213 6 unneback
   parameter length = 4;
1214
   input cke;
1215
   output reg [length:1] q;
1216
   output [length:1] q_bin;
1217
   input rst;
1218
   input clk;
1219
   parameter clear_value = 0;
1220
   parameter set_value = 1;
1221
   parameter wrap_value = 8;
1222
   parameter level1_value = 15;
1223
   reg  [length:1] qi;
1224
   wire [length:1] q_next;
1225
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1226
   always @ (posedge clk or posedge rst)
1227
     if (rst)
1228
       qi <= {length{1'b0}};
1229
     else
1230
     if (cke)
1231
       qi <= q_next;
1232
   always @ (posedge clk or posedge rst)
1233
     if (rst)
1234
       q <= {length{1'b0}};
1235
     else
1236
       if (cke)
1237
         q <= (q_next>>1) ^ q_next;
1238
   assign q_bin = qi;
1239
endmodule
1240
//////////////////////////////////////////////////////////////////////
1241
////                                                              ////
1242
////  Versatile library, counters                                 ////
1243
////                                                              ////
1244
////  Description                                                 ////
1245
////  counters                                                    ////
1246
////                                                              ////
1247
////                                                              ////
1248
////  To Do:                                                      ////
1249
////   - add more counters                                        ////
1250
////                                                              ////
1251
////  Author(s):                                                  ////
1252
////      - Michael Unneback, unneback@opencores.org              ////
1253
////        ORSoC AB                                              ////
1254
////                                                              ////
1255
//////////////////////////////////////////////////////////////////////
1256
////                                                              ////
1257
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1258
////                                                              ////
1259
//// This source file may be used and distributed without         ////
1260
//// restriction provided that this copyright statement is not    ////
1261
//// removed from the file and that any derivative work contains  ////
1262
//// the original copyright notice and the associated disclaimer. ////
1263
////                                                              ////
1264
//// This source file is free software; you can redistribute it   ////
1265
//// and/or modify it under the terms of the GNU Lesser General   ////
1266
//// Public License as published by the Free Software Foundation; ////
1267
//// either version 2.1 of the License, or (at your option) any   ////
1268
//// later version.                                               ////
1269
////                                                              ////
1270
//// This source is distributed in the hope that it will be       ////
1271
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1272
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1273
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1274
//// details.                                                     ////
1275
////                                                              ////
1276
//// You should have received a copy of the GNU Lesser General    ////
1277
//// Public License along with this source; if not, download it   ////
1278
//// from http://www.opencores.org/lgpl.shtml                     ////
1279
////                                                              ////
1280
//////////////////////////////////////////////////////////////////////
1281 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1282 6 unneback
   parameter length = 4;
1283
   output reg [0:length-1] q;
1284
   input rst;
1285
   input clk;
1286
    always @ (posedge clk or posedge rst)
1287
    if (rst)
1288
        q <= {1'b1,{length-1{1'b0}}};
1289
    else
1290
        q <= {q[length-1],q[0:length-2]};
1291
endmodule
1292 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1293 6 unneback
   parameter length = 4;
1294
   input cke;
1295
   output reg [0:length-1] q;
1296
   input rst;
1297
   input clk;
1298
    always @ (posedge clk or posedge rst)
1299
    if (rst)
1300
        q <= {1'b1,{length-1{1'b0}}};
1301
    else
1302
        if (cke)
1303
            q <= {q[length-1],q[0:length-2]};
1304
endmodule
1305 105 unneback
module vl_cnt_shreg_clear ( clear, q, rst, clk);
1306
   parameter length = 4;
1307
   input clear;
1308
   output reg [0:length-1] q;
1309
   input rst;
1310
   input clk;
1311
    always @ (posedge clk or posedge rst)
1312
    if (rst)
1313
        q <= {1'b1,{length-1{1'b0}}};
1314
    else
1315
        if (clear)
1316
            q <= {1'b1,{length-1{1'b0}}};
1317
        else
1318
            q <= q >> 1;
1319
endmodule
1320 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1321 6 unneback
   parameter length = 4;
1322
   input cke, clear;
1323
   output reg [0:length-1] q;
1324
   input rst;
1325
   input clk;
1326
    always @ (posedge clk or posedge rst)
1327
    if (rst)
1328
        q <= {1'b1,{length-1{1'b0}}};
1329
    else
1330
        if (cke)
1331
            if (clear)
1332
                q <= {1'b1,{length-1{1'b0}}};
1333
            else
1334
                q <= q >> 1;
1335
endmodule
1336 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1337 6 unneback
   parameter length = 4;
1338
   input cke, clear;
1339
   output reg [0:length-1] q;
1340
   input rst;
1341
   input clk;
1342
    always @ (posedge clk or posedge rst)
1343
    if (rst)
1344
        q <= {1'b1,{length-1{1'b0}}};
1345
    else
1346
        if (cke)
1347
            if (clear)
1348
                q <= {1'b1,{length-1{1'b0}}};
1349
            else
1350
            q <= {q[length-1],q[0:length-2]};
1351
endmodule
1352
//////////////////////////////////////////////////////////////////////
1353
////                                                              ////
1354
////  Versatile library, memories                                 ////
1355
////                                                              ////
1356
////  Description                                                 ////
1357
////  memories                                                    ////
1358
////                                                              ////
1359
////                                                              ////
1360
////  To Do:                                                      ////
1361
////   - add more memory types                                    ////
1362
////                                                              ////
1363
////  Author(s):                                                  ////
1364
////      - Michael Unneback, unneback@opencores.org              ////
1365
////        ORSoC AB                                              ////
1366
////                                                              ////
1367
//////////////////////////////////////////////////////////////////////
1368
////                                                              ////
1369
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1370
////                                                              ////
1371
//// This source file may be used and distributed without         ////
1372
//// restriction provided that this copyright statement is not    ////
1373
//// removed from the file and that any derivative work contains  ////
1374
//// the original copyright notice and the associated disclaimer. ////
1375
////                                                              ////
1376
//// This source file is free software; you can redistribute it   ////
1377
//// and/or modify it under the terms of the GNU Lesser General   ////
1378
//// Public License as published by the Free Software Foundation; ////
1379
//// either version 2.1 of the License, or (at your option) any   ////
1380
//// later version.                                               ////
1381
////                                                              ////
1382
//// This source is distributed in the hope that it will be       ////
1383
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1384
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1385
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1386
//// details.                                                     ////
1387
////                                                              ////
1388
//// You should have received a copy of the GNU Lesser General    ////
1389
//// Public License along with this source; if not, download it   ////
1390
//// from http://www.opencores.org/lgpl.shtml                     ////
1391
////                                                              ////
1392
//////////////////////////////////////////////////////////////////////
1393
/// ROM
1394 7 unneback
module vl_rom_init ( adr, q, clk);
1395
   parameter data_width = 32;
1396
   parameter addr_width = 8;
1397 75 unneback
   parameter mem_size = 1<<addr_width;
1398 7 unneback
   input [(addr_width-1):0]       adr;
1399
   output reg [(data_width-1):0] q;
1400
   input                         clk;
1401 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1402 7 unneback
   parameter memory_file = "vl_rom.vmem";
1403
   initial
1404
     begin
1405
        $readmemh(memory_file, rom);
1406
     end
1407
   always @ (posedge clk)
1408
     q <= rom[adr];
1409
endmodule
1410 6 unneback
// Single port RAM
1411
module vl_ram ( d, adr, we, q, clk);
1412
   parameter data_width = 32;
1413
   parameter addr_width = 8;
1414 75 unneback
   parameter mem_size = 1<<addr_width;
1415 100 unneback
   parameter debug = 0;
1416 6 unneback
   input [(data_width-1):0]      d;
1417
   input [(addr_width-1):0]       adr;
1418
   input                         we;
1419 7 unneback
   output reg [(data_width-1):0] q;
1420 6 unneback
   input                         clk;
1421 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
1422 100 unneback
    parameter memory_init = 0;
1423
    parameter memory_file = "vl_ram.vmem";
1424
    generate
1425
    if (memory_init == 1) begin : init_mem
1426
        initial
1427
            $readmemh(memory_file, ram);
1428
   end else if (memory_init == 2) begin : init_zero
1429
        integer k;
1430
        initial
1431
            for (k = 0; k < mem_size; k = k + 1)
1432
                ram[k] = 0;
1433 7 unneback
   end
1434
   endgenerate
1435 100 unneback
    generate
1436
    if (debug==1) begin : debug_we
1437
        always @ (posedge clk)
1438
        if (we)
1439
            $display ("Value %h written at address %h : time %t", d, adr, $time);
1440
    end
1441
    endgenerate
1442 6 unneback
   always @ (posedge clk)
1443
   begin
1444
   if (we)
1445
     ram[adr] <= d;
1446
   q <= ram[adr];
1447
   end
1448
endmodule
1449 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1450 7 unneback
   parameter data_width = 32;
1451 72 unneback
   parameter addr_width = 6;
1452 75 unneback
   parameter mem_size = 1<<addr_width;
1453 7 unneback
   input [(data_width-1):0]      d;
1454
   input [(addr_width-1):0]       adr;
1455 73 unneback
   input [(data_width/8)-1:0]    be;
1456 7 unneback
   input                         we;
1457
   output reg [(data_width-1):0] q;
1458
   input                         clk;
1459 65 unneback
`ifdef SYSTEMVERILOG
1460 95 unneback
    // use a multi-dimensional packed array
1461
    //t o model individual bytes within the word
1462
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
1463 65 unneback
`else
1464 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1465
    wire [data_width/8-1:0] cke;
1466 65 unneback
`endif
1467 100 unneback
    parameter memory_init = 0;
1468
    parameter memory_file = "vl_ram.vmem";
1469
    generate
1470
    if (memory_init == 1) begin : init_mem
1471
        initial
1472
            $readmemh(memory_file, ram);
1473
    end else if (memory_init == 2) begin : init_zero
1474
        integer k;
1475
        initial
1476
            for (k = 0; k < mem_size; k = k + 1)
1477
                ram[k] = 0;
1478
    end
1479 7 unneback
   endgenerate
1480 60 unneback
`ifdef SYSTEMVERILOG
1481
always_ff@(posedge clk)
1482
begin
1483 95 unneback
    if(we) begin
1484 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1485
        if(be[2]) ram[adr][2] <= d[23:16];
1486
        if(be[1]) ram[adr][1] <= d[15:8];
1487
        if(be[0]) ram[adr][0] <= d[7:0];
1488 60 unneback
    end
1489 90 unneback
        q <= ram[adr];
1490 60 unneback
end
1491
`else
1492 85 unneback
assign cke = {data_width/8{we}} & be;
1493 7 unneback
   genvar i;
1494 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1495 7 unneback
      always @ (posedge clk)
1496 85 unneback
      if (cke[i])
1497 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1498
   end
1499
   endgenerate
1500
   always @ (posedge clk)
1501
      q <= ram[adr];
1502 60 unneback
`endif
1503 93 unneback
`ifdef verilator
1504 85 unneback
   // Function to access RAM (for use by Verilator).
1505
   function [31:0] get_mem;
1506
      // verilator public
1507 90 unneback
      input [addr_width-1:0]             addr;
1508 85 unneback
      get_mem = ram[addr];
1509
   endfunction // get_mem
1510
   // Function to write RAM (for use by Verilator).
1511
   function set_mem;
1512
      // verilator public
1513 90 unneback
      input [addr_width-1:0]             addr;
1514
      input [data_width-1:0]             data;
1515 85 unneback
      ram[addr] = data;
1516
   endfunction // set_mem
1517 93 unneback
`endif
1518 7 unneback
endmodule
1519
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1520 6 unneback
   parameter data_width = 32;
1521
   parameter addr_width = 8;
1522 75 unneback
   parameter mem_size = 1<<addr_width;
1523 6 unneback
   input [(data_width-1):0]      d_a;
1524
   input [(addr_width-1):0]       adr_a;
1525
   input [(addr_width-1):0]       adr_b;
1526
   input                         we_a;
1527 118 unneback
   output reg [(data_width-1):0]          q_b;
1528 6 unneback
   input                         clk_a, clk_b;
1529 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] ;
1530 100 unneback
    parameter memory_init = 0;
1531
    parameter memory_file = "vl_ram.vmem";
1532
    parameter debug = 0;
1533
    generate
1534
    if (memory_init == 1) begin : init_mem
1535
        initial
1536
            $readmemh(memory_file, ram);
1537
    end else if (memory_init == 2) begin : init_zero
1538
        integer k;
1539
        initial
1540
            for (k = 0; k < mem_size; k = k + 1)
1541
                ram[k] = 0;
1542
    end
1543 7 unneback
   endgenerate
1544 100 unneback
    generate
1545
    if (debug==1) begin : debug_we
1546
        always @ (posedge clk_a)
1547
        if (we_a)
1548
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1549
    end
1550
    endgenerate
1551 6 unneback
   always @ (posedge clk_a)
1552
   if (we_a)
1553
     ram[adr_a] <= d_a;
1554
   always @ (posedge clk_b)
1555 118 unneback
      q_b = ram[adr_b];
1556 6 unneback
endmodule
1557 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1558 6 unneback
   parameter data_width = 32;
1559
   parameter addr_width = 8;
1560 75 unneback
   parameter mem_size = 1<<addr_width;
1561 6 unneback
   input [(data_width-1):0]      d_a;
1562
   input [(addr_width-1):0]       adr_a;
1563
   input [(addr_width-1):0]       adr_b;
1564
   input                         we_a;
1565
   output [(data_width-1):0]      q_b;
1566
   output reg [(data_width-1):0] q_a;
1567
   input                         clk_a, clk_b;
1568
   reg [(data_width-1):0]         q_b;
1569 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] ;
1570 100 unneback
    parameter memory_init = 0;
1571
    parameter memory_file = "vl_ram.vmem";
1572
    parameter debug = 0;
1573
    generate
1574
    if (memory_init == 1) begin : init_mem
1575
        initial
1576
            $readmemh(memory_file, ram);
1577
    end else if (memory_init == 2) begin : init_zero
1578
        integer k;
1579
        initial
1580
            for (k = 0; k < mem_size; k = k + 1)
1581
                ram[k] = 0;
1582
    end
1583 7 unneback
   endgenerate
1584 100 unneback
    generate
1585
    if (debug==1) begin : debug_we
1586
        always @ (posedge clk_a)
1587
        if (we_a)
1588
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1589
    end
1590
    endgenerate
1591 6 unneback
   always @ (posedge clk_a)
1592
     begin
1593
        q_a <= ram[adr_a];
1594
        if (we_a)
1595
             ram[adr_a] <= d_a;
1596
     end
1597
   always @ (posedge clk_b)
1598
          q_b <= ram[adr_b];
1599
endmodule
1600 100 unneback
module vl_dpram_1r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
1601
   parameter data_width = 32;
1602
   parameter addr_width = 8;
1603
   parameter mem_size = 1<<addr_width;
1604
   input [(data_width-1):0]      d_a;
1605
   input [(addr_width-1):0]       adr_a;
1606
   input [(addr_width-1):0]       adr_b;
1607
   input                         we_a;
1608
   input [(data_width-1):0]       d_b;
1609
   output reg [(data_width-1):0] q_a;
1610
   input                         we_b;
1611
   input                         clk_a, clk_b;
1612
   reg [(data_width-1):0]         q_b;
1613 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] ;
1614 100 unneback
    parameter memory_init = 0;
1615
    parameter memory_file = "vl_ram.vmem";
1616
    parameter debug = 0;
1617
    generate
1618
    if (memory_init == 1) begin : init_mem
1619
        initial
1620
            $readmemh(memory_file, ram);
1621
    end else if (memory_init == 2) begin : init_zero
1622
        integer k;
1623
        initial
1624
            for (k = 0; k < mem_size; k = k + 1)
1625
                ram[k] = 0;
1626
    end
1627
   endgenerate
1628
    generate
1629
    if (debug==1) begin : debug_we
1630
        always @ (posedge clk_a)
1631
        if (we_a)
1632
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1633
        always @ (posedge clk_b)
1634
        if (we_b)
1635
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1636
    end
1637
    endgenerate
1638
   always @ (posedge clk_a)
1639
     begin
1640
        q_a <= ram[adr_a];
1641
        if (we_a)
1642
             ram[adr_a] <= d_a;
1643
     end
1644
   always @ (posedge clk_b)
1645
     begin
1646
        if (we_b)
1647
          ram[adr_b] <= d_b;
1648
     end
1649
endmodule
1650 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1651 6 unneback
   parameter data_width = 32;
1652
   parameter addr_width = 8;
1653 75 unneback
   parameter mem_size = 1<<addr_width;
1654 6 unneback
   input [(data_width-1):0]      d_a;
1655
   input [(addr_width-1):0]       adr_a;
1656
   input [(addr_width-1):0]       adr_b;
1657
   input                         we_a;
1658
   output [(data_width-1):0]      q_b;
1659
   input [(data_width-1):0]       d_b;
1660
   output reg [(data_width-1):0] q_a;
1661
   input                         we_b;
1662
   input                         clk_a, clk_b;
1663
   reg [(data_width-1):0]         q_b;
1664 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] ;
1665 100 unneback
    parameter memory_init = 0;
1666
    parameter memory_file = "vl_ram.vmem";
1667
    parameter debug = 0;
1668
    generate
1669
    if (memory_init) begin : init_mem
1670
        initial
1671
            $readmemh(memory_file, ram);
1672
    end else if (memory_init == 2) begin : init_zero
1673
        integer k;
1674
        initial
1675
            for (k = 0; k < mem_size; k = k + 1)
1676
                ram[k] = 0;
1677
    end
1678 7 unneback
   endgenerate
1679 100 unneback
    generate
1680
    if (debug==1) begin : debug_we
1681
        always @ (posedge clk_a)
1682
        if (we_a)
1683
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1684
        always @ (posedge clk_b)
1685
        if (we_b)
1686
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1687
    end
1688
    endgenerate
1689 6 unneback
   always @ (posedge clk_a)
1690
     begin
1691
        q_a <= ram[adr_a];
1692
        if (we_a)
1693
             ram[adr_a] <= d_a;
1694
     end
1695
   always @ (posedge clk_b)
1696
     begin
1697
        q_b <= ram[adr_b];
1698
        if (we_b)
1699
          ram[adr_b] <= d_b;
1700
     end
1701
endmodule
1702 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
1703 75 unneback
   parameter a_data_width = 32;
1704
   parameter a_addr_width = 8;
1705 95 unneback
   parameter b_data_width = 64; //a_data_width;
1706 124 unneback
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1707
   localparam b_addr_width =
1708 125 unneback
        (a_data_width==b_data_width) ? a_addr_width :
1709
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
1710
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
1711
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
1712
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
1713
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
1714
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
1715
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
1716
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
1717
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
1718
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
1719 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
1720
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
1721 100 unneback
   parameter memory_init = 0;
1722 95 unneback
   parameter memory_file = "vl_ram.vmem";
1723 100 unneback
   parameter debug = 0;
1724 75 unneback
   input [(a_data_width-1):0]      d_a;
1725 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1726
   input [(a_data_width/8-1):0]    be_a;
1727
   input                           we_a;
1728 75 unneback
   output reg [(a_data_width-1):0] q_a;
1729 91 unneback
   input [(b_data_width-1):0]       d_b;
1730
   input [(b_addr_width-1):0]       adr_b;
1731 92 unneback
   input [(b_data_width/8-1):0]    be_b;
1732
   input                           we_b;
1733
   output reg [(b_data_width-1):0]          q_b;
1734 91 unneback
   input                           clk_a, clk_b;
1735 100 unneback
    generate
1736
    if (debug==1) begin : debug_we
1737
        always @ (posedge clk_a)
1738
        if (we_a)
1739
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1740
        always @ (posedge clk_b)
1741
        if (we_b)
1742
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1743
    end
1744
    endgenerate
1745 91 unneback
`ifdef SYSTEMVERILOG
1746
// use a multi-dimensional packed array
1747
//to model individual bytes within the word
1748 75 unneback
generate
1749 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1750 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] ;
1751 95 unneback
    initial
1752 100 unneback
        if (memory_init==1)
1753 95 unneback
            $readmemh(memory_file, ram);
1754 100 unneback
    integer k;
1755
    initial
1756
        if (memory_init==2)
1757
            for (k = 0; k < mem_size; k = k + 1)
1758
                ram[k] = 0;
1759 91 unneback
    always_ff@(posedge clk_a)
1760
    begin
1761
        if(we_a) begin
1762 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
1763
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
1764
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
1765
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
1766 91 unneback
        end
1767
    end
1768 92 unneback
    always@(posedge clk_a)
1769
        q_a = ram[adr_a];
1770 91 unneback
    always_ff@(posedge clk_b)
1771 92 unneback
    begin
1772
        if(we_b) begin
1773 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
1774
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
1775
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
1776
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
1777 92 unneback
        end
1778
    end
1779
    always@(posedge clk_b)
1780
        q_b = ram[adr_b];
1781 75 unneback
end
1782
endgenerate
1783 95 unneback
generate
1784
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
1785 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] ;
1786 95 unneback
    initial
1787 100 unneback
        if (memory_init==1)
1788 95 unneback
            $readmemh(memory_file, ram);
1789 100 unneback
    integer k;
1790
    initial
1791
        if (memory_init==2)
1792
            for (k = 0; k < mem_size; k = k + 1)
1793
                ram[k] = 0;
1794 95 unneback
    always_ff@(posedge clk_a)
1795
    begin
1796
        if(we_a) begin
1797
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
1798
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
1799
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
1800
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
1801
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1802
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1803
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1804
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1805
        end
1806
    end
1807
    always@(posedge clk_a)
1808
        q_a = ram[adr_a];
1809
    always_ff@(posedge clk_b)
1810
    begin
1811
        if(we_b) begin
1812
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
1813
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
1814
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
1815
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
1816
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1817
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1818
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1819
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1820
        end
1821
    end
1822
    always@(posedge clk_b)
1823
        q_b = ram[adr_b];
1824
end
1825
endgenerate
1826
generate
1827
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
1828
logic [31:0] temp;
1829 128 unneback
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
1830
dpram3232 (
1831 95 unneback
    .d_a(d_a),
1832
    .q_a(q_a),
1833
    .adr_a(adr_a),
1834
    .be_a(be_a),
1835
    .we_a(we_a),
1836
    .clk_a(clk_a),
1837
    .d_b({d_b,d_b}),
1838
    .q_b(temp),
1839 128 unneback
    .adr_b(adr_b[b_addr_width-1:1]),
1840 95 unneback
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
1841
    .we_b(we_b),
1842
    .clk_b(clk_b)
1843
);
1844 100 unneback
always @ (adr_b[0] or temp)
1845 95 unneback
    if (adr_b[0])
1846
        q_b = temp[31:16];
1847
    else
1848
        q_b = temp[15:0];
1849
end
1850
endgenerate
1851
generate
1852
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
1853
logic [63:0] temp;
1854 128 unneback
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
1855 95 unneback
dpram6464 (
1856
    .d_a({d_a,d_a}),
1857
    .q_a(temp),
1858
    .adr_a(adr_a[a_addr_width-1:1]),
1859
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
1860
    .we_a(we_a),
1861
    .clk_a(clk_a),
1862
    .d_b(d_b),
1863
    .q_b(q_b),
1864
    .adr_b(adr_b),
1865
    .be_b(be_b),
1866
    .we_b(we_b),
1867
    .clk_b(clk_b)
1868
);
1869 100 unneback
always @ (adr_a[0] or temp)
1870 95 unneback
    if (adr_a[0])
1871
        q_a = temp[63:32];
1872
    else
1873
        q_a = temp[31:0];
1874
end
1875
endgenerate
1876 91 unneback
`else
1877 92 unneback
    // This modules requires SystemVerilog
1878 98 unneback
    // at this point anyway
1879 91 unneback
`endif
1880 75 unneback
endmodule
1881 6 unneback
// FIFO
1882 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1883
    d, wr, fifo_full,
1884
    q, rd, fifo_empty,
1885
    fill_level,
1886
    clk, rst
1887
    );
1888
parameter data_width = 18;
1889
parameter addr_width = 4;
1890
// write side
1891
input  [data_width-1:0] d;
1892
input                   wr;
1893
output                  fifo_full;
1894
// read side
1895
output [data_width-1:0] q;
1896
input                   rd;
1897
output                  fifo_empty;
1898
// common
1899
output [addr_width:0]   fill_level;
1900
input rst, clk;
1901
wire [addr_width:1] wadr, radr;
1902
vl_cnt_bin_ce
1903
    # ( .length(addr_width))
1904
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1905
vl_cnt_bin_ce
1906
    # (.length(addr_width))
1907
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1908
vl_dpram_1r1w
1909
    # (.data_width(data_width), .addr_width(addr_width))
1910
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1911 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1912 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1913 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1914
endmodule
1915 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1916
// RAM is supposed to be larger than the two FIFOs
1917
// LFSR counters used adr pointers
1918
module vl_fifo_2r2w_sync_simplex (
1919
    // a side
1920
    a_d, a_wr, a_fifo_full,
1921
    a_q, a_rd, a_fifo_empty,
1922
    a_fill_level,
1923
    // b side
1924
    b_d, b_wr, b_fifo_full,
1925
    b_q, b_rd, b_fifo_empty,
1926
    b_fill_level,
1927
    // common
1928
    clk, rst
1929
    );
1930
parameter data_width = 8;
1931
parameter addr_width = 5;
1932
parameter fifo_full_level = (1<<addr_width)-1;
1933
// a side
1934
input  [data_width-1:0] a_d;
1935
input                   a_wr;
1936
output                  a_fifo_full;
1937
output [data_width-1:0] a_q;
1938
input                   a_rd;
1939
output                  a_fifo_empty;
1940
output [addr_width-1:0] a_fill_level;
1941
// b side
1942
input  [data_width-1:0] b_d;
1943
input                   b_wr;
1944
output                  b_fifo_full;
1945
output [data_width-1:0] b_q;
1946
input                   b_rd;
1947
output                  b_fifo_empty;
1948
output [addr_width-1:0] b_fill_level;
1949
input                   clk;
1950
input                   rst;
1951
// adr_gen
1952
wire [addr_width:1] a_wadr, a_radr;
1953
wire [addr_width:1] b_wadr, b_radr;
1954
// dpram
1955
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1956
vl_cnt_lfsr_ce
1957
    # ( .length(addr_width))
1958
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1959
vl_cnt_lfsr_ce
1960
    # (.length(addr_width))
1961
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1962
vl_cnt_lfsr_ce
1963
    # ( .length(addr_width))
1964
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1965
vl_cnt_lfsr_ce
1966
    # (.length(addr_width))
1967
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1968
// mux read or write adr to DPRAM
1969
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1970
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1971
vl_dpram_2r2w
1972
    # (.data_width(data_width), .addr_width(addr_width+1))
1973
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1974
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1975
vl_cnt_bin_ce_rew_zq_l1
1976 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1977 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1978
vl_cnt_bin_ce_rew_zq_l1
1979 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1980 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1981
endmodule
1982 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1983 11 unneback
   parameter addr_width = 4;
1984
   parameter N = addr_width-1;
1985 6 unneback
   parameter Q1 = 2'b00;
1986
   parameter Q2 = 2'b01;
1987
   parameter Q3 = 2'b11;
1988
   parameter Q4 = 2'b10;
1989
   parameter going_empty = 1'b0;
1990
   parameter going_full  = 1'b1;
1991
   input [N:0]  wptr, rptr;
1992 14 unneback
   output       fifo_empty;
1993 6 unneback
   output       fifo_full;
1994
   input        wclk, rclk, rst;
1995
   wire direction;
1996
   reg  direction_set, direction_clr;
1997
   wire async_empty, async_full;
1998
   wire fifo_full2;
1999 14 unneback
   wire fifo_empty2;
2000 6 unneback
   // direction_set
2001
   always @ (wptr[N:N-1] or rptr[N:N-1])
2002
     case ({wptr[N:N-1],rptr[N:N-1]})
2003
       {Q1,Q2} : direction_set <= 1'b1;
2004
       {Q2,Q3} : direction_set <= 1'b1;
2005
       {Q3,Q4} : direction_set <= 1'b1;
2006
       {Q4,Q1} : direction_set <= 1'b1;
2007
       default : direction_set <= 1'b0;
2008
     endcase
2009
   // direction_clear
2010
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2011
     if (rst)
2012
       direction_clr <= 1'b1;
2013
     else
2014
       case ({wptr[N:N-1],rptr[N:N-1]})
2015
         {Q2,Q1} : direction_clr <= 1'b1;
2016
         {Q3,Q2} : direction_clr <= 1'b1;
2017
         {Q4,Q3} : direction_clr <= 1'b1;
2018
         {Q1,Q4} : direction_clr <= 1'b1;
2019
         default : direction_clr <= 1'b0;
2020
       endcase
2021 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2022 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2023
   assign async_full  = (wptr == rptr) && (direction==going_full);
2024 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2025
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2026 6 unneback
/*
2027
   always @ (posedge wclk or posedge rst or posedge async_full)
2028
     if (rst)
2029
       {fifo_full, fifo_full2} <= 2'b00;
2030
     else if (async_full)
2031
       {fifo_full, fifo_full2} <= 2'b11;
2032
     else
2033
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2034
*/
2035 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2036 6 unneback
     if (async_empty)
2037
       {fifo_empty, fifo_empty2} <= 2'b11;
2038
     else
2039 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2040 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2041
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2042 27 unneback
endmodule // async_compb
2043 6 unneback
module vl_fifo_1r1w_async (
2044
    d, wr, fifo_full, wr_clk, wr_rst,
2045
    q, rd, fifo_empty, rd_clk, rd_rst
2046
    );
2047
parameter data_width = 18;
2048
parameter addr_width = 4;
2049
// write side
2050
input  [data_width-1:0] d;
2051
input                   wr;
2052
output                  fifo_full;
2053
input                   wr_clk;
2054
input                   wr_rst;
2055
// read side
2056
output [data_width-1:0] q;
2057
input                   rd;
2058
output                  fifo_empty;
2059
input                   rd_clk;
2060
input                   rd_rst;
2061
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2062 18 unneback
vl_cnt_gray_ce_bin
2063 6 unneback
    # ( .length(addr_width))
2064
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2065 18 unneback
vl_cnt_gray_ce_bin
2066 6 unneback
    # (.length(addr_width))
2067 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2068 7 unneback
vl_dpram_1r1w
2069 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2070
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2071
vl_fifo_cmp_async
2072
    # (.addr_width(addr_width))
2073
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2074
endmodule
2075 8 unneback
module vl_fifo_2r2w_async (
2076 6 unneback
    // a side
2077
    a_d, a_wr, a_fifo_full,
2078
    a_q, a_rd, a_fifo_empty,
2079
    a_clk, a_rst,
2080
    // b side
2081
    b_d, b_wr, b_fifo_full,
2082
    b_q, b_rd, b_fifo_empty,
2083
    b_clk, b_rst
2084
    );
2085
parameter data_width = 18;
2086
parameter addr_width = 4;
2087
// a side
2088
input  [data_width-1:0] a_d;
2089
input                   a_wr;
2090
output                  a_fifo_full;
2091
output [data_width-1:0] a_q;
2092
input                   a_rd;
2093
output                  a_fifo_empty;
2094
input                   a_clk;
2095
input                   a_rst;
2096
// b side
2097
input  [data_width-1:0] b_d;
2098
input                   b_wr;
2099
output                  b_fifo_full;
2100
output [data_width-1:0] b_q;
2101
input                   b_rd;
2102
output                  b_fifo_empty;
2103
input                   b_clk;
2104
input                   b_rst;
2105
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2106
vl_fifo_1r1w_async_a (
2107
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2108
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2109
    );
2110
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2111
vl_fifo_1r1w_async_b (
2112
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2113
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2114
    );
2115
endmodule
2116 8 unneback
module vl_fifo_2r2w_async_simplex (
2117 6 unneback
    // a side
2118
    a_d, a_wr, a_fifo_full,
2119
    a_q, a_rd, a_fifo_empty,
2120
    a_clk, a_rst,
2121
    // b side
2122
    b_d, b_wr, b_fifo_full,
2123
    b_q, b_rd, b_fifo_empty,
2124
    b_clk, b_rst
2125
    );
2126
parameter data_width = 18;
2127
parameter addr_width = 4;
2128
// a side
2129
input  [data_width-1:0] a_d;
2130
input                   a_wr;
2131
output                  a_fifo_full;
2132
output [data_width-1:0] a_q;
2133
input                   a_rd;
2134
output                  a_fifo_empty;
2135
input                   a_clk;
2136
input                   a_rst;
2137
// b side
2138
input  [data_width-1:0] b_d;
2139
input                   b_wr;
2140
output                  b_fifo_full;
2141
output [data_width-1:0] b_q;
2142
input                   b_rd;
2143
output                  b_fifo_empty;
2144
input                   b_clk;
2145
input                   b_rst;
2146
// adr_gen
2147
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2148
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2149
// dpram
2150
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2151 18 unneback
vl_cnt_gray_ce_bin
2152 6 unneback
    # ( .length(addr_width))
2153
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2154 18 unneback
vl_cnt_gray_ce_bin
2155 6 unneback
    # (.length(addr_width))
2156
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2157 18 unneback
vl_cnt_gray_ce_bin
2158 6 unneback
    # ( .length(addr_width))
2159
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2160 18 unneback
vl_cnt_gray_ce_bin
2161 6 unneback
    # (.length(addr_width))
2162
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2163
// mux read or write adr to DPRAM
2164
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2165
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2166 11 unneback
vl_dpram_2r2w
2167 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2168
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2169
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2170 11 unneback
vl_fifo_cmp_async
2171 6 unneback
    # (.addr_width(addr_width))
2172
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2173 11 unneback
vl_fifo_cmp_async
2174 6 unneback
    # (.addr_width(addr_width))
2175
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2176
endmodule
2177 48 unneback
module vl_reg_file (
2178
    a1, a2, a3, wd3, we3, rd1, rd2, clk
2179
);
2180
parameter data_width = 32;
2181
parameter addr_width = 5;
2182
input [addr_width-1:0] a1, a2, a3;
2183
input [data_width-1:0] wd3;
2184
input we3;
2185
output [data_width-1:0] rd1, rd2;
2186
input clk;
2187
vl_dpram_1r1w
2188
    # ( .data_width(data_width), .addr_width(addr_width))
2189
    ram1 (
2190
        .d_a(wd3),
2191
        .adr_a(a3),
2192
        .we_a(we3),
2193
        .clk_a(clk),
2194
        .q_b(rd1),
2195
        .adr_b(a1),
2196
        .clk_b(clk) );
2197
vl_dpram_1r1w
2198
    # ( .data_width(data_width), .addr_width(addr_width))
2199
    ram2 (
2200
        .d_a(wd3),
2201
        .adr_a(a3),
2202
        .we_a(we3),
2203
        .clk_a(clk),
2204
        .q_b(rd2),
2205
        .adr_b(a2),
2206
        .clk_b(clk) );
2207
endmodule
2208 12 unneback
//////////////////////////////////////////////////////////////////////
2209
////                                                              ////
2210
////  Versatile library, wishbone stuff                           ////
2211
////                                                              ////
2212
////  Description                                                 ////
2213
////  Wishbone compliant modules                                  ////
2214
////                                                              ////
2215
////                                                              ////
2216
////  To Do:                                                      ////
2217
////   -                                                          ////
2218
////                                                              ////
2219
////  Author(s):                                                  ////
2220
////      - Michael Unneback, unneback@opencores.org              ////
2221
////        ORSoC AB                                              ////
2222
////                                                              ////
2223
//////////////////////////////////////////////////////////////////////
2224
////                                                              ////
2225
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2226
////                                                              ////
2227
//// This source file may be used and distributed without         ////
2228
//// restriction provided that this copyright statement is not    ////
2229
//// removed from the file and that any derivative work contains  ////
2230
//// the original copyright notice and the associated disclaimer. ////
2231
////                                                              ////
2232
//// This source file is free software; you can redistribute it   ////
2233
//// and/or modify it under the terms of the GNU Lesser General   ////
2234
//// Public License as published by the Free Software Foundation; ////
2235
//// either version 2.1 of the License, or (at your option) any   ////
2236
//// later version.                                               ////
2237
////                                                              ////
2238
//// This source is distributed in the hope that it will be       ////
2239
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2240
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2241
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2242
//// details.                                                     ////
2243
////                                                              ////
2244
//// You should have received a copy of the GNU Lesser General    ////
2245
//// Public License along with this source; if not, download it   ////
2246
//// from http://www.opencores.org/lgpl.shtml                     ////
2247
////                                                              ////
2248
//////////////////////////////////////////////////////////////////////
2249
`timescale 1ns/1ns
2250 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
2251 83 unneback
parameter adr_width = 10;
2252
parameter max_burst_width = 4;
2253 85 unneback
input cyc_i, stb_i, we_i;
2254 83 unneback
input [2:0] cti_i;
2255
input [1:0] bte_i;
2256
input [adr_width-1:0] adr_i;
2257
output [adr_width-1:0] adr_o;
2258
output ack_o;
2259
input clk, rst;
2260
reg [adr_width-1:0] adr;
2261 90 unneback
wire [max_burst_width-1:0] to_adr;
2262 91 unneback
reg [max_burst_width-1:0] last_adr;
2263 92 unneback
reg last_cycle;
2264
localparam idle_or_eoc = 1'b0;
2265
localparam cyc_or_ws   = 1'b1;
2266 91 unneback
always @ (posedge clk or posedge rst)
2267
if (rst)
2268
    last_adr <= {max_burst_width{1'b0}};
2269
else
2270
    if (stb_i)
2271 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
2272 83 unneback
generate
2273
if (max_burst_width==0) begin : inst_0
2274 97 unneback
        reg ack_o;
2275
        assign adr_o = adr_i;
2276
        always @ (posedge clk or posedge rst)
2277
        if (rst)
2278
            ack_o <= 1'b0;
2279
        else
2280
            ack_o <= cyc_i & stb_i & !ack_o;
2281 83 unneback
end else begin
2282
    always @ (posedge clk or posedge rst)
2283
    if (rst)
2284 92 unneback
        last_cycle <= idle_or_eoc;
2285 83 unneback
    else
2286 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
2287
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
2288
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
2289
                      cyc_or_ws; // cyc
2290
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
2291 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
2292 91 unneback
                                        (!stb_i) ? last_adr :
2293 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
2294 85 unneback
                                        adr[max_burst_width-1:0];
2295 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
2296 83 unneback
end
2297
endgenerate
2298
generate
2299
if (max_burst_width==2) begin : inst_2
2300
    always @ (posedge clk or posedge rst)
2301
    if (rst)
2302
        adr <= 2'h0;
2303
    else
2304
        if (cyc_i & stb_i)
2305
            adr[1:0] <= to_adr[1:0] + 2'd1;
2306
        else
2307
            adr <= to_adr[1:0];
2308
end
2309
endgenerate
2310
generate
2311
if (max_burst_width==3) begin : inst_3
2312
    always @ (posedge clk or posedge rst)
2313
    if (rst)
2314
        adr <= 3'h0;
2315
    else
2316
        if (cyc_i & stb_i)
2317
            case (bte_i)
2318
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
2319
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
2320
            endcase
2321
        else
2322
            adr <= to_adr[2:0];
2323
end
2324
endgenerate
2325
generate
2326
if (max_burst_width==4) begin : inst_4
2327
    always @ (posedge clk or posedge rst)
2328
    if (rst)
2329
        adr <= 4'h0;
2330
    else
2331 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
2332 83 unneback
            case (bte_i)
2333
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
2334
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
2335
            default: adr[3:0] <= to_adr + 4'd1;
2336
            endcase
2337
        else
2338
            adr <= to_adr[3:0];
2339
end
2340
endgenerate
2341
generate
2342
if (adr_width > max_burst_width) begin : pass_through
2343
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
2344
end
2345
endgenerate
2346
endmodule
2347
// async wb3 - wb3 bridge
2348
`timescale 1ns/1ns
2349 18 unneback
module vl_wb3wb3_bridge (
2350 12 unneback
        // wishbone slave side
2351
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2352
        // wishbone master side
2353
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2354 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
2355
parameter addr_width = 4;
2356 12 unneback
input [31:0] wbs_dat_i;
2357
input [31:2] wbs_adr_i;
2358
input [3:0]  wbs_sel_i;
2359
input [1:0]  wbs_bte_i;
2360
input [2:0]  wbs_cti_i;
2361
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2362
output [31:0] wbs_dat_o;
2363 14 unneback
output wbs_ack_o;
2364 12 unneback
input wbs_clk, wbs_rst;
2365
output [31:0] wbm_dat_o;
2366
output reg [31:2] wbm_adr_o;
2367
output [3:0]  wbm_sel_o;
2368
output reg [1:0]  wbm_bte_o;
2369
output reg [2:0]  wbm_cti_o;
2370 14 unneback
output reg wbm_we_o;
2371
output wbm_cyc_o;
2372 12 unneback
output wbm_stb_o;
2373
input [31:0]  wbm_dat_i;
2374
input wbm_ack_i;
2375
input wbm_clk, wbm_rst;
2376
// bte
2377
parameter linear       = 2'b00;
2378
parameter wrap4        = 2'b01;
2379
parameter wrap8        = 2'b10;
2380
parameter wrap16       = 2'b11;
2381
// cti
2382
parameter classic      = 3'b000;
2383
parameter incburst     = 3'b010;
2384
parameter endofburst   = 3'b111;
2385 95 unneback
localparam wbs_adr  = 1'b0;
2386
localparam wbs_data = 1'b1;
2387
localparam wbm_adr0      = 2'b00;
2388
localparam wbm_adr1      = 2'b01;
2389
localparam wbm_data      = 2'b10;
2390
localparam wbm_data_wait = 2'b11;
2391 12 unneback
reg [1:0] wbs_bte_reg;
2392
reg wbs;
2393