Subversion Repositories versatile_library

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile library, clock and reset                          ////

////                                                              ////

////  Description                                                 ////

////  Logic related to clock and reset                            ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////   - add more different registers                             ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// Global buffer

// usage:

// use to enable global buffers for high fan out signals such as clock and reset

altera

 // ALTERA

 //ACTEL

// sync reset

// input active lo async reset, normally from external reset generetaor and/or switch

// output active high global reset sync with two DFFs 

`timescale 1 ns/100 ps

module vl_sync_rst ( rst_n_i, rst_o, clk);

input rst_n_i, clk;

output rst_o;

reg [0:1] tmp;

always @ (posedge clk or negedge rst_n_i)

if (!rst_n_i)

        tmp <= 2'b00;

else

        tmp <= {1'b1,tmp[0]};

vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));

endmodule

// vl_pll

 //altera

 //actel

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile library, registers                                ////

////                                                              ////

////  Description                                                 ////

////  Different type of registers                                 ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////   - add more different registers                             ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

module dff ( d, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

                q <= reset_value;

        else

                q <= d;

endmodule

module dff_array ( d, q, clk, rst);

        parameter width = 1;

        parameter depth = 2;

        parameter reset_value = 1'b0;

        input [width-1:0] d;

        input clk, rst;

        output [width-1:0] q;

        reg  [0:depth-1] q_tmp [width-1:0];

        integer i;

        always @ (posedge clk or posedge rst)

        if (rst) begin

            for (i=0;i<depth;i=i+1)

                q_tmp[i] <= {width{reset_value}};

        end else begin

            q_tmp[0] <= d;

            for (i=1;i<depth;i=i+1)

                q_tmp[i] <= q_tmp[i-1];

        end

    assign q = q_tmp[depth-1];

endmodule

module dff_ce ( d, ce, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input ce, clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

                q <= reset_value;

        else

                if (ce)

                        q <= d;

endmodule

module dff_ce_clear ( d, ce, clear, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input ce, clear, clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

            q <= reset_value;

        else

            if (ce)

                if (clear)

                    q <= {width{1'b0}};

                else

                    q <= d;

endmodule

// megafunction wizard: %LPM_FF%

// GENERATION: STANDARD

// VERSION: WM1.0

// MODULE: lpm_ff 

// ============================================================

// File Name: dff_sr.v

// Megafunction Name(s):

//                      lpm_ff

//

// Simulation Library Files(s):

//                      lpm

// ============================================================

// ************************************************************

// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

//

// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version

// ************************************************************

//Copyright (C) 1991-2010 Altera Corporation

//Your use of Altera Corporation's design tools, logic functions 

//and other software and tools, and its AMPP partner logic 

//functions, and any output files from any of the foregoing 

//(including device programming or simulation files), and any 

//associated documentation or information are expressly subject 

//to the terms and conditions of the Altera Program License 

//Subscription Agreement, Altera MegaCore Function License 

//Agreement, or other applicable license agreement, including, 

//without limitation, that your use is for the sole purpose of 

//programming logic devices manufactured by Altera and sold by 

//Altera or its authorized distributors.  Please refer to the 

//applicable agreement for further details.

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module dff_sr (

        aclr,

        aset,

        clock,

        data,

        q);

        input     aclr;

        input     aset;

        input     clock;

        input     data;

        output    q;

        wire [0:0] sub_wire0;

        wire [0:0] sub_wire1 = sub_wire0[0:0];

        wire  q = sub_wire1;

        wire  sub_wire2 = data;

        wire  sub_wire3 = sub_wire2;

        lpm_ff  lpm_ff_component (

                                .aclr (aclr),

                                .clock (clock),

                                .data (sub_wire3),

                                .aset (aset),

                                .q (sub_wire0)

                                // synopsys translate_off

                                ,

                                .aload (),

                                .enable (),

                                .sclr (),

                                .sload (),

                                .sset ()

                                // synopsys translate_on

                                );

        defparam

                lpm_ff_component.lpm_fftype = "DFF",

                lpm_ff_component.lpm_type = "LPM_FF",

                lpm_ff_component.lpm_width = 1;

endmodule

// ============================================================

// CNX file retrieval info

// ============================================================

// Retrieval info: PRIVATE: ACLR NUMERIC "1"

// Retrieval info: PRIVATE: ALOAD NUMERIC "0"

// Retrieval info: PRIVATE: ASET NUMERIC "1"

// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"

// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"

// Retrieval info: PRIVATE: DFF NUMERIC "1"

// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"

// Retrieval info: PRIVATE: SCLR NUMERIC "0"

// Retrieval info: PRIVATE: SLOAD NUMERIC "0"

// Retrieval info: PRIVATE: SSET NUMERIC "0"

// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"

// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"

// Retrieval info: PRIVATE: nBit NUMERIC "1"

// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"

// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"

// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"

// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr

// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset

// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock

// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data

// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q

// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0

// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0

// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0

// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0

// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0

// Retrieval info: LIBRARY: lpm lpm.lpm_components.all

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE

// Retrieval info: LIB_FILE: lpm

// LATCH

// For targtes not supporting LATCH use dff_sr with clk=1 and data=1

module latch ( d, le, q, clk);

input d, le;

output q;

input clk;

dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module cnt_bin_ce ( cke, q, rst, clk);

   parameter length = 4;

   input cke;

   output [length:1] q;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   reg  [length:1] qi;

   wire [length:1] q_next;

   assign q_next = qi + {{length-1{1'b0}},1'b1};

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

   assign q = qi;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module cnt_bin_ce_clear ( clear, cke, q, rst, clk);

   parameter length = 4;

   input clear;

   input cke;

   output [length:1] q;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   reg  [length:1] qi;

   wire [length:1] q_next;

   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

   assign q = qi;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);

   parameter length = 4;

   input clear;

   input set;

   input cke;

   input rew;

   output [length:1] q;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   reg  [length:1] qi;

   wire  [length:1] q_next, q_next_fw, q_next_rew;

   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};

   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};

   assign q_next = rew ? q_next_rew : q_next_fw;

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

   assign q = qi;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);

   parameter length = 4;

   input cke;

   input rew;

   output reg level1;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 1;

   parameter level1_value = 15;

   reg  [length:1] qi;

   wire  [length:1] q_next, q_next_fw, q_next_rew;

   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};

   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};

   assign q_next = rew ? q_next_rew : q_next_fw;

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

    always @ (posedge clk or posedge rst)

    if (rst)

        level1 <= 1'b0;

    else

    if (cke)

    if (q_next == level1_value)

        level1 <= 1'b1;

    else if (qi == level1_value & rew)

        level1 <= 1'b0;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// LFSR counter

module cnt_lfsr_zq ( zq, rst, clk);

   parameter length = 4;

   output reg zq;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 8;

   parameter level1_value = 15;

   reg  [length:1] qi;

   reg lfsr_fb;

   wire [length:1] q_next;

   reg [32:1] polynom;

   integer i;

   always @ (qi)

   begin

        case (length)

         2: polynom = 32'b11;                               // 0x3

         3: polynom = 32'b110;                              // 0x6

         4: polynom = 32'b1100;                             // 0xC

         5: polynom = 32'b10100;                            // 0x14

         6: polynom = 32'b110000;                           // 0x30

         7: polynom = 32'b1100000;                          // 0x60

         8: polynom = 32'b10111000;                         // 0xb8

         9: polynom = 32'b100010000;                        // 0x110

        10: polynom = 32'b1001000000;                       // 0x240

        11: polynom = 32'b10100000000;                      // 0x500

        12: polynom = 32'b100000101001;                     // 0x829

        13: polynom = 32'b1000000001100;                    // 0x100C

        14: polynom = 32'b10000000010101;                   // 0x2015

        15: polynom = 32'b110000000000000;                  // 0x6000

        16: polynom = 32'b1101000000001000;                 // 0xD008

        17: polynom = 32'b10010000000000000;                // 0x12000

        18: polynom = 32'b100000010000000000;               // 0x20400

        19: polynom = 32'b1000000000000100011;              // 0x40023

        20: polynom = 32'b10000010000000000000;             // 0x82000

        21: polynom = 32'b101000000000000000000;            // 0x140000

        22: polynom = 32'b1100000000000000000000;           // 0x300000

        23: polynom = 32'b10000100000000000000000;          // 0x420000

        24: polynom = 32'b111000010000000000000000;         // 0xE10000

        25: polynom = 32'b1001000000000000000000000;        // 0x1200000

        26: polynom = 32'b10000000000000000000100011;       // 0x2000023

        27: polynom = 32'b100000000000000000000010011;      // 0x4000013

        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000

        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000

        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029

        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000

        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003

        default: polynom = 32'b0;

        endcase

        lfsr_fb = qi[length];

        for (i=length-1; i>=1; i=i-1) begin

            if (polynom[i])

                lfsr_fb = lfsr_fb  ~^ qi[i];

        end

    end

   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

       qi <= q_next;

   always @ (posedge clk or posedge rst)

     if (rst)

       zq <= 1'b1;

     else

       zq <= q_next == {length{1'b0}};

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////