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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 153

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1 60 unneback
// default SYN_KEEP definition
2 136 unneback
///////////////////////////////////////
3
// dependencies
4
///////////////////////////////////////
5 97 unneback
// size to width
6 6 unneback
//////////////////////////////////////////////////////////////////////
7
////                                                              ////
8
////  Versatile library, clock and reset                          ////
9
////                                                              ////
10
////  Description                                                 ////
11
////  Logic related to clock and reset                            ////
12
////                                                              ////
13
////                                                              ////
14
////  To Do:                                                      ////
15
////   - add more different registers                             ////
16
////                                                              ////
17
////  Author(s):                                                  ////
18
////      - Michael Unneback, unneback@opencores.org              ////
19
////        ORSoC AB                                              ////
20
////                                                              ////
21
//////////////////////////////////////////////////////////////////////
22
////                                                              ////
23
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
24
////                                                              ////
25
//// This source file may be used and distributed without         ////
26
//// restriction provided that this copyright statement is not    ////
27
//// removed from the file and that any derivative work contains  ////
28
//// the original copyright notice and the associated disclaimer. ////
29
////                                                              ////
30
//// This source file is free software; you can redistribute it   ////
31
//// and/or modify it under the terms of the GNU Lesser General   ////
32
//// Public License as published by the Free Software Foundation; ////
33
//// either version 2.1 of the License, or (at your option) any   ////
34
//// later version.                                               ////
35
////                                                              ////
36
//// This source is distributed in the hope that it will be       ////
37
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
38
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
39
//// PURPOSE.  See the GNU Lesser General Public License for more ////
40
//// details.                                                     ////
41
////                                                              ////
42
//// You should have received a copy of the GNU Lesser General    ////
43
//// Public License along with this source; if not, download it   ////
44
//// from http://www.opencores.org/lgpl.shtml                     ////
45
////                                                              ////
46
//////////////////////////////////////////////////////////////////////
47 21 unneback
//altera
48 33 unneback
module vl_gbuf ( i, o);
49
input i;
50
output o;
51
assign o = i;
52
endmodule
53 6 unneback
 // ALTERA
54
 //ACTEL
55
// sync reset
56 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
57 6 unneback
// output active high global reset sync with two DFFs 
58
`timescale 1 ns/100 ps
59
module vl_sync_rst ( rst_n_i, rst_o, clk);
60
input rst_n_i, clk;
61
output rst_o;
62 18 unneback
reg [1:0] tmp;
63 6 unneback
always @ (posedge clk or negedge rst_n_i)
64
if (!rst_n_i)
65 17 unneback
        tmp <= 2'b11;
66 6 unneback
else
67 33 unneback
        tmp <= {1'b0,tmp[1]};
68 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
69 6 unneback
endmodule
70
// vl_pll
71 32 unneback
///////////////////////////////////////////////////////////////////////////////
72
`timescale 1 ps/1 ps
73
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
74
parameter index = 0;
75
parameter number_of_clk = 1;
76
parameter period_time_0 = 20000;
77
parameter period_time_1 = 20000;
78
parameter period_time_2 = 20000;
79
parameter period_time_3 = 20000;
80
parameter period_time_4 = 20000;
81
parameter lock_delay = 2000000;
82
input clk_i, rst_n_i;
83
output lock;
84
output reg [0:number_of_clk-1] clk_o;
85
output [0:number_of_clk-1] rst_o;
86 33 unneback
`ifdef SIM_PLL
87 32 unneback
always
88
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
89
generate if (number_of_clk > 1)
90
always
91
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
92
endgenerate
93
generate if (number_of_clk > 2)
94
always
95
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
96
endgenerate
97 33 unneback
generate if (number_of_clk > 3)
98 32 unneback
always
99
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
100
endgenerate
101 33 unneback
generate if (number_of_clk > 4)
102 32 unneback
always
103
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110 33 unneback
//assign #lock_delay lock = rst_n_i;
111
assign lock = rst_n_i;
112 32 unneback
endmodule
113 33 unneback
`else
114
`ifdef VL_PLL0
115
`ifdef VL_PLL0_CLK1
116
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
117
`endif
118
`ifdef VL_PLL0_CLK2
119
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
120
`endif
121
`ifdef VL_PLL0_CLK3
122
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
123
`endif
124
`ifdef VL_PLL0_CLK4
125
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
126
`endif
127
`ifdef VL_PLL0_CLK5
128
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
129
`endif
130
`endif
131
`ifdef VL_PLL1
132
`ifdef VL_PLL1_CLK1
133
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
134
`endif
135
`ifdef VL_PLL1_CLK2
136
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
137
`endif
138
`ifdef VL_PLL1_CLK3
139
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
140
`endif
141
`ifdef VL_PLL1_CLK4
142
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
143
`endif
144
`ifdef VL_PLL1_CLK5
145
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
146
`endif
147
`endif
148
`ifdef VL_PLL2
149
`ifdef VL_PLL2_CLK1
150
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
151
`endif
152
`ifdef VL_PLL2_CLK2
153
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
154
`endif
155
`ifdef VL_PLL2_CLK3
156
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
157
`endif
158
`ifdef VL_PLL2_CLK4
159
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
160
`endif
161
`ifdef VL_PLL2_CLK5
162
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
163
`endif
164
`endif
165
`ifdef VL_PLL3
166
`ifdef VL_PLL3_CLK1
167
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
168
`endif
169
`ifdef VL_PLL3_CLK2
170
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
171
`endif
172
`ifdef VL_PLL3_CLK3
173
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
174
`endif
175
`ifdef VL_PLL3_CLK4
176
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
177
`endif
178
`ifdef VL_PLL3_CLK5
179
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
180
`endif
181
`endif
182 32 unneback
genvar i;
183
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
184 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
185 32 unneback
end
186
endgenerate
187
endmodule
188 33 unneback
`endif
189 32 unneback
///////////////////////////////////////////////////////////////////////////////
190 6 unneback
 //altera
191
 //actel
192
//////////////////////////////////////////////////////////////////////
193
////                                                              ////
194
////  Versatile library, registers                                ////
195
////                                                              ////
196
////  Description                                                 ////
197
////  Different type of registers                                 ////
198
////                                                              ////
199
////                                                              ////
200
////  To Do:                                                      ////
201
////   - add more different registers                             ////
202
////                                                              ////
203
////  Author(s):                                                  ////
204
////      - Michael Unneback, unneback@opencores.org              ////
205
////        ORSoC AB                                              ////
206
////                                                              ////
207
//////////////////////////////////////////////////////////////////////
208
////                                                              ////
209
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
210
////                                                              ////
211
//// This source file may be used and distributed without         ////
212
//// restriction provided that this copyright statement is not    ////
213
//// removed from the file and that any derivative work contains  ////
214
//// the original copyright notice and the associated disclaimer. ////
215
////                                                              ////
216
//// This source file is free software; you can redistribute it   ////
217
//// and/or modify it under the terms of the GNU Lesser General   ////
218
//// Public License as published by the Free Software Foundation; ////
219
//// either version 2.1 of the License, or (at your option) any   ////
220
//// later version.                                               ////
221
////                                                              ////
222
//// This source is distributed in the hope that it will be       ////
223
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
224
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
225
//// PURPOSE.  See the GNU Lesser General Public License for more ////
226
//// details.                                                     ////
227
////                                                              ////
228
//// You should have received a copy of the GNU Lesser General    ////
229
//// Public License along with this source; if not, download it   ////
230
//// from http://www.opencores.org/lgpl.shtml                     ////
231
////                                                              ////
232
//////////////////////////////////////////////////////////////////////
233 18 unneback
module vl_dff ( d, q, clk, rst);
234 6 unneback
        parameter width = 1;
235 139 unneback
        parameter reset_value = {width{1'b0}};
236 6 unneback
        input [width-1:0] d;
237
        input clk, rst;
238
        output reg [width-1:0] q;
239
        always @ (posedge clk or posedge rst)
240
        if (rst)
241
                q <= reset_value;
242
        else
243
                q <= d;
244
endmodule
245 18 unneback
module vl_dff_array ( d, q, clk, rst);
246 6 unneback
        parameter width = 1;
247
        parameter depth = 2;
248
        parameter reset_value = 1'b0;
249
        input [width-1:0] d;
250
        input clk, rst;
251
        output [width-1:0] q;
252
        reg  [0:depth-1] q_tmp [width-1:0];
253
        integer i;
254
        always @ (posedge clk or posedge rst)
255
        if (rst) begin
256
            for (i=0;i<depth;i=i+1)
257
                q_tmp[i] <= {width{reset_value}};
258
        end else begin
259
            q_tmp[0] <= d;
260
            for (i=1;i<depth;i=i+1)
261
                q_tmp[i] <= q_tmp[i-1];
262
        end
263
    assign q = q_tmp[depth-1];
264
endmodule
265 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
266 6 unneback
        parameter width = 1;
267 139 unneback
        parameter reset_value = {width{1'b0}};
268 6 unneback
        input [width-1:0] d;
269
        input ce, clk, rst;
270
        output reg [width-1:0] q;
271
        always @ (posedge clk or posedge rst)
272
        if (rst)
273
                q <= reset_value;
274
        else
275
                if (ce)
276
                        q <= d;
277
endmodule
278 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
279 8 unneback
        parameter width = 1;
280 139 unneback
        parameter reset_value = {width{1'b0}};
281 8 unneback
        input [width-1:0] d;
282 10 unneback
        input ce, clear, clk, rst;
283 8 unneback
        output reg [width-1:0] q;
284
        always @ (posedge clk or posedge rst)
285
        if (rst)
286
            q <= reset_value;
287
        else
288
            if (ce)
289
                if (clear)
290
                    q <= {width{1'b0}};
291
                else
292
                    q <= d;
293
endmodule
294 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
295
        parameter width = 1;
296 139 unneback
        parameter reset_value = {width{1'b0}};
297 24 unneback
        input [width-1:0] d;
298
        input ce, set, clk, rst;
299
        output reg [width-1:0] q;
300
        always @ (posedge clk or posedge rst)
301
        if (rst)
302
            q <= reset_value;
303
        else
304
            if (ce)
305
                if (set)
306
                    q <= {width{1'b1}};
307
                else
308
                    q <= d;
309
endmodule
310 29 unneback
module vl_spr ( sp, r, q, clk, rst);
311 64 unneback
        //parameter width = 1;
312
        parameter reset_value = 1'b0;
313 29 unneback
        input sp, r;
314
        output reg q;
315
        input clk, rst;
316
        always @ (posedge clk or posedge rst)
317
        if (rst)
318
            q <= reset_value;
319
        else
320
            if (sp)
321
                q <= 1'b1;
322
            else if (r)
323
                q <= 1'b0;
324
endmodule
325
module vl_srp ( s, rp, q, clk, rst);
326
        parameter width = 1;
327
        parameter reset_value = 0;
328
        input s, rp;
329
        output reg q;
330
        input clk, rst;
331
        always @ (posedge clk or posedge rst)
332
        if (rst)
333
            q <= reset_value;
334
        else
335
            if (rp)
336
                q <= 1'b0;
337
            else if (s)
338
                q <= 1'b1;
339
endmodule
340 6 unneback
// megafunction wizard: %LPM_FF%
341
// GENERATION: STANDARD
342
// VERSION: WM1.0
343
// MODULE: lpm_ff 
344
// ============================================================
345
// File Name: dff_sr.v
346
// Megafunction Name(s):
347
//                      lpm_ff
348
//
349
// Simulation Library Files(s):
350
//                      lpm
351
// ============================================================
352
// ************************************************************
353
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
354
//
355
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
356
// ************************************************************
357
//Copyright (C) 1991-2010 Altera Corporation
358
//Your use of Altera Corporation's design tools, logic functions 
359
//and other software and tools, and its AMPP partner logic 
360
//functions, and any output files from any of the foregoing 
361
//(including device programming or simulation files), and any 
362
//associated documentation or information are expressly subject 
363
//to the terms and conditions of the Altera Program License 
364
//Subscription Agreement, Altera MegaCore Function License 
365
//Agreement, or other applicable license agreement, including, 
366
//without limitation, that your use is for the sole purpose of 
367
//programming logic devices manufactured by Altera and sold by 
368
//Altera or its authorized distributors.  Please refer to the 
369
//applicable agreement for further details.
370
// synopsys translate_off
371
`timescale 1 ps / 1 ps
372
// synopsys translate_on
373 18 unneback
module vl_dff_sr (
374 6 unneback
        aclr,
375
        aset,
376
        clock,
377
        data,
378
        q);
379
        input     aclr;
380
        input     aset;
381
        input     clock;
382
        input     data;
383
        output    q;
384
        wire [0:0] sub_wire0;
385
        wire [0:0] sub_wire1 = sub_wire0[0:0];
386
        wire  q = sub_wire1;
387
        wire  sub_wire2 = data;
388
        wire  sub_wire3 = sub_wire2;
389
        lpm_ff  lpm_ff_component (
390
                                .aclr (aclr),
391
                                .clock (clock),
392
                                .data (sub_wire3),
393
                                .aset (aset),
394
                                .q (sub_wire0)
395
                                // synopsys translate_off
396
                                ,
397
                                .aload (),
398
                                .enable (),
399
                                .sclr (),
400
                                .sload (),
401
                                .sset ()
402
                                // synopsys translate_on
403
                                );
404
        defparam
405
                lpm_ff_component.lpm_fftype = "DFF",
406
                lpm_ff_component.lpm_type = "LPM_FF",
407
                lpm_ff_component.lpm_width = 1;
408
endmodule
409
// ============================================================
410
// CNX file retrieval info
411
// ============================================================
412
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
413
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
414
// Retrieval info: PRIVATE: ASET NUMERIC "1"
415
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
416
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
417
// Retrieval info: PRIVATE: DFF NUMERIC "1"
418
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
419
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
420
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
421
// Retrieval info: PRIVATE: SSET NUMERIC "0"
422
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
423
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
424
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
425
// Retrieval info: PRIVATE: nBit NUMERIC "1"
426
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
427
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
428
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
429
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
430
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
431
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
432
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
433
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
434
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
435
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
436
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
437
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
438
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
439
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
444
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
445
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
446
// Retrieval info: LIB_FILE: lpm
447
// LATCH
448
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
449 18 unneback
module vl_latch ( d, le, q, clk);
450 6 unneback
input d, le;
451
output q;
452
input clk;
453
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
454
endmodule
455 18 unneback
module vl_shreg ( d, q, clk, rst);
456 17 unneback
parameter depth = 10;
457
input d;
458
output q;
459
input clk, rst;
460
reg [1:depth] dffs;
461
always @ (posedge clk or posedge rst)
462
if (rst)
463
    dffs <= {depth{1'b0}};
464
else
465
    dffs <= {d,dffs[1:depth-1]};
466
assign q = dffs[depth];
467
endmodule
468 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
469 17 unneback
parameter depth = 10;
470
input d, ce;
471
output q;
472
input clk, rst;
473
reg [1:depth] dffs;
474
always @ (posedge clk or posedge rst)
475
if (rst)
476
    dffs <= {depth{1'b0}};
477
else
478
    if (ce)
479
        dffs <= {d,dffs[1:depth-1]};
480
assign q = dffs[depth];
481
endmodule
482 18 unneback
module vl_delay ( d, q, clk, rst);
483 15 unneback
parameter depth = 10;
484
input d;
485
output q;
486
input clk, rst;
487
reg [1:depth] dffs;
488
always @ (posedge clk or posedge rst)
489
if (rst)
490
    dffs <= {depth{1'b0}};
491
else
492
    dffs <= {d,dffs[1:depth-1]};
493
assign q = dffs[depth];
494
endmodule
495 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
496 17 unneback
parameter depth = 10;
497
input d;
498
output q, emptyflag;
499
input clk, rst;
500
reg [1:depth] dffs;
501
always @ (posedge clk or posedge rst)
502
if (rst)
503
    dffs <= {depth{1'b0}};
504
else
505
    dffs <= {d,dffs[1:depth-1]};
506
assign q = dffs[depth];
507
assign emptyflag = !(|dffs);
508
endmodule
509 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
510 94 unneback
input pl;
511 98 unneback
output reg q;
512 94 unneback
input clk, rst;
513
always @ (posedge clk or posedge rst)
514
if (rst)
515
    q <= 1'b0;
516
else
517
    q <= pl ^ q;
518
endmodule
519 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
520 94 unneback
input d;
521
output pl;
522
input clk, rst;
523
reg dff;
524
always @ (posedge clk or posedge rst)
525
if (rst)
526
    dff <= 1'b0;
527
else
528
    dff <= d;
529 98 unneback
assign pl = d ^ dff;
530 94 unneback
endmodule
531
module vl_synchronizer (d, q, clk, rst);
532
input d;
533
output reg q;
534 116 unneback
input clk, rst;
535 94 unneback
reg dff;
536
always @ (posedge clk or posedge rst)
537
if (rst)
538 100 unneback
    {q,dff} <= 2'b00;
539 94 unneback
else
540 100 unneback
    {q,dff} <= {dff,d};
541 94 unneback
endmodule
542 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
543 94 unneback
input start_pl;
544
output take_it_pl;
545
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
546
output got_it_pl;
547
input clk_src, rst_src;
548
input clk_dst, rst_dst;
549
wire take_it_tg, take_it_tg_sync;
550
wire got_it_tg, got_it_tg_sync;
551
// src -> dst
552
vl_pulse2toggle p2t0 (
553
    .pl(start_pl),
554
    .q(take_it_tg),
555
    .clk(clk_src),
556
    .rst(rst_src));
557
vl_synchronizer sync0 (
558
    .d(take_it_tg),
559
    .q(take_it_tg_sync),
560
    .clk(clk_dst),
561
    .rst(rst_dst));
562
vl_toggle2pulse t2p0 (
563 100 unneback
    .d(take_it_tg_sync),
564 94 unneback
    .pl(take_it_pl),
565
    .clk(clk_dst),
566
    .rst(rst_dst));
567
// dst -> src
568 98 unneback
vl_pulse2toggle p2t1 (
569 94 unneback
    .pl(take_it_grant_pl),
570
    .q(got_it_tg),
571
    .clk(clk_dst),
572
    .rst(rst_dst));
573
vl_synchronizer sync1 (
574
    .d(got_it_tg),
575
    .q(got_it_tg_sync),
576
    .clk(clk_src),
577
    .rst(rst_src));
578
vl_toggle2pulse t2p1 (
579 100 unneback
    .d(got_it_tg_sync),
580 94 unneback
    .pl(got_it_pl),
581
    .clk(clk_src),
582
    .rst(rst_src));
583
endmodule
584 6 unneback
//////////////////////////////////////////////////////////////////////
585
////                                                              ////
586 18 unneback
////  Logic functions                                             ////
587
////                                                              ////
588
////  Description                                                 ////
589
////  Logic functions such as multiplexers                        ////
590
////                                                              ////
591
////                                                              ////
592
////  To Do:                                                      ////
593
////   -                                                          ////
594
////                                                              ////
595
////  Author(s):                                                  ////
596
////      - Michael Unneback, unneback@opencores.org              ////
597
////        ORSoC AB                                              ////
598
////                                                              ////
599
//////////////////////////////////////////////////////////////////////
600
////                                                              ////
601
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
602
////                                                              ////
603
//// This source file may be used and distributed without         ////
604
//// restriction provided that this copyright statement is not    ////
605
//// removed from the file and that any derivative work contains  ////
606
//// the original copyright notice and the associated disclaimer. ////
607
////                                                              ////
608
//// This source file is free software; you can redistribute it   ////
609
//// and/or modify it under the terms of the GNU Lesser General   ////
610
//// Public License as published by the Free Software Foundation; ////
611
//// either version 2.1 of the License, or (at your option) any   ////
612
//// later version.                                               ////
613
////                                                              ////
614
//// This source is distributed in the hope that it will be       ////
615
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
616
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
617
//// PURPOSE.  See the GNU Lesser General Public License for more ////
618
//// details.                                                     ////
619
////                                                              ////
620
//// You should have received a copy of the GNU Lesser General    ////
621
//// Public License along with this source; if not, download it   ////
622
//// from http://www.opencores.org/lgpl.shtml                     ////
623
////                                                              ////
624
//////////////////////////////////////////////////////////////////////
625 36 unneback
module vl_mux_andor ( a, sel, dout);
626
parameter width = 32;
627
parameter nr_of_ports = 4;
628
input [nr_of_ports*width-1:0] a;
629
input [nr_of_ports-1:0] sel;
630
output reg [width-1:0] dout;
631 38 unneback
integer i,j;
632 36 unneback
always @ (a, sel)
633
begin
634
    dout = a[width-1:0] & {width{sel[0]}};
635 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
636
        for (j=0;j<width;j=j+1)
637
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
638 36 unneback
end
639
endmodule
640 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
641
parameter width = 32;
642 35 unneback
localparam nr_of_ports = 2;
643 34 unneback
input [width-1:0] a1, a0;
644
input [nr_of_ports-1:0] sel;
645
output [width-1:0] dout;
646 36 unneback
vl_mux_andor
647 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
648 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
649 34 unneback
endmodule
650
module vl_mux3_andor ( a2, a1, a0, sel, dout);
651
parameter width = 32;
652 35 unneback
localparam nr_of_ports = 3;
653 34 unneback
input [width-1:0] a2, a1, a0;
654
input [nr_of_ports-1:0] sel;
655
output [width-1:0] dout;
656 36 unneback
vl_mux_andor
657 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
658 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
659 34 unneback
endmodule
660 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
661
parameter width = 32;
662 35 unneback
localparam nr_of_ports = 4;
663 18 unneback
input [width-1:0] a3, a2, a1, a0;
664
input [nr_of_ports-1:0] sel;
665 22 unneback
output [width-1:0] dout;
666 36 unneback
vl_mux_andor
667 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
668 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
669 18 unneback
endmodule
670
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
671
parameter width = 32;
672 35 unneback
localparam nr_of_ports = 5;
673 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
674
input [nr_of_ports-1:0] sel;
675 22 unneback
output [width-1:0] dout;
676 36 unneback
vl_mux_andor
677 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
678 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
679 18 unneback
endmodule
680
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
681
parameter width = 32;
682 35 unneback
localparam nr_of_ports = 6;
683 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
684
input [nr_of_ports-1:0] sel;
685 22 unneback
output [width-1:0] dout;
686 36 unneback
vl_mux_andor
687 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
688 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
689 18 unneback
endmodule
690 43 unneback
module vl_parity_generate (data, parity);
691
parameter word_size = 32;
692
parameter chunk_size = 8;
693
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
694
input [word_size-1:0] data;
695
output reg [word_size/chunk_size-1:0] parity;
696
integer i,j;
697
always @ (data)
698
for (i=0;i<word_size/chunk_size;i=i+1) begin
699
    parity[i] = parity_type;
700
    for (j=0;j<chunk_size;j=j+1) begin
701 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
702 43 unneback
    end
703
end
704
endmodule
705
module vl_parity_check( data, parity, parity_error);
706
parameter word_size = 32;
707
parameter chunk_size = 8;
708
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
709
input [word_size-1:0] data;
710
input [word_size/chunk_size-1:0] parity;
711
output parity_error;
712 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
713 43 unneback
integer i,j;
714
always @ (data or parity)
715
for (i=0;i<word_size/chunk_size;i=i+1) begin
716
    error_flag[i] = parity[i] ^ parity_type;
717
    for (j=0;j<chunk_size;j=j+1) begin
718 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
719 43 unneback
    end
720
end
721
assign parity_error = |error_flag;
722
endmodule
723 18 unneback
//////////////////////////////////////////////////////////////////////
724
////                                                              ////
725 44 unneback
////  IO functions                                                ////
726
////                                                              ////
727
////  Description                                                 ////
728
////  IO functions such as IOB flip-flops                         ////
729
////                                                              ////
730
////                                                              ////
731
////  To Do:                                                      ////
732
////   -                                                          ////
733
////                                                              ////
734
////  Author(s):                                                  ////
735
////      - Michael Unneback, unneback@opencores.org              ////
736
////        ORSoC AB                                              ////
737
////                                                              ////
738
//////////////////////////////////////////////////////////////////////
739
////                                                              ////
740
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
741
////                                                              ////
742
//// This source file may be used and distributed without         ////
743
//// restriction provided that this copyright statement is not    ////
744
//// removed from the file and that any derivative work contains  ////
745
//// the original copyright notice and the associated disclaimer. ////
746
////                                                              ////
747
//// This source file is free software; you can redistribute it   ////
748
//// and/or modify it under the terms of the GNU Lesser General   ////
749
//// Public License as published by the Free Software Foundation; ////
750
//// either version 2.1 of the License, or (at your option) any   ////
751
//// later version.                                               ////
752
////                                                              ////
753
//// This source is distributed in the hope that it will be       ////
754
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
755
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
756
//// PURPOSE.  See the GNU Lesser General Public License for more ////
757
//// details.                                                     ////
758
////                                                              ////
759
//// You should have received a copy of the GNU Lesser General    ////
760
//// Public License along with this source; if not, download it   ////
761
//// from http://www.opencores.org/lgpl.shtml                     ////
762
////                                                              ////
763
//////////////////////////////////////////////////////////////////////
764 45 unneback
`timescale 1ns/1ns
765 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
766
parameter width = 1;
767 45 unneback
parameter reset_value = {width{1'b0}};
768
input  [width-1:0]  d_i;
769 44 unneback
output [width-1:0] o_pad;
770
input clk, rst;
771 60 unneback
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
772 45 unneback
reg  [width-1:0] o_pad_int;
773 44 unneback
assign d_i_int = d_i;
774
genvar i;
775 45 unneback
generate
776 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
777 44 unneback
    always @ (posedge clk or posedge rst)
778
    if (rst)
779 45 unneback
        o_pad_int[i] <= reset_value[i];
780 44 unneback
    else
781 45 unneback
        o_pad_int[i] <= d_i_int[i];
782
    assign #1 o_pad[i] = o_pad_int[i];
783 44 unneback
end
784
endgenerate
785
endmodule
786 45 unneback
`timescale 1ns/1ns
787 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
788
parameter width = 1;
789 140 unneback
parameter reset_value = 1'b0;
790 44 unneback
input  [width-1:0] d_o;
791
output reg [width-1:0] d_i;
792
input oe;
793
inout [width-1:0] io_pad;
794
input clk, rst;
795 60 unneback
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
796 44 unneback
reg [width-1:0] oe_q;
797
reg [width-1:0] d_o_q;
798
assign oe_d = {width{oe}};
799
genvar i;
800
generate
801 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
802 44 unneback
    always @ (posedge clk or posedge rst)
803
    if (rst)
804
        oe_q[i] <= 1'b0;
805
    else
806
        oe_q[i] <= oe_d[i];
807
    always @ (posedge clk or posedge rst)
808
    if (rst)
809 140 unneback
        d_o_q[i] <= reset_value;
810 44 unneback
    else
811
        d_o_q[i] <= d_o[i];
812
    always @ (posedge clk or posedge rst)
813
    if (rst)
814 140 unneback
        d_i[i] <= reset_value;
815 44 unneback
    else
816
        d_i[i] <= io_pad[i];
817 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
818 44 unneback
end
819
endgenerate
820
endmodule
821 136 unneback
module vl_o_ddr (d_h_i, d_l_i, o_pad, clk, rst);
822
parameter width = 1;
823
input  [width-1:0] d_h_i, d_l_i;
824
output [width-1:0] o_pad;
825
input clk, rst;
826
genvar i;
827
generate
828
for (i=0;i<width;i=i+1) begin : ddr
829
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
830
end
831
endgenerate
832
endmodule
833
module vl_o_clk ( clk_o_pad, clk, rst);
834
input clk, rst;
835
output clk_o_pad;
836
vl_o_ddr o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
837
endmodule
838 44 unneback
//////////////////////////////////////////////////////////////////////
839
////                                                              ////
840 6 unneback
////  Versatile counter                                           ////
841
////                                                              ////
842
////  Description                                                 ////
843
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
844
////  counter                                                     ////
845
////                                                              ////
846
////  To Do:                                                      ////
847
////   - add LFSR with more taps                                  ////
848
////                                                              ////
849
////  Author(s):                                                  ////
850
////      - Michael Unneback, unneback@opencores.org              ////
851
////        ORSoC AB                                              ////
852
////                                                              ////
853
//////////////////////////////////////////////////////////////////////
854
////                                                              ////
855
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
856
////                                                              ////
857
//// This source file may be used and distributed without         ////
858
//// restriction provided that this copyright statement is not    ////
859
//// removed from the file and that any derivative work contains  ////
860
//// the original copyright notice and the associated disclaimer. ////
861
////                                                              ////
862
//// This source file is free software; you can redistribute it   ////
863
//// and/or modify it under the terms of the GNU Lesser General   ////
864
//// Public License as published by the Free Software Foundation; ////
865
//// either version 2.1 of the License, or (at your option) any   ////
866
//// later version.                                               ////
867
////                                                              ////
868
//// This source is distributed in the hope that it will be       ////
869
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
870
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
871
//// PURPOSE.  See the GNU Lesser General Public License for more ////
872
//// details.                                                     ////
873
////                                                              ////
874
//// You should have received a copy of the GNU Lesser General    ////
875
//// Public License along with this source; if not, download it   ////
876
//// from http://www.opencores.org/lgpl.shtml                     ////
877
////                                                              ////
878
//////////////////////////////////////////////////////////////////////
879
// binary counter
880 139 unneback
module vl_cnt_bin (
881
 q, rst, clk);
882
   parameter length = 4;
883
   output [length:1] q;
884
   input rst;
885
   input clk;
886
   parameter clear_value = 0;
887
   parameter set_value = 1;
888
   parameter wrap_value = 0;
889
   parameter level1_value = 15;
890
   reg  [length:1] qi;
891
   wire [length:1] q_next;
892
   assign q_next = qi + {{length-1{1'b0}},1'b1};
893
   always @ (posedge clk or posedge rst)
894
     if (rst)
895
       qi <= {length{1'b0}};
896
     else
897
       qi <= q_next;
898
   assign q = qi;
899
endmodule
900
//////////////////////////////////////////////////////////////////////
901
////                                                              ////
902
////  Versatile counter                                           ////
903
////                                                              ////
904
////  Description                                                 ////
905
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
906
////  counter                                                     ////
907
////                                                              ////
908
////  To Do:                                                      ////
909
////   - add LFSR with more taps                                  ////
910
////                                                              ////
911
////  Author(s):                                                  ////
912
////      - Michael Unneback, unneback@opencores.org              ////
913
////        ORSoC AB                                              ////
914
////                                                              ////
915
//////////////////////////////////////////////////////////////////////
916
////                                                              ////
917
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
918
////                                                              ////
919
//// This source file may be used and distributed without         ////
920
//// restriction provided that this copyright statement is not    ////
921
//// removed from the file and that any derivative work contains  ////
922
//// the original copyright notice and the associated disclaimer. ////
923
////                                                              ////
924
//// This source file is free software; you can redistribute it   ////
925
//// and/or modify it under the terms of the GNU Lesser General   ////
926
//// Public License as published by the Free Software Foundation; ////
927
//// either version 2.1 of the License, or (at your option) any   ////
928
//// later version.                                               ////
929
////                                                              ////
930
//// This source is distributed in the hope that it will be       ////
931
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
932
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
933
//// PURPOSE.  See the GNU Lesser General Public License for more ////
934
//// details.                                                     ////
935
////                                                              ////
936
//// You should have received a copy of the GNU Lesser General    ////
937
//// Public License along with this source; if not, download it   ////
938
//// from http://www.opencores.org/lgpl.shtml                     ////
939
////                                                              ////
940
//////////////////////////////////////////////////////////////////////
941
// binary counter
942
module vl_cnt_bin_clear (
943
 clear, q, rst, clk);
944
   parameter length = 4;
945
   input clear;
946
   output [length:1] q;
947
   input rst;
948
   input clk;
949
   parameter clear_value = 0;
950
   parameter set_value = 1;
951
   parameter wrap_value = 0;
952
   parameter level1_value = 15;
953
   reg  [length:1] qi;
954
   wire [length:1] q_next;
955
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
956
   always @ (posedge clk or posedge rst)
957
     if (rst)
958
       qi <= {length{1'b0}};
959
     else
960
       qi <= q_next;
961
   assign q = qi;
962
endmodule
963
//////////////////////////////////////////////////////////////////////
964
////                                                              ////
965
////  Versatile counter                                           ////
966
////                                                              ////
967
////  Description                                                 ////
968
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
969
////  counter                                                     ////
970
////                                                              ////
971
////  To Do:                                                      ////
972
////   - add LFSR with more taps                                  ////
973
////                                                              ////
974
////  Author(s):                                                  ////
975
////      - Michael Unneback, unneback@opencores.org              ////
976
////        ORSoC AB                                              ////
977
////                                                              ////
978
//////////////////////////////////////////////////////////////////////
979
////                                                              ////
980
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
981
////                                                              ////
982
//// This source file may be used and distributed without         ////
983
//// restriction provided that this copyright statement is not    ////
984
//// removed from the file and that any derivative work contains  ////
985
//// the original copyright notice and the associated disclaimer. ////
986
////                                                              ////
987
//// This source file is free software; you can redistribute it   ////
988
//// and/or modify it under the terms of the GNU Lesser General   ////
989
//// Public License as published by the Free Software Foundation; ////
990
//// either version 2.1 of the License, or (at your option) any   ////
991
//// later version.                                               ////
992
////                                                              ////
993
//// This source is distributed in the hope that it will be       ////
994
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
995
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
996
//// PURPOSE.  See the GNU Lesser General Public License for more ////
997
//// details.                                                     ////
998
////                                                              ////
999
//// You should have received a copy of the GNU Lesser General    ////
1000
//// Public License along with this source; if not, download it   ////
1001
//// from http://www.opencores.org/lgpl.shtml                     ////
1002
////                                                              ////
1003
//////////////////////////////////////////////////////////////////////
1004
// binary counter
1005 40 unneback
module vl_cnt_bin_ce (
1006
 cke, q, rst, clk);
1007 22 unneback
   parameter length = 4;
1008 6 unneback
   input cke;
1009
   output [length:1] q;
1010
   input rst;
1011
   input clk;
1012
   parameter clear_value = 0;
1013
   parameter set_value = 1;
1014
   parameter wrap_value = 0;
1015
   parameter level1_value = 15;
1016
   reg  [length:1] qi;
1017
   wire [length:1] q_next;
1018
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1019
   always @ (posedge clk or posedge rst)
1020
     if (rst)
1021
       qi <= {length{1'b0}};
1022
     else
1023
     if (cke)
1024
       qi <= q_next;
1025
   assign q = qi;
1026
endmodule
1027
//////////////////////////////////////////////////////////////////////
1028
////                                                              ////
1029
////  Versatile counter                                           ////
1030
////                                                              ////
1031
////  Description                                                 ////
1032
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1033
////  counter                                                     ////
1034
////                                                              ////
1035
////  To Do:                                                      ////
1036
////   - add LFSR with more taps                                  ////
1037
////                                                              ////
1038
////  Author(s):                                                  ////
1039
////      - Michael Unneback, unneback@opencores.org              ////
1040
////        ORSoC AB                                              ////
1041
////                                                              ////
1042
//////////////////////////////////////////////////////////////////////
1043
////                                                              ////
1044
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1045
////                                                              ////
1046
//// This source file may be used and distributed without         ////
1047
//// restriction provided that this copyright statement is not    ////
1048
//// removed from the file and that any derivative work contains  ////
1049
//// the original copyright notice and the associated disclaimer. ////
1050
////                                                              ////
1051
//// This source file is free software; you can redistribute it   ////
1052
//// and/or modify it under the terms of the GNU Lesser General   ////
1053
//// Public License as published by the Free Software Foundation; ////
1054
//// either version 2.1 of the License, or (at your option) any   ////
1055
//// later version.                                               ////
1056
////                                                              ////
1057
//// This source is distributed in the hope that it will be       ////
1058
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1059
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1060
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1061
//// details.                                                     ////
1062
////                                                              ////
1063
//// You should have received a copy of the GNU Lesser General    ////
1064
//// Public License along with this source; if not, download it   ////
1065
//// from http://www.opencores.org/lgpl.shtml                     ////
1066
////                                                              ////
1067
//////////////////////////////////////////////////////////////////////
1068
// binary counter
1069 139 unneback
module vl_cnt_bin_ce_clear (
1070
 clear, cke, q, rst, clk);
1071
   parameter length = 4;
1072
   input clear;
1073
   input cke;
1074
   output [length:1] q;
1075
   input rst;
1076
   input clk;
1077
   parameter clear_value = 0;
1078
   parameter set_value = 1;
1079
   parameter wrap_value = 0;
1080
   parameter level1_value = 15;
1081
   reg  [length:1] qi;
1082
   wire [length:1] q_next;
1083
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1084
   always @ (posedge clk or posedge rst)
1085
     if (rst)
1086
       qi <= {length{1'b0}};
1087
     else
1088
     if (cke)
1089
       qi <= q_next;
1090
   assign q = qi;
1091
endmodule
1092
//////////////////////////////////////////////////////////////////////
1093
////                                                              ////
1094
////  Versatile counter                                           ////
1095
////                                                              ////
1096
////  Description                                                 ////
1097
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1098
////  counter                                                     ////
1099
////                                                              ////
1100
////  To Do:                                                      ////
1101
////   - add LFSR with more taps                                  ////
1102
////                                                              ////
1103
////  Author(s):                                                  ////
1104
////      - Michael Unneback, unneback@opencores.org              ////
1105
////        ORSoC AB                                              ////
1106
////                                                              ////
1107
//////////////////////////////////////////////////////////////////////
1108
////                                                              ////
1109
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1110
////                                                              ////
1111
//// This source file may be used and distributed without         ////
1112
//// restriction provided that this copyright statement is not    ////
1113
//// removed from the file and that any derivative work contains  ////
1114
//// the original copyright notice and the associated disclaimer. ////
1115
////                                                              ////
1116
//// This source file is free software; you can redistribute it   ////
1117
//// and/or modify it under the terms of the GNU Lesser General   ////
1118
//// Public License as published by the Free Software Foundation; ////
1119
//// either version 2.1 of the License, or (at your option) any   ////
1120
//// later version.                                               ////
1121
////                                                              ////
1122
//// This source is distributed in the hope that it will be       ////
1123
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1124
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1125
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1126
//// details.                                                     ////
1127
////                                                              ////
1128
//// You should have received a copy of the GNU Lesser General    ////
1129
//// Public License along with this source; if not, download it   ////
1130
//// from http://www.opencores.org/lgpl.shtml                     ////
1131
////                                                              ////
1132
//////////////////////////////////////////////////////////////////////
1133
// binary counter
1134
module vl_cnt_bin_ce_clear_l1_l2 (
1135
 clear, cke, q, level1, level2, rst, clk);
1136
   parameter length = 4;
1137
   input clear;
1138
   input cke;
1139
   output [length:1] q;
1140
   output reg level1;
1141
   output reg level2;
1142
   input rst;
1143
   input clk;
1144
   parameter clear_value = 0;
1145
   parameter set_value = 1;
1146
   parameter wrap_value = 15;
1147
   parameter level1_value = 8;
1148
   parameter level2_value = 15;
1149
   wire rew;
1150
   assign rew = 1'b0;
1151
   reg  [length:1] qi;
1152
   wire [length:1] q_next;
1153
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1154
   always @ (posedge clk or posedge rst)
1155
     if (rst)
1156
       qi <= {length{1'b0}};
1157
     else
1158
     if (cke)
1159
       qi <= q_next;
1160
   assign q = qi;
1161
    always @ (posedge clk or posedge rst)
1162
    if (rst)
1163
        level1 <= 1'b0;
1164
    else
1165
    if (cke)
1166
    if (clear)
1167
        level1 <= 1'b0;
1168
    else if (q_next == level1_value)
1169
        level1 <= 1'b1;
1170
    else if (qi == level1_value & rew)
1171
        level1 <= 1'b0;
1172
    always @ (posedge clk or posedge rst)
1173
    if (rst)
1174
        level2 <= 1'b0;
1175
    else
1176
    if (cke)
1177
    if (clear)
1178
        level2 <= 1'b0;
1179
    else if (q_next == level2_value)
1180
        level2 <= 1'b1;
1181
    else if (qi == level2_value & rew)
1182
        level2 <= 1'b0;
1183
endmodule
1184
//////////////////////////////////////////////////////////////////////
1185
////                                                              ////
1186
////  Versatile counter                                           ////
1187
////                                                              ////
1188
////  Description                                                 ////
1189
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1190
////  counter                                                     ////
1191
////                                                              ////
1192
////  To Do:                                                      ////
1193
////   - add LFSR with more taps                                  ////
1194
////                                                              ////
1195
////  Author(s):                                                  ////
1196
////      - Michael Unneback, unneback@opencores.org              ////
1197
////        ORSoC AB                                              ////
1198
////                                                              ////
1199
//////////////////////////////////////////////////////////////////////
1200
////                                                              ////
1201
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1202
////                                                              ////
1203
//// This source file may be used and distributed without         ////
1204
//// restriction provided that this copyright statement is not    ////
1205
//// removed from the file and that any derivative work contains  ////
1206
//// the original copyright notice and the associated disclaimer. ////
1207
////                                                              ////
1208
//// This source file is free software; you can redistribute it   ////
1209
//// and/or modify it under the terms of the GNU Lesser General   ////
1210
//// Public License as published by the Free Software Foundation; ////
1211
//// either version 2.1 of the License, or (at your option) any   ////
1212
//// later version.                                               ////
1213
////                                                              ////
1214
//// This source is distributed in the hope that it will be       ////
1215
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1216
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1217
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1218
//// details.                                                     ////
1219
////                                                              ////
1220
//// You should have received a copy of the GNU Lesser General    ////
1221
//// Public License along with this source; if not, download it   ////
1222
//// from http://www.opencores.org/lgpl.shtml                     ////
1223
////                                                              ////
1224
//////////////////////////////////////////////////////////////////////
1225
// binary counter
1226
module vl_cnt_bin_ce_clear_set_rew (
1227
 clear, set, cke, rew, q, rst, clk);
1228
   parameter length = 4;
1229
   input clear;
1230
   input set;
1231
   input cke;
1232
   input rew;
1233
   output [length:1] q;
1234
   input rst;
1235
   input clk;
1236
   parameter clear_value = 0;
1237
   parameter set_value = 1;
1238
   parameter wrap_value = 0;
1239
   parameter level1_value = 15;
1240
   reg  [length:1] qi;
1241
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1242
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1243
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1244
   assign q_next = rew ? q_next_rew : q_next_fw;
1245
   always @ (posedge clk or posedge rst)
1246
     if (rst)
1247
       qi <= {length{1'b0}};
1248
     else
1249
     if (cke)
1250
       qi <= q_next;
1251
   assign q = qi;
1252
endmodule
1253
//////////////////////////////////////////////////////////////////////
1254
////                                                              ////
1255
////  Versatile counter                                           ////
1256
////                                                              ////
1257
////  Description                                                 ////
1258
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1259
////  counter                                                     ////
1260
////                                                              ////
1261
////  To Do:                                                      ////
1262
////   - add LFSR with more taps                                  ////
1263
////                                                              ////
1264
////  Author(s):                                                  ////
1265
////      - Michael Unneback, unneback@opencores.org              ////
1266
////        ORSoC AB                                              ////
1267
////                                                              ////
1268
//////////////////////////////////////////////////////////////////////
1269
////                                                              ////
1270
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1271
////                                                              ////
1272
//// This source file may be used and distributed without         ////
1273
//// restriction provided that this copyright statement is not    ////
1274
//// removed from the file and that any derivative work contains  ////
1275
//// the original copyright notice and the associated disclaimer. ////
1276
////                                                              ////
1277
//// This source file is free software; you can redistribute it   ////
1278
//// and/or modify it under the terms of the GNU Lesser General   ////
1279
//// Public License as published by the Free Software Foundation; ////
1280
//// either version 2.1 of the License, or (at your option) any   ////
1281
//// later version.                                               ////
1282
////                                                              ////
1283
//// This source is distributed in the hope that it will be       ////
1284
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1285
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1286
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1287
//// details.                                                     ////
1288
////                                                              ////
1289
//// You should have received a copy of the GNU Lesser General    ////
1290
//// Public License along with this source; if not, download it   ////
1291
//// from http://www.opencores.org/lgpl.shtml                     ////
1292
////                                                              ////
1293
//////////////////////////////////////////////////////////////////////
1294
// binary counter
1295
module vl_cnt_bin_ce_rew_l1 (
1296
 cke, rew, level1, rst, clk);
1297
   parameter length = 4;
1298
   input cke;
1299
   input rew;
1300
   output reg level1;
1301
   input rst;
1302
   input clk;
1303
   parameter clear_value = 0;
1304
   parameter set_value = 1;
1305
   parameter wrap_value = 1;
1306
   parameter level1_value = 15;
1307
   wire clear;
1308
   assign clear = 1'b0;
1309
   reg  [length:1] qi;
1310
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1311
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1312
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1313
   assign q_next = rew ? q_next_rew : q_next_fw;
1314
   always @ (posedge clk or posedge rst)
1315
     if (rst)
1316
       qi <= {length{1'b0}};
1317
     else
1318
     if (cke)
1319
       qi <= q_next;
1320
    always @ (posedge clk or posedge rst)
1321
    if (rst)
1322
        level1 <= 1'b0;
1323
    else
1324
    if (cke)
1325
    if (clear)
1326
        level1 <= 1'b0;
1327
    else if (q_next == level1_value)
1328
        level1 <= 1'b1;
1329
    else if (qi == level1_value & rew)
1330
        level1 <= 1'b0;
1331
endmodule
1332
//////////////////////////////////////////////////////////////////////
1333
////                                                              ////
1334
////  Versatile counter                                           ////
1335
////                                                              ////
1336
////  Description                                                 ////
1337
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1338
////  counter                                                     ////
1339
////                                                              ////
1340
////  To Do:                                                      ////
1341
////   - add LFSR with more taps                                  ////
1342
////                                                              ////
1343
////  Author(s):                                                  ////
1344
////      - Michael Unneback, unneback@opencores.org              ////
1345
////        ORSoC AB                                              ////
1346
////                                                              ////
1347
//////////////////////////////////////////////////////////////////////
1348
////                                                              ////
1349
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1350
////                                                              ////
1351
//// This source file may be used and distributed without         ////
1352
//// restriction provided that this copyright statement is not    ////
1353
//// removed from the file and that any derivative work contains  ////
1354
//// the original copyright notice and the associated disclaimer. ////
1355
////                                                              ////
1356
//// This source file is free software; you can redistribute it   ////
1357
//// and/or modify it under the terms of the GNU Lesser General   ////
1358
//// Public License as published by the Free Software Foundation; ////
1359
//// either version 2.1 of the License, or (at your option) any   ////
1360
//// later version.                                               ////
1361
////                                                              ////
1362
//// This source is distributed in the hope that it will be       ////
1363
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1364
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1365
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1366
//// details.                                                     ////
1367
////                                                              ////
1368
//// You should have received a copy of the GNU Lesser General    ////
1369
//// Public License along with this source; if not, download it   ////
1370
//// from http://www.opencores.org/lgpl.shtml                     ////
1371
////                                                              ////
1372
//////////////////////////////////////////////////////////////////////
1373
// binary counter
1374 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
1375
 cke, rew, zq, level1, rst, clk);
1376 6 unneback
   parameter length = 4;
1377
   input cke;
1378
   input rew;
1379 25 unneback
   output reg zq;
1380
   output reg level1;
1381
   input rst;
1382
   input clk;
1383
   parameter clear_value = 0;
1384
   parameter set_value = 1;
1385
   parameter wrap_value = 1;
1386
   parameter level1_value = 15;
1387 29 unneback
   wire clear;
1388 30 unneback
   assign clear = 1'b0;
1389 25 unneback
   reg  [length:1] qi;
1390
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1391
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1392
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1393
   assign q_next = rew ? q_next_rew : q_next_fw;
1394
   always @ (posedge clk or posedge rst)
1395
     if (rst)
1396
       qi <= {length{1'b0}};
1397
     else
1398
     if (cke)
1399
       qi <= q_next;
1400
   always @ (posedge clk or posedge rst)
1401
     if (rst)
1402
       zq <= 1'b1;
1403
     else
1404
     if (cke)
1405
       zq <= q_next == {length{1'b0}};
1406
    always @ (posedge clk or posedge rst)
1407
    if (rst)
1408
        level1 <= 1'b0;
1409
    else
1410
    if (cke)
1411 29 unneback
    if (clear)
1412
        level1 <= 1'b0;
1413
    else if (q_next == level1_value)
1414 25 unneback
        level1 <= 1'b1;
1415
    else if (qi == level1_value & rew)
1416
        level1 <= 1'b0;
1417
endmodule
1418
//////////////////////////////////////////////////////////////////////
1419
////                                                              ////
1420
////  Versatile counter                                           ////
1421
////                                                              ////
1422
////  Description                                                 ////
1423
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1424
////  counter                                                     ////
1425
////                                                              ////
1426
////  To Do:                                                      ////
1427
////   - add LFSR with more taps                                  ////
1428
////                                                              ////
1429
////  Author(s):                                                  ////
1430
////      - Michael Unneback, unneback@opencores.org              ////
1431
////        ORSoC AB                                              ////
1432
////                                                              ////
1433
//////////////////////////////////////////////////////////////////////
1434
////                                                              ////
1435
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1436
////                                                              ////
1437
//// This source file may be used and distributed without         ////
1438
//// restriction provided that this copyright statement is not    ////
1439
//// removed from the file and that any derivative work contains  ////
1440
//// the original copyright notice and the associated disclaimer. ////
1441
////                                                              ////
1442
//// This source file is free software; you can redistribute it   ////
1443
//// and/or modify it under the terms of the GNU Lesser General   ////
1444
//// Public License as published by the Free Software Foundation; ////
1445
//// either version 2.1 of the License, or (at your option) any   ////
1446
//// later version.                                               ////
1447
////                                                              ////
1448
//// This source is distributed in the hope that it will be       ////
1449
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1450
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1451
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1452
//// details.                                                     ////
1453
////                                                              ////
1454
//// You should have received a copy of the GNU Lesser General    ////
1455
//// Public License along with this source; if not, download it   ////
1456
//// from http://www.opencores.org/lgpl.shtml                     ////
1457
////                                                              ////
1458
//////////////////////////////////////////////////////////////////////
1459
// binary counter
1460 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
1461
 cke, rew, q, zq, level1, rst, clk);
1462 25 unneback
   parameter length = 4;
1463
   input cke;
1464
   input rew;
1465
   output [length:1] q;
1466
   output reg zq;
1467
   output reg level1;
1468
   input rst;
1469
   input clk;
1470
   parameter clear_value = 0;
1471
   parameter set_value = 1;
1472
   parameter wrap_value = 1;
1473
   parameter level1_value = 15;
1474 29 unneback
   wire clear;
1475 30 unneback
   assign clear = 1'b0;
1476 25 unneback
   reg  [length:1] qi;
1477
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1478
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1479
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1480
   assign q_next = rew ? q_next_rew : q_next_fw;
1481
   always @ (posedge clk or posedge rst)
1482
     if (rst)
1483
       qi <= {length{1'b0}};
1484
     else
1485
     if (cke)
1486
       qi <= q_next;
1487
   assign q = qi;
1488
   always @ (posedge clk or posedge rst)
1489
     if (rst)
1490
       zq <= 1'b1;
1491
     else
1492
     if (cke)
1493
       zq <= q_next == {length{1'b0}};
1494
    always @ (posedge clk or posedge rst)
1495
    if (rst)
1496
        level1 <= 1'b0;
1497
    else
1498
    if (cke)
1499 29 unneback
    if (clear)
1500
        level1 <= 1'b0;
1501
    else if (q_next == level1_value)
1502 25 unneback
        level1 <= 1'b1;
1503
    else if (qi == level1_value & rew)
1504
        level1 <= 1'b0;
1505
endmodule
1506
//////////////////////////////////////////////////////////////////////
1507
////                                                              ////
1508
////  Versatile counter                                           ////
1509
////                                                              ////
1510
////  Description                                                 ////
1511
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1512
////  counter                                                     ////
1513
////                                                              ////
1514
////  To Do:                                                      ////
1515
////   - add LFSR with more taps                                  ////
1516
////                                                              ////
1517
////  Author(s):                                                  ////
1518
////      - Michael Unneback, unneback@opencores.org              ////
1519
////        ORSoC AB                                              ////
1520
////                                                              ////
1521
//////////////////////////////////////////////////////////////////////
1522
////                                                              ////
1523
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1524
////                                                              ////
1525
//// This source file may be used and distributed without         ////
1526
//// restriction provided that this copyright statement is not    ////
1527
//// removed from the file and that any derivative work contains  ////
1528
//// the original copyright notice and the associated disclaimer. ////
1529
////                                                              ////
1530
//// This source file is free software; you can redistribute it   ////
1531
//// and/or modify it under the terms of the GNU Lesser General   ////
1532
//// Public License as published by the Free Software Foundation; ////
1533
//// either version 2.1 of the License, or (at your option) any   ////
1534
//// later version.                                               ////
1535
////                                                              ////
1536
//// This source is distributed in the hope that it will be       ////
1537
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1538
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1539
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1540
//// details.                                                     ////
1541
////                                                              ////
1542
//// You should have received a copy of the GNU Lesser General    ////
1543
//// Public License along with this source; if not, download it   ////
1544
//// from http://www.opencores.org/lgpl.shtml                     ////
1545
////                                                              ////
1546
//////////////////////////////////////////////////////////////////////
1547 75 unneback
// LFSR counter
1548 136 unneback
module vl_cnt_lfsr_zq (
1549
 zq, rst, clk);
1550
   parameter length = 4;
1551
   output reg zq;
1552
   input rst;
1553
   input clk;
1554
   parameter clear_value = 0;
1555
   parameter set_value = 1;
1556
   parameter wrap_value = 8;
1557
   parameter level1_value = 15;
1558
   reg  [length:1] qi;
1559
   reg lfsr_fb;
1560
   wire [length:1] q_next;
1561
   reg [32:1] polynom;
1562
   integer i;
1563
   always @ (qi)
1564
   begin
1565
        case (length)
1566
         2: polynom = 32'b11;                               // 0x3
1567
         3: polynom = 32'b110;                              // 0x6
1568
         4: polynom = 32'b1100;                             // 0xC
1569
         5: polynom = 32'b10100;                            // 0x14
1570
         6: polynom = 32'b110000;                           // 0x30
1571
         7: polynom = 32'b1100000;                          // 0x60
1572
         8: polynom = 32'b10111000;                         // 0xb8
1573
         9: polynom = 32'b100010000;                        // 0x110
1574
        10: polynom = 32'b1001000000;                       // 0x240
1575
        11: polynom = 32'b10100000000;                      // 0x500
1576
        12: polynom = 32'b100000101001;                     // 0x829
1577
        13: polynom = 32'b1000000001100;                    // 0x100C
1578
        14: polynom = 32'b10000000010101;                   // 0x2015
1579
        15: polynom = 32'b110000000000000;                  // 0x6000
1580
        16: polynom = 32'b1101000000001000;                 // 0xD008
1581
        17: polynom = 32'b10010000000000000;                // 0x12000
1582
        18: polynom = 32'b100000010000000000;               // 0x20400
1583
        19: polynom = 32'b1000000000000100011;              // 0x40023
1584
        20: polynom = 32'b10010000000000000000;             // 0x90000
1585
        21: polynom = 32'b101000000000000000000;            // 0x140000
1586
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1587
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1588
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1589
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1590
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1591
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1592
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1593
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1594
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1595
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1596
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1597
        default: polynom = 32'b0;
1598
        endcase
1599
        lfsr_fb = qi[length];
1600
        for (i=length-1; i>=1; i=i-1) begin
1601
            if (polynom[i])
1602
                lfsr_fb = lfsr_fb  ~^ qi[i];
1603
        end
1604
    end
1605
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1606
   always @ (posedge clk or posedge rst)
1607
     if (rst)
1608
       qi <= {length{1'b0}};
1609
     else
1610
       qi <= q_next;
1611
   always @ (posedge clk or posedge rst)
1612
     if (rst)
1613
       zq <= 1'b1;
1614
     else
1615
       zq <= q_next == {length{1'b0}};
1616
endmodule
1617
//////////////////////////////////////////////////////////////////////
1618
////                                                              ////
1619
////  Versatile counter                                           ////
1620
////                                                              ////
1621
////  Description                                                 ////
1622
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1623
////  counter                                                     ////
1624
////                                                              ////
1625
////  To Do:                                                      ////
1626
////   - add LFSR with more taps                                  ////
1627
////                                                              ////
1628
////  Author(s):                                                  ////
1629
////      - Michael Unneback, unneback@opencores.org              ////
1630
////        ORSoC AB                                              ////
1631
////                                                              ////
1632
//////////////////////////////////////////////////////////////////////
1633
////                                                              ////
1634
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1635
////                                                              ////
1636
//// This source file may be used and distributed without         ////
1637
//// restriction provided that this copyright statement is not    ////
1638
//// removed from the file and that any derivative work contains  ////
1639
//// the original copyright notice and the associated disclaimer. ////
1640
////                                                              ////
1641
//// This source file is free software; you can redistribute it   ////
1642
//// and/or modify it under the terms of the GNU Lesser General   ////
1643
//// Public License as published by the Free Software Foundation; ////
1644
//// either version 2.1 of the License, or (at your option) any   ////
1645
//// later version.                                               ////
1646
////                                                              ////
1647
//// This source is distributed in the hope that it will be       ////
1648
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1649
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1650
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1651
//// details.                                                     ////
1652
////                                                              ////
1653
//// You should have received a copy of the GNU Lesser General    ////
1654
//// Public License along with this source; if not, download it   ////
1655
//// from http://www.opencores.org/lgpl.shtml                     ////
1656
////                                                              ////
1657
//////////////////////////////////////////////////////////////////////
1658
// LFSR counter
1659 75 unneback
module vl_cnt_lfsr_ce (
1660
 cke, zq, rst, clk);
1661
   parameter length = 4;
1662
   input cke;
1663
   output reg zq;
1664
   input rst;
1665
   input clk;
1666
   parameter clear_value = 0;
1667
   parameter set_value = 1;
1668
   parameter wrap_value = 0;
1669
   parameter level1_value = 15;
1670
   reg  [length:1] qi;
1671
   reg lfsr_fb;
1672
   wire [length:1] q_next;
1673
   reg [32:1] polynom;
1674
   integer i;
1675
   always @ (qi)
1676
   begin
1677
        case (length)
1678
         2: polynom = 32'b11;                               // 0x3
1679
         3: polynom = 32'b110;                              // 0x6
1680
         4: polynom = 32'b1100;                             // 0xC
1681
         5: polynom = 32'b10100;                            // 0x14
1682
         6: polynom = 32'b110000;                           // 0x30
1683
         7: polynom = 32'b1100000;                          // 0x60
1684
         8: polynom = 32'b10111000;                         // 0xb8
1685
         9: polynom = 32'b100010000;                        // 0x110
1686
        10: polynom = 32'b1001000000;                       // 0x240
1687
        11: polynom = 32'b10100000000;                      // 0x500
1688
        12: polynom = 32'b100000101001;                     // 0x829
1689
        13: polynom = 32'b1000000001100;                    // 0x100C
1690
        14: polynom = 32'b10000000010101;                   // 0x2015
1691
        15: polynom = 32'b110000000000000;                  // 0x6000
1692
        16: polynom = 32'b1101000000001000;                 // 0xD008
1693
        17: polynom = 32'b10010000000000000;                // 0x12000
1694
        18: polynom = 32'b100000010000000000;               // 0x20400
1695
        19: polynom = 32'b1000000000000100011;              // 0x40023
1696
        20: polynom = 32'b10010000000000000000;             // 0x90000
1697
        21: polynom = 32'b101000000000000000000;            // 0x140000
1698
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1699
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1700
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1701
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1702
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1703
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1704
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1705
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1706
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1707
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1708
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1709
        default: polynom = 32'b0;
1710
        endcase
1711
        lfsr_fb = qi[length];
1712
        for (i=length-1; i>=1; i=i-1) begin
1713
            if (polynom[i])
1714
                lfsr_fb = lfsr_fb  ~^ qi[i];
1715
        end
1716
    end
1717
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1718
   always @ (posedge clk or posedge rst)
1719
     if (rst)
1720
       qi <= {length{1'b0}};
1721
     else
1722
     if (cke)
1723
       qi <= q_next;
1724
   always @ (posedge clk or posedge rst)
1725
     if (rst)
1726
       zq <= 1'b1;
1727
     else
1728
     if (cke)
1729
       zq <= q_next == {length{1'b0}};
1730
endmodule
1731
//////////////////////////////////////////////////////////////////////
1732
////                                                              ////
1733
////  Versatile counter                                           ////
1734
////                                                              ////
1735
////  Description                                                 ////
1736
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1737
////  counter                                                     ////
1738
////                                                              ////
1739
////  To Do:                                                      ////
1740
////   - add LFSR with more taps                                  ////
1741
////                                                              ////
1742
////  Author(s):                                                  ////
1743
////      - Michael Unneback, unneback@opencores.org              ////
1744
////        ORSoC AB                                              ////
1745
////                                                              ////
1746
//////////////////////////////////////////////////////////////////////
1747
////                                                              ////
1748
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1749
////                                                              ////
1750
//// This source file may be used and distributed without         ////
1751
//// restriction provided that this copyright statement is not    ////
1752
//// removed from the file and that any derivative work contains  ////
1753
//// the original copyright notice and the associated disclaimer. ////
1754
////                                                              ////
1755
//// This source file is free software; you can redistribute it   ////
1756
//// and/or modify it under the terms of the GNU Lesser General   ////
1757
//// Public License as published by the Free Software Foundation; ////
1758
//// either version 2.1 of the License, or (at your option) any   ////
1759
//// later version.                                               ////
1760
////                                                              ////
1761
//// This source is distributed in the hope that it will be       ////
1762
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1763
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1764
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1765
//// details.                                                     ////
1766
////                                                              ////
1767
//// You should have received a copy of the GNU Lesser General    ////
1768
//// Public License along with this source; if not, download it   ////
1769
//// from http://www.opencores.org/lgpl.shtml                     ////
1770
////                                                              ////
1771
//////////////////////////////////////////////////////////////////////
1772 139 unneback
// LFSR counter
1773
module vl_cnt_lfsr_ce_zq (
1774
 cke, zq, rst, clk);
1775
   parameter length = 4;
1776
   input cke;
1777
   output reg zq;
1778
   input rst;
1779
   input clk;
1780
   parameter clear_value = 0;
1781
   parameter set_value = 1;
1782
   parameter wrap_value = 8;
1783
   parameter level1_value = 15;
1784
   reg  [length:1] qi;
1785
   reg lfsr_fb;
1786
   wire [length:1] q_next;
1787
   reg [32:1] polynom;
1788
   integer i;
1789
   always @ (qi)
1790
   begin
1791
        case (length)
1792
         2: polynom = 32'b11;                               // 0x3
1793
         3: polynom = 32'b110;                              // 0x6
1794
         4: polynom = 32'b1100;                             // 0xC
1795
         5: polynom = 32'b10100;                            // 0x14
1796
         6: polynom = 32'b110000;                           // 0x30
1797
         7: polynom = 32'b1100000;                          // 0x60
1798
         8: polynom = 32'b10111000;                         // 0xb8
1799
         9: polynom = 32'b100010000;                        // 0x110
1800
        10: polynom = 32'b1001000000;                       // 0x240
1801
        11: polynom = 32'b10100000000;                      // 0x500
1802
        12: polynom = 32'b100000101001;                     // 0x829
1803
        13: polynom = 32'b1000000001100;                    // 0x100C
1804
        14: polynom = 32'b10000000010101;                   // 0x2015
1805
        15: polynom = 32'b110000000000000;                  // 0x6000
1806
        16: polynom = 32'b1101000000001000;                 // 0xD008
1807
        17: polynom = 32'b10010000000000000;                // 0x12000
1808
        18: polynom = 32'b100000010000000000;               // 0x20400
1809
        19: polynom = 32'b1000000000000100011;              // 0x40023
1810
        20: polynom = 32'b10010000000000000000;             // 0x90000
1811
        21: polynom = 32'b101000000000000000000;            // 0x140000
1812
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1813
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1814
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1815
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1816
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1817
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1818
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1819
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1820
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1821
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1822
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1823
        default: polynom = 32'b0;
1824
        endcase
1825
        lfsr_fb = qi[length];
1826
        for (i=length-1; i>=1; i=i-1) begin
1827
            if (polynom[i])
1828
                lfsr_fb = lfsr_fb  ~^ qi[i];
1829
        end
1830
    end
1831
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1832
   always @ (posedge clk or posedge rst)
1833
     if (rst)
1834
       qi <= {length{1'b0}};
1835
     else
1836
     if (cke)
1837
       qi <= q_next;
1838
   always @ (posedge clk or posedge rst)
1839
     if (rst)
1840
       zq <= 1'b1;
1841
     else
1842
     if (cke)
1843
       zq <= q_next == {length{1'b0}};
1844
endmodule
1845
//////////////////////////////////////////////////////////////////////
1846
////                                                              ////
1847
////  Versatile counter                                           ////
1848
////                                                              ////
1849
////  Description                                                 ////
1850
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1851
////  counter                                                     ////
1852
////                                                              ////
1853
////  To Do:                                                      ////
1854
////   - add LFSR with more taps                                  ////
1855
////                                                              ////
1856
////  Author(s):                                                  ////
1857
////      - Michael Unneback, unneback@opencores.org              ////
1858
////        ORSoC AB                                              ////
1859
////                                                              ////
1860
//////////////////////////////////////////////////////////////////////
1861
////                                                              ////
1862
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1863
////                                                              ////
1864
//// This source file may be used and distributed without         ////
1865
//// restriction provided that this copyright statement is not    ////
1866
//// removed from the file and that any derivative work contains  ////
1867
//// the original copyright notice and the associated disclaimer. ////
1868
////                                                              ////
1869
//// This source file is free software; you can redistribute it   ////
1870
//// and/or modify it under the terms of the GNU Lesser General   ////
1871
//// Public License as published by the Free Software Foundation; ////
1872
//// either version 2.1 of the License, or (at your option) any   ////
1873
//// later version.                                               ////
1874
////                                                              ////
1875
//// This source is distributed in the hope that it will be       ////
1876
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1877
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1878
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1879
//// details.                                                     ////
1880
////                                                              ////
1881
//// You should have received a copy of the GNU Lesser General    ////
1882
//// Public License along with this source; if not, download it   ////
1883
//// from http://www.opencores.org/lgpl.shtml                     ////
1884
////                                                              ////
1885
//////////////////////////////////////////////////////////////////////
1886
// LFSR counter
1887
module vl_cnt_lfsr_ce_q (
1888
 cke, q, rst, clk);
1889
   parameter length = 4;
1890
   input cke;
1891
   output [length:1] q;
1892
   input rst;
1893
   input clk;
1894
   parameter clear_value = 0;
1895
   parameter set_value = 1;
1896
   parameter wrap_value = 8;
1897
   parameter level1_value = 15;
1898
   reg  [length:1] qi;
1899
   reg lfsr_fb;
1900
   wire [length:1] q_next;
1901
   reg [32:1] polynom;
1902
   integer i;
1903
   always @ (qi)
1904
   begin
1905
        case (length)
1906
         2: polynom = 32'b11;                               // 0x3
1907
         3: polynom = 32'b110;                              // 0x6
1908
         4: polynom = 32'b1100;                             // 0xC
1909
         5: polynom = 32'b10100;                            // 0x14
1910
         6: polynom = 32'b110000;                           // 0x30
1911
         7: polynom = 32'b1100000;                          // 0x60
1912
         8: polynom = 32'b10111000;                         // 0xb8
1913
         9: polynom = 32'b100010000;                        // 0x110
1914
        10: polynom = 32'b1001000000;                       // 0x240
1915
        11: polynom = 32'b10100000000;                      // 0x500
1916
        12: polynom = 32'b100000101001;                     // 0x829
1917
        13: polynom = 32'b1000000001100;                    // 0x100C
1918
        14: polynom = 32'b10000000010101;                   // 0x2015
1919
        15: polynom = 32'b110000000000000;                  // 0x6000
1920
        16: polynom = 32'b1101000000001000;                 // 0xD008
1921
        17: polynom = 32'b10010000000000000;                // 0x12000
1922
        18: polynom = 32'b100000010000000000;               // 0x20400
1923
        19: polynom = 32'b1000000000000100011;              // 0x40023
1924
        20: polynom = 32'b10010000000000000000;             // 0x90000
1925
        21: polynom = 32'b101000000000000000000;            // 0x140000
1926
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1927
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1928
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1929
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1930
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1931
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1932
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1933
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1934
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1935
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1936
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1937
        default: polynom = 32'b0;
1938
        endcase
1939
        lfsr_fb = qi[length];
1940
        for (i=length-1; i>=1; i=i-1) begin
1941
            if (polynom[i])
1942
                lfsr_fb = lfsr_fb  ~^ qi[i];
1943
        end
1944
    end
1945
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1946
   always @ (posedge clk or posedge rst)
1947
     if (rst)
1948
       qi <= {length{1'b0}};
1949
     else
1950
     if (cke)
1951
       qi <= q_next;
1952
   assign q = qi;
1953
endmodule
1954
//////////////////////////////////////////////////////////////////////
1955
////                                                              ////
1956
////  Versatile counter                                           ////
1957
////                                                              ////
1958
////  Description                                                 ////
1959
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1960
////  counter                                                     ////
1961
////                                                              ////
1962
////  To Do:                                                      ////
1963
////   - add LFSR with more taps                                  ////
1964
////                                                              ////
1965
////  Author(s):                                                  ////
1966
////      - Michael Unneback, unneback@opencores.org              ////
1967
////        ORSoC AB                                              ////
1968
////                                                              ////
1969
//////////////////////////////////////////////////////////////////////
1970
////                                                              ////
1971
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1972
////                                                              ////
1973
//// This source file may be used and distributed without         ////
1974
//// restriction provided that this copyright statement is not    ////
1975
//// removed from the file and that any derivative work contains  ////
1976
//// the original copyright notice and the associated disclaimer. ////
1977
////                                                              ////
1978
//// This source file is free software; you can redistribute it   ////
1979
//// and/or modify it under the terms of the GNU Lesser General   ////
1980
//// Public License as published by the Free Software Foundation; ////
1981
//// either version 2.1 of the License, or (at your option) any   ////
1982
//// later version.                                               ////
1983
////                                                              ////
1984
//// This source is distributed in the hope that it will be       ////
1985
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1986
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1987
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1988
//// details.                                                     ////
1989
////                                                              ////
1990
//// You should have received a copy of the GNU Lesser General    ////
1991
//// Public License along with this source; if not, download it   ////
1992
//// from http://www.opencores.org/lgpl.shtml                     ////
1993
////                                                              ////
1994
//////////////////////////////////////////////////////////////////////
1995
// LFSR counter
1996
module vl_cnt_lfsr_ce_clear_q (
1997
 clear, cke, q, rst, clk);
1998
   parameter length = 4;
1999
   input clear;
2000
   input cke;
2001
   output [length:1] q;
2002
   input rst;
2003
   input clk;
2004
   parameter clear_value = 0;
2005
   parameter set_value = 1;
2006
   parameter wrap_value = 8;
2007
   parameter level1_value = 15;
2008
   reg  [length:1] qi;
2009
   reg lfsr_fb;
2010
   wire [length:1] q_next;
2011
   reg [32:1] polynom;
2012
   integer i;
2013
   always @ (qi)
2014
   begin
2015
        case (length)
2016
         2: polynom = 32'b11;                               // 0x3
2017
         3: polynom = 32'b110;                              // 0x6
2018
         4: polynom = 32'b1100;                             // 0xC
2019
         5: polynom = 32'b10100;                            // 0x14
2020
         6: polynom = 32'b110000;                           // 0x30
2021
         7: polynom = 32'b1100000;                          // 0x60
2022
         8: polynom = 32'b10111000;                         // 0xb8
2023
         9: polynom = 32'b100010000;                        // 0x110
2024
        10: polynom = 32'b1001000000;                       // 0x240
2025
        11: polynom = 32'b10100000000;                      // 0x500
2026
        12: polynom = 32'b100000101001;                     // 0x829
2027
        13: polynom = 32'b1000000001100;                    // 0x100C
2028
        14: polynom = 32'b10000000010101;                   // 0x2015
2029
        15: polynom = 32'b110000000000000;                  // 0x6000
2030
        16: polynom = 32'b1101000000001000;                 // 0xD008
2031
        17: polynom = 32'b10010000000000000;                // 0x12000
2032
        18: polynom = 32'b100000010000000000;               // 0x20400
2033
        19: polynom = 32'b1000000000000100011;              // 0x40023
2034
        20: polynom = 32'b10010000000000000000;             // 0x90000
2035
        21: polynom = 32'b101000000000000000000;            // 0x140000
2036
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2037
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2038
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2039
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2040
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2041
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2042
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2043
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2044
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2045
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2046
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2047
        default: polynom = 32'b0;
2048
        endcase
2049
        lfsr_fb = qi[length];
2050
        for (i=length-1; i>=1; i=i-1) begin
2051
            if (polynom[i])
2052
                lfsr_fb = lfsr_fb  ~^ qi[i];
2053
        end
2054
    end
2055
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2056
   always @ (posedge clk or posedge rst)
2057
     if (rst)
2058
       qi <= {length{1'b0}};
2059
     else
2060
     if (cke)
2061
       qi <= q_next;
2062
   assign q = qi;
2063
endmodule
2064
//////////////////////////////////////////////////////////////////////
2065
////                                                              ////
2066
////  Versatile counter                                           ////
2067
////                                                              ////
2068
////  Description                                                 ////
2069
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2070
////  counter                                                     ////
2071
////                                                              ////
2072
////  To Do:                                                      ////
2073
////   - add LFSR with more taps                                  ////
2074
////                                                              ////
2075
////  Author(s):                                                  ////
2076
////      - Michael Unneback, unneback@opencores.org              ////
2077
////        ORSoC AB                                              ////
2078
////                                                              ////
2079
//////////////////////////////////////////////////////////////////////
2080
////                                                              ////
2081
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2082
////                                                              ////
2083
//// This source file may be used and distributed without         ////
2084
//// restriction provided that this copyright statement is not    ////
2085
//// removed from the file and that any derivative work contains  ////
2086
//// the original copyright notice and the associated disclaimer. ////
2087
////                                                              ////
2088
//// This source file is free software; you can redistribute it   ////
2089
//// and/or modify it under the terms of the GNU Lesser General   ////
2090
//// Public License as published by the Free Software Foundation; ////
2091
//// either version 2.1 of the License, or (at your option) any   ////
2092
//// later version.                                               ////
2093
////                                                              ////
2094
//// This source is distributed in the hope that it will be       ////
2095
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2096
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2097
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2098
//// details.                                                     ////
2099
////                                                              ////
2100
//// You should have received a copy of the GNU Lesser General    ////
2101
//// Public License along with this source; if not, download it   ////
2102
//// from http://www.opencores.org/lgpl.shtml                     ////
2103
////                                                              ////
2104
//////////////////////////////////////////////////////////////////////
2105
// LFSR counter
2106
module vl_cnt_lfsr_ce_q_zq (
2107
 cke, q, zq, rst, clk);
2108
   parameter length = 4;
2109
   input cke;
2110
   output [length:1] q;
2111
   output reg zq;
2112
   input rst;
2113
   input clk;
2114
   parameter clear_value = 0;
2115
   parameter set_value = 1;
2116
   parameter wrap_value = 8;
2117
   parameter level1_value = 15;
2118
   reg  [length:1] qi;
2119
   reg lfsr_fb;
2120
   wire [length:1] q_next;
2121
   reg [32:1] polynom;
2122
   integer i;
2123
   always @ (qi)
2124
   begin
2125
        case (length)
2126
         2: polynom = 32'b11;                               // 0x3
2127
         3: polynom = 32'b110;                              // 0x6
2128
         4: polynom = 32'b1100;                             // 0xC
2129
         5: polynom = 32'b10100;                            // 0x14
2130
         6: polynom = 32'b110000;                           // 0x30
2131
         7: polynom = 32'b1100000;                          // 0x60
2132
         8: polynom = 32'b10111000;                         // 0xb8
2133
         9: polynom = 32'b100010000;                        // 0x110
2134
        10: polynom = 32'b1001000000;                       // 0x240
2135
        11: polynom = 32'b10100000000;                      // 0x500
2136
        12: polynom = 32'b100000101001;                     // 0x829
2137
        13: polynom = 32'b1000000001100;                    // 0x100C
2138
        14: polynom = 32'b10000000010101;                   // 0x2015
2139
        15: polynom = 32'b110000000000000;                  // 0x6000
2140
        16: polynom = 32'b1101000000001000;                 // 0xD008
2141
        17: polynom = 32'b10010000000000000;                // 0x12000
2142
        18: polynom = 32'b100000010000000000;               // 0x20400
2143
        19: polynom = 32'b1000000000000100011;              // 0x40023
2144
        20: polynom = 32'b10010000000000000000;             // 0x90000
2145
        21: polynom = 32'b101000000000000000000;            // 0x140000
2146
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2147
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2148
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2149
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2150
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2151
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2152
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2153
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2154
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2155
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2156
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2157
        default: polynom = 32'b0;
2158
        endcase
2159
        lfsr_fb = qi[length];
2160
        for (i=length-1; i>=1; i=i-1) begin
2161
            if (polynom[i])
2162
                lfsr_fb = lfsr_fb  ~^ qi[i];
2163
        end
2164
    end
2165
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2166
   always @ (posedge clk or posedge rst)
2167
     if (rst)
2168
       qi <= {length{1'b0}};
2169
     else
2170
     if (cke)
2171
       qi <= q_next;
2172
   assign q = qi;
2173
   always @ (posedge clk or posedge rst)
2174
     if (rst)
2175
       zq <= 1'b1;
2176
     else
2177
     if (cke)
2178
       zq <= q_next == {length{1'b0}};
2179
endmodule
2180
//////////////////////////////////////////////////////////////////////
2181
////                                                              ////
2182
////  Versatile counter                                           ////
2183
////                                                              ////
2184
////  Description                                                 ////
2185
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2186
////  counter                                                     ////
2187
////                                                              ////
2188
////  To Do:                                                      ////
2189
////   - add LFSR with more taps                                  ////
2190
////                                                              ////
2191
////  Author(s):                                                  ////
2192
////      - Michael Unneback, unneback@opencores.org              ////
2193
////        ORSoC AB                                              ////
2194
////                                                              ////
2195
//////////////////////////////////////////////////////////////////////
2196
////                                                              ////
2197
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2198
////                                                              ////
2199
//// This source file may be used and distributed without         ////
2200
//// restriction provided that this copyright statement is not    ////
2201
//// removed from the file and that any derivative work contains  ////
2202
//// the original copyright notice and the associated disclaimer. ////
2203
////                                                              ////
2204
//// This source file is free software; you can redistribute it   ////
2205
//// and/or modify it under the terms of the GNU Lesser General   ////
2206
//// Public License as published by the Free Software Foundation; ////
2207
//// either version 2.1 of the License, or (at your option) any   ////
2208
//// later version.                                               ////
2209
////                                                              ////
2210
//// This source is distributed in the hope that it will be       ////
2211
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2212
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2213
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2214
//// details.                                                     ////
2215
////                                                              ////
2216
//// You should have received a copy of the GNU Lesser General    ////
2217
//// Public License along with this source; if not, download it   ////
2218
//// from http://www.opencores.org/lgpl.shtml                     ////
2219
////                                                              ////
2220
//////////////////////////////////////////////////////////////////////
2221
// LFSR counter
2222
module vl_cnt_lfsr_ce_rew_l1 (
2223
 cke, rew, level1, rst, clk);
2224
   parameter length = 4;
2225
   input cke;
2226
   input rew;
2227
   output reg level1;
2228
   input rst;
2229
   input clk;
2230
   parameter clear_value = 0;
2231
   parameter set_value = 1;
2232
   parameter wrap_value = 8;
2233
   parameter level1_value = 15;
2234
   wire clear;
2235
   assign clear = 1'b0;
2236
   reg  [length:1] qi;
2237
   reg lfsr_fb, lfsr_fb_rew;
2238
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2239
   reg [32:1] polynom_rew;
2240
   integer j;
2241
   reg [32:1] polynom;
2242
   integer i;
2243
   always @ (qi)
2244
   begin
2245
        case (length)
2246
         2: polynom = 32'b11;                               // 0x3
2247
         3: polynom = 32'b110;                              // 0x6
2248
         4: polynom = 32'b1100;                             // 0xC
2249
         5: polynom = 32'b10100;                            // 0x14
2250
         6: polynom = 32'b110000;                           // 0x30
2251
         7: polynom = 32'b1100000;                          // 0x60
2252
         8: polynom = 32'b10111000;                         // 0xb8
2253
         9: polynom = 32'b100010000;                        // 0x110
2254
        10: polynom = 32'b1001000000;                       // 0x240
2255
        11: polynom = 32'b10100000000;                      // 0x500
2256
        12: polynom = 32'b100000101001;                     // 0x829
2257
        13: polynom = 32'b1000000001100;                    // 0x100C
2258
        14: polynom = 32'b10000000010101;                   // 0x2015
2259
        15: polynom = 32'b110000000000000;                  // 0x6000
2260
        16: polynom = 32'b1101000000001000;                 // 0xD008
2261
        17: polynom = 32'b10010000000000000;                // 0x12000
2262
        18: polynom = 32'b100000010000000000;               // 0x20400
2263
        19: polynom = 32'b1000000000000100011;              // 0x40023
2264
        20: polynom = 32'b10010000000000000000;             // 0x90000
2265
        21: polynom = 32'b101000000000000000000;            // 0x140000
2266
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2267
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2268
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2269
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2270
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2271
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2272
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2273
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2274
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2275
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2276
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2277
        default: polynom = 32'b0;
2278
        endcase
2279
        lfsr_fb = qi[length];
2280
        for (i=length-1; i>=1; i=i-1) begin
2281
            if (polynom[i])
2282
                lfsr_fb = lfsr_fb  ~^ qi[i];
2283
        end
2284
    end
2285
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2286
   always @ (qi)
2287
   begin
2288
        case (length)
2289
         2: polynom_rew = 32'b11;
2290
         3: polynom_rew = 32'b110;
2291
         4: polynom_rew = 32'b1100;
2292
         5: polynom_rew = 32'b10100;
2293
         6: polynom_rew = 32'b110000;
2294
         7: polynom_rew = 32'b1100000;
2295
         8: polynom_rew = 32'b10111000;
2296
         9: polynom_rew = 32'b100010000;
2297
        10: polynom_rew = 32'b1001000000;
2298
        11: polynom_rew = 32'b10100000000;
2299
        12: polynom_rew = 32'b100000101001;
2300
        13: polynom_rew = 32'b1000000001100;
2301
        14: polynom_rew = 32'b10000000010101;
2302
        15: polynom_rew = 32'b110000000000000;
2303
        16: polynom_rew = 32'b1101000000001000;
2304
        17: polynom_rew = 32'b10010000000000000;
2305
        18: polynom_rew = 32'b100000010000000000;
2306
        19: polynom_rew = 32'b1000000000000100011;
2307
        20: polynom_rew = 32'b10000010000000000000;
2308
        21: polynom_rew = 32'b101000000000000000000;
2309
        22: polynom_rew = 32'b1100000000000000000000;
2310
        23: polynom_rew = 32'b10000100000000000000000;
2311
        24: polynom_rew = 32'b111000010000000000000000;
2312
        25: polynom_rew = 32'b1001000000000000000000000;
2313
        26: polynom_rew = 32'b10000000000000000000100011;
2314
        27: polynom_rew = 32'b100000000000000000000010011;
2315
        28: polynom_rew = 32'b1100100000000000000000000000;
2316
        29: polynom_rew = 32'b10100000000000000000000000000;
2317
        30: polynom_rew = 32'b100000000000000000000000101001;
2318
        31: polynom_rew = 32'b1001000000000000000000000000000;
2319
        32: polynom_rew = 32'b10000000001000000000000000000011;
2320
        default: polynom_rew = 32'b0;
2321
        endcase
2322
        // rotate left
2323
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2324
        lfsr_fb_rew = qi[length];
2325
        for (i=length-1; i>=1; i=i-1) begin
2326
            if (polynom_rew[i])
2327
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2328
        end
2329
    end
2330
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2331
   assign q_next = rew ? q_next_rew : q_next_fw;
2332
   always @ (posedge clk or posedge rst)
2333
     if (rst)
2334
       qi <= {length{1'b0}};
2335
     else
2336
     if (cke)
2337
       qi <= q_next;
2338
    always @ (posedge clk or posedge rst)
2339
    if (rst)
2340
        level1 <= 1'b0;
2341
    else
2342
    if (cke)
2343
    if (clear)
2344
        level1 <= 1'b0;
2345
    else if (q_next == level1_value)
2346
        level1 <= 1'b1;
2347
    else if (qi == level1_value & rew)
2348
        level1 <= 1'b0;
2349
endmodule
2350
//////////////////////////////////////////////////////////////////////
2351
////                                                              ////
2352
////  Versatile counter                                           ////
2353
////                                                              ////
2354
////  Description                                                 ////
2355
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2356
////  counter                                                     ////
2357
////                                                              ////
2358
////  To Do:                                                      ////
2359
////   - add LFSR with more taps                                  ////
2360
////                                                              ////
2361
////  Author(s):                                                  ////
2362
////      - Michael Unneback, unneback@opencores.org              ////
2363
////        ORSoC AB                                              ////
2364
////                                                              ////
2365
//////////////////////////////////////////////////////////////////////
2366
////                                                              ////
2367
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2368
////                                                              ////
2369
//// This source file may be used and distributed without         ////
2370
//// restriction provided that this copyright statement is not    ////
2371
//// removed from the file and that any derivative work contains  ////
2372
//// the original copyright notice and the associated disclaimer. ////
2373
////                                                              ////
2374
//// This source file is free software; you can redistribute it   ////
2375
//// and/or modify it under the terms of the GNU Lesser General   ////
2376
//// Public License as published by the Free Software Foundation; ////
2377
//// either version 2.1 of the License, or (at your option) any   ////
2378
//// later version.                                               ////
2379
////                                                              ////
2380
//// This source is distributed in the hope that it will be       ////
2381
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2382
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2383
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2384
//// details.                                                     ////
2385
////                                                              ////
2386
//// You should have received a copy of the GNU Lesser General    ////
2387
//// Public License along with this source; if not, download it   ////
2388
//// from http://www.opencores.org/lgpl.shtml                     ////
2389
////                                                              ////
2390
//////////////////////////////////////////////////////////////////////
2391 6 unneback
// GRAY counter
2392 139 unneback
module vl_cnt_gray (
2393
 q, rst, clk);
2394
   parameter length = 4;
2395
   output reg [length:1] q;
2396
   input rst;
2397
   input clk;
2398
   parameter clear_value = 0;
2399
   parameter set_value = 1;
2400
   parameter wrap_value = 8;
2401
   parameter level1_value = 15;
2402
   reg  [length:1] qi;
2403
   wire [length:1] q_next;
2404
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2405
   always @ (posedge clk or posedge rst)
2406
     if (rst)
2407
       qi <= {length{1'b0}};
2408
     else
2409
       qi <= q_next;
2410
   always @ (posedge clk or posedge rst)
2411
     if (rst)
2412
       q <= {length{1'b0}};
2413
     else
2414
         q <= (q_next>>1) ^ q_next;
2415
endmodule
2416
//////////////////////////////////////////////////////////////////////
2417
////                                                              ////
2418
////  Versatile counter                                           ////
2419
////                                                              ////
2420
////  Description                                                 ////
2421
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2422
////  counter                                                     ////
2423
////                                                              ////
2424
////  To Do:                                                      ////
2425
////   - add LFSR with more taps                                  ////
2426
////                                                              ////
2427
////  Author(s):                                                  ////
2428
////      - Michael Unneback, unneback@opencores.org              ////
2429
////        ORSoC AB                                              ////
2430
////                                                              ////
2431
//////////////////////////////////////////////////////////////////////
2432
////                                                              ////
2433
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2434
////                                                              ////
2435
//// This source file may be used and distributed without         ////
2436
//// restriction provided that this copyright statement is not    ////
2437
//// removed from the file and that any derivative work contains  ////
2438
//// the original copyright notice and the associated disclaimer. ////
2439
////                                                              ////
2440
//// This source file is free software; you can redistribute it   ////
2441
//// and/or modify it under the terms of the GNU Lesser General   ////
2442
//// Public License as published by the Free Software Foundation; ////
2443
//// either version 2.1 of the License, or (at your option) any   ////
2444
//// later version.                                               ////
2445
////                                                              ////
2446
//// This source is distributed in the hope that it will be       ////
2447
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2448
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2449
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2450
//// details.                                                     ////
2451
////                                                              ////
2452
//// You should have received a copy of the GNU Lesser General    ////
2453
//// Public License along with this source; if not, download it   ////
2454
//// from http://www.opencores.org/lgpl.shtml                     ////
2455
////                                                              ////
2456
//////////////////////////////////////////////////////////////////////
2457
// GRAY counter
2458
module vl_cnt_gray_ce (
2459
 cke, q, rst, clk);
2460
   parameter length = 4;
2461
   input cke;
2462
   output reg [length:1] q;
2463
   input rst;
2464
   input clk;
2465
   parameter clear_value = 0;
2466
   parameter set_value = 1;
2467
   parameter wrap_value = 8;
2468
   parameter level1_value = 15;
2469
   reg  [length:1] qi;
2470
   wire [length:1] q_next;
2471
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2472
   always @ (posedge clk or posedge rst)
2473
     if (rst)
2474
       qi <= {length{1'b0}};
2475
     else
2476
     if (cke)
2477
       qi <= q_next;
2478
   always @ (posedge clk or posedge rst)
2479
     if (rst)
2480
       q <= {length{1'b0}};
2481
     else
2482
       if (cke)
2483
         q <= (q_next>>1) ^ q_next;
2484
endmodule
2485
//////////////////////////////////////////////////////////////////////
2486
////                                                              ////
2487
////  Versatile counter                                           ////
2488
////                                                              ////
2489
////  Description                                                 ////
2490
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2491
////  counter                                                     ////
2492
////                                                              ////
2493
////  To Do:                                                      ////
2494
////   - add LFSR with more taps                                  ////
2495
////                                                              ////
2496
////  Author(s):                                                  ////
2497
////      - Michael Unneback, unneback@opencores.org              ////
2498
////        ORSoC AB                                              ////
2499
////                                                              ////
2500
//////////////////////////////////////////////////////////////////////
2501
////                                                              ////
2502
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2503
////                                                              ////
2504
//// This source file may be used and distributed without         ////
2505
//// restriction provided that this copyright statement is not    ////
2506
//// removed from the file and that any derivative work contains  ////
2507
//// the original copyright notice and the associated disclaimer. ////
2508
////                                                              ////
2509
//// This source file is free software; you can redistribute it   ////
2510
//// and/or modify it under the terms of the GNU Lesser General   ////
2511
//// Public License as published by the Free Software Foundation; ////
2512
//// either version 2.1 of the License, or (at your option) any   ////
2513
//// later version.                                               ////
2514
////                                                              ////
2515
//// This source is distributed in the hope that it will be       ////
2516
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2517
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2518
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2519
//// details.                                                     ////
2520
////                                                              ////
2521
//// You should have received a copy of the GNU Lesser General    ////
2522
//// Public License along with this source; if not, download it   ////
2523
//// from http://www.opencores.org/lgpl.shtml                     ////
2524
////                                                              ////
2525
//////////////////////////////////////////////////////////////////////
2526
// GRAY counter
2527 40 unneback
module vl_cnt_gray_ce_bin (
2528
 cke, q, q_bin, rst, clk);
2529 6 unneback
   parameter length = 4;
2530
   input cke;
2531
   output reg [length:1] q;
2532
   output [length:1] q_bin;
2533
   input rst;
2534
   input clk;
2535
   parameter clear_value = 0;
2536
   parameter set_value = 1;
2537
   parameter wrap_value = 8;
2538
   parameter level1_value = 15;
2539
   reg  [length:1] qi;
2540
   wire [length:1] q_next;
2541
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2542
   always @ (posedge clk or posedge rst)
2543
     if (rst)
2544
       qi <= {length{1'b0}};
2545
     else
2546
     if (cke)
2547
       qi <= q_next;
2548
   always @ (posedge clk or posedge rst)
2549
     if (rst)
2550
       q <= {length{1'b0}};
2551
     else
2552
       if (cke)
2553
         q <= (q_next>>1) ^ q_next;
2554
   assign q_bin = qi;
2555
endmodule
2556
//////////////////////////////////////////////////////////////////////
2557
////                                                              ////
2558
////  Versatile library, counters                                 ////
2559
////                                                              ////
2560
////  Description                                                 ////
2561
////  counters                                                    ////
2562
////                                                              ////
2563
////                                                              ////
2564
////  To Do:                                                      ////
2565
////   - add more counters                                        ////
2566
////                                                              ////
2567
////  Author(s):                                                  ////
2568
////      - Michael Unneback, unneback@opencores.org              ////
2569
////        ORSoC AB                                              ////
2570
////                                                              ////
2571
//////////////////////////////////////////////////////////////////////
2572
////                                                              ////
2573
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2574
////                                                              ////
2575
//// This source file may be used and distributed without         ////
2576
//// restriction provided that this copyright statement is not    ////
2577
//// removed from the file and that any derivative work contains  ////
2578
//// the original copyright notice and the associated disclaimer. ////
2579
////                                                              ////
2580
//// This source file is free software; you can redistribute it   ////
2581
//// and/or modify it under the terms of the GNU Lesser General   ////
2582
//// Public License as published by the Free Software Foundation; ////
2583
//// either version 2.1 of the License, or (at your option) any   ////
2584
//// later version.                                               ////
2585
////                                                              ////
2586
//// This source is distributed in the hope that it will be       ////
2587
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2588
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2589
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2590
//// details.                                                     ////
2591
////                                                              ////
2592
//// You should have received a copy of the GNU Lesser General    ////
2593
//// Public License along with this source; if not, download it   ////
2594
//// from http://www.opencores.org/lgpl.shtml                     ////
2595
////                                                              ////
2596
//////////////////////////////////////////////////////////////////////
2597 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2598 6 unneback
   parameter length = 4;
2599
   output reg [0:length-1] q;
2600
   input rst;
2601
   input clk;
2602
    always @ (posedge clk or posedge rst)
2603
    if (rst)
2604
        q <= {1'b1,{length-1{1'b0}}};
2605
    else
2606
        q <= {q[length-1],q[0:length-2]};
2607
endmodule
2608 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2609 6 unneback
   parameter length = 4;
2610
   input cke;
2611
   output reg