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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
altera
46
 // ALTERA
47
 //ACTEL
48
// sync reset
49 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
50 6 unneback
// output active high global reset sync with two DFFs 
51
`timescale 1 ns/100 ps
52
module vl_sync_rst ( rst_n_i, rst_o, clk);
53
input rst_n_i, clk;
54
output rst_o;
55
reg [0:1] tmp;
56
always @ (posedge clk or negedge rst_n_i)
57
if (!rst_n_i)
58 17 unneback
        tmp <= 2'b11;
59 6 unneback
else
60 17 unneback
        tmp <= {1'b0,tmp[0]};
61
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
62 6 unneback
endmodule
63
// vl_pll
64
 //altera
65
 //actel
66
//////////////////////////////////////////////////////////////////////
67
////                                                              ////
68
////  Versatile library, registers                                ////
69
////                                                              ////
70
////  Description                                                 ////
71
////  Different type of registers                                 ////
72
////                                                              ////
73
////                                                              ////
74
////  To Do:                                                      ////
75
////   - add more different registers                             ////
76
////                                                              ////
77
////  Author(s):                                                  ////
78
////      - Michael Unneback, unneback@opencores.org              ////
79
////        ORSoC AB                                              ////
80
////                                                              ////
81
//////////////////////////////////////////////////////////////////////
82
////                                                              ////
83
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84
////                                                              ////
85
//// This source file may be used and distributed without         ////
86
//// restriction provided that this copyright statement is not    ////
87
//// removed from the file and that any derivative work contains  ////
88
//// the original copyright notice and the associated disclaimer. ////
89
////                                                              ////
90
//// This source file is free software; you can redistribute it   ////
91
//// and/or modify it under the terms of the GNU Lesser General   ////
92
//// Public License as published by the Free Software Foundation; ////
93
//// either version 2.1 of the License, or (at your option) any   ////
94
//// later version.                                               ////
95
////                                                              ////
96
//// This source is distributed in the hope that it will be       ////
97
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100
//// details.                                                     ////
101
////                                                              ////
102
//// You should have received a copy of the GNU Lesser General    ////
103
//// Public License along with this source; if not, download it   ////
104
//// from http://www.opencores.org/lgpl.shtml                     ////
105
////                                                              ////
106
//////////////////////////////////////////////////////////////////////
107
module dff ( d, q, clk, rst);
108
        parameter width = 1;
109
        parameter reset_value = 0;
110
        input [width-1:0] d;
111
        input clk, rst;
112
        output reg [width-1:0] q;
113
        always @ (posedge clk or posedge rst)
114
        if (rst)
115
                q <= reset_value;
116
        else
117
                q <= d;
118
endmodule
119
module dff_array ( d, q, clk, rst);
120
        parameter width = 1;
121
        parameter depth = 2;
122
        parameter reset_value = 1'b0;
123
        input [width-1:0] d;
124
        input clk, rst;
125
        output [width-1:0] q;
126
        reg  [0:depth-1] q_tmp [width-1:0];
127
        integer i;
128
        always @ (posedge clk or posedge rst)
129
        if (rst) begin
130
            for (i=0;i<depth;i=i+1)
131
                q_tmp[i] <= {width{reset_value}};
132
        end else begin
133
            q_tmp[0] <= d;
134
            for (i=1;i<depth;i=i+1)
135
                q_tmp[i] <= q_tmp[i-1];
136
        end
137
    assign q = q_tmp[depth-1];
138
endmodule
139
module dff_ce ( d, ce, q, clk, rst);
140
        parameter width = 1;
141
        parameter reset_value = 0;
142
        input [width-1:0] d;
143
        input ce, clk, rst;
144
        output reg [width-1:0] q;
145
        always @ (posedge clk or posedge rst)
146
        if (rst)
147
                q <= reset_value;
148
        else
149
                if (ce)
150
                        q <= d;
151
endmodule
152 8 unneback
module dff_ce_clear ( d, ce, clear, q, clk, rst);
153
        parameter width = 1;
154
        parameter reset_value = 0;
155
        input [width-1:0] d;
156 10 unneback
        input ce, clear, clk, rst;
157 8 unneback
        output reg [width-1:0] q;
158
        always @ (posedge clk or posedge rst)
159
        if (rst)
160
            q <= reset_value;
161
        else
162
            if (ce)
163
                if (clear)
164
                    q <= {width{1'b0}};
165
                else
166
                    q <= d;
167
endmodule
168 6 unneback
// megafunction wizard: %LPM_FF%
169
// GENERATION: STANDARD
170
// VERSION: WM1.0
171
// MODULE: lpm_ff 
172
// ============================================================
173
// File Name: dff_sr.v
174
// Megafunction Name(s):
175
//                      lpm_ff
176
//
177
// Simulation Library Files(s):
178
//                      lpm
179
// ============================================================
180
// ************************************************************
181
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
182
//
183
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
184
// ************************************************************
185
//Copyright (C) 1991-2010 Altera Corporation
186
//Your use of Altera Corporation's design tools, logic functions 
187
//and other software and tools, and its AMPP partner logic 
188
//functions, and any output files from any of the foregoing 
189
//(including device programming or simulation files), and any 
190
//associated documentation or information are expressly subject 
191
//to the terms and conditions of the Altera Program License 
192
//Subscription Agreement, Altera MegaCore Function License 
193
//Agreement, or other applicable license agreement, including, 
194
//without limitation, that your use is for the sole purpose of 
195
//programming logic devices manufactured by Altera and sold by 
196
//Altera or its authorized distributors.  Please refer to the 
197
//applicable agreement for further details.
198
// synopsys translate_off
199
`timescale 1 ps / 1 ps
200
// synopsys translate_on
201
module dff_sr (
202
        aclr,
203
        aset,
204
        clock,
205
        data,
206
        q);
207
        input     aclr;
208
        input     aset;
209
        input     clock;
210
        input     data;
211
        output    q;
212
        wire [0:0] sub_wire0;
213
        wire [0:0] sub_wire1 = sub_wire0[0:0];
214
        wire  q = sub_wire1;
215
        wire  sub_wire2 = data;
216
        wire  sub_wire3 = sub_wire2;
217
        lpm_ff  lpm_ff_component (
218
                                .aclr (aclr),
219
                                .clock (clock),
220
                                .data (sub_wire3),
221
                                .aset (aset),
222
                                .q (sub_wire0)
223
                                // synopsys translate_off
224
                                ,
225
                                .aload (),
226
                                .enable (),
227
                                .sclr (),
228
                                .sload (),
229
                                .sset ()
230
                                // synopsys translate_on
231
                                );
232
        defparam
233
                lpm_ff_component.lpm_fftype = "DFF",
234
                lpm_ff_component.lpm_type = "LPM_FF",
235
                lpm_ff_component.lpm_width = 1;
236
endmodule
237
// ============================================================
238
// CNX file retrieval info
239
// ============================================================
240
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
241
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
242
// Retrieval info: PRIVATE: ASET NUMERIC "1"
243
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
244
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
245
// Retrieval info: PRIVATE: DFF NUMERIC "1"
246
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
247
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
248
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
249
// Retrieval info: PRIVATE: SSET NUMERIC "0"
250
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
251
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
252
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
253
// Retrieval info: PRIVATE: nBit NUMERIC "1"
254
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
255
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
256
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
257
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
258
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
259
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
260
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
261
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
262
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
263
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
264
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
265
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
266
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
267
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
268
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
269
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
270
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
271
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
272
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
273
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
274
// Retrieval info: LIB_FILE: lpm
275
// LATCH
276
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
277
module latch ( d, le, q, clk);
278
input d, le;
279
output q;
280
input clk;
281
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
282
endmodule
283 17 unneback
module shreg ( d, q, clk, rst);
284
parameter depth = 10;
285
input d;
286
output q;
287
input clk, rst;
288
reg [1:depth] dffs;
289
always @ (posedge clk or posedge rst)
290
if (rst)
291
    dffs <= {depth{1'b0}};
292
else
293
    dffs <= {d,dffs[1:depth-1]};
294
assign q = dffs[depth];
295
endmodule
296
module shreg_ce ( d, ce, q, clk, rst);
297
parameter depth = 10;
298
input d, ce;
299
output q;
300
input clk, rst;
301
reg [1:depth] dffs;
302
always @ (posedge clk or posedge rst)
303
if (rst)
304
    dffs <= {depth{1'b0}};
305
else
306
    if (ce)
307
        dffs <= {d,dffs[1:depth-1]};
308
assign q = dffs[depth];
309
endmodule
310 15 unneback
module delay ( d, q, clk, rst);
311
parameter depth = 10;
312
input d;
313
output q;
314
input clk, rst;
315
reg [1:depth] dffs;
316
always @ (posedge clk or posedge rst)
317
if (rst)
318
    dffs <= {depth{1'b0}};
319
else
320
    dffs <= {d,dffs[1:depth-1]};
321
assign q = dffs[depth];
322
endmodule
323 17 unneback
module delay_emptyflag ( d, q, emptyflag, clk, rst);
324
parameter depth = 10;
325
input d;
326
output q, emptyflag;
327
input clk, rst;
328
reg [1:depth] dffs;
329
always @ (posedge clk or posedge rst)
330
if (rst)
331
    dffs <= {depth{1'b0}};
332
else
333
    dffs <= {d,dffs[1:depth-1]};
334
assign q = dffs[depth];
335
assign emptyflag = !(|dffs);
336
endmodule
337 6 unneback
//////////////////////////////////////////////////////////////////////
338
////                                                              ////
339
////  Versatile counter                                           ////
340
////                                                              ////
341
////  Description                                                 ////
342
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
343
////  counter                                                     ////
344
////                                                              ////
345
////  To Do:                                                      ////
346
////   - add LFSR with more taps                                  ////
347
////                                                              ////
348
////  Author(s):                                                  ////
349
////      - Michael Unneback, unneback@opencores.org              ////
350
////        ORSoC AB                                              ////
351
////                                                              ////
352
//////////////////////////////////////////////////////////////////////
353
////                                                              ////
354
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
355
////                                                              ////
356
//// This source file may be used and distributed without         ////
357
//// restriction provided that this copyright statement is not    ////
358
//// removed from the file and that any derivative work contains  ////
359
//// the original copyright notice and the associated disclaimer. ////
360
////                                                              ////
361
//// This source file is free software; you can redistribute it   ////
362
//// and/or modify it under the terms of the GNU Lesser General   ////
363
//// Public License as published by the Free Software Foundation; ////
364
//// either version 2.1 of the License, or (at your option) any   ////
365
//// later version.                                               ////
366
////                                                              ////
367
//// This source is distributed in the hope that it will be       ////
368
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
369
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
370
//// PURPOSE.  See the GNU Lesser General Public License for more ////
371
//// details.                                                     ////
372
////                                                              ////
373
//// You should have received a copy of the GNU Lesser General    ////
374
//// Public License along with this source; if not, download it   ////
375
//// from http://www.opencores.org/lgpl.shtml                     ////
376
////                                                              ////
377
//////////////////////////////////////////////////////////////////////
378
// binary counter
379
module cnt_bin_ce ( cke, q, rst, clk);
380
   parameter length = 4;
381
   input cke;
382
   output [length:1] q;
383
   input rst;
384
   input clk;
385
   parameter clear_value = 0;
386
   parameter set_value = 1;
387
   parameter wrap_value = 0;
388
   parameter level1_value = 15;
389
   reg  [length:1] qi;
390
   wire [length:1] q_next;
391
   assign q_next = qi + {{length-1{1'b0}},1'b1};
392
   always @ (posedge clk or posedge rst)
393
     if (rst)
394
       qi <= {length{1'b0}};
395
     else
396
     if (cke)
397
       qi <= q_next;
398
   assign q = qi;
399
endmodule
400
//////////////////////////////////////////////////////////////////////
401
////                                                              ////
402
////  Versatile counter                                           ////
403
////                                                              ////
404
////  Description                                                 ////
405
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
406
////  counter                                                     ////
407
////                                                              ////
408
////  To Do:                                                      ////
409
////   - add LFSR with more taps                                  ////
410
////                                                              ////
411
////  Author(s):                                                  ////
412
////      - Michael Unneback, unneback@opencores.org              ////
413
////        ORSoC AB                                              ////
414
////                                                              ////
415
//////////////////////////////////////////////////////////////////////
416
////                                                              ////
417
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
418
////                                                              ////
419
//// This source file may be used and distributed without         ////
420
//// restriction provided that this copyright statement is not    ////
421
//// removed from the file and that any derivative work contains  ////
422
//// the original copyright notice and the associated disclaimer. ////
423
////                                                              ////
424
//// This source file is free software; you can redistribute it   ////
425
//// and/or modify it under the terms of the GNU Lesser General   ////
426
//// Public License as published by the Free Software Foundation; ////
427
//// either version 2.1 of the License, or (at your option) any   ////
428
//// later version.                                               ////
429
////                                                              ////
430
//// This source is distributed in the hope that it will be       ////
431
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
432
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
433
//// PURPOSE.  See the GNU Lesser General Public License for more ////
434
//// details.                                                     ////
435
////                                                              ////
436
//// You should have received a copy of the GNU Lesser General    ////
437
//// Public License along with this source; if not, download it   ////
438
//// from http://www.opencores.org/lgpl.shtml                     ////
439
////                                                              ////
440
//////////////////////////////////////////////////////////////////////
441
// binary counter
442
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
443
   parameter length = 4;
444
   input clear;
445
   input cke;
446
   output [length:1] q;
447
   input rst;
448
   input clk;
449
   parameter clear_value = 0;
450
   parameter set_value = 1;
451
   parameter wrap_value = 0;
452
   parameter level1_value = 15;
453
   reg  [length:1] qi;
454
   wire [length:1] q_next;
455
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
456
   always @ (posedge clk or posedge rst)
457
     if (rst)
458
       qi <= {length{1'b0}};
459
     else
460
     if (cke)
461
       qi <= q_next;
462
   assign q = qi;
463
endmodule
464
//////////////////////////////////////////////////////////////////////
465
////                                                              ////
466
////  Versatile counter                                           ////
467
////                                                              ////
468
////  Description                                                 ////
469
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
470
////  counter                                                     ////
471
////                                                              ////
472
////  To Do:                                                      ////
473
////   - add LFSR with more taps                                  ////
474
////                                                              ////
475
////  Author(s):                                                  ////
476
////      - Michael Unneback, unneback@opencores.org              ////
477
////        ORSoC AB                                              ////
478
////                                                              ////
479
//////////////////////////////////////////////////////////////////////
480
////                                                              ////
481
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
482
////                                                              ////
483
//// This source file may be used and distributed without         ////
484
//// restriction provided that this copyright statement is not    ////
485
//// removed from the file and that any derivative work contains  ////
486
//// the original copyright notice and the associated disclaimer. ////
487
////                                                              ////
488
//// This source file is free software; you can redistribute it   ////
489
//// and/or modify it under the terms of the GNU Lesser General   ////
490
//// Public License as published by the Free Software Foundation; ////
491
//// either version 2.1 of the License, or (at your option) any   ////
492
//// later version.                                               ////
493
////                                                              ////
494
//// This source is distributed in the hope that it will be       ////
495
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
496
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
497
//// PURPOSE.  See the GNU Lesser General Public License for more ////
498
//// details.                                                     ////
499
////                                                              ////
500
//// You should have received a copy of the GNU Lesser General    ////
501
//// Public License along with this source; if not, download it   ////
502
//// from http://www.opencores.org/lgpl.shtml                     ////
503
////                                                              ////
504
//////////////////////////////////////////////////////////////////////
505
// binary counter
506
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
507
   parameter length = 4;
508
   input clear;
509
   input set;
510
   input cke;
511
   input rew;
512
   output [length:1] q;
513
   input rst;
514
   input clk;
515
   parameter clear_value = 0;
516
   parameter set_value = 1;
517
   parameter wrap_value = 0;
518
   parameter level1_value = 15;
519
   reg  [length:1] qi;
520
   wire  [length:1] q_next, q_next_fw, q_next_rew;
521
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
522
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
523
   assign q_next = rew ? q_next_rew : q_next_fw;
524
   always @ (posedge clk or posedge rst)
525
     if (rst)
526
       qi <= {length{1'b0}};
527
     else
528
     if (cke)
529
       qi <= q_next;
530
   assign q = qi;
531
endmodule
532
//////////////////////////////////////////////////////////////////////
533
////                                                              ////
534
////  Versatile counter                                           ////
535
////                                                              ////
536
////  Description                                                 ////
537
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
538
////  counter                                                     ////
539
////                                                              ////
540
////  To Do:                                                      ////
541
////   - add LFSR with more taps                                  ////
542
////                                                              ////
543
////  Author(s):                                                  ////
544
////      - Michael Unneback, unneback@opencores.org              ////
545
////        ORSoC AB                                              ////
546
////                                                              ////
547
//////////////////////////////////////////////////////////////////////
548
////                                                              ////
549
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
550
////                                                              ////
551
//// This source file may be used and distributed without         ////
552
//// restriction provided that this copyright statement is not    ////
553
//// removed from the file and that any derivative work contains  ////
554
//// the original copyright notice and the associated disclaimer. ////
555
////                                                              ////
556
//// This source file is free software; you can redistribute it   ////
557
//// and/or modify it under the terms of the GNU Lesser General   ////
558
//// Public License as published by the Free Software Foundation; ////
559
//// either version 2.1 of the License, or (at your option) any   ////
560
//// later version.                                               ////
561
////                                                              ////
562
//// This source is distributed in the hope that it will be       ////
563
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
564
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
565
//// PURPOSE.  See the GNU Lesser General Public License for more ////
566
//// details.                                                     ////
567
////                                                              ////
568
//// You should have received a copy of the GNU Lesser General    ////
569
//// Public License along with this source; if not, download it   ////
570
//// from http://www.opencores.org/lgpl.shtml                     ////
571
////                                                              ////
572
//////////////////////////////////////////////////////////////////////
573
// binary counter
574
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
575
   parameter length = 4;
576
   input cke;
577
   input rew;
578
   output reg level1;
579
   input rst;
580
   input clk;
581
   parameter clear_value = 0;
582
   parameter set_value = 1;
583
   parameter wrap_value = 1;
584
   parameter level1_value = 15;
585
   reg  [length:1] qi;
586
   wire  [length:1] q_next, q_next_fw, q_next_rew;
587
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
588
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
589
   assign q_next = rew ? q_next_rew : q_next_fw;
590
   always @ (posedge clk or posedge rst)
591
     if (rst)
592
       qi <= {length{1'b0}};
593
     else
594
     if (cke)
595
       qi <= q_next;
596
    always @ (posedge clk or posedge rst)
597
    if (rst)
598
        level1 <= 1'b0;
599
    else
600
    if (cke)
601
    if (q_next == level1_value)
602
        level1 <= 1'b1;
603
    else if (qi == level1_value & rew)
604
        level1 <= 1'b0;
605
endmodule
606
//////////////////////////////////////////////////////////////////////
607
////                                                              ////
608
////  Versatile counter                                           ////
609
////                                                              ////
610
////  Description                                                 ////
611
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
612
////  counter                                                     ////
613
////                                                              ////
614
////  To Do:                                                      ////
615
////   - add LFSR with more taps                                  ////
616
////                                                              ////
617
////  Author(s):                                                  ////
618
////      - Michael Unneback, unneback@opencores.org              ////
619
////        ORSoC AB                                              ////
620
////                                                              ////
621
//////////////////////////////////////////////////////////////////////
622
////                                                              ////
623
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
624
////                                                              ////
625
//// This source file may be used and distributed without         ////
626
//// restriction provided that this copyright statement is not    ////
627
//// removed from the file and that any derivative work contains  ////
628
//// the original copyright notice and the associated disclaimer. ////
629
////                                                              ////
630
//// This source file is free software; you can redistribute it   ////
631
//// and/or modify it under the terms of the GNU Lesser General   ////
632
//// Public License as published by the Free Software Foundation; ////
633
//// either version 2.1 of the License, or (at your option) any   ////
634
//// later version.                                               ////
635
////                                                              ////
636
//// This source is distributed in the hope that it will be       ////
637
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
638
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
639
//// PURPOSE.  See the GNU Lesser General Public License for more ////
640
//// details.                                                     ////
641
////                                                              ////
642
//// You should have received a copy of the GNU Lesser General    ////
643
//// Public License along with this source; if not, download it   ////
644
//// from http://www.opencores.org/lgpl.shtml                     ////
645
////                                                              ////
646
//////////////////////////////////////////////////////////////////////
647
// LFSR counter
648
module cnt_lfsr_zq ( zq, rst, clk);
649
   parameter length = 4;
650
   output reg zq;
651
   input rst;
652
   input clk;
653
   parameter clear_value = 0;
654
   parameter set_value = 1;
655
   parameter wrap_value = 8;
656
   parameter level1_value = 15;
657
   reg  [length:1] qi;
658
   reg lfsr_fb;
659
   wire [length:1] q_next;
660
   reg [32:1] polynom;
661
   integer i;
662
   always @ (qi)
663
   begin
664
        case (length)
665
         2: polynom = 32'b11;                               // 0x3
666
         3: polynom = 32'b110;                              // 0x6
667
         4: polynom = 32'b1100;                             // 0xC
668
         5: polynom = 32'b10100;                            // 0x14
669
         6: polynom = 32'b110000;                           // 0x30
670
         7: polynom = 32'b1100000;                          // 0x60
671
         8: polynom = 32'b10111000;                         // 0xb8
672
         9: polynom = 32'b100010000;                        // 0x110
673
        10: polynom = 32'b1001000000;                       // 0x240
674
        11: polynom = 32'b10100000000;                      // 0x500
675
        12: polynom = 32'b100000101001;                     // 0x829
676
        13: polynom = 32'b1000000001100;                    // 0x100C
677
        14: polynom = 32'b10000000010101;                   // 0x2015
678
        15: polynom = 32'b110000000000000;                  // 0x6000
679
        16: polynom = 32'b1101000000001000;                 // 0xD008
680
        17: polynom = 32'b10010000000000000;                // 0x12000
681
        18: polynom = 32'b100000010000000000;               // 0x20400
682
        19: polynom = 32'b1000000000000100011;              // 0x40023
683
        20: polynom = 32'b10000010000000000000;             // 0x82000
684
        21: polynom = 32'b101000000000000000000;            // 0x140000
685
        22: polynom = 32'b1100000000000000000000;           // 0x300000
686
        23: polynom = 32'b10000100000000000000000;          // 0x420000
687
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
688
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
689
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
690
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
691
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
692
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
693
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
694
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
695
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
696
        default: polynom = 32'b0;
697
        endcase
698
        lfsr_fb = qi[length];
699
        for (i=length-1; i>=1; i=i-1) begin
700
            if (polynom[i])
701
                lfsr_fb = lfsr_fb  ~^ qi[i];
702
        end
703
    end
704
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
705
   always @ (posedge clk or posedge rst)
706
     if (rst)
707
       qi <= {length{1'b0}};
708
     else
709
       qi <= q_next;
710
   always @ (posedge clk or posedge rst)
711
     if (rst)
712
       zq <= 1'b1;
713
     else
714
       zq <= q_next == {length{1'b0}};
715
endmodule
716
//////////////////////////////////////////////////////////////////////
717
////                                                              ////
718
////  Versatile counter                                           ////
719
////                                                              ////
720
////  Description                                                 ////
721
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
722
////  counter                                                     ////
723
////                                                              ////
724
////  To Do:                                                      ////
725
////   - add LFSR with more taps                                  ////
726
////                                                              ////
727
////  Author(s):                                                  ////
728
////      - Michael Unneback, unneback@opencores.org              ////
729
////        ORSoC AB                                              ////
730
////                                                              ////
731
//////////////////////////////////////////////////////////////////////
732
////                                                              ////
733
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
734
////                                                              ////
735
//// This source file may be used and distributed without         ////
736
//// restriction provided that this copyright statement is not    ////
737
//// removed from the file and that any derivative work contains  ////
738
//// the original copyright notice and the associated disclaimer. ////
739
////                                                              ////
740
//// This source file is free software; you can redistribute it   ////
741
//// and/or modify it under the terms of the GNU Lesser General   ////
742
//// Public License as published by the Free Software Foundation; ////
743
//// either version 2.1 of the License, or (at your option) any   ////
744
//// later version.                                               ////
745
////                                                              ////
746
//// This source is distributed in the hope that it will be       ////
747
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
748
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
749
//// PURPOSE.  See the GNU Lesser General Public License for more ////
750
//// details.                                                     ////
751
////                                                              ////
752
//// You should have received a copy of the GNU Lesser General    ////
753
//// Public License along with this source; if not, download it   ////
754
//// from http://www.opencores.org/lgpl.shtml                     ////
755
////                                                              ////
756
//////////////////////////////////////////////////////////////////////
757
// LFSR counter
758
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
759
   parameter length = 4;
760
   input cke;
761
   output reg zq;
762
   input rst;
763
   input clk;
764
   parameter clear_value = 0;
765
   parameter set_value = 1;
766
   parameter wrap_value = 8;
767
   parameter level1_value = 15;
768
   reg  [length:1] qi;
769
   reg lfsr_fb;
770
   wire [length:1] q_next;
771
   reg [32:1] polynom;
772
   integer i;
773
   always @ (qi)
774
   begin
775
        case (length)
776
         2: polynom = 32'b11;                               // 0x3
777
         3: polynom = 32'b110;                              // 0x6
778
         4: polynom = 32'b1100;                             // 0xC
779
         5: polynom = 32'b10100;                            // 0x14
780
         6: polynom = 32'b110000;                           // 0x30
781
         7: polynom = 32'b1100000;                          // 0x60
782
         8: polynom = 32'b10111000;                         // 0xb8
783
         9: polynom = 32'b100010000;                        // 0x110
784
        10: polynom = 32'b1001000000;                       // 0x240
785
        11: polynom = 32'b10100000000;                      // 0x500
786
        12: polynom = 32'b100000101001;                     // 0x829
787
        13: polynom = 32'b1000000001100;                    // 0x100C
788
        14: polynom = 32'b10000000010101;                   // 0x2015
789
        15: polynom = 32'b110000000000000;                  // 0x6000
790
        16: polynom = 32'b1101000000001000;                 // 0xD008
791
        17: polynom = 32'b10010000000000000;                // 0x12000
792
        18: polynom = 32'b100000010000000000;               // 0x20400
793
        19: polynom = 32'b1000000000000100011;              // 0x40023
794
        20: polynom = 32'b10000010000000000000;             // 0x82000
795
        21: polynom = 32'b101000000000000000000;            // 0x140000
796
        22: polynom = 32'b1100000000000000000000;           // 0x300000
797
        23: polynom = 32'b10000100000000000000000;          // 0x420000
798
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
799
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
800
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
801
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
802
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
803
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
804
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
805
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
806
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
807
        default: polynom = 32'b0;
808
        endcase
809
        lfsr_fb = qi[length];
810
        for (i=length-1; i>=1; i=i-1) begin
811
            if (polynom[i])
812
                lfsr_fb = lfsr_fb  ~^ qi[i];
813
        end
814
    end
815
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
816
   always @ (posedge clk or posedge rst)
817
     if (rst)
818
       qi <= {length{1'b0}};
819
     else
820
     if (cke)
821
       qi <= q_next;
822
   always @ (posedge clk or posedge rst)
823
     if (rst)
824
       zq <= 1'b1;
825
     else
826
     if (cke)
827
       zq <= q_next == {length{1'b0}};
828
endmodule
829
//////////////////////////////////////////////////////////////////////
830
////                                                              ////
831
////  Versatile counter                                           ////
832
////                                                              ////
833
////  Description                                                 ////
834
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
835
////  counter                                                     ////
836
////                                                              ////
837
////  To Do:                                                      ////
838
////   - add LFSR with more taps                                  ////
839
////                                                              ////
840
////  Author(s):                                                  ////
841
////      - Michael Unneback, unneback@opencores.org              ////
842
////        ORSoC AB                                              ////
843
////                                                              ////
844
//////////////////////////////////////////////////////////////////////
845
////                                                              ////
846
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
847
////                                                              ////
848
//// This source file may be used and distributed without         ////
849
//// restriction provided that this copyright statement is not    ////
850
//// removed from the file and that any derivative work contains  ////
851
//// the original copyright notice and the associated disclaimer. ////
852
////                                                              ////
853
//// This source file is free software; you can redistribute it   ////
854
//// and/or modify it under the terms of the GNU Lesser General   ////
855
//// Public License as published by the Free Software Foundation; ////
856
//// either version 2.1 of the License, or (at your option) any   ////
857
//// later version.                                               ////
858
////                                                              ////
859
//// This source is distributed in the hope that it will be       ////
860
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
861
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
862
//// PURPOSE.  See the GNU Lesser General Public License for more ////
863
//// details.                                                     ////
864
////                                                              ////
865
//// You should have received a copy of the GNU Lesser General    ////
866
//// Public License along with this source; if not, download it   ////
867
//// from http://www.opencores.org/lgpl.shtml                     ////
868
////                                                              ////
869
//////////////////////////////////////////////////////////////////////
870
// LFSR counter
871
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
872
   parameter length = 4;
873
   input cke;
874
   input rew;
875
   output reg level1;
876
   input rst;
877
   input clk;
878
   parameter clear_value = 0;
879
   parameter set_value = 1;
880
   parameter wrap_value = 8;
881
   parameter level1_value = 15;
882
   reg  [length:1] qi;
883
   reg lfsr_fb, lfsr_fb_rew;
884
   wire  [length:1] q_next, q_next_fw, q_next_rew;
885
   reg [32:1] polynom_rew;
886
   integer j;
887
   reg [32:1] polynom;
888
   integer i;
889
   always @ (qi)
890
   begin
891
        case (length)
892
         2: polynom = 32'b11;                               // 0x3
893
         3: polynom = 32'b110;                              // 0x6
894
         4: polynom = 32'b1100;                             // 0xC
895
         5: polynom = 32'b10100;                            // 0x14
896
         6: polynom = 32'b110000;                           // 0x30
897
         7: polynom = 32'b1100000;                          // 0x60
898
         8: polynom = 32'b10111000;                         // 0xb8
899
         9: polynom = 32'b100010000;                        // 0x110
900
        10: polynom = 32'b1001000000;                       // 0x240
901
        11: polynom = 32'b10100000000;                      // 0x500
902
        12: polynom = 32'b100000101001;                     // 0x829
903
        13: polynom = 32'b1000000001100;                    // 0x100C
904
        14: polynom = 32'b10000000010101;                   // 0x2015
905
        15: polynom = 32'b110000000000000;                  // 0x6000
906
        16: polynom = 32'b1101000000001000;                 // 0xD008
907
        17: polynom = 32'b10010000000000000;                // 0x12000
908
        18: polynom = 32'b100000010000000000;               // 0x20400
909
        19: polynom = 32'b1000000000000100011;              // 0x40023
910
        20: polynom = 32'b10000010000000000000;             // 0x82000
911
        21: polynom = 32'b101000000000000000000;            // 0x140000
912
        22: polynom = 32'b1100000000000000000000;           // 0x300000
913
        23: polynom = 32'b10000100000000000000000;          // 0x420000
914
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
915
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
916
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
917
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
918
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
919
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
920
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
921
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
922
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
923
        default: polynom = 32'b0;
924
        endcase
925
        lfsr_fb = qi[length];
926
        for (i=length-1; i>=1; i=i-1) begin
927
            if (polynom[i])
928
                lfsr_fb = lfsr_fb  ~^ qi[i];
929
        end
930
    end
931
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
932
   always @ (qi)
933
   begin
934
        case (length)
935
         2: polynom_rew = 32'b11;
936
         3: polynom_rew = 32'b110;
937
         4: polynom_rew = 32'b1100;
938
         5: polynom_rew = 32'b10100;
939
         6: polynom_rew = 32'b110000;
940
         7: polynom_rew = 32'b1100000;
941
         8: polynom_rew = 32'b10111000;
942
         9: polynom_rew = 32'b100010000;
943
        10: polynom_rew = 32'b1001000000;
944
        11: polynom_rew = 32'b10100000000;
945
        12: polynom_rew = 32'b100000101001;
946
        13: polynom_rew = 32'b1000000001100;
947
        14: polynom_rew = 32'b10000000010101;
948
        15: polynom_rew = 32'b110000000000000;
949
        16: polynom_rew = 32'b1101000000001000;
950
        17: polynom_rew = 32'b10010000000000000;
951
        18: polynom_rew = 32'b100000010000000000;
952
        19: polynom_rew = 32'b1000000000000100011;
953
        20: polynom_rew = 32'b10000010000000000000;
954
        21: polynom_rew = 32'b101000000000000000000;
955
        22: polynom_rew = 32'b1100000000000000000000;
956
        23: polynom_rew = 32'b10000100000000000000000;
957
        24: polynom_rew = 32'b111000010000000000000000;
958
        25: polynom_rew = 32'b1001000000000000000000000;
959
        26: polynom_rew = 32'b10000000000000000000100011;
960
        27: polynom_rew = 32'b100000000000000000000010011;
961
        28: polynom_rew = 32'b1100100000000000000000000000;
962
        29: polynom_rew = 32'b10100000000000000000000000000;
963
        30: polynom_rew = 32'b100000000000000000000000101001;
964
        31: polynom_rew = 32'b1001000000000000000000000000000;
965
        32: polynom_rew = 32'b10000000001000000000000000000011;
966
        default: polynom_rew = 32'b0;
967
        endcase
968
        // rotate left
969
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
970
        lfsr_fb_rew = qi[length];
971
        for (i=length-1; i>=1; i=i-1) begin
972
            if (polynom_rew[i])
973
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
974
        end
975
    end
976
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
977
   assign q_next = rew ? q_next_rew : q_next_fw;
978
   always @ (posedge clk or posedge rst)
979
     if (rst)
980
       qi <= {length{1'b0}};
981
     else
982
     if (cke)
983
       qi <= q_next;
984
    always @ (posedge clk or posedge rst)
985
    if (rst)
986
        level1 <= 1'b0;
987
    else
988
    if (cke)
989
    if (q_next == level1_value)
990
        level1 <= 1'b1;
991
    else if (qi == level1_value & rew)
992
        level1 <= 1'b0;
993
endmodule
994
//////////////////////////////////////////////////////////////////////
995
////                                                              ////
996
////  Versatile counter                                           ////
997
////                                                              ////
998
////  Description                                                 ////
999
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1000
////  counter                                                     ////
1001
////                                                              ////
1002
////  To Do:                                                      ////
1003
////   - add LFSR with more taps                                  ////
1004
////                                                              ////
1005
////  Author(s):                                                  ////
1006
////      - Michael Unneback, unneback@opencores.org              ////
1007
////        ORSoC AB                                              ////
1008
////                                                              ////
1009
//////////////////////////////////////////////////////////////////////
1010
////                                                              ////
1011
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1012
////                                                              ////
1013
//// This source file may be used and distributed without         ////
1014
//// restriction provided that this copyright statement is not    ////
1015
//// removed from the file and that any derivative work contains  ////
1016
//// the original copyright notice and the associated disclaimer. ////
1017
////                                                              ////
1018
//// This source file is free software; you can redistribute it   ////
1019
//// and/or modify it under the terms of the GNU Lesser General   ////
1020
//// Public License as published by the Free Software Foundation; ////
1021
//// either version 2.1 of the License, or (at your option) any   ////
1022
//// later version.                                               ////
1023
////                                                              ////
1024
//// This source is distributed in the hope that it will be       ////
1025
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1026
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1027
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1028
//// details.                                                     ////
1029
////                                                              ////
1030
//// You should have received a copy of the GNU Lesser General    ////
1031
//// Public License along with this source; if not, download it   ////
1032
//// from http://www.opencores.org/lgpl.shtml                     ////
1033
////                                                              ////
1034
//////////////////////////////////////////////////////////////////////
1035
// GRAY counter
1036
module cnt_gray ( q, rst, clk);
1037
   parameter length = 4;
1038
   output reg [length:1] q;
1039
   input rst;
1040
   input clk;
1041
   parameter clear_value = 0;
1042
   parameter set_value = 1;
1043
   parameter wrap_value = 8;
1044
   parameter level1_value = 15;
1045
   reg  [length:1] qi;
1046
   wire [length:1] q_next;
1047
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1048
   always @ (posedge clk or posedge rst)
1049
     if (rst)
1050
       qi <= {length{1'b0}};
1051
     else
1052
       qi <= q_next;
1053
   always @ (posedge clk or posedge rst)
1054
     if (rst)
1055
       q <= {length{1'b0}};
1056
     else
1057
         q <= (q_next>>1) ^ q_next;
1058
endmodule
1059
//////////////////////////////////////////////////////////////////////
1060
////                                                              ////
1061
////  Versatile counter                                           ////
1062
////                                                              ////
1063
////  Description                                                 ////
1064
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1065
////  counter                                                     ////
1066
////                                                              ////
1067
////  To Do:                                                      ////
1068
////   - add LFSR with more taps                                  ////
1069
////                                                              ////
1070
////  Author(s):                                                  ////
1071
////      - Michael Unneback, unneback@opencores.org              ////
1072
////        ORSoC AB                                              ////
1073
////                                                              ////
1074
//////////////////////////////////////////////////////////////////////
1075
////                                                              ////
1076
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1077
////                                                              ////
1078
//// This source file may be used and distributed without         ////
1079
//// restriction provided that this copyright statement is not    ////
1080
//// removed from the file and that any derivative work contains  ////
1081
//// the original copyright notice and the associated disclaimer. ////
1082
////                                                              ////
1083
//// This source file is free software; you can redistribute it   ////
1084
//// and/or modify it under the terms of the GNU Lesser General   ////
1085
//// Public License as published by the Free Software Foundation; ////
1086
//// either version 2.1 of the License, or (at your option) any   ////
1087
//// later version.                                               ////
1088
////                                                              ////
1089
//// This source is distributed in the hope that it will be       ////
1090
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1091
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1092
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1093
//// details.                                                     ////
1094
////                                                              ////
1095
//// You should have received a copy of the GNU Lesser General    ////
1096
//// Public License along with this source; if not, download it   ////
1097
//// from http://www.opencores.org/lgpl.shtml                     ////
1098
////                                                              ////
1099
//////////////////////////////////////////////////////////////////////
1100
// GRAY counter
1101
module cnt_gray_ce ( cke, q, rst, clk);
1102
   parameter length = 4;
1103
   input cke;
1104
   output reg [length:1] q;
1105
   input rst;
1106
   input clk;
1107
   parameter clear_value = 0;
1108
   parameter set_value = 1;
1109
   parameter wrap_value = 8;
1110
   parameter level1_value = 15;
1111
   reg  [length:1] qi;
1112
   wire [length:1] q_next;
1113
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1114
   always @ (posedge clk or posedge rst)
1115
     if (rst)
1116
       qi <= {length{1'b0}};
1117
     else
1118
     if (cke)
1119
       qi <= q_next;
1120
   always @ (posedge clk or posedge rst)
1121
     if (rst)
1122
       q <= {length{1'b0}};
1123
     else
1124
       if (cke)
1125
         q <= (q_next>>1) ^ q_next;
1126
endmodule
1127
//////////////////////////////////////////////////////////////////////
1128
////                                                              ////
1129
////  Versatile counter                                           ////
1130
////                                                              ////
1131
////  Description                                                 ////
1132
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1133
////  counter                                                     ////
1134
////                                                              ////
1135
////  To Do:                                                      ////
1136
////   - add LFSR with more taps                                  ////
1137
////                                                              ////
1138
////  Author(s):                                                  ////
1139
////      - Michael Unneback, unneback@opencores.org              ////
1140
////        ORSoC AB                                              ////
1141
////                                                              ////
1142
//////////////////////////////////////////////////////////////////////
1143
////                                                              ////
1144
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1145
////                                                              ////
1146
//// This source file may be used and distributed without         ////
1147
//// restriction provided that this copyright statement is not    ////
1148
//// removed from the file and that any derivative work contains  ////
1149
//// the original copyright notice and the associated disclaimer. ////
1150
////                                                              ////
1151
//// This source file is free software; you can redistribute it   ////
1152
//// and/or modify it under the terms of the GNU Lesser General   ////
1153
//// Public License as published by the Free Software Foundation; ////
1154
//// either version 2.1 of the License, or (at your option) any   ////
1155
//// later version.                                               ////
1156
////                                                              ////
1157
//// This source is distributed in the hope that it will be       ////
1158
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1159
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1160
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1161
//// details.                                                     ////
1162
////                                                              ////
1163
//// You should have received a copy of the GNU Lesser General    ////
1164
//// Public License along with this source; if not, download it   ////
1165
//// from http://www.opencores.org/lgpl.shtml                     ////
1166
////                                                              ////
1167
//////////////////////////////////////////////////////////////////////
1168
// GRAY counter
1169
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1170
   parameter length = 4;
1171
   input cke;
1172
   output reg [length:1] q;
1173
   output [length:1] q_bin;
1174
   input rst;
1175
   input clk;
1176
   parameter clear_value = 0;
1177
   parameter set_value = 1;
1178
   parameter wrap_value = 8;
1179
   parameter level1_value = 15;
1180
   reg  [length:1] qi;
1181
   wire [length:1] q_next;
1182
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1183
   always @ (posedge clk or posedge rst)
1184
     if (rst)
1185
       qi <= {length{1'b0}};
1186
     else
1187
     if (cke)
1188
       qi <= q_next;
1189
   always @ (posedge clk or posedge rst)
1190
     if (rst)
1191
       q <= {length{1'b0}};
1192
     else
1193
       if (cke)
1194
         q <= (q_next>>1) ^ q_next;
1195
   assign q_bin = qi;
1196
endmodule
1197
//////////////////////////////////////////////////////////////////////
1198
////                                                              ////
1199
////  Versatile library, counters                                 ////
1200
////                                                              ////
1201
////  Description                                                 ////
1202
////  counters                                                    ////
1203
////                                                              ////
1204
////                                                              ////
1205
////  To Do:                                                      ////
1206
////   - add more counters                                        ////
1207
////                                                              ////
1208
////  Author(s):                                                  ////
1209
////      - Michael Unneback, unneback@opencores.org              ////
1210
////        ORSoC AB                                              ////
1211
////                                                              ////
1212
//////////////////////////////////////////////////////////////////////
1213
////                                                              ////
1214
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1215
////                                                              ////
1216
//// This source file may be used and distributed without         ////
1217
//// restriction provided that this copyright statement is not    ////
1218
//// removed from the file and that any derivative work contains  ////
1219
//// the original copyright notice and the associated disclaimer. ////
1220
////                                                              ////
1221
//// This source file is free software; you can redistribute it   ////
1222
//// and/or modify it under the terms of the GNU Lesser General   ////
1223
//// Public License as published by the Free Software Foundation; ////
1224
//// either version 2.1 of the License, or (at your option) any   ////
1225
//// later version.                                               ////
1226
////                                                              ////
1227
//// This source is distributed in the hope that it will be       ////
1228
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1229
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1230
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1231
//// details.                                                     ////
1232
////                                                              ////
1233
//// You should have received a copy of the GNU Lesser General    ////
1234
//// Public License along with this source; if not, download it   ////
1235
//// from http://www.opencores.org/lgpl.shtml                     ////
1236
////                                                              ////
1237
//////////////////////////////////////////////////////////////////////
1238
module cnt_shreg_wrap ( q, rst, clk);
1239
   parameter length = 4;
1240
   output reg [0:length-1] q;
1241
   input rst;
1242
   input clk;
1243
    always @ (posedge clk or posedge rst)
1244
    if (rst)
1245
        q <= {1'b1,{length-1{1'b0}}};
1246
    else
1247
        q <= {q[length-1],q[0:length-2]};
1248
endmodule
1249
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1250
   parameter length = 4;
1251
   input cke;
1252
   output reg [0:length-1] q;
1253
   input rst;
1254
   input clk;
1255
    always @ (posedge clk or posedge rst)
1256
    if (rst)
1257
        q <= {1'b1,{length-1{1'b0}}};
1258
    else
1259
        if (cke)
1260
            q <= {q[length-1],q[0:length-2]};
1261
endmodule
1262
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1263
   parameter length = 4;
1264
   input cke, clear;
1265
   output reg [0:length-1] q;
1266
   input rst;
1267
   input clk;
1268
    always @ (posedge clk or posedge rst)
1269
    if (rst)
1270
        q <= {1'b1,{length-1{1'b0}}};
1271
    else
1272
        if (cke)
1273
            if (clear)
1274
                q <= {1'b1,{length-1{1'b0}}};
1275
            else
1276
                q <= q >> 1;
1277
endmodule
1278
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1279
   parameter length = 4;
1280
   input cke, clear;
1281
   output reg [0:length-1] q;
1282
   input rst;
1283
   input clk;
1284
    always @ (posedge clk or posedge rst)
1285
    if (rst)
1286
        q <= {1'b1,{length-1{1'b0}}};
1287
    else
1288
        if (cke)
1289
            if (clear)
1290
                q <= {1'b1,{length-1{1'b0}}};
1291
            else
1292
            q <= {q[length-1],q[0:length-2]};
1293
endmodule
1294
//////////////////////////////////////////////////////////////////////
1295
////                                                              ////
1296
////  Versatile library, memories                                 ////
1297
////                                                              ////
1298
////  Description                                                 ////
1299
////  memories                                                    ////
1300
////                                                              ////
1301
////                                                              ////
1302
////  To Do:                                                      ////
1303
////   - add more memory types                                    ////
1304
////                                                              ////
1305
////  Author(s):                                                  ////
1306
////      - Michael Unneback, unneback@opencores.org              ////
1307
////        ORSoC AB                                              ////
1308
////                                                              ////
1309
//////////////////////////////////////////////////////////////////////
1310
////                                                              ////
1311
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1312
////                                                              ////
1313
//// This source file may be used and distributed without         ////
1314
//// restriction provided that this copyright statement is not    ////
1315
//// removed from the file and that any derivative work contains  ////
1316
//// the original copyright notice and the associated disclaimer. ////
1317
////                                                              ////
1318
//// This source file is free software; you can redistribute it   ////
1319
//// and/or modify it under the terms of the GNU Lesser General   ////
1320
//// Public License as published by the Free Software Foundation; ////
1321
//// either version 2.1 of the License, or (at your option) any   ////
1322
//// later version.                                               ////
1323
////                                                              ////
1324
//// This source is distributed in the hope that it will be       ////
1325
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1326
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1327
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1328
//// details.                                                     ////
1329
////                                                              ////
1330
//// You should have received a copy of the GNU Lesser General    ////
1331
//// Public License along with this source; if not, download it   ////
1332
//// from http://www.opencores.org/lgpl.shtml                     ////
1333
////                                                              ////
1334
//////////////////////////////////////////////////////////////////////
1335
/// ROM
1336 7 unneback
module vl_rom_init ( adr, q, clk);
1337
   parameter data_width = 32;
1338
   parameter addr_width = 8;
1339
   input [(addr_width-1):0]       adr;
1340
   output reg [(data_width-1):0] q;
1341
   input                         clk;
1342
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1343
   parameter memory_file = "vl_rom.vmem";
1344
   initial
1345
     begin
1346
        $readmemh(memory_file, rom);
1347
     end
1348
   always @ (posedge clk)
1349
     q <= rom[adr];
1350
endmodule
1351 14 unneback
/*
1352 7 unneback
module vl_rom ( adr, q, clk);
1353 6 unneback
parameter data_width = 32;
1354
parameter addr_width = 4;
1355
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1356
    {32'h18000000},
1357
    {32'hA8200000},
1358
    {32'hA8200000},
1359
    {32'hA8200000},
1360
    {32'h44003000},
1361
    {32'h15000000},
1362
    {32'h15000000},
1363
    {32'h15000000},
1364
    {32'h15000000},
1365
    {32'h15000000},
1366
    {32'h15000000},
1367
    {32'h15000000},
1368
    {32'h15000000},
1369
    {32'h15000000},
1370
    {32'h15000000},
1371
    {32'h15000000}};
1372 7 unneback
input [addr_width-1:0] adr;
1373 6 unneback
output reg [data_width-1:0] q;
1374
input clk;
1375
always @ (posedge clk)
1376 7 unneback
    q <= data[adr];
1377 6 unneback
endmodule
1378 14 unneback
*/
1379 6 unneback
// Single port RAM
1380
module vl_ram ( d, adr, we, q, clk);
1381
   parameter data_width = 32;
1382
   parameter addr_width = 8;
1383
   input [(data_width-1):0]      d;
1384
   input [(addr_width-1):0]       adr;
1385
   input                         we;
1386 7 unneback
   output reg [(data_width-1):0] q;
1387 6 unneback
   input                         clk;
1388
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1389 7 unneback
   parameter init = 0;
1390
   parameter memory_file = "vl_ram.vmem";
1391
   generate if (init) begin : init_mem
1392
   initial
1393
     begin
1394
        $readmemh(memory_file, ram);
1395
     end
1396
   end
1397
   endgenerate
1398 6 unneback
   always @ (posedge clk)
1399
   begin
1400
   if (we)
1401
     ram[adr] <= d;
1402
   q <= ram[adr];
1403
   end
1404
endmodule
1405 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1406
   parameter data_width = 32;
1407
   parameter addr_width = 8;
1408
   input [(data_width-1):0]      d;
1409
   input [(addr_width-1):0]       adr;
1410
   input [(addr_width/4)-1:0]    be;
1411
   input                         we;
1412
   output reg [(data_width-1):0] q;
1413
   input                         clk;
1414
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1415
   parameter init = 0;
1416
   parameter memory_file = "vl_ram.vmem";
1417
   generate if (init) begin : init_mem
1418
   initial
1419
     begin
1420
        $readmemh(memory_file, ram);
1421
     end
1422
   end
1423
   endgenerate
1424
   genvar i;
1425
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1426
      always @ (posedge clk)
1427
      if (we & be[i])
1428
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1429
   end
1430
   endgenerate
1431
   always @ (posedge clk)
1432
      q <= ram[adr];
1433
endmodule
1434 6 unneback
// Dual port RAM
1435
// ACTEL FPGA should not use logic to handle rw collision
1436 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1437 6 unneback
   parameter data_width = 32;
1438
   parameter addr_width = 8;
1439
   input [(data_width-1):0]      d_a;
1440
   input [(addr_width-1):0]       adr_a;
1441
   input [(addr_width-1):0]       adr_b;
1442
   input                         we_a;
1443
   output [(data_width-1):0]      q_b;
1444
   input                         clk_a, clk_b;
1445
   reg [(addr_width-1):0]         adr_b_reg;
1446
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1447 7 unneback
   parameter init = 0;
1448
   parameter memory_file = "vl_ram.vmem";
1449
   generate if (init) begin : init_mem
1450
   initial
1451
     begin
1452
        $readmemh(memory_file, ram);
1453
     end
1454
   end
1455
   endgenerate
1456 6 unneback
   always @ (posedge clk_a)
1457
   if (we_a)
1458
     ram[adr_a] <= d_a;
1459
   always @ (posedge clk_b)
1460
   adr_b_reg <= adr_b;
1461
   assign q_b = ram[adr_b_reg];
1462
endmodule
1463 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1464 6 unneback
   parameter data_width = 32;
1465
   parameter addr_width = 8;
1466
   input [(data_width-1):0]      d_a;
1467
   input [(addr_width-1):0]       adr_a;
1468
   input [(addr_width-1):0]       adr_b;
1469
   input                         we_a;
1470
   output [(data_width-1):0]      q_b;
1471
   output reg [(data_width-1):0] q_a;
1472
   input                         clk_a, clk_b;
1473
   reg [(data_width-1):0]         q_b;
1474
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1475 7 unneback
   parameter init = 0;
1476
   parameter memory_file = "vl_ram.vmem";
1477
   generate if (init) begin : init_mem
1478
   initial
1479
     begin
1480
        $readmemh(memory_file, ram);
1481
     end
1482
   end
1483
   endgenerate
1484 6 unneback
   always @ (posedge clk_a)
1485
     begin
1486
        q_a <= ram[adr_a];
1487
        if (we_a)
1488
             ram[adr_a] <= d_a;
1489
     end
1490
   always @ (posedge clk_b)
1491
          q_b <= ram[adr_b];
1492
endmodule
1493 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1494 6 unneback
   parameter data_width = 32;
1495
   parameter addr_width = 8;
1496
   input [(data_width-1):0]      d_a;
1497
   input [(addr_width-1):0]       adr_a;
1498
   input [(addr_width-1):0]       adr_b;
1499
   input                         we_a;
1500
   output [(data_width-1):0]      q_b;
1501
   input [(data_width-1):0]       d_b;
1502
   output reg [(data_width-1):0] q_a;
1503
   input                         we_b;
1504
   input                         clk_a, clk_b;
1505
   reg [(data_width-1):0]         q_b;
1506
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1507 7 unneback
   parameter init = 0;
1508
   parameter memory_file = "vl_ram.vmem";
1509
   generate if (init) begin : init_mem
1510
   initial
1511
     begin
1512
        $readmemh(memory_file, ram);
1513
     end
1514
   end
1515
   endgenerate
1516 6 unneback
   always @ (posedge clk_a)
1517
     begin
1518
        q_a <= ram[adr_a];
1519
        if (we_a)
1520
             ram[adr_a] <= d_a;
1521
     end
1522
   always @ (posedge clk_b)
1523
     begin
1524
        q_b <= ram[adr_b];
1525
        if (we_b)
1526
          ram[adr_b] <= d_b;
1527
     end
1528
endmodule
1529
// Content addresable memory, CAM
1530
// FIFO
1531
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1532 11 unneback
   parameter addr_width = 4;
1533
   parameter N = addr_width-1;
1534 6 unneback
   parameter Q1 = 2'b00;
1535
   parameter Q2 = 2'b01;
1536
   parameter Q3 = 2'b11;
1537
   parameter Q4 = 2'b10;
1538
   parameter going_empty = 1'b0;
1539
   parameter going_full  = 1'b1;
1540
   input [N:0]  wptr, rptr;
1541 14 unneback
   output       fifo_empty;
1542 6 unneback
   output       fifo_full;
1543
   input        wclk, rclk, rst;
1544
   wire direction;
1545
   reg  direction_set, direction_clr;
1546
   wire async_empty, async_full;
1547
   wire fifo_full2;
1548 14 unneback
   wire fifo_empty2;
1549 6 unneback
   // direction_set
1550
   always @ (wptr[N:N-1] or rptr[N:N-1])
1551
     case ({wptr[N:N-1],rptr[N:N-1]})
1552
       {Q1,Q2} : direction_set <= 1'b1;
1553
       {Q2,Q3} : direction_set <= 1'b1;
1554
       {Q3,Q4} : direction_set <= 1'b1;
1555
       {Q4,Q1} : direction_set <= 1'b1;
1556
       default : direction_set <= 1'b0;
1557
     endcase
1558
   // direction_clear
1559
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1560
     if (rst)
1561
       direction_clr <= 1'b1;
1562
     else
1563
       case ({wptr[N:N-1],rptr[N:N-1]})
1564
         {Q2,Q1} : direction_clr <= 1'b1;
1565
         {Q3,Q2} : direction_clr <= 1'b1;
1566
         {Q4,Q3} : direction_clr <= 1'b1;
1567
         {Q1,Q4} : direction_clr <= 1'b1;
1568
         default : direction_clr <= 1'b0;
1569
       endcase
1570
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1571
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1572
   assign async_full  = (wptr == rptr) && (direction==going_full);
1573
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1574
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1575
/*
1576
   always @ (posedge wclk or posedge rst or posedge async_full)
1577
     if (rst)
1578
       {fifo_full, fifo_full2} <= 2'b00;
1579
     else if (async_full)
1580
       {fifo_full, fifo_full2} <= 2'b11;
1581
     else
1582
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1583
*/
1584 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1585 6 unneback
     if (async_empty)
1586
       {fifo_empty, fifo_empty2} <= 2'b11;
1587
     else
1588 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1589
    dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1590
    dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1591 6 unneback
endmodule // async_comp
1592
module vl_fifo_1r1w_async (
1593
    d, wr, fifo_full, wr_clk, wr_rst,
1594
    q, rd, fifo_empty, rd_clk, rd_rst
1595
    );
1596
parameter data_width = 18;
1597
parameter addr_width = 4;
1598
// write side
1599
input  [data_width-1:0] d;
1600
input                   wr;
1601
output                  fifo_full;
1602
input                   wr_clk;
1603
input                   wr_rst;
1604
// read side
1605
output [data_width-1:0] q;
1606
input                   rd;
1607
output                  fifo_empty;
1608
input                   rd_clk;
1609
input                   rd_rst;
1610
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1611
vl_fifo_1r1w_async (
1612
    d, wr, fifo_full, wr_clk, wr_rst,
1613
    q, rd, fifo_empty, rd_clk, rd_rst
1614
    );
1615 7 unneback
cnt_gray_ce_bin
1616 6 unneback
    # ( .length(addr_width))
1617
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1618 7 unneback
cnt_gray_ce_bin
1619 6 unneback
    # (.length(addr_width))
1620
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1621 7 unneback
vl_dpram_1r1w
1622 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1623
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1624
vl_fifo_cmp_async
1625
    # (.addr_width(addr_width))
1626
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1627
endmodule
1628 8 unneback
module vl_fifo_2r2w_async (
1629 6 unneback
    // a side
1630
    a_d, a_wr, a_fifo_full,
1631
    a_q, a_rd, a_fifo_empty,
1632
    a_clk, a_rst,
1633
    // b side
1634
    b_d, b_wr, b_fifo_full,
1635
    b_q, b_rd, b_fifo_empty,
1636
    b_clk, b_rst
1637
    );
1638
parameter data_width = 18;
1639
parameter addr_width = 4;
1640
// a side
1641
input  [data_width-1:0] a_d;
1642
input                   a_wr;
1643
output                  a_fifo_full;
1644
output [data_width-1:0] a_q;
1645
input                   a_rd;
1646
output                  a_fifo_empty;
1647
input                   a_clk;
1648
input                   a_rst;
1649
// b side
1650
input  [data_width-1:0] b_d;
1651
input                   b_wr;
1652
output                  b_fifo_full;
1653
output [data_width-1:0] b_q;
1654
input                   b_rd;
1655
output                  b_fifo_empty;
1656
input                   b_clk;
1657
input                   b_rst;
1658
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1659
vl_fifo_1r1w_async_a (
1660
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1661
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1662
    );
1663
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1664
vl_fifo_1r1w_async_b (
1665
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1666
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1667
    );
1668
endmodule
1669 8 unneback
module vl_fifo_2r2w_async_simplex (
1670 6 unneback
    // a side
1671
    a_d, a_wr, a_fifo_full,
1672
    a_q, a_rd, a_fifo_empty,
1673
    a_clk, a_rst,
1674
    // b side
1675
    b_d, b_wr, b_fifo_full,
1676
    b_q, b_rd, b_fifo_empty,
1677
    b_clk, b_rst
1678
    );
1679
parameter data_width = 18;
1680
parameter addr_width = 4;
1681
// a side
1682
input  [data_width-1:0] a_d;
1683
input                   a_wr;
1684
output                  a_fifo_full;
1685
output [data_width-1:0] a_q;
1686
input                   a_rd;
1687
output                  a_fifo_empty;
1688
input                   a_clk;
1689
input                   a_rst;
1690
// b side
1691
input  [data_width-1:0] b_d;
1692
input                   b_wr;
1693
output                  b_fifo_full;
1694
output [data_width-1:0] b_q;
1695
input                   b_rd;
1696
output                  b_fifo_empty;
1697
input                   b_clk;
1698
input                   b_rst;
1699
// adr_gen
1700
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1701
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1702
// dpram
1703
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1704 7 unneback
cnt_gray_ce_bin
1705 6 unneback
    # ( .length(addr_width))
1706
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1707 7 unneback
cnt_gray_ce_bin
1708 6 unneback
    # (.length(addr_width))
1709
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1710 7 unneback
cnt_gray_ce_bin
1711 6 unneback
    # ( .length(addr_width))
1712
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1713 7 unneback
cnt_gray_ce_bin
1714 6 unneback
    # (.length(addr_width))
1715
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1716
// mux read or write adr to DPRAM
1717
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1718
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1719 11 unneback
vl_dpram_2r2w
1720 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1721
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1722
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1723 11 unneback
vl_fifo_cmp_async
1724 6 unneback
    # (.addr_width(addr_width))
1725
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1726 11 unneback
vl_fifo_cmp_async
1727 6 unneback
    # (.addr_width(addr_width))
1728
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1729
endmodule
1730 12 unneback
//////////////////////////////////////////////////////////////////////
1731
////                                                              ////
1732
////  Versatile library, wishbone stuff                           ////
1733
////                                                              ////
1734
////  Description                                                 ////
1735
////  Wishbone compliant modules                                  ////
1736
////                                                              ////
1737
////                                                              ////
1738
////  To Do:                                                      ////
1739
////   -                                                          ////
1740
////                                                              ////
1741
////  Author(s):                                                  ////
1742
////      - Michael Unneback, unneback@opencores.org              ////
1743
////        ORSoC AB                                              ////
1744
////                                                              ////
1745
//////////////////////////////////////////////////////////////////////
1746
////                                                              ////
1747
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1748
////                                                              ////
1749
//// This source file may be used and distributed without         ////
1750
//// restriction provided that this copyright statement is not    ////
1751
//// removed from the file and that any derivative work contains  ////
1752
//// the original copyright notice and the associated disclaimer. ////
1753
////                                                              ////
1754
//// This source file is free software; you can redistribute it   ////
1755
//// and/or modify it under the terms of the GNU Lesser General   ////
1756
//// Public License as published by the Free Software Foundation; ////
1757
//// either version 2.1 of the License, or (at your option) any   ////
1758
//// later version.                                               ////
1759
////                                                              ////
1760
//// This source is distributed in the hope that it will be       ////
1761
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1762
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1763
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1764
//// details.                                                     ////
1765
////                                                              ////
1766
//// You should have received a copy of the GNU Lesser General    ////
1767
//// Public License along with this source; if not, download it   ////
1768
//// from http://www.opencores.org/lgpl.shtml                     ////
1769
////                                                              ////
1770
//////////////////////////////////////////////////////////////////////
1771
// async wb3 - wb3 bridge
1772
`timescale 1ns/1ns
1773
module wb3wb3_bridge (
1774
        // wishbone slave side
1775
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1776
        // wishbone master side
1777
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1778
input [31:0] wbs_dat_i;
1779
input [31:2] wbs_adr_i;
1780
input [3:0]  wbs_sel_i;
1781
input [1:0]  wbs_bte_i;
1782
input [2:0]  wbs_cti_i;
1783
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1784
output [31:0] wbs_dat_o;
1785 14 unneback
output wbs_ack_o;
1786 12 unneback
input wbs_clk, wbs_rst;
1787
output [31:0] wbm_dat_o;
1788
output reg [31:2] wbm_adr_o;
1789
output [3:0]  wbm_sel_o;
1790
output reg [1:0]  wbm_bte_o;
1791
output reg [2:0]  wbm_cti_o;
1792 14 unneback
output reg wbm_we_o;
1793
output wbm_cyc_o;
1794 12 unneback
output wbm_stb_o;
1795
input [31:0]  wbm_dat_i;
1796
input wbm_ack_i;
1797
input wbm_clk, wbm_rst;
1798
parameter addr_width = 4;
1799
// bte
1800
parameter linear       = 2'b00;
1801
parameter wrap4        = 2'b01;
1802
parameter wrap8        = 2'b10;
1803
parameter wrap16       = 2'b11;
1804
// cti
1805
parameter classic      = 3'b000;
1806
parameter incburst     = 3'b010;
1807
parameter endofburst   = 3'b111;
1808
parameter wbs_adr  = 1'b0;
1809
parameter wbs_data = 1'b1;
1810
parameter wbm_adr0 = 2'b00;
1811
parameter wbm_adr1 = 2'b01;
1812
parameter wbm_data = 2'b10;
1813
reg [1:0] wbs_bte_reg;
1814
reg wbs;
1815
wire wbs_eoc_alert, wbm_eoc_alert;
1816
reg wbs_eoc, wbm_eoc;
1817
reg [1:0] wbm;
1818 14 unneback
wire [1:16] wbs_count, wbm_count;
1819 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1820
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1821
reg a_rd_reg;
1822
wire b_rd_adr, b_rd_data;
1823 14 unneback
wire b_rd_data_reg;
1824
wire [35:0] temp;
1825 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1826
always @ (posedge wbs_clk or posedge wbs_rst)
1827
if (wbs_rst)
1828
        wbs_eoc <= 1'b0;
1829
else
1830
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1831
                wbs_eoc <= wbs_bte_i==linear;
1832
        else if (wbs_eoc_alert & (a_rd | a_wr))
1833
                wbs_eoc <= 1'b1;
1834
cnt_shreg_ce_clear # ( .length(16))
1835
    cnt0 (
1836
        .cke(wbs_ack_o),
1837
        .clear(wbs_eoc),
1838
        .q(wbs_count),
1839
        .rst(wbs_rst),
1840
        .clk(wbs_clk));
1841
always @ (posedge wbs_clk or posedge wbs_rst)
1842
if (wbs_rst)
1843
        wbs <= wbs_adr;
1844
else
1845
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1846
                wbs <= wbs_data;
1847
        else if (wbs_eoc & wbs_ack_o)
1848
                wbs <= wbs_adr;
1849
// wbs FIFO
1850
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1851
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1852
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1853
              1'b0;
1854
assign a_rd = !a_fifo_empty;
1855
always @ (posedge wbs_clk or posedge wbs_rst)
1856
if (wbs_rst)
1857
        a_rd_reg <= 1'b0;
1858
else
1859
        a_rd_reg <= a_rd;
1860
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1861
assign wbs_dat_o = a_q[35:4];
1862
always @ (posedge wbs_clk or posedge wbs_rst)
1863
if (wbs_rst)
1864 13 unneback
        wbs_bte_reg <= 2'b00;
1865 12 unneback
else
1866 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1867 12 unneback
// wbm FIFO
1868
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1869
always @ (posedge wbm_clk or posedge wbm_rst)
1870
if (wbm_rst)
1871
        wbm_eoc <= 1'b0;
1872
else
1873
        if (wbm==wbm_adr0 & !b_fifo_empty)
1874
                wbm_eoc <= b_q[4:3] == linear;
1875
        else if (wbm_eoc_alert & wbm_ack_i)
1876
                wbm_eoc <= 1'b1;
1877
always @ (posedge wbm_clk or posedge wbm_rst)
1878
if (wbm_rst)
1879
        wbm <= wbm_adr0;
1880
else
1881
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1882
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1883
        (wbm==wbm_adr1 & !wbm_we_o) |
1884
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1885
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1886
assign b_d = {wbm_dat_i,4'b1111};
1887
assign b_wr = !wbm_we_o & wbm_ack_i;
1888
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1889
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1890
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1891
                   1'b0;
1892
assign b_rd = b_rd_adr | b_rd_data;
1893
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1894
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1895
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1896
cnt_shreg_ce_clear # ( .length(16))
1897
    cnt1 (
1898
        .cke(wbm_ack_i),
1899
        .clear(wbm_eoc),
1900
        .q(wbm_count),
1901
        .rst(wbm_rst),
1902
        .clk(wbm_clk));
1903
assign wbm_cyc_o = wbm==wbm_data;
1904
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
1905
                   (wbm==wbm_data) ? 1'b1 :
1906
                   1'b0;
1907
always @ (posedge wbm_clk or posedge wbm_rst)
1908
if (wbm_rst)
1909
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1910
else begin
1911
        if (wbm==wbm_adr0 & !b_fifo_empty)
1912
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1913
        else if (wbm_eoc_alert & wbm_ack_i)
1914
                wbm_cti_o <= endofburst;
1915
end
1916
//async_fifo_dw_simplex_top
1917
vl_fifo_2r2w_async_simplex
1918
# ( .data_width(36), .addr_width(addr_width))
1919
fifo (
1920
    // a side
1921
    .a_d(a_d),
1922
    .a_wr(a_wr),
1923
    .a_fifo_full(a_fifo_full),
1924
    .a_q(a_q),
1925
    .a_rd(a_rd),
1926
    .a_fifo_empty(a_fifo_empty),
1927
    .a_clk(wbs_clk),
1928
    .a_rst(wbs_rst),
1929
    // b side
1930
    .b_d(b_d),
1931
    .b_wr(b_wr),
1932
    .b_fifo_full(b_fifo_full),
1933
    .b_q(b_q),
1934
    .b_rd(b_rd),
1935
    .b_fifo_empty(b_fifo_empty),
1936
    .b_clk(wbm_clk),
1937
    .b_rst(wbm_rst)
1938
    );
1939
endmodule
1940 17 unneback
// WB ROM
1941
module wb_boot_rom (
1942
    wb_adr_i, wb_stb_i, wb_cyc_i,
1943
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
1944
//E2_ifndef BOOT_ROM
1945
//E2_define BOOT_ROM "boot_rom.v"
1946
//E2_endif
1947
    parameter addr_width = 5;
1948
   input [(addr_width+2)-1:2]       wb_adr_i;
1949
   input                            wb_stb_i;
1950
   input                            wb_cyc_i;
1951
   output reg [31:0]                 wb_dat_o;
1952
   output reg                       wb_ack_o;
1953
   input                            wb_clk;
1954
   input                            wb_rst;
1955
always @ (posedge wb_clk or posedge wb_rst)
1956
    if (wb_rst)
1957
        wb_dat_o <= 32'h15000000;
1958
    else
1959
         case (wb_adr_i)
1960
//E2_include `BOOT_ROM
1961
           /*
1962
            // Zero r0 and jump to 0x00000100
1963
 
1964
            1 : wb_dat_o <= 32'hA8200000;
1965
            2 : wb_dat_o <= 32'hA8C00100;
1966
            3 : wb_dat_o <= 32'h44003000;
1967
            4 : wb_dat_o <= 32'h15000000;
1968
            */
1969
           default:
1970
             wb_dat_o <= 32'h00000000;
1971
         endcase // case (wb_adr_i)
1972
always @ (posedge wb_clk or posedge wb_rst)
1973
    if (wb_rst)
1974
        wb_ack_o <= 1'b0;
1975
    else
1976
        wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
1977
endmodule

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