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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 6 unneback
 // ALTERA
47
 //ACTEL
48
// sync reset
49 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
50 6 unneback
// output active high global reset sync with two DFFs 
51
`timescale 1 ns/100 ps
52
module vl_sync_rst ( rst_n_i, rst_o, clk);
53
input rst_n_i, clk;
54
output rst_o;
55 18 unneback
reg [1:0] tmp;
56 6 unneback
always @ (posedge clk or negedge rst_n_i)
57
if (!rst_n_i)
58 17 unneback
        tmp <= 2'b11;
59 6 unneback
else
60 17 unneback
        tmp <= {1'b0,tmp[0]};
61
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
62 6 unneback
endmodule
63
// vl_pll
64
 //altera
65
 //actel
66
//////////////////////////////////////////////////////////////////////
67
////                                                              ////
68
////  Versatile library, registers                                ////
69
////                                                              ////
70
////  Description                                                 ////
71
////  Different type of registers                                 ////
72
////                                                              ////
73
////                                                              ////
74
////  To Do:                                                      ////
75
////   - add more different registers                             ////
76
////                                                              ////
77
////  Author(s):                                                  ////
78
////      - Michael Unneback, unneback@opencores.org              ////
79
////        ORSoC AB                                              ////
80
////                                                              ////
81
//////////////////////////////////////////////////////////////////////
82
////                                                              ////
83
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84
////                                                              ////
85
//// This source file may be used and distributed without         ////
86
//// restriction provided that this copyright statement is not    ////
87
//// removed from the file and that any derivative work contains  ////
88
//// the original copyright notice and the associated disclaimer. ////
89
////                                                              ////
90
//// This source file is free software; you can redistribute it   ////
91
//// and/or modify it under the terms of the GNU Lesser General   ////
92
//// Public License as published by the Free Software Foundation; ////
93
//// either version 2.1 of the License, or (at your option) any   ////
94
//// later version.                                               ////
95
////                                                              ////
96
//// This source is distributed in the hope that it will be       ////
97
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100
//// details.                                                     ////
101
////                                                              ////
102
//// You should have received a copy of the GNU Lesser General    ////
103
//// Public License along with this source; if not, download it   ////
104
//// from http://www.opencores.org/lgpl.shtml                     ////
105
////                                                              ////
106
//////////////////////////////////////////////////////////////////////
107 18 unneback
module vl_dff ( d, q, clk, rst);
108 6 unneback
        parameter width = 1;
109
        parameter reset_value = 0;
110
        input [width-1:0] d;
111
        input clk, rst;
112
        output reg [width-1:0] q;
113
        always @ (posedge clk or posedge rst)
114
        if (rst)
115
                q <= reset_value;
116
        else
117
                q <= d;
118
endmodule
119 18 unneback
module vl_dff_array ( d, q, clk, rst);
120 6 unneback
        parameter width = 1;
121
        parameter depth = 2;
122
        parameter reset_value = 1'b0;
123
        input [width-1:0] d;
124
        input clk, rst;
125
        output [width-1:0] q;
126
        reg  [0:depth-1] q_tmp [width-1:0];
127
        integer i;
128
        always @ (posedge clk or posedge rst)
129
        if (rst) begin
130
            for (i=0;i<depth;i=i+1)
131
                q_tmp[i] <= {width{reset_value}};
132
        end else begin
133
            q_tmp[0] <= d;
134
            for (i=1;i<depth;i=i+1)
135
                q_tmp[i] <= q_tmp[i-1];
136
        end
137
    assign q = q_tmp[depth-1];
138
endmodule
139 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
140 6 unneback
        parameter width = 1;
141
        parameter reset_value = 0;
142
        input [width-1:0] d;
143
        input ce, clk, rst;
144
        output reg [width-1:0] q;
145
        always @ (posedge clk or posedge rst)
146
        if (rst)
147
                q <= reset_value;
148
        else
149
                if (ce)
150
                        q <= d;
151
endmodule
152 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
153 8 unneback
        parameter width = 1;
154
        parameter reset_value = 0;
155
        input [width-1:0] d;
156 10 unneback
        input ce, clear, clk, rst;
157 8 unneback
        output reg [width-1:0] q;
158
        always @ (posedge clk or posedge rst)
159
        if (rst)
160
            q <= reset_value;
161
        else
162
            if (ce)
163
                if (clear)
164
                    q <= {width{1'b0}};
165
                else
166
                    q <= d;
167
endmodule
168 6 unneback
// megafunction wizard: %LPM_FF%
169
// GENERATION: STANDARD
170
// VERSION: WM1.0
171
// MODULE: lpm_ff 
172
// ============================================================
173
// File Name: dff_sr.v
174
// Megafunction Name(s):
175
//                      lpm_ff
176
//
177
// Simulation Library Files(s):
178
//                      lpm
179
// ============================================================
180
// ************************************************************
181
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
182
//
183
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
184
// ************************************************************
185
//Copyright (C) 1991-2010 Altera Corporation
186
//Your use of Altera Corporation's design tools, logic functions 
187
//and other software and tools, and its AMPP partner logic 
188
//functions, and any output files from any of the foregoing 
189
//(including device programming or simulation files), and any 
190
//associated documentation or information are expressly subject 
191
//to the terms and conditions of the Altera Program License 
192
//Subscription Agreement, Altera MegaCore Function License 
193
//Agreement, or other applicable license agreement, including, 
194
//without limitation, that your use is for the sole purpose of 
195
//programming logic devices manufactured by Altera and sold by 
196
//Altera or its authorized distributors.  Please refer to the 
197
//applicable agreement for further details.
198
// synopsys translate_off
199
`timescale 1 ps / 1 ps
200
// synopsys translate_on
201 18 unneback
module vl_dff_sr (
202 6 unneback
        aclr,
203
        aset,
204
        clock,
205
        data,
206
        q);
207
        input     aclr;
208
        input     aset;
209
        input     clock;
210
        input     data;
211
        output    q;
212
        wire [0:0] sub_wire0;
213
        wire [0:0] sub_wire1 = sub_wire0[0:0];
214
        wire  q = sub_wire1;
215
        wire  sub_wire2 = data;
216
        wire  sub_wire3 = sub_wire2;
217
        lpm_ff  lpm_ff_component (
218
                                .aclr (aclr),
219
                                .clock (clock),
220
                                .data (sub_wire3),
221
                                .aset (aset),
222
                                .q (sub_wire0)
223
                                // synopsys translate_off
224
                                ,
225
                                .aload (),
226
                                .enable (),
227
                                .sclr (),
228
                                .sload (),
229
                                .sset ()
230
                                // synopsys translate_on
231
                                );
232
        defparam
233
                lpm_ff_component.lpm_fftype = "DFF",
234
                lpm_ff_component.lpm_type = "LPM_FF",
235
                lpm_ff_component.lpm_width = 1;
236
endmodule
237
// ============================================================
238
// CNX file retrieval info
239
// ============================================================
240
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
241
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
242
// Retrieval info: PRIVATE: ASET NUMERIC "1"
243
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
244
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
245
// Retrieval info: PRIVATE: DFF NUMERIC "1"
246
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
247
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
248
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
249
// Retrieval info: PRIVATE: SSET NUMERIC "0"
250
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
251
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
252
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
253
// Retrieval info: PRIVATE: nBit NUMERIC "1"
254
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
255
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
256
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
257
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
258
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
259
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
260
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
261
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
262
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
263
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
264
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
265
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
266
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
267
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
268
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
269
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
270
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
271
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
272
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
273
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
274
// Retrieval info: LIB_FILE: lpm
275
// LATCH
276
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
277 18 unneback
module vl_latch ( d, le, q, clk);
278 6 unneback
input d, le;
279
output q;
280
input clk;
281
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
282
endmodule
283 18 unneback
module vl_shreg ( d, q, clk, rst);
284 17 unneback
parameter depth = 10;
285
input d;
286
output q;
287
input clk, rst;
288
reg [1:depth] dffs;
289
always @ (posedge clk or posedge rst)
290
if (rst)
291
    dffs <= {depth{1'b0}};
292
else
293
    dffs <= {d,dffs[1:depth-1]};
294
assign q = dffs[depth];
295
endmodule
296 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
297 17 unneback
parameter depth = 10;
298
input d, ce;
299
output q;
300
input clk, rst;
301
reg [1:depth] dffs;
302
always @ (posedge clk or posedge rst)
303
if (rst)
304
    dffs <= {depth{1'b0}};
305
else
306
    if (ce)
307
        dffs <= {d,dffs[1:depth-1]};
308
assign q = dffs[depth];
309
endmodule
310 18 unneback
module vl_delay ( d, q, clk, rst);
311 15 unneback
parameter depth = 10;
312
input d;
313
output q;
314
input clk, rst;
315
reg [1:depth] dffs;
316
always @ (posedge clk or posedge rst)
317
if (rst)
318
    dffs <= {depth{1'b0}};
319
else
320
    dffs <= {d,dffs[1:depth-1]};
321
assign q = dffs[depth];
322
endmodule
323 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
324 17 unneback
parameter depth = 10;
325
input d;
326
output q, emptyflag;
327
input clk, rst;
328
reg [1:depth] dffs;
329
always @ (posedge clk or posedge rst)
330
if (rst)
331
    dffs <= {depth{1'b0}};
332
else
333
    dffs <= {d,dffs[1:depth-1]};
334
assign q = dffs[depth];
335
assign emptyflag = !(|dffs);
336
endmodule
337 6 unneback
//////////////////////////////////////////////////////////////////////
338
////                                                              ////
339 18 unneback
////  Logic functions                                             ////
340
////                                                              ////
341
////  Description                                                 ////
342
////  Logic functions such as multiplexers                        ////
343
////                                                              ////
344
////                                                              ////
345
////  To Do:                                                      ////
346
////   -                                                          ////
347
////                                                              ////
348
////  Author(s):                                                  ////
349
////      - Michael Unneback, unneback@opencores.org              ////
350
////        ORSoC AB                                              ////
351
////                                                              ////
352
//////////////////////////////////////////////////////////////////////
353
////                                                              ////
354
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
355
////                                                              ////
356
//// This source file may be used and distributed without         ////
357
//// restriction provided that this copyright statement is not    ////
358
//// removed from the file and that any derivative work contains  ////
359
//// the original copyright notice and the associated disclaimer. ////
360
////                                                              ////
361
//// This source file is free software; you can redistribute it   ////
362
//// and/or modify it under the terms of the GNU Lesser General   ////
363
//// Public License as published by the Free Software Foundation; ////
364
//// either version 2.1 of the License, or (at your option) any   ////
365
//// later version.                                               ////
366
////                                                              ////
367
//// This source is distributed in the hope that it will be       ////
368
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
369
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
370
//// PURPOSE.  See the GNU Lesser General Public License for more ////
371
//// details.                                                     ////
372
////                                                              ////
373
//// You should have received a copy of the GNU Lesser General    ////
374
//// Public License along with this source; if not, download it   ////
375
//// from http://www.opencores.org/lgpl.shtml                     ////
376
////                                                              ////
377
//////////////////////////////////////////////////////////////////////
378
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
379
parameter width = 32;
380
parameter nr_of_ports = 4;
381
input [width-1:0] a3, a2, a1, a0;
382
input [nr_of_ports-1:0] sel;
383 22 unneback
output [width-1:0] dout;
384 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
385 18 unneback
integer i;
386
// and
387
assign tmp[0] = {width{sel[0]}} & a0;
388
assign tmp[1] = {width{sel[1]}} & a1;
389
assign tmp[2] = {width{sel[2]}} & a2;
390
assign tmp[3] = {width{sel[3]}} & a3;
391
// or
392
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
393
endmodule
394
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
395
parameter width = 32;
396
parameter nr_of_ports = 5;
397
input [width-1:0] a4, a3, a2, a1, a0;
398
input [nr_of_ports-1:0] sel;
399 22 unneback
output [width-1:0] dout;
400 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
401 18 unneback
integer i;
402
// and
403
assign tmp[0] = {width{sel[0]}} & a0;
404
assign tmp[1] = {width{sel[1]}} & a1;
405
assign tmp[2] = {width{sel[2]}} & a2;
406
assign tmp[3] = {width{sel[3]}} & a3;
407
assign tmp[4] = {width{sel[4]}} & a4;
408
// or
409
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
410
endmodule
411
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
412
parameter width = 32;
413
parameter nr_of_ports = 6;
414
input [width-1:0] a5, a4, a3, a2, a1, a0;
415
input [nr_of_ports-1:0] sel;
416 22 unneback
output [width-1:0] dout;
417 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
418 18 unneback
integer i;
419
// and
420
assign tmp[0] = {width{sel[0]}} & a0;
421
assign tmp[1] = {width{sel[1]}} & a1;
422
assign tmp[2] = {width{sel[2]}} & a2;
423
assign tmp[3] = {width{sel[3]}} & a3;
424
assign tmp[4] = {width{sel[4]}} & a4;
425
assign tmp[5] = {width{sel[5]}} & a5;
426
// or
427
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
428
endmodule
429
//////////////////////////////////////////////////////////////////////
430
////                                                              ////
431 6 unneback
////  Versatile counter                                           ////
432
////                                                              ////
433
////  Description                                                 ////
434
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
435
////  counter                                                     ////
436
////                                                              ////
437
////  To Do:                                                      ////
438
////   - add LFSR with more taps                                  ////
439
////                                                              ////
440
////  Author(s):                                                  ////
441
////      - Michael Unneback, unneback@opencores.org              ////
442
////        ORSoC AB                                              ////
443
////                                                              ////
444
//////////////////////////////////////////////////////////////////////
445
////                                                              ////
446
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
447
////                                                              ////
448
//// This source file may be used and distributed without         ////
449
//// restriction provided that this copyright statement is not    ////
450
//// removed from the file and that any derivative work contains  ////
451
//// the original copyright notice and the associated disclaimer. ////
452
////                                                              ////
453
//// This source file is free software; you can redistribute it   ////
454
//// and/or modify it under the terms of the GNU Lesser General   ////
455
//// Public License as published by the Free Software Foundation; ////
456
//// either version 2.1 of the License, or (at your option) any   ////
457
//// later version.                                               ////
458
////                                                              ////
459
//// This source is distributed in the hope that it will be       ////
460
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
461
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
462
//// PURPOSE.  See the GNU Lesser General Public License for more ////
463
//// details.                                                     ////
464
////                                                              ////
465
//// You should have received a copy of the GNU Lesser General    ////
466
//// Public License along with this source; if not, download it   ////
467
//// from http://www.opencores.org/lgpl.shtml                     ////
468
////                                                              ////
469
//////////////////////////////////////////////////////////////////////
470
// binary counter
471 22 unneback
module vl_cnt_bin ( q, rst, clk);
472
   parameter length = 4;
473
   output [length:1] q;
474
   input rst;
475
   input clk;
476
   parameter clear_value = 0;
477
   parameter set_value = 1;
478
   parameter wrap_value = 0;
479
   parameter level1_value = 15;
480
   reg  [length:1] qi;
481
   wire [length:1] q_next;
482
   assign q_next = qi + {{length-1{1'b0}},1'b1};
483
   always @ (posedge clk or posedge rst)
484
     if (rst)
485
       qi <= {length{1'b0}};
486
     else
487
       qi <= q_next;
488
   assign q = qi;
489
endmodule
490
//////////////////////////////////////////////////////////////////////
491
////                                                              ////
492
////  Versatile counter                                           ////
493
////                                                              ////
494
////  Description                                                 ////
495
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
496
////  counter                                                     ////
497
////                                                              ////
498
////  To Do:                                                      ////
499
////   - add LFSR with more taps                                  ////
500
////                                                              ////
501
////  Author(s):                                                  ////
502
////      - Michael Unneback, unneback@opencores.org              ////
503
////        ORSoC AB                                              ////
504
////                                                              ////
505
//////////////////////////////////////////////////////////////////////
506
////                                                              ////
507
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
508
////                                                              ////
509
//// This source file may be used and distributed without         ////
510
//// restriction provided that this copyright statement is not    ////
511
//// removed from the file and that any derivative work contains  ////
512
//// the original copyright notice and the associated disclaimer. ////
513
////                                                              ////
514
//// This source file is free software; you can redistribute it   ////
515
//// and/or modify it under the terms of the GNU Lesser General   ////
516
//// Public License as published by the Free Software Foundation; ////
517
//// either version 2.1 of the License, or (at your option) any   ////
518
//// later version.                                               ////
519
////                                                              ////
520
//// This source is distributed in the hope that it will be       ////
521
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
522
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
523
//// PURPOSE.  See the GNU Lesser General Public License for more ////
524
//// details.                                                     ////
525
////                                                              ////
526
//// You should have received a copy of the GNU Lesser General    ////
527
//// Public License along with this source; if not, download it   ////
528
//// from http://www.opencores.org/lgpl.shtml                     ////
529
////                                                              ////
530
//////////////////////////////////////////////////////////////////////
531
// binary counter
532
module vl_cnt_bin_clear ( clear, q, rst, clk);
533
   parameter length = 4;
534
   input clear;
535
   output [length:1] q;
536
   input rst;
537
   input clk;
538
   parameter clear_value = 0;
539
   parameter set_value = 1;
540
   parameter wrap_value = 0;
541
   parameter level1_value = 15;
542
   reg  [length:1] qi;
543
   wire [length:1] q_next;
544
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
545
   always @ (posedge clk or posedge rst)
546
     if (rst)
547
       qi <= {length{1'b0}};
548
     else
549
       qi <= q_next;
550
   assign q = qi;
551
endmodule
552
//////////////////////////////////////////////////////////////////////
553
////                                                              ////
554
////  Versatile counter                                           ////
555
////                                                              ////
556
////  Description                                                 ////
557
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
558
////  counter                                                     ////
559
////                                                              ////
560
////  To Do:                                                      ////
561
////   - add LFSR with more taps                                  ////
562
////                                                              ////
563
////  Author(s):                                                  ////
564
////      - Michael Unneback, unneback@opencores.org              ////
565
////        ORSoC AB                                              ////
566
////                                                              ////
567
//////////////////////////////////////////////////////////////////////
568
////                                                              ////
569
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
570
////                                                              ////
571
//// This source file may be used and distributed without         ////
572
//// restriction provided that this copyright statement is not    ////
573
//// removed from the file and that any derivative work contains  ////
574
//// the original copyright notice and the associated disclaimer. ////
575
////                                                              ////
576
//// This source file is free software; you can redistribute it   ////
577
//// and/or modify it under the terms of the GNU Lesser General   ////
578
//// Public License as published by the Free Software Foundation; ////
579
//// either version 2.1 of the License, or (at your option) any   ////
580
//// later version.                                               ////
581
////                                                              ////
582
//// This source is distributed in the hope that it will be       ////
583
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
584
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
585
//// PURPOSE.  See the GNU Lesser General Public License for more ////
586
//// details.                                                     ////
587
////                                                              ////
588
//// You should have received a copy of the GNU Lesser General    ////
589
//// Public License along with this source; if not, download it   ////
590
//// from http://www.opencores.org/lgpl.shtml                     ////
591
////                                                              ////
592
//////////////////////////////////////////////////////////////////////
593
// binary counter
594 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
595 6 unneback
   parameter length = 4;
596
   input cke;
597
   output [length:1] q;
598
   input rst;
599
   input clk;
600
   parameter clear_value = 0;
601
   parameter set_value = 1;
602
   parameter wrap_value = 0;
603
   parameter level1_value = 15;
604
   reg  [length:1] qi;
605
   wire [length:1] q_next;
606
   assign q_next = qi + {{length-1{1'b0}},1'b1};
607
   always @ (posedge clk or posedge rst)
608
     if (rst)
609
       qi <= {length{1'b0}};
610
     else
611
     if (cke)
612
       qi <= q_next;
613
   assign q = qi;
614
endmodule
615
//////////////////////////////////////////////////////////////////////
616
////                                                              ////
617
////  Versatile counter                                           ////
618
////                                                              ////
619
////  Description                                                 ////
620
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
621
////  counter                                                     ////
622
////                                                              ////
623
////  To Do:                                                      ////
624
////   - add LFSR with more taps                                  ////
625
////                                                              ////
626
////  Author(s):                                                  ////
627
////      - Michael Unneback, unneback@opencores.org              ////
628
////        ORSoC AB                                              ////
629
////                                                              ////
630
//////////////////////////////////////////////////////////////////////
631
////                                                              ////
632
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
633
////                                                              ////
634
//// This source file may be used and distributed without         ////
635
//// restriction provided that this copyright statement is not    ////
636
//// removed from the file and that any derivative work contains  ////
637
//// the original copyright notice and the associated disclaimer. ////
638
////                                                              ////
639
//// This source file is free software; you can redistribute it   ////
640
//// and/or modify it under the terms of the GNU Lesser General   ////
641
//// Public License as published by the Free Software Foundation; ////
642
//// either version 2.1 of the License, or (at your option) any   ////
643
//// later version.                                               ////
644
////                                                              ////
645
//// This source is distributed in the hope that it will be       ////
646
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
647
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
648
//// PURPOSE.  See the GNU Lesser General Public License for more ////
649
//// details.                                                     ////
650
////                                                              ////
651
//// You should have received a copy of the GNU Lesser General    ////
652
//// Public License along with this source; if not, download it   ////
653
//// from http://www.opencores.org/lgpl.shtml                     ////
654
////                                                              ////
655
//////////////////////////////////////////////////////////////////////
656
// binary counter
657 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
658 6 unneback
   parameter length = 4;
659
   input clear;
660
   input cke;
661
   output [length:1] q;
662
   input rst;
663
   input clk;
664
   parameter clear_value = 0;
665
   parameter set_value = 1;
666
   parameter wrap_value = 0;
667
   parameter level1_value = 15;
668
   reg  [length:1] qi;
669
   wire [length:1] q_next;
670
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
671
   always @ (posedge clk or posedge rst)
672
     if (rst)
673
       qi <= {length{1'b0}};
674
     else
675
     if (cke)
676
       qi <= q_next;
677
   assign q = qi;
678
endmodule
679
//////////////////////////////////////////////////////////////////////
680
////                                                              ////
681
////  Versatile counter                                           ////
682
////                                                              ////
683
////  Description                                                 ////
684
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
685
////  counter                                                     ////
686
////                                                              ////
687
////  To Do:                                                      ////
688
////   - add LFSR with more taps                                  ////
689
////                                                              ////
690
////  Author(s):                                                  ////
691
////      - Michael Unneback, unneback@opencores.org              ////
692
////        ORSoC AB                                              ////
693
////                                                              ////
694
//////////////////////////////////////////////////////////////////////
695
////                                                              ////
696
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
697
////                                                              ////
698
//// This source file may be used and distributed without         ////
699
//// restriction provided that this copyright statement is not    ////
700
//// removed from the file and that any derivative work contains  ////
701
//// the original copyright notice and the associated disclaimer. ////
702
////                                                              ////
703
//// This source file is free software; you can redistribute it   ////
704
//// and/or modify it under the terms of the GNU Lesser General   ////
705
//// Public License as published by the Free Software Foundation; ////
706
//// either version 2.1 of the License, or (at your option) any   ////
707
//// later version.                                               ////
708
////                                                              ////
709
//// This source is distributed in the hope that it will be       ////
710
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
711
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
712
//// PURPOSE.  See the GNU Lesser General Public License for more ////
713
//// details.                                                     ////
714
////                                                              ////
715
//// You should have received a copy of the GNU Lesser General    ////
716
//// Public License along with this source; if not, download it   ////
717
//// from http://www.opencores.org/lgpl.shtml                     ////
718
////                                                              ////
719
//////////////////////////////////////////////////////////////////////
720
// binary counter
721 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
722 6 unneback
   parameter length = 4;
723
   input clear;
724
   input set;
725
   input cke;
726
   input rew;
727
   output [length:1] q;
728
   input rst;
729
   input clk;
730
   parameter clear_value = 0;
731
   parameter set_value = 1;
732
   parameter wrap_value = 0;
733
   parameter level1_value = 15;
734
   reg  [length:1] qi;
735
   wire  [length:1] q_next, q_next_fw, q_next_rew;
736
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
737
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
738
   assign q_next = rew ? q_next_rew : q_next_fw;
739
   always @ (posedge clk or posedge rst)
740
     if (rst)
741
       qi <= {length{1'b0}};
742
     else
743
     if (cke)
744
       qi <= q_next;
745
   assign q = qi;
746
endmodule
747
//////////////////////////////////////////////////////////////////////
748
////                                                              ////
749
////  Versatile counter                                           ////
750
////                                                              ////
751
////  Description                                                 ////
752
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
753
////  counter                                                     ////
754
////                                                              ////
755
////  To Do:                                                      ////
756
////   - add LFSR with more taps                                  ////
757
////                                                              ////
758
////  Author(s):                                                  ////
759
////      - Michael Unneback, unneback@opencores.org              ////
760
////        ORSoC AB                                              ////
761
////                                                              ////
762
//////////////////////////////////////////////////////////////////////
763
////                                                              ////
764
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
765
////                                                              ////
766
//// This source file may be used and distributed without         ////
767
//// restriction provided that this copyright statement is not    ////
768
//// removed from the file and that any derivative work contains  ////
769
//// the original copyright notice and the associated disclaimer. ////
770
////                                                              ////
771
//// This source file is free software; you can redistribute it   ////
772
//// and/or modify it under the terms of the GNU Lesser General   ////
773
//// Public License as published by the Free Software Foundation; ////
774
//// either version 2.1 of the License, or (at your option) any   ////
775
//// later version.                                               ////
776
////                                                              ////
777
//// This source is distributed in the hope that it will be       ////
778
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
779
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
780
//// PURPOSE.  See the GNU Lesser General Public License for more ////
781
//// details.                                                     ////
782
////                                                              ////
783
//// You should have received a copy of the GNU Lesser General    ////
784
//// Public License along with this source; if not, download it   ////
785
//// from http://www.opencores.org/lgpl.shtml                     ////
786
////                                                              ////
787
//////////////////////////////////////////////////////////////////////
788
// binary counter
789 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
790 6 unneback
   parameter length = 4;
791
   input cke;
792
   input rew;
793
   output reg level1;
794
   input rst;
795
   input clk;
796
   parameter clear_value = 0;
797
   parameter set_value = 1;
798
   parameter wrap_value = 1;
799
   parameter level1_value = 15;
800
   reg  [length:1] qi;
801
   wire  [length:1] q_next, q_next_fw, q_next_rew;
802
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
803
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
804
   assign q_next = rew ? q_next_rew : q_next_fw;
805
   always @ (posedge clk or posedge rst)
806
     if (rst)
807
       qi <= {length{1'b0}};
808
     else
809
     if (cke)
810
       qi <= q_next;
811
    always @ (posedge clk or posedge rst)
812
    if (rst)
813
        level1 <= 1'b0;
814
    else
815
    if (cke)
816
    if (q_next == level1_value)
817
        level1 <= 1'b1;
818
    else if (qi == level1_value & rew)
819
        level1 <= 1'b0;
820
endmodule
821
//////////////////////////////////////////////////////////////////////
822
////                                                              ////
823
////  Versatile counter                                           ////
824
////                                                              ////
825
////  Description                                                 ////
826
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
827
////  counter                                                     ////
828
////                                                              ////
829
////  To Do:                                                      ////
830
////   - add LFSR with more taps                                  ////
831
////                                                              ////
832
////  Author(s):                                                  ////
833
////      - Michael Unneback, unneback@opencores.org              ////
834
////        ORSoC AB                                              ////
835
////                                                              ////
836
//////////////////////////////////////////////////////////////////////
837
////                                                              ////
838
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
839
////                                                              ////
840
//// This source file may be used and distributed without         ////
841
//// restriction provided that this copyright statement is not    ////
842
//// removed from the file and that any derivative work contains  ////
843
//// the original copyright notice and the associated disclaimer. ////
844
////                                                              ////
845
//// This source file is free software; you can redistribute it   ////
846
//// and/or modify it under the terms of the GNU Lesser General   ////
847
//// Public License as published by the Free Software Foundation; ////
848
//// either version 2.1 of the License, or (at your option) any   ////
849
//// later version.                                               ////
850
////                                                              ////
851
//// This source is distributed in the hope that it will be       ////
852
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
853
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
854
//// PURPOSE.  See the GNU Lesser General Public License for more ////
855
//// details.                                                     ////
856
////                                                              ////
857
//// You should have received a copy of the GNU Lesser General    ////
858
//// Public License along with this source; if not, download it   ////
859
//// from http://www.opencores.org/lgpl.shtml                     ////
860
////                                                              ////
861
//////////////////////////////////////////////////////////////////////
862
// LFSR counter
863 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
864 6 unneback
   parameter length = 4;
865
   output reg zq;
866
   input rst;
867
   input clk;
868
   parameter clear_value = 0;
869
   parameter set_value = 1;
870
   parameter wrap_value = 8;
871
   parameter level1_value = 15;
872
   reg  [length:1] qi;
873
   reg lfsr_fb;
874
   wire [length:1] q_next;
875
   reg [32:1] polynom;
876
   integer i;
877
   always @ (qi)
878
   begin
879
        case (length)
880
         2: polynom = 32'b11;                               // 0x3
881
         3: polynom = 32'b110;                              // 0x6
882
         4: polynom = 32'b1100;                             // 0xC
883
         5: polynom = 32'b10100;                            // 0x14
884
         6: polynom = 32'b110000;                           // 0x30
885
         7: polynom = 32'b1100000;                          // 0x60
886
         8: polynom = 32'b10111000;                         // 0xb8
887
         9: polynom = 32'b100010000;                        // 0x110
888
        10: polynom = 32'b1001000000;                       // 0x240
889
        11: polynom = 32'b10100000000;                      // 0x500
890
        12: polynom = 32'b100000101001;                     // 0x829
891
        13: polynom = 32'b1000000001100;                    // 0x100C
892
        14: polynom = 32'b10000000010101;                   // 0x2015
893
        15: polynom = 32'b110000000000000;                  // 0x6000
894
        16: polynom = 32'b1101000000001000;                 // 0xD008
895
        17: polynom = 32'b10010000000000000;                // 0x12000
896
        18: polynom = 32'b100000010000000000;               // 0x20400
897
        19: polynom = 32'b1000000000000100011;              // 0x40023
898
        20: polynom = 32'b10000010000000000000;             // 0x82000
899
        21: polynom = 32'b101000000000000000000;            // 0x140000
900
        22: polynom = 32'b1100000000000000000000;           // 0x300000
901
        23: polynom = 32'b10000100000000000000000;          // 0x420000
902
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
903
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
904
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
905
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
906
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
907
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
908
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
909
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
910
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
911
        default: polynom = 32'b0;
912
        endcase
913
        lfsr_fb = qi[length];
914
        for (i=length-1; i>=1; i=i-1) begin
915
            if (polynom[i])
916
                lfsr_fb = lfsr_fb  ~^ qi[i];
917
        end
918
    end
919
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
920
   always @ (posedge clk or posedge rst)
921
     if (rst)
922
       qi <= {length{1'b0}};
923
     else
924
       qi <= q_next;
925
   always @ (posedge clk or posedge rst)
926
     if (rst)
927
       zq <= 1'b1;
928
     else
929
       zq <= q_next == {length{1'b0}};
930
endmodule
931
//////////////////////////////////////////////////////////////////////
932
////                                                              ////
933
////  Versatile counter                                           ////
934
////                                                              ////
935
////  Description                                                 ////
936
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
937
////  counter                                                     ////
938
////                                                              ////
939
////  To Do:                                                      ////
940
////   - add LFSR with more taps                                  ////
941
////                                                              ////
942
////  Author(s):                                                  ////
943
////      - Michael Unneback, unneback@opencores.org              ////
944
////        ORSoC AB                                              ////
945
////                                                              ////
946
//////////////////////////////////////////////////////////////////////
947
////                                                              ////
948
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
949
////                                                              ////
950
//// This source file may be used and distributed without         ////
951
//// restriction provided that this copyright statement is not    ////
952
//// removed from the file and that any derivative work contains  ////
953
//// the original copyright notice and the associated disclaimer. ////
954
////                                                              ////
955
//// This source file is free software; you can redistribute it   ////
956
//// and/or modify it under the terms of the GNU Lesser General   ////
957
//// Public License as published by the Free Software Foundation; ////
958
//// either version 2.1 of the License, or (at your option) any   ////
959
//// later version.                                               ////
960
////                                                              ////
961
//// This source is distributed in the hope that it will be       ////
962
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
963
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
964
//// PURPOSE.  See the GNU Lesser General Public License for more ////
965
//// details.                                                     ////
966
////                                                              ////
967
//// You should have received a copy of the GNU Lesser General    ////
968
//// Public License along with this source; if not, download it   ////
969
//// from http://www.opencores.org/lgpl.shtml                     ////
970
////                                                              ////
971
//////////////////////////////////////////////////////////////////////
972
// LFSR counter
973 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
974 6 unneback
   parameter length = 4;
975
   input cke;
976
   output reg zq;
977
   input rst;
978
   input clk;
979
   parameter clear_value = 0;
980
   parameter set_value = 1;
981
   parameter wrap_value = 8;
982
   parameter level1_value = 15;
983
   reg  [length:1] qi;
984
   reg lfsr_fb;
985
   wire [length:1] q_next;
986
   reg [32:1] polynom;
987
   integer i;
988
   always @ (qi)
989
   begin
990
        case (length)
991
         2: polynom = 32'b11;                               // 0x3
992
         3: polynom = 32'b110;                              // 0x6
993
         4: polynom = 32'b1100;                             // 0xC
994
         5: polynom = 32'b10100;                            // 0x14
995
         6: polynom = 32'b110000;                           // 0x30
996
         7: polynom = 32'b1100000;                          // 0x60
997
         8: polynom = 32'b10111000;                         // 0xb8
998
         9: polynom = 32'b100010000;                        // 0x110
999
        10: polynom = 32'b1001000000;                       // 0x240
1000
        11: polynom = 32'b10100000000;                      // 0x500
1001
        12: polynom = 32'b100000101001;                     // 0x829
1002
        13: polynom = 32'b1000000001100;                    // 0x100C
1003
        14: polynom = 32'b10000000010101;                   // 0x2015
1004
        15: polynom = 32'b110000000000000;                  // 0x6000
1005
        16: polynom = 32'b1101000000001000;                 // 0xD008
1006
        17: polynom = 32'b10010000000000000;                // 0x12000
1007
        18: polynom = 32'b100000010000000000;               // 0x20400
1008
        19: polynom = 32'b1000000000000100011;              // 0x40023
1009
        20: polynom = 32'b10000010000000000000;             // 0x82000
1010
        21: polynom = 32'b101000000000000000000;            // 0x140000
1011
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1012
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1013
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1014
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1015
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1016
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1017
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1018
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1019
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1020
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1021
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1022
        default: polynom = 32'b0;
1023
        endcase
1024
        lfsr_fb = qi[length];
1025
        for (i=length-1; i>=1; i=i-1) begin
1026
            if (polynom[i])
1027
                lfsr_fb = lfsr_fb  ~^ qi[i];
1028
        end
1029
    end
1030
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1031
   always @ (posedge clk or posedge rst)
1032
     if (rst)
1033
       qi <= {length{1'b0}};
1034
     else
1035
     if (cke)
1036
       qi <= q_next;
1037
   always @ (posedge clk or posedge rst)
1038
     if (rst)
1039
       zq <= 1'b1;
1040
     else
1041
     if (cke)
1042
       zq <= q_next == {length{1'b0}};
1043
endmodule
1044
//////////////////////////////////////////////////////////////////////
1045
////                                                              ////
1046
////  Versatile counter                                           ////
1047
////                                                              ////
1048
////  Description                                                 ////
1049
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1050
////  counter                                                     ////
1051
////                                                              ////
1052
////  To Do:                                                      ////
1053
////   - add LFSR with more taps                                  ////
1054
////                                                              ////
1055
////  Author(s):                                                  ////
1056
////      - Michael Unneback, unneback@opencores.org              ////
1057
////        ORSoC AB                                              ////
1058
////                                                              ////
1059
//////////////////////////////////////////////////////////////////////
1060
////                                                              ////
1061
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1062
////                                                              ////
1063
//// This source file may be used and distributed without         ////
1064
//// restriction provided that this copyright statement is not    ////
1065
//// removed from the file and that any derivative work contains  ////
1066
//// the original copyright notice and the associated disclaimer. ////
1067
////                                                              ////
1068
//// This source file is free software; you can redistribute it   ////
1069
//// and/or modify it under the terms of the GNU Lesser General   ////
1070
//// Public License as published by the Free Software Foundation; ////
1071
//// either version 2.1 of the License, or (at your option) any   ////
1072
//// later version.                                               ////
1073
////                                                              ////
1074
//// This source is distributed in the hope that it will be       ////
1075
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1076
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1077
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1078
//// details.                                                     ////
1079
////                                                              ////
1080
//// You should have received a copy of the GNU Lesser General    ////
1081
//// Public License along with this source; if not, download it   ////
1082
//// from http://www.opencores.org/lgpl.shtml                     ////
1083
////                                                              ////
1084
//////////////////////////////////////////////////////////////////////
1085
// LFSR counter
1086 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1087
   parameter length = 4;
1088
   input cke;
1089
   output [length:1] q;
1090
   output reg zq;
1091
   input rst;
1092
   input clk;
1093
   parameter clear_value = 0;
1094
   parameter set_value = 1;
1095
   parameter wrap_value = 8;
1096
   parameter level1_value = 15;
1097
   reg  [length:1] qi;
1098
   reg lfsr_fb;
1099
   wire [length:1] q_next;
1100
   reg [32:1] polynom;
1101
   integer i;
1102
   always @ (qi)
1103
   begin
1104
        case (length)
1105
         2: polynom = 32'b11;                               // 0x3
1106
         3: polynom = 32'b110;                              // 0x6
1107
         4: polynom = 32'b1100;                             // 0xC
1108
         5: polynom = 32'b10100;                            // 0x14
1109
         6: polynom = 32'b110000;                           // 0x30
1110
         7: polynom = 32'b1100000;                          // 0x60
1111
         8: polynom = 32'b10111000;                         // 0xb8
1112
         9: polynom = 32'b100010000;                        // 0x110
1113
        10: polynom = 32'b1001000000;                       // 0x240
1114
        11: polynom = 32'b10100000000;                      // 0x500
1115
        12: polynom = 32'b100000101001;                     // 0x829
1116
        13: polynom = 32'b1000000001100;                    // 0x100C
1117
        14: polynom = 32'b10000000010101;                   // 0x2015
1118
        15: polynom = 32'b110000000000000;                  // 0x6000
1119
        16: polynom = 32'b1101000000001000;                 // 0xD008
1120
        17: polynom = 32'b10010000000000000;                // 0x12000
1121
        18: polynom = 32'b100000010000000000;               // 0x20400
1122
        19: polynom = 32'b1000000000000100011;              // 0x40023
1123
        20: polynom = 32'b10000010000000000000;             // 0x82000
1124
        21: polynom = 32'b101000000000000000000;            // 0x140000
1125
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1126
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1127
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1128
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1129
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1130
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1131
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1132
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1133
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1134
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1135
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1136
        default: polynom = 32'b0;
1137
        endcase
1138
        lfsr_fb = qi[length];
1139
        for (i=length-1; i>=1; i=i-1) begin
1140
            if (polynom[i])
1141
                lfsr_fb = lfsr_fb  ~^ qi[i];
1142
        end
1143
    end
1144
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1145
   always @ (posedge clk or posedge rst)
1146
     if (rst)
1147
       qi <= {length{1'b0}};
1148
     else
1149
     if (cke)
1150
       qi <= q_next;
1151
   assign q = qi;
1152
   always @ (posedge clk or posedge rst)
1153
     if (rst)
1154
       zq <= 1'b1;
1155
     else
1156
     if (cke)
1157
       zq <= q_next == {length{1'b0}};
1158
endmodule
1159
//////////////////////////////////////////////////////////////////////
1160
////                                                              ////
1161
////  Versatile counter                                           ////
1162
////                                                              ////
1163
////  Description                                                 ////
1164
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1165
////  counter                                                     ////
1166
////                                                              ////
1167
////  To Do:                                                      ////
1168
////   - add LFSR with more taps                                  ////
1169
////                                                              ////
1170
////  Author(s):                                                  ////
1171
////      - Michael Unneback, unneback@opencores.org              ////
1172
////        ORSoC AB                                              ////
1173
////                                                              ////
1174
//////////////////////////////////////////////////////////////////////
1175
////                                                              ////
1176
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1177
////                                                              ////
1178
//// This source file may be used and distributed without         ////
1179
//// restriction provided that this copyright statement is not    ////
1180
//// removed from the file and that any derivative work contains  ////
1181
//// the original copyright notice and the associated disclaimer. ////
1182
////                                                              ////
1183
//// This source file is free software; you can redistribute it   ////
1184
//// and/or modify it under the terms of the GNU Lesser General   ////
1185
//// Public License as published by the Free Software Foundation; ////
1186
//// either version 2.1 of the License, or (at your option) any   ////
1187
//// later version.                                               ////
1188
////                                                              ////
1189
//// This source is distributed in the hope that it will be       ////
1190
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1191
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1192
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1193
//// details.                                                     ////
1194
////                                                              ////
1195
//// You should have received a copy of the GNU Lesser General    ////
1196
//// Public License along with this source; if not, download it   ////
1197
//// from http://www.opencores.org/lgpl.shtml                     ////
1198
////                                                              ////
1199
//////////////////////////////////////////////////////////////////////
1200
// LFSR counter
1201 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1202 6 unneback
   parameter length = 4;
1203
   input cke;
1204
   input rew;
1205
   output reg level1;
1206
   input rst;
1207
   input clk;
1208
   parameter clear_value = 0;
1209
   parameter set_value = 1;
1210
   parameter wrap_value = 8;
1211
   parameter level1_value = 15;
1212
   reg  [length:1] qi;
1213
   reg lfsr_fb, lfsr_fb_rew;
1214
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1215
   reg [32:1] polynom_rew;
1216
   integer j;
1217
   reg [32:1] polynom;
1218
   integer i;
1219
   always @ (qi)
1220
   begin
1221
        case (length)
1222
         2: polynom = 32'b11;                               // 0x3
1223
         3: polynom = 32'b110;                              // 0x6
1224
         4: polynom = 32'b1100;                             // 0xC
1225
         5: polynom = 32'b10100;                            // 0x14
1226
         6: polynom = 32'b110000;                           // 0x30
1227
         7: polynom = 32'b1100000;                          // 0x60
1228
         8: polynom = 32'b10111000;                         // 0xb8
1229
         9: polynom = 32'b100010000;                        // 0x110
1230
        10: polynom = 32'b1001000000;                       // 0x240
1231
        11: polynom = 32'b10100000000;                      // 0x500
1232
        12: polynom = 32'b100000101001;                     // 0x829
1233
        13: polynom = 32'b1000000001100;                    // 0x100C
1234
        14: polynom = 32'b10000000010101;                   // 0x2015
1235
        15: polynom = 32'b110000000000000;                  // 0x6000
1236
        16: polynom = 32'b1101000000001000;                 // 0xD008
1237
        17: polynom = 32'b10010000000000000;                // 0x12000
1238
        18: polynom = 32'b100000010000000000;               // 0x20400
1239
        19: polynom = 32'b1000000000000100011;              // 0x40023
1240
        20: polynom = 32'b10000010000000000000;             // 0x82000
1241
        21: polynom = 32'b101000000000000000000;            // 0x140000
1242
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1243
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1244
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1245
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1246
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1247
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1248
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1249
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1250
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1251
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1252
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1253
        default: polynom = 32'b0;
1254
        endcase
1255
        lfsr_fb = qi[length];
1256
        for (i=length-1; i>=1; i=i-1) begin
1257
            if (polynom[i])
1258
                lfsr_fb = lfsr_fb  ~^ qi[i];
1259
        end
1260
    end
1261
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1262
   always @ (qi)
1263
   begin
1264
        case (length)
1265
         2: polynom_rew = 32'b11;
1266
         3: polynom_rew = 32'b110;
1267
         4: polynom_rew = 32'b1100;
1268
         5: polynom_rew = 32'b10100;
1269
         6: polynom_rew = 32'b110000;
1270
         7: polynom_rew = 32'b1100000;
1271
         8: polynom_rew = 32'b10111000;
1272
         9: polynom_rew = 32'b100010000;
1273
        10: polynom_rew = 32'b1001000000;
1274
        11: polynom_rew = 32'b10100000000;
1275
        12: polynom_rew = 32'b100000101001;
1276
        13: polynom_rew = 32'b1000000001100;
1277
        14: polynom_rew = 32'b10000000010101;
1278
        15: polynom_rew = 32'b110000000000000;
1279
        16: polynom_rew = 32'b1101000000001000;
1280
        17: polynom_rew = 32'b10010000000000000;
1281
        18: polynom_rew = 32'b100000010000000000;
1282
        19: polynom_rew = 32'b1000000000000100011;
1283
        20: polynom_rew = 32'b10000010000000000000;
1284
        21: polynom_rew = 32'b101000000000000000000;
1285
        22: polynom_rew = 32'b1100000000000000000000;
1286
        23: polynom_rew = 32'b10000100000000000000000;
1287
        24: polynom_rew = 32'b111000010000000000000000;
1288
        25: polynom_rew = 32'b1001000000000000000000000;
1289
        26: polynom_rew = 32'b10000000000000000000100011;
1290
        27: polynom_rew = 32'b100000000000000000000010011;
1291
        28: polynom_rew = 32'b1100100000000000000000000000;
1292
        29: polynom_rew = 32'b10100000000000000000000000000;
1293
        30: polynom_rew = 32'b100000000000000000000000101001;
1294
        31: polynom_rew = 32'b1001000000000000000000000000000;
1295
        32: polynom_rew = 32'b10000000001000000000000000000011;
1296
        default: polynom_rew = 32'b0;
1297
        endcase
1298
        // rotate left
1299
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1300
        lfsr_fb_rew = qi[length];
1301
        for (i=length-1; i>=1; i=i-1) begin
1302
            if (polynom_rew[i])
1303
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1304
        end
1305
    end
1306
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1307
   assign q_next = rew ? q_next_rew : q_next_fw;
1308
   always @ (posedge clk or posedge rst)
1309
     if (rst)
1310
       qi <= {length{1'b0}};
1311
     else
1312
     if (cke)
1313
       qi <= q_next;
1314
    always @ (posedge clk or posedge rst)
1315
    if (rst)
1316
        level1 <= 1'b0;
1317
    else
1318
    if (cke)
1319
    if (q_next == level1_value)
1320
        level1 <= 1'b1;
1321
    else if (qi == level1_value & rew)
1322
        level1 <= 1'b0;
1323
endmodule
1324
//////////////////////////////////////////////////////////////////////
1325
////                                                              ////
1326
////  Versatile counter                                           ////
1327
////                                                              ////
1328
////  Description                                                 ////
1329
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1330
////  counter                                                     ////
1331
////                                                              ////
1332
////  To Do:                                                      ////
1333
////   - add LFSR with more taps                                  ////
1334
////                                                              ////
1335
////  Author(s):                                                  ////
1336
////      - Michael Unneback, unneback@opencores.org              ////
1337
////        ORSoC AB                                              ////
1338
////                                                              ////
1339
//////////////////////////////////////////////////////////////////////
1340
////                                                              ////
1341
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1342
////                                                              ////
1343
//// This source file may be used and distributed without         ////
1344
//// restriction provided that this copyright statement is not    ////
1345
//// removed from the file and that any derivative work contains  ////
1346
//// the original copyright notice and the associated disclaimer. ////
1347
////                                                              ////
1348
//// This source file is free software; you can redistribute it   ////
1349
//// and/or modify it under the terms of the GNU Lesser General   ////
1350
//// Public License as published by the Free Software Foundation; ////
1351
//// either version 2.1 of the License, or (at your option) any   ////
1352
//// later version.                                               ////
1353
////                                                              ////
1354
//// This source is distributed in the hope that it will be       ////
1355
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1356
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1357
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1358
//// details.                                                     ////
1359
////                                                              ////
1360
//// You should have received a copy of the GNU Lesser General    ////
1361
//// Public License along with this source; if not, download it   ////
1362
//// from http://www.opencores.org/lgpl.shtml                     ////
1363
////                                                              ////
1364
//////////////////////////////////////////////////////////////////////
1365
// GRAY counter
1366 18 unneback
module vl_cnt_gray ( q, rst, clk);
1367 6 unneback
   parameter length = 4;
1368
   output reg [length:1] q;
1369
   input rst;
1370
   input clk;
1371
   parameter clear_value = 0;
1372
   parameter set_value = 1;
1373
   parameter wrap_value = 8;
1374
   parameter level1_value = 15;
1375
   reg  [length:1] qi;
1376
   wire [length:1] q_next;
1377
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1378
   always @ (posedge clk or posedge rst)
1379
     if (rst)
1380
       qi <= {length{1'b0}};
1381
     else
1382
       qi <= q_next;
1383
   always @ (posedge clk or posedge rst)
1384
     if (rst)
1385
       q <= {length{1'b0}};
1386
     else
1387
         q <= (q_next>>1) ^ q_next;
1388
endmodule
1389
//////////////////////////////////////////////////////////////////////
1390
////                                                              ////
1391
////  Versatile counter                                           ////
1392
////                                                              ////
1393
////  Description                                                 ////
1394
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1395
////  counter                                                     ////
1396
////                                                              ////
1397
////  To Do:                                                      ////
1398
////   - add LFSR with more taps                                  ////
1399
////                                                              ////
1400
////  Author(s):                                                  ////
1401
////      - Michael Unneback, unneback@opencores.org              ////
1402
////        ORSoC AB                                              ////
1403
////                                                              ////
1404
//////////////////////////////////////////////////////////////////////
1405
////                                                              ////
1406
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1407
////                                                              ////
1408
//// This source file may be used and distributed without         ////
1409
//// restriction provided that this copyright statement is not    ////
1410
//// removed from the file and that any derivative work contains  ////
1411
//// the original copyright notice and the associated disclaimer. ////
1412
////                                                              ////
1413
//// This source file is free software; you can redistribute it   ////
1414
//// and/or modify it under the terms of the GNU Lesser General   ////
1415
//// Public License as published by the Free Software Foundation; ////
1416
//// either version 2.1 of the License, or (at your option) any   ////
1417
//// later version.                                               ////
1418
////                                                              ////
1419
//// This source is distributed in the hope that it will be       ////
1420
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1421
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1422
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1423
//// details.                                                     ////
1424
////                                                              ////
1425
//// You should have received a copy of the GNU Lesser General    ////
1426
//// Public License along with this source; if not, download it   ////
1427
//// from http://www.opencores.org/lgpl.shtml                     ////
1428
////                                                              ////
1429
//////////////////////////////////////////////////////////////////////
1430
// GRAY counter
1431 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1432 6 unneback
   parameter length = 4;
1433
   input cke;
1434
   output reg [length:1] q;
1435
   input rst;
1436
   input clk;
1437
   parameter clear_value = 0;
1438
   parameter set_value = 1;
1439
   parameter wrap_value = 8;
1440
   parameter level1_value = 15;
1441
   reg  [length:1] qi;
1442
   wire [length:1] q_next;
1443
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1444
   always @ (posedge clk or posedge rst)
1445
     if (rst)
1446
       qi <= {length{1'b0}};
1447
     else
1448
     if (cke)
1449
       qi <= q_next;
1450
   always @ (posedge clk or posedge rst)
1451
     if (rst)
1452
       q <= {length{1'b0}};
1453
     else
1454
       if (cke)
1455
         q <= (q_next>>1) ^ q_next;
1456
endmodule
1457
//////////////////////////////////////////////////////////////////////
1458
////                                                              ////
1459
////  Versatile counter                                           ////
1460
////                                                              ////
1461
////  Description                                                 ////
1462
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1463
////  counter                                                     ////
1464
////                                                              ////
1465
////  To Do:                                                      ////
1466
////   - add LFSR with more taps                                  ////
1467
////                                                              ////
1468
////  Author(s):                                                  ////
1469
////      - Michael Unneback, unneback@opencores.org              ////
1470
////        ORSoC AB                                              ////
1471
////                                                              ////
1472
//////////////////////////////////////////////////////////////////////
1473
////                                                              ////
1474
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1475
////                                                              ////
1476
//// This source file may be used and distributed without         ////
1477
//// restriction provided that this copyright statement is not    ////
1478
//// removed from the file and that any derivative work contains  ////
1479
//// the original copyright notice and the associated disclaimer. ////
1480
////                                                              ////
1481
//// This source file is free software; you can redistribute it   ////
1482
//// and/or modify it under the terms of the GNU Lesser General   ////
1483
//// Public License as published by the Free Software Foundation; ////
1484
//// either version 2.1 of the License, or (at your option) any   ////
1485
//// later version.                                               ////
1486
////                                                              ////
1487
//// This source is distributed in the hope that it will be       ////
1488
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1489
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1490
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1491
//// details.                                                     ////
1492
////                                                              ////
1493
//// You should have received a copy of the GNU Lesser General    ////
1494
//// Public License along with this source; if not, download it   ////
1495
//// from http://www.opencores.org/lgpl.shtml                     ////
1496
////                                                              ////
1497
//////////////////////////////////////////////////////////////////////
1498
// GRAY counter
1499 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1500 6 unneback
   parameter length = 4;
1501
   input cke;
1502
   output reg [length:1] q;
1503
   output [length:1] q_bin;
1504
   input rst;
1505
   input clk;
1506
   parameter clear_value = 0;
1507
   parameter set_value = 1;
1508
   parameter wrap_value = 8;
1509
   parameter level1_value = 15;
1510
   reg  [length:1] qi;
1511
   wire [length:1] q_next;
1512
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1513
   always @ (posedge clk or posedge rst)
1514
     if (rst)
1515
       qi <= {length{1'b0}};
1516
     else
1517
     if (cke)
1518
       qi <= q_next;
1519
   always @ (posedge clk or posedge rst)
1520
     if (rst)
1521
       q <= {length{1'b0}};
1522
     else
1523
       if (cke)
1524
         q <= (q_next>>1) ^ q_next;
1525
   assign q_bin = qi;
1526
endmodule
1527
//////////////////////////////////////////////////////////////////////
1528
////                                                              ////
1529
////  Versatile library, counters                                 ////
1530
////                                                              ////
1531
////  Description                                                 ////
1532
////  counters                                                    ////
1533
////                                                              ////
1534
////                                                              ////
1535
////  To Do:                                                      ////
1536
////   - add more counters                                        ////
1537
////                                                              ////
1538
////  Author(s):                                                  ////
1539
////      - Michael Unneback, unneback@opencores.org              ////
1540
////        ORSoC AB                                              ////
1541
////                                                              ////
1542
//////////////////////////////////////////////////////////////////////
1543
////                                                              ////
1544
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1545
////                                                              ////
1546
//// This source file may be used and distributed without         ////
1547
//// restriction provided that this copyright statement is not    ////
1548
//// removed from the file and that any derivative work contains  ////
1549
//// the original copyright notice and the associated disclaimer. ////
1550
////                                                              ////
1551
//// This source file is free software; you can redistribute it   ////
1552
//// and/or modify it under the terms of the GNU Lesser General   ////
1553
//// Public License as published by the Free Software Foundation; ////
1554
//// either version 2.1 of the License, or (at your option) any   ////
1555
//// later version.                                               ////
1556
////                                                              ////
1557
//// This source is distributed in the hope that it will be       ////
1558
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1559
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1560
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1561
//// details.                                                     ////
1562
////                                                              ////
1563
//// You should have received a copy of the GNU Lesser General    ////
1564
//// Public License along with this source; if not, download it   ////
1565
//// from http://www.opencores.org/lgpl.shtml                     ////
1566
////                                                              ////
1567
//////////////////////////////////////////////////////////////////////
1568 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1569 6 unneback
   parameter length = 4;
1570
   output reg [0:length-1] q;
1571
   input rst;
1572
   input clk;
1573
    always @ (posedge clk or posedge rst)
1574
    if (rst)
1575
        q <= {1'b1,{length-1{1'b0}}};
1576
    else
1577
        q <= {q[length-1],q[0:length-2]};
1578
endmodule
1579 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1580 6 unneback
   parameter length = 4;
1581
   input cke;
1582
   output reg [0:length-1] q;
1583
   input rst;
1584
   input clk;
1585
    always @ (posedge clk or posedge rst)
1586
    if (rst)
1587
        q <= {1'b1,{length-1{1'b0}}};
1588
    else
1589
        if (cke)
1590
            q <= {q[length-1],q[0:length-2]};
1591
endmodule
1592 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1593 6 unneback
   parameter length = 4;
1594
   input cke, clear;
1595
   output reg [0:length-1] q;
1596
   input rst;
1597
   input clk;
1598
    always @ (posedge clk or posedge rst)
1599
    if (rst)
1600
        q <= {1'b1,{length-1{1'b0}}};
1601
    else
1602
        if (cke)
1603
            if (clear)
1604
                q <= {1'b1,{length-1{1'b0}}};
1605
            else
1606
                q <= q >> 1;
1607
endmodule
1608 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1609 6 unneback
   parameter length = 4;
1610
   input cke, clear;
1611
   output reg [0:length-1] q;
1612
   input rst;
1613
   input clk;
1614
    always @ (posedge clk or posedge rst)
1615
    if (rst)
1616
        q <= {1'b1,{length-1{1'b0}}};
1617
    else
1618
        if (cke)
1619
            if (clear)
1620
                q <= {1'b1,{length-1{1'b0}}};
1621
            else
1622
            q <= {q[length-1],q[0:length-2]};
1623
endmodule
1624
//////////////////////////////////////////////////////////////////////
1625
////                                                              ////
1626
////  Versatile library, memories                                 ////
1627
////                                                              ////
1628
////  Description                                                 ////
1629
////  memories                                                    ////
1630
////                                                              ////
1631
////                                                              ////
1632
////  To Do:                                                      ////
1633
////   - add more memory types                                    ////
1634
////                                                              ////
1635
////  Author(s):                                                  ////
1636
////      - Michael Unneback, unneback@opencores.org              ////
1637
////        ORSoC AB                                              ////
1638
////                                                              ////
1639
//////////////////////////////////////////////////////////////////////
1640
////                                                              ////
1641
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1642
////                                                              ////
1643
//// This source file may be used and distributed without         ////
1644
//// restriction provided that this copyright statement is not    ////
1645
//// removed from the file and that any derivative work contains  ////
1646
//// the original copyright notice and the associated disclaimer. ////
1647
////                                                              ////
1648
//// This source file is free software; you can redistribute it   ////
1649
//// and/or modify it under the terms of the GNU Lesser General   ////
1650
//// Public License as published by the Free Software Foundation; ////
1651
//// either version 2.1 of the License, or (at your option) any   ////
1652
//// later version.                                               ////
1653
////                                                              ////
1654
//// This source is distributed in the hope that it will be       ////
1655
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1656
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1657
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1658
//// details.                                                     ////
1659
////                                                              ////
1660
//// You should have received a copy of the GNU Lesser General    ////
1661
//// Public License along with this source; if not, download it   ////
1662
//// from http://www.opencores.org/lgpl.shtml                     ////
1663
////                                                              ////
1664
//////////////////////////////////////////////////////////////////////
1665
/// ROM
1666 7 unneback
module vl_rom_init ( adr, q, clk);
1667
   parameter data_width = 32;
1668
   parameter addr_width = 8;
1669
   input [(addr_width-1):0]       adr;
1670
   output reg [(data_width-1):0] q;
1671
   input                         clk;
1672
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1673
   parameter memory_file = "vl_rom.vmem";
1674
   initial
1675
     begin
1676
        $readmemh(memory_file, rom);
1677
     end
1678
   always @ (posedge clk)
1679
     q <= rom[adr];
1680
endmodule
1681 14 unneback
/*
1682 7 unneback
module vl_rom ( adr, q, clk);
1683 6 unneback
parameter data_width = 32;
1684
parameter addr_width = 4;
1685
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1686
    {32'h18000000},
1687
    {32'hA8200000},
1688
    {32'hA8200000},
1689
    {32'hA8200000},
1690
    {32'h44003000},
1691
    {32'h15000000},
1692
    {32'h15000000},
1693
    {32'h15000000},
1694
    {32'h15000000},
1695
    {32'h15000000},
1696
    {32'h15000000},
1697
    {32'h15000000},
1698
    {32'h15000000},
1699
    {32'h15000000},
1700
    {32'h15000000},
1701
    {32'h15000000}};
1702 7 unneback
input [addr_width-1:0] adr;
1703 6 unneback
output reg [data_width-1:0] q;
1704
input clk;
1705
always @ (posedge clk)
1706 7 unneback
    q <= data[adr];
1707 6 unneback
endmodule
1708 14 unneback
*/
1709 6 unneback
// Single port RAM
1710
module vl_ram ( d, adr, we, q, clk);
1711
   parameter data_width = 32;
1712
   parameter addr_width = 8;
1713
   input [(data_width-1):0]      d;
1714
   input [(addr_width-1):0]       adr;
1715
   input                         we;
1716 7 unneback
   output reg [(data_width-1):0] q;
1717 6 unneback
   input                         clk;
1718
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1719 7 unneback
   parameter init = 0;
1720
   parameter memory_file = "vl_ram.vmem";
1721
   generate if (init) begin : init_mem
1722
   initial
1723
     begin
1724
        $readmemh(memory_file, ram);
1725
     end
1726
   end
1727
   endgenerate
1728 6 unneback
   always @ (posedge clk)
1729
   begin
1730
   if (we)
1731
     ram[adr] <= d;
1732
   q <= ram[adr];
1733
   end
1734
endmodule
1735 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1736
   parameter data_width = 32;
1737
   parameter addr_width = 8;
1738
   input [(data_width-1):0]      d;
1739
   input [(addr_width-1):0]       adr;
1740
   input [(addr_width/4)-1:0]    be;
1741
   input                         we;
1742
   output reg [(data_width-1):0] q;
1743
   input                         clk;
1744
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1745
   parameter init = 0;
1746
   parameter memory_file = "vl_ram.vmem";
1747
   generate if (init) begin : init_mem
1748
   initial
1749
     begin
1750
        $readmemh(memory_file, ram);
1751
     end
1752
   end
1753
   endgenerate
1754
   genvar i;
1755
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1756
      always @ (posedge clk)
1757
      if (we & be[i])
1758
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1759
   end
1760
   endgenerate
1761
   always @ (posedge clk)
1762
      q <= ram[adr];
1763
endmodule
1764 6 unneback
// Dual port RAM
1765
// ACTEL FPGA should not use logic to handle rw collision
1766 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1767 6 unneback
   parameter data_width = 32;
1768
   parameter addr_width = 8;
1769
   input [(data_width-1):0]      d_a;
1770
   input [(addr_width-1):0]       adr_a;
1771
   input [(addr_width-1):0]       adr_b;
1772
   input                         we_a;
1773
   output [(data_width-1):0]      q_b;
1774
   input                         clk_a, clk_b;
1775
   reg [(addr_width-1):0]         adr_b_reg;
1776
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1777 7 unneback
   parameter init = 0;
1778
   parameter memory_file = "vl_ram.vmem";
1779
   generate if (init) begin : init_mem
1780
   initial
1781
     begin
1782
        $readmemh(memory_file, ram);
1783
     end
1784
   end
1785
   endgenerate
1786 6 unneback
   always @ (posedge clk_a)
1787
   if (we_a)
1788
     ram[adr_a] <= d_a;
1789
   always @ (posedge clk_b)
1790
   adr_b_reg <= adr_b;
1791
   assign q_b = ram[adr_b_reg];
1792
endmodule
1793 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1794 6 unneback
   parameter data_width = 32;
1795
   parameter addr_width = 8;
1796
   input [(data_width-1):0]      d_a;
1797
   input [(addr_width-1):0]       adr_a;
1798
   input [(addr_width-1):0]       adr_b;
1799
   input                         we_a;
1800
   output [(data_width-1):0]      q_b;
1801
   output reg [(data_width-1):0] q_a;
1802
   input                         clk_a, clk_b;
1803
   reg [(data_width-1):0]         q_b;
1804
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1805 7 unneback
   parameter init = 0;
1806
   parameter memory_file = "vl_ram.vmem";
1807
   generate if (init) begin : init_mem
1808
   initial
1809
     begin
1810
        $readmemh(memory_file, ram);
1811
     end
1812
   end
1813
   endgenerate
1814 6 unneback
   always @ (posedge clk_a)
1815
     begin
1816
        q_a <= ram[adr_a];
1817
        if (we_a)
1818
             ram[adr_a] <= d_a;
1819
     end
1820
   always @ (posedge clk_b)
1821
          q_b <= ram[adr_b];
1822
endmodule
1823 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1824 6 unneback
   parameter data_width = 32;
1825
   parameter addr_width = 8;
1826
   input [(data_width-1):0]      d_a;
1827
   input [(addr_width-1):0]       adr_a;
1828
   input [(addr_width-1):0]       adr_b;
1829
   input                         we_a;
1830
   output [(data_width-1):0]      q_b;
1831
   input [(data_width-1):0]       d_b;
1832
   output reg [(data_width-1):0] q_a;
1833
   input                         we_b;
1834
   input                         clk_a, clk_b;
1835
   reg [(data_width-1):0]         q_b;
1836
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1837 7 unneback
   parameter init = 0;
1838
   parameter memory_file = "vl_ram.vmem";
1839
   generate if (init) begin : init_mem
1840
   initial
1841
     begin
1842
        $readmemh(memory_file, ram);
1843
     end
1844
   end
1845
   endgenerate
1846 6 unneback
   always @ (posedge clk_a)
1847
     begin
1848
        q_a <= ram[adr_a];
1849
        if (we_a)
1850
             ram[adr_a] <= d_a;
1851
     end
1852
   always @ (posedge clk_b)
1853
     begin
1854
        q_b <= ram[adr_b];
1855
        if (we_b)
1856
          ram[adr_b] <= d_b;
1857
     end
1858
endmodule
1859
// Content addresable memory, CAM
1860
// FIFO
1861
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1862 11 unneback
   parameter addr_width = 4;
1863
   parameter N = addr_width-1;
1864 6 unneback
   parameter Q1 = 2'b00;
1865
   parameter Q2 = 2'b01;
1866
   parameter Q3 = 2'b11;
1867
   parameter Q4 = 2'b10;
1868
   parameter going_empty = 1'b0;
1869
   parameter going_full  = 1'b1;
1870
   input [N:0]  wptr, rptr;
1871 14 unneback
   output       fifo_empty;
1872 6 unneback
   output       fifo_full;
1873
   input        wclk, rclk, rst;
1874
   wire direction;
1875
   reg  direction_set, direction_clr;
1876
   wire async_empty, async_full;
1877
   wire fifo_full2;
1878 14 unneback
   wire fifo_empty2;
1879 6 unneback
   // direction_set
1880
   always @ (wptr[N:N-1] or rptr[N:N-1])
1881
     case ({wptr[N:N-1],rptr[N:N-1]})
1882
       {Q1,Q2} : direction_set <= 1'b1;
1883
       {Q2,Q3} : direction_set <= 1'b1;
1884
       {Q3,Q4} : direction_set <= 1'b1;
1885
       {Q4,Q1} : direction_set <= 1'b1;
1886
       default : direction_set <= 1'b0;
1887
     endcase
1888
   // direction_clear
1889
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1890
     if (rst)
1891
       direction_clr <= 1'b1;
1892
     else
1893
       case ({wptr[N:N-1],rptr[N:N-1]})
1894
         {Q2,Q1} : direction_clr <= 1'b1;
1895
         {Q3,Q2} : direction_clr <= 1'b1;
1896
         {Q4,Q3} : direction_clr <= 1'b1;
1897
         {Q1,Q4} : direction_clr <= 1'b1;
1898
         default : direction_clr <= 1'b0;
1899
       endcase
1900 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1901 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1902
   assign async_full  = (wptr == rptr) && (direction==going_full);
1903 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1904
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1905 6 unneback
/*
1906
   always @ (posedge wclk or posedge rst or posedge async_full)
1907
     if (rst)
1908
       {fifo_full, fifo_full2} <= 2'b00;
1909
     else if (async_full)
1910
       {fifo_full, fifo_full2} <= 2'b11;
1911
     else
1912
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1913
*/
1914 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1915 6 unneback
     if (async_empty)
1916
       {fifo_empty, fifo_empty2} <= 2'b11;
1917
     else
1918 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1919 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1920
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1921 6 unneback
endmodule // async_comp
1922
module vl_fifo_1r1w_async (
1923
    d, wr, fifo_full, wr_clk, wr_rst,
1924
    q, rd, fifo_empty, rd_clk, rd_rst
1925
    );
1926
parameter data_width = 18;
1927
parameter addr_width = 4;
1928
// write side
1929
input  [data_width-1:0] d;
1930
input                   wr;
1931
output                  fifo_full;
1932
input                   wr_clk;
1933
input                   wr_rst;
1934
// read side
1935
output [data_width-1:0] q;
1936
input                   rd;
1937
output                  fifo_empty;
1938
input                   rd_clk;
1939
input                   rd_rst;
1940
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1941 21 unneback
/*
1942 6 unneback
vl_fifo_1r1w_async (
1943
    d, wr, fifo_full, wr_clk, wr_rst,
1944
    q, rd, fifo_empty, rd_clk, rd_rst
1945
    );
1946 21 unneback
*/
1947 18 unneback
vl_cnt_gray_ce_bin
1948 6 unneback
    # ( .length(addr_width))
1949
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1950 18 unneback
vl_cnt_gray_ce_bin
1951 6 unneback
    # (.length(addr_width))
1952
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1953 7 unneback
vl_dpram_1r1w
1954 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1955
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1956
vl_fifo_cmp_async
1957
    # (.addr_width(addr_width))
1958
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1959
endmodule
1960 8 unneback
module vl_fifo_2r2w_async (
1961 6 unneback
    // a side
1962
    a_d, a_wr, a_fifo_full,
1963
    a_q, a_rd, a_fifo_empty,
1964
    a_clk, a_rst,
1965
    // b side
1966
    b_d, b_wr, b_fifo_full,
1967
    b_q, b_rd, b_fifo_empty,
1968
    b_clk, b_rst
1969
    );
1970
parameter data_width = 18;
1971
parameter addr_width = 4;
1972
// a side
1973
input  [data_width-1:0] a_d;
1974
input                   a_wr;
1975
output                  a_fifo_full;
1976
output [data_width-1:0] a_q;
1977
input                   a_rd;
1978
output                  a_fifo_empty;
1979
input                   a_clk;
1980
input                   a_rst;
1981
// b side
1982
input  [data_width-1:0] b_d;
1983
input                   b_wr;
1984
output                  b_fifo_full;
1985
output [data_width-1:0] b_q;
1986
input                   b_rd;
1987
output                  b_fifo_empty;
1988
input                   b_clk;
1989
input                   b_rst;
1990
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1991
vl_fifo_1r1w_async_a (
1992
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1993
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1994
    );
1995
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1996
vl_fifo_1r1w_async_b (
1997
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1998
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1999
    );
2000
endmodule
2001 8 unneback
module vl_fifo_2r2w_async_simplex (
2002 6 unneback
    // a side
2003
    a_d, a_wr, a_fifo_full,
2004
    a_q, a_rd, a_fifo_empty,
2005
    a_clk, a_rst,
2006
    // b side
2007
    b_d, b_wr, b_fifo_full,
2008
    b_q, b_rd, b_fifo_empty,
2009
    b_clk, b_rst
2010
    );
2011
parameter data_width = 18;
2012
parameter addr_width = 4;
2013
// a side
2014
input  [data_width-1:0] a_d;
2015
input                   a_wr;
2016
output                  a_fifo_full;
2017
output [data_width-1:0] a_q;
2018
input                   a_rd;
2019
output                  a_fifo_empty;
2020
input                   a_clk;
2021
input                   a_rst;
2022
// b side
2023
input  [data_width-1:0] b_d;
2024
input                   b_wr;
2025
output                  b_fifo_full;
2026
output [data_width-1:0] b_q;
2027
input                   b_rd;
2028
output                  b_fifo_empty;
2029
input                   b_clk;
2030
input                   b_rst;
2031
// adr_gen
2032
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2033
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2034
// dpram
2035
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2036 18 unneback
vl_cnt_gray_ce_bin
2037 6 unneback
    # ( .length(addr_width))
2038
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2039 18 unneback
vl_cnt_gray_ce_bin
2040 6 unneback
    # (.length(addr_width))
2041
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2042 18 unneback
vl_cnt_gray_ce_bin
2043 6 unneback
    # ( .length(addr_width))
2044
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2045 18 unneback
vl_cnt_gray_ce_bin
2046 6 unneback
    # (.length(addr_width))
2047
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2048
// mux read or write adr to DPRAM
2049
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2050
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2051 11 unneback
vl_dpram_2r2w
2052 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2053
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2054
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2055 11 unneback
vl_fifo_cmp_async
2056 6 unneback
    # (.addr_width(addr_width))
2057
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2058 11 unneback
vl_fifo_cmp_async
2059 6 unneback
    # (.addr_width(addr_width))
2060
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2061
endmodule
2062 12 unneback
//////////////////////////////////////////////////////////////////////
2063
////                                                              ////
2064
////  Versatile library, wishbone stuff                           ////
2065
////                                                              ////
2066
////  Description                                                 ////
2067
////  Wishbone compliant modules                                  ////
2068
////                                                              ////
2069
////                                                              ////
2070
////  To Do:                                                      ////
2071
////   -                                                          ////
2072
////                                                              ////
2073
////  Author(s):                                                  ////
2074
////      - Michael Unneback, unneback@opencores.org              ////
2075
////        ORSoC AB                                              ////
2076
////                                                              ////
2077
//////////////////////////////////////////////////////////////////////
2078
////                                                              ////
2079
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2080
////                                                              ////
2081
//// This source file may be used and distributed without         ////
2082
//// restriction provided that this copyright statement is not    ////
2083
//// removed from the file and that any derivative work contains  ////
2084
//// the original copyright notice and the associated disclaimer. ////
2085
////                                                              ////
2086
//// This source file is free software; you can redistribute it   ////
2087
//// and/or modify it under the terms of the GNU Lesser General   ////
2088
//// Public License as published by the Free Software Foundation; ////
2089
//// either version 2.1 of the License, or (at your option) any   ////
2090
//// later version.                                               ////
2091
////                                                              ////
2092
//// This source is distributed in the hope that it will be       ////
2093
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2094
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2095
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2096
//// details.                                                     ////
2097
////                                                              ////
2098
//// You should have received a copy of the GNU Lesser General    ////
2099
//// Public License along with this source; if not, download it   ////
2100
//// from http://www.opencores.org/lgpl.shtml                     ////
2101
////                                                              ////
2102
//////////////////////////////////////////////////////////////////////
2103
// async wb3 - wb3 bridge
2104
`timescale 1ns/1ns
2105 18 unneback
module vl_wb3wb3_bridge (
2106 12 unneback
        // wishbone slave side
2107
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2108
        // wishbone master side
2109
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2110
input [31:0] wbs_dat_i;
2111
input [31:2] wbs_adr_i;
2112
input [3:0]  wbs_sel_i;
2113
input [1:0]  wbs_bte_i;
2114
input [2:0]  wbs_cti_i;
2115
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2116
output [31:0] wbs_dat_o;
2117 14 unneback
output wbs_ack_o;
2118 12 unneback
input wbs_clk, wbs_rst;
2119
output [31:0] wbm_dat_o;
2120
output reg [31:2] wbm_adr_o;
2121
output [3:0]  wbm_sel_o;
2122
output reg [1:0]  wbm_bte_o;
2123
output reg [2:0]  wbm_cti_o;
2124 14 unneback
output reg wbm_we_o;
2125
output wbm_cyc_o;
2126 12 unneback
output wbm_stb_o;
2127
input [31:0]  wbm_dat_i;
2128
input wbm_ack_i;
2129
input wbm_clk, wbm_rst;
2130
parameter addr_width = 4;
2131
// bte
2132
parameter linear       = 2'b00;
2133
parameter wrap4        = 2'b01;
2134
parameter wrap8        = 2'b10;
2135
parameter wrap16       = 2'b11;
2136
// cti
2137
parameter classic      = 3'b000;
2138
parameter incburst     = 3'b010;
2139
parameter endofburst   = 3'b111;
2140
parameter wbs_adr  = 1'b0;
2141
parameter wbs_data = 1'b1;
2142
parameter wbm_adr0 = 2'b00;
2143
parameter wbm_adr1 = 2'b01;
2144
parameter wbm_data = 2'b10;
2145
reg [1:0] wbs_bte_reg;
2146
reg wbs;
2147
wire wbs_eoc_alert, wbm_eoc_alert;
2148
reg wbs_eoc, wbm_eoc;
2149
reg [1:0] wbm;
2150 14 unneback
wire [1:16] wbs_count, wbm_count;
2151 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2152
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2153
reg a_rd_reg;
2154
wire b_rd_adr, b_rd_data;
2155 14 unneback
wire b_rd_data_reg;
2156
wire [35:0] temp;
2157 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2158
always @ (posedge wbs_clk or posedge wbs_rst)
2159
if (wbs_rst)
2160
        wbs_eoc <= 1'b0;
2161
else
2162
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2163
                wbs_eoc <= wbs_bte_i==linear;
2164
        else if (wbs_eoc_alert & (a_rd | a_wr))
2165
                wbs_eoc <= 1'b1;
2166 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2167 12 unneback
    cnt0 (
2168
        .cke(wbs_ack_o),
2169
        .clear(wbs_eoc),
2170
        .q(wbs_count),
2171
        .rst(wbs_rst),
2172
        .clk(wbs_clk));
2173
always @ (posedge wbs_clk or posedge wbs_rst)
2174
if (wbs_rst)
2175
        wbs <= wbs_adr;
2176
else
2177
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2178
                wbs <= wbs_data;
2179
        else if (wbs_eoc & wbs_ack_o)
2180
                wbs <= wbs_adr;
2181
// wbs FIFO
2182
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2183
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2184
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2185
              1'b0;
2186
assign a_rd = !a_fifo_empty;
2187
always @ (posedge wbs_clk or posedge wbs_rst)
2188
if (wbs_rst)
2189
        a_rd_reg <= 1'b0;
2190
else
2191
        a_rd_reg <= a_rd;
2192
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2193
assign wbs_dat_o = a_q[35:4];
2194
always @ (posedge wbs_clk or posedge wbs_rst)
2195
if (wbs_rst)
2196 13 unneback
        wbs_bte_reg <= 2'b00;
2197 12 unneback
else
2198 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2199 12 unneback
// wbm FIFO
2200
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2201
always @ (posedge wbm_clk or posedge wbm_rst)
2202
if (wbm_rst)
2203
        wbm_eoc <= 1'b0;
2204
else
2205
        if (wbm==wbm_adr0 & !b_fifo_empty)
2206
                wbm_eoc <= b_q[4:3] == linear;
2207
        else if (wbm_eoc_alert & wbm_ack_i)
2208
                wbm_eoc <= 1'b1;
2209
always @ (posedge wbm_clk or posedge wbm_rst)
2210
if (wbm_rst)
2211
        wbm <= wbm_adr0;
2212
else
2213
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2214
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2215
        (wbm==wbm_adr1 & !wbm_we_o) |
2216
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2217
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2218
assign b_d = {wbm_dat_i,4'b1111};
2219
assign b_wr = !wbm_we_o & wbm_ack_i;
2220
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2221
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2222
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2223
                   1'b0;
2224
assign b_rd = b_rd_adr | b_rd_data;
2225 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2226
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2227 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2228 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2229 12 unneback
    cnt1 (
2230
        .cke(wbm_ack_i),
2231
        .clear(wbm_eoc),
2232
        .q(wbm_count),
2233
        .rst(wbm_rst),
2234
        .clk(wbm_clk));
2235
assign wbm_cyc_o = wbm==wbm_data;
2236
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2237
                   (wbm==wbm_data) ? 1'b1 :
2238
                   1'b0;
2239
always @ (posedge wbm_clk or posedge wbm_rst)
2240
if (wbm_rst)
2241
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2242
else begin
2243
        if (wbm==wbm_adr0 & !b_fifo_empty)
2244
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2245
        else if (wbm_eoc_alert & wbm_ack_i)
2246
                wbm_cti_o <= endofburst;
2247
end
2248
//async_fifo_dw_simplex_top
2249
vl_fifo_2r2w_async_simplex
2250
# ( .data_width(36), .addr_width(addr_width))
2251
fifo (
2252
    // a side
2253
    .a_d(a_d),
2254
    .a_wr(a_wr),
2255
    .a_fifo_full(a_fifo_full),
2256
    .a_q(a_q),
2257
    .a_rd(a_rd),
2258
    .a_fifo_empty(a_fifo_empty),
2259
    .a_clk(wbs_clk),
2260
    .a_rst(wbs_rst),
2261
    // b side
2262
    .b_d(b_d),
2263
    .b_wr(b_wr),
2264
    .b_fifo_full(b_fifo_full),
2265
    .b_q(b_q),
2266
    .b_rd(b_rd),
2267
    .b_fifo_empty(b_fifo_empty),
2268
    .b_clk(wbm_clk),
2269
    .b_rst(wbm_rst)
2270
    );
2271
endmodule
2272 17 unneback
// WB ROM
2273 18 unneback
module vl_wb_boot_rom (
2274 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2275 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2276
    parameter adr_hi = 31;
2277
    parameter adr_lo = 28;
2278
    parameter adr_sel = 4'hf;
2279
    parameter addr_width = 5;
2280 17 unneback
//E2_ifndef BOOT_ROM
2281
//E2_define BOOT_ROM "boot_rom.v"
2282
//E2_endif
2283 18 unneback
    input [adr_hi:2]    wb_adr_i;
2284
    input               wb_stb_i;
2285
    input               wb_cyc_i;
2286
    output [31:0]        wb_dat_o;
2287
    output              wb_ack_o;
2288
    output              hit_o;
2289
    input               wb_clk;
2290
    input               wb_rst;
2291
    wire hit;
2292
    reg [31:0] wb_dat;
2293
    reg wb_ack;
2294
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2295 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2296
    if (wb_rst)
2297 18 unneback
        wb_dat <= 32'h15000000;
2298 17 unneback
    else
2299 18 unneback
         case (wb_adr_i[addr_width-1:2])
2300 17 unneback
//E2_include `BOOT_ROM
2301
           /*
2302
            // Zero r0 and jump to 0x00000100
2303 18 unneback
 
2304
            1 : wb_dat <= 32'hA8200000;
2305
            2 : wb_dat <= 32'hA8C00100;
2306
            3 : wb_dat <= 32'h44003000;
2307
            4 : wb_dat <= 32'h15000000;
2308 17 unneback
            */
2309
           default:
2310 18 unneback
             wb_dat <= 32'h00000000;
2311 17 unneback
         endcase // case (wb_adr_i)
2312
always @ (posedge wb_clk or posedge wb_rst)
2313
    if (wb_rst)
2314 18 unneback
        wb_ack <= 1'b0;
2315 17 unneback
    else
2316 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2317
assign hit_o = hit;
2318
assign wb_dat_o = wb_dat & {32{wb_ack}};
2319
assign wb_ack_o = wb_ack;
2320 17 unneback
endmodule
2321 18 unneback
//////////////////////////////////////////////////////////////////////
2322
////                                                              ////
2323
////  Arithmetic functions                                        ////
2324
////                                                              ////
2325
////  Description                                                 ////
2326
////  Arithmetic functions for ALU and DSP                        ////
2327
////                                                              ////
2328
////                                                              ////
2329
////  To Do:                                                      ////
2330
////   -                                                          ////
2331
////                                                              ////
2332
////  Author(s):                                                  ////
2333
////      - Michael Unneback, unneback@opencores.org              ////
2334
////        ORSoC AB                                              ////
2335
////                                                              ////
2336
//////////////////////////////////////////////////////////////////////
2337
////                                                              ////
2338
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2339
////                                                              ////
2340
//// This source file may be used and distributed without         ////
2341
//// restriction provided that this copyright statement is not    ////
2342
//// removed from the file and that any derivative work contains  ////
2343
//// the original copyright notice and the associated disclaimer. ////
2344
////                                                              ////
2345
//// This source file is free software; you can redistribute it   ////
2346
//// and/or modify it under the terms of the GNU Lesser General   ////
2347
//// Public License as published by the Free Software Foundation; ////
2348
//// either version 2.1 of the License, or (at your option) any   ////
2349
//// later version.                                               ////
2350
////                                                              ////
2351
//// This source is distributed in the hope that it will be       ////
2352
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2353
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2354
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2355
//// details.                                                     ////
2356
////                                                              ////
2357
//// You should have received a copy of the GNU Lesser General    ////
2358
//// Public License along with this source; if not, download it   ////
2359
//// from http://www.opencores.org/lgpl.shtml                     ////
2360
////                                                              ////
2361
//////////////////////////////////////////////////////////////////////
2362
// signed multiplication
2363
module vl_mults (a,b,p);
2364
parameter operand_a_width = 18;
2365
parameter operand_b_width = 18;
2366
parameter result_hi = 35;
2367
parameter result_lo = 0;
2368
input [operand_a_width-1:0] a;
2369
input [operand_b_width-1:0] b;
2370
output [result_hi:result_lo] p;
2371
wire signed [operand_a_width-1:0] ai;
2372
wire signed [operand_b_width-1:0] bi;
2373
wire signed [operand_a_width+operand_b_width-1:0] result;
2374
    assign ai = a;
2375
    assign bi = b;
2376
    assign result = ai * bi;
2377
    assign p = result[result_hi:result_lo];
2378
endmodule
2379
module vl_mults18x18 (a,b,p);
2380
input [17:0] a,b;
2381
output [35:0] p;
2382
vl_mult
2383
    # (.operand_a_width(18), .operand_b_width(18))
2384
    mult0 (.a(a), .b(b), .p(p));
2385
endmodule
2386
// unsigned multiplication
2387
module vl_mult (a,b,p);
2388
parameter operand_a_width = 18;
2389
parameter operand_b_width = 18;
2390
parameter result_hi = 35;
2391
parameter result_lo = 0;
2392
input [operand_a_width-1:0] a;
2393
input [operand_b_width-1:0] b;
2394
output [result_hi:result_hi] p;
2395
wire [operand_a_width+operand_b_width-1:0] result;
2396
    assign result = a * b;
2397
    assign p = result[result_hi:result_lo];
2398
endmodule
2399
// shift unit
2400
// supporting the following shift functions
2401
//   SLL
2402
//   SRL
2403
//   SRA
2404
module vl_shift_unit_32( din, s, dout, opcode);
2405
input [31:0] din; // data in operand
2406
input [4:0] s; // shift operand
2407
input [1:0] opcode;
2408
output [31:0] dout;
2409
parameter opcode_sll = 2'b00;
2410
//parameter opcode_srl = 2'b01;
2411
parameter opcode_sra = 2'b10;
2412
//parameter opcode_ror = 2'b11;
2413
wire sll, sra;
2414
assign sll = opcode == opcode_sll;
2415
assign sra = opcode == opcode_sra;
2416
wire [15:1] s1;
2417
wire [3:0] sign;
2418
wire [7:0] tmp [0:3];
2419
// first stage is multiplier based
2420
// shift operand as fractional 8.7
2421
assign s1[15] = sll & s[2:0]==3'd7;
2422
assign s1[14] = sll & s[2:0]==3'd6;
2423
assign s1[13] = sll & s[2:0]==3'd5;
2424
assign s1[12] = sll & s[2:0]==3'd4;
2425
assign s1[11] = sll & s[2:0]==3'd3;
2426
assign s1[10] = sll & s[2:0]==3'd2;
2427
assign s1[ 9] = sll & s[2:0]==3'd1;
2428
assign s1[ 8] = s[2:0]==3'd0;
2429
assign s1[ 7] = !sll & s[2:0]==3'd1;
2430
assign s1[ 6] = !sll & s[2:0]==3'd2;
2431
assign s1[ 5] = !sll & s[2:0]==3'd3;
2432
assign s1[ 4] = !sll & s[2:0]==3'd4;
2433
assign s1[ 3] = !sll & s[2:0]==3'd5;
2434
assign s1[ 2] = !sll & s[2:0]==3'd6;
2435
assign s1[ 1] = !sll & s[2:0]==3'd7;
2436
assign sign[3] = din[31] & sra;
2437
assign sign[2] = sign[3] & (&din[31:24]);
2438
assign sign[1] = sign[2] & (&din[23:16]);
2439
assign sign[0] = sign[1] & (&din[15:8]);
2440
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2441
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2442
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2443
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2444
// second stage is multiplexer based
2445
// shift on byte level
2446
// mux byte 3
2447
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2448
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2449
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2450
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2451
                     {8{sign[3]}};
2452
// mux byte 2
2453
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2454
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2455
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2456
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2457
                     (s[4:3]==2'b01) ? tmp[3] :
2458
                     {8{sign[3]}};
2459
// mux byte 1
2460
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2461
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2462
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2463
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2464
                     (s[4:3]==2'b01) ? tmp[2] :
2465
                     (s[4:3]==2'b10) ? tmp[3] :
2466
                     {8{sign[3]}};
2467
// mux byte 0
2468
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2469
                     (sll) ?  {8{1'b0}}:
2470
                     (s[4:3]==2'b01) ? tmp[1] :
2471
                     (s[4:3]==2'b10) ? tmp[2] :
2472
                     tmp[3];
2473
endmodule
2474
// logic unit
2475
// supporting the following logic functions
2476
//    a and b
2477
//    a or  b
2478
//    a xor b
2479
//    not b
2480
module vl_logic_unit( a, b, result, opcode);
2481
parameter width = 32;
2482
parameter opcode_and = 2'b00;
2483
parameter opcode_or  = 2'b01;
2484
parameter opcode_xor = 2'b10;
2485
input [width-1:0] a,b;
2486
output [width-1:0] result;
2487
input [1:0] opcode;
2488
assign result = (opcode==opcode_and) ? a & b :
2489
                (opcode==opcode_or)  ? a | b :
2490
                (opcode==opcode_xor) ? a ^ b :
2491
                b;
2492
endmodule
2493
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2494
parameter width = 32;
2495
parameter opcode_add = 1'b0;
2496
parameter opcode_sub = 1'b1;
2497
input [width-1:0] a,b;
2498
input c_in, add_sub, sign;
2499
output [width-1:0] result;
2500
output c_out, z, ovfl;
2501
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2502
assign z = (result=={width{1'b0}});
2503
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2504
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2505
endmodule

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