OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 25

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 6 unneback
 // ALTERA
47
 //ACTEL
48
// sync reset
49 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
50 6 unneback
// output active high global reset sync with two DFFs 
51
`timescale 1 ns/100 ps
52
module vl_sync_rst ( rst_n_i, rst_o, clk);
53
input rst_n_i, clk;
54
output rst_o;
55 18 unneback
reg [1:0] tmp;
56 6 unneback
always @ (posedge clk or negedge rst_n_i)
57
if (!rst_n_i)
58 17 unneback
        tmp <= 2'b11;
59 6 unneback
else
60 17 unneback
        tmp <= {1'b0,tmp[0]};
61
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
62 6 unneback
endmodule
63
// vl_pll
64
 //altera
65
 //actel
66
//////////////////////////////////////////////////////////////////////
67
////                                                              ////
68
////  Versatile library, registers                                ////
69
////                                                              ////
70
////  Description                                                 ////
71
////  Different type of registers                                 ////
72
////                                                              ////
73
////                                                              ////
74
////  To Do:                                                      ////
75
////   - add more different registers                             ////
76
////                                                              ////
77
////  Author(s):                                                  ////
78
////      - Michael Unneback, unneback@opencores.org              ////
79
////        ORSoC AB                                              ////
80
////                                                              ////
81
//////////////////////////////////////////////////////////////////////
82
////                                                              ////
83
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84
////                                                              ////
85
//// This source file may be used and distributed without         ////
86
//// restriction provided that this copyright statement is not    ////
87
//// removed from the file and that any derivative work contains  ////
88
//// the original copyright notice and the associated disclaimer. ////
89
////                                                              ////
90
//// This source file is free software; you can redistribute it   ////
91
//// and/or modify it under the terms of the GNU Lesser General   ////
92
//// Public License as published by the Free Software Foundation; ////
93
//// either version 2.1 of the License, or (at your option) any   ////
94
//// later version.                                               ////
95
////                                                              ////
96
//// This source is distributed in the hope that it will be       ////
97
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100
//// details.                                                     ////
101
////                                                              ////
102
//// You should have received a copy of the GNU Lesser General    ////
103
//// Public License along with this source; if not, download it   ////
104
//// from http://www.opencores.org/lgpl.shtml                     ////
105
////                                                              ////
106
//////////////////////////////////////////////////////////////////////
107 18 unneback
module vl_dff ( d, q, clk, rst);
108 6 unneback
        parameter width = 1;
109
        parameter reset_value = 0;
110
        input [width-1:0] d;
111
        input clk, rst;
112
        output reg [width-1:0] q;
113
        always @ (posedge clk or posedge rst)
114
        if (rst)
115
                q <= reset_value;
116
        else
117
                q <= d;
118
endmodule
119 18 unneback
module vl_dff_array ( d, q, clk, rst);
120 6 unneback
        parameter width = 1;
121
        parameter depth = 2;
122
        parameter reset_value = 1'b0;
123
        input [width-1:0] d;
124
        input clk, rst;
125
        output [width-1:0] q;
126
        reg  [0:depth-1] q_tmp [width-1:0];
127
        integer i;
128
        always @ (posedge clk or posedge rst)
129
        if (rst) begin
130
            for (i=0;i<depth;i=i+1)
131
                q_tmp[i] <= {width{reset_value}};
132
        end else begin
133
            q_tmp[0] <= d;
134
            for (i=1;i<depth;i=i+1)
135
                q_tmp[i] <= q_tmp[i-1];
136
        end
137
    assign q = q_tmp[depth-1];
138
endmodule
139 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
140 6 unneback
        parameter width = 1;
141
        parameter reset_value = 0;
142
        input [width-1:0] d;
143
        input ce, clk, rst;
144
        output reg [width-1:0] q;
145
        always @ (posedge clk or posedge rst)
146
        if (rst)
147
                q <= reset_value;
148
        else
149
                if (ce)
150
                        q <= d;
151
endmodule
152 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
153 8 unneback
        parameter width = 1;
154
        parameter reset_value = 0;
155
        input [width-1:0] d;
156 10 unneback
        input ce, clear, clk, rst;
157 8 unneback
        output reg [width-1:0] q;
158
        always @ (posedge clk or posedge rst)
159
        if (rst)
160
            q <= reset_value;
161
        else
162
            if (ce)
163
                if (clear)
164
                    q <= {width{1'b0}};
165
                else
166
                    q <= d;
167
endmodule
168 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
169
        parameter width = 1;
170
        parameter reset_value = 0;
171
        input [width-1:0] d;
172
        input ce, set, clk, rst;
173
        output reg [width-1:0] q;
174
        always @ (posedge clk or posedge rst)
175
        if (rst)
176
            q <= reset_value;
177
        else
178
            if (ce)
179
                if (set)
180
                    q <= {width{1'b1}};
181
                else
182
                    q <= d;
183
endmodule
184 6 unneback
// megafunction wizard: %LPM_FF%
185
// GENERATION: STANDARD
186
// VERSION: WM1.0
187
// MODULE: lpm_ff 
188
// ============================================================
189
// File Name: dff_sr.v
190
// Megafunction Name(s):
191
//                      lpm_ff
192
//
193
// Simulation Library Files(s):
194
//                      lpm
195
// ============================================================
196
// ************************************************************
197
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
198
//
199
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
200
// ************************************************************
201
//Copyright (C) 1991-2010 Altera Corporation
202
//Your use of Altera Corporation's design tools, logic functions 
203
//and other software and tools, and its AMPP partner logic 
204
//functions, and any output files from any of the foregoing 
205
//(including device programming or simulation files), and any 
206
//associated documentation or information are expressly subject 
207
//to the terms and conditions of the Altera Program License 
208
//Subscription Agreement, Altera MegaCore Function License 
209
//Agreement, or other applicable license agreement, including, 
210
//without limitation, that your use is for the sole purpose of 
211
//programming logic devices manufactured by Altera and sold by 
212
//Altera or its authorized distributors.  Please refer to the 
213
//applicable agreement for further details.
214
// synopsys translate_off
215
`timescale 1 ps / 1 ps
216
// synopsys translate_on
217 18 unneback
module vl_dff_sr (
218 6 unneback
        aclr,
219
        aset,
220
        clock,
221
        data,
222
        q);
223
        input     aclr;
224
        input     aset;
225
        input     clock;
226
        input     data;
227
        output    q;
228
        wire [0:0] sub_wire0;
229
        wire [0:0] sub_wire1 = sub_wire0[0:0];
230
        wire  q = sub_wire1;
231
        wire  sub_wire2 = data;
232
        wire  sub_wire3 = sub_wire2;
233
        lpm_ff  lpm_ff_component (
234
                                .aclr (aclr),
235
                                .clock (clock),
236
                                .data (sub_wire3),
237
                                .aset (aset),
238
                                .q (sub_wire0)
239
                                // synopsys translate_off
240
                                ,
241
                                .aload (),
242
                                .enable (),
243
                                .sclr (),
244
                                .sload (),
245
                                .sset ()
246
                                // synopsys translate_on
247
                                );
248
        defparam
249
                lpm_ff_component.lpm_fftype = "DFF",
250
                lpm_ff_component.lpm_type = "LPM_FF",
251
                lpm_ff_component.lpm_width = 1;
252
endmodule
253
// ============================================================
254
// CNX file retrieval info
255
// ============================================================
256
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
257
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
258
// Retrieval info: PRIVATE: ASET NUMERIC "1"
259
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
260
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
261
// Retrieval info: PRIVATE: DFF NUMERIC "1"
262
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
263
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
264
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
265
// Retrieval info: PRIVATE: SSET NUMERIC "0"
266
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
267
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
268
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
269
// Retrieval info: PRIVATE: nBit NUMERIC "1"
270
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
271
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
272
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
273
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
274
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
275
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
276
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
277
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
278
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
279
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
280
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
281
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
282
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
283
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
284
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
285
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
286
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
287
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
288
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
289
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
290
// Retrieval info: LIB_FILE: lpm
291
// LATCH
292
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
293 18 unneback
module vl_latch ( d, le, q, clk);
294 6 unneback
input d, le;
295
output q;
296
input clk;
297
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
298
endmodule
299 18 unneback
module vl_shreg ( d, q, clk, rst);
300 17 unneback
parameter depth = 10;
301
input d;
302
output q;
303
input clk, rst;
304
reg [1:depth] dffs;
305
always @ (posedge clk or posedge rst)
306
if (rst)
307
    dffs <= {depth{1'b0}};
308
else
309
    dffs <= {d,dffs[1:depth-1]};
310
assign q = dffs[depth];
311
endmodule
312 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
313 17 unneback
parameter depth = 10;
314
input d, ce;
315
output q;
316
input clk, rst;
317
reg [1:depth] dffs;
318
always @ (posedge clk or posedge rst)
319
if (rst)
320
    dffs <= {depth{1'b0}};
321
else
322
    if (ce)
323
        dffs <= {d,dffs[1:depth-1]};
324
assign q = dffs[depth];
325
endmodule
326 18 unneback
module vl_delay ( d, q, clk, rst);
327 15 unneback
parameter depth = 10;
328
input d;
329
output q;
330
input clk, rst;
331
reg [1:depth] dffs;
332
always @ (posedge clk or posedge rst)
333
if (rst)
334
    dffs <= {depth{1'b0}};
335
else
336
    dffs <= {d,dffs[1:depth-1]};
337
assign q = dffs[depth];
338
endmodule
339 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
340 17 unneback
parameter depth = 10;
341
input d;
342
output q, emptyflag;
343
input clk, rst;
344
reg [1:depth] dffs;
345
always @ (posedge clk or posedge rst)
346
if (rst)
347
    dffs <= {depth{1'b0}};
348
else
349
    dffs <= {d,dffs[1:depth-1]};
350
assign q = dffs[depth];
351
assign emptyflag = !(|dffs);
352
endmodule
353 6 unneback
//////////////////////////////////////////////////////////////////////
354
////                                                              ////
355 18 unneback
////  Logic functions                                             ////
356
////                                                              ////
357
////  Description                                                 ////
358
////  Logic functions such as multiplexers                        ////
359
////                                                              ////
360
////                                                              ////
361
////  To Do:                                                      ////
362
////   -                                                          ////
363
////                                                              ////
364
////  Author(s):                                                  ////
365
////      - Michael Unneback, unneback@opencores.org              ////
366
////        ORSoC AB                                              ////
367
////                                                              ////
368
//////////////////////////////////////////////////////////////////////
369
////                                                              ////
370
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
371
////                                                              ////
372
//// This source file may be used and distributed without         ////
373
//// restriction provided that this copyright statement is not    ////
374
//// removed from the file and that any derivative work contains  ////
375
//// the original copyright notice and the associated disclaimer. ////
376
////                                                              ////
377
//// This source file is free software; you can redistribute it   ////
378
//// and/or modify it under the terms of the GNU Lesser General   ////
379
//// Public License as published by the Free Software Foundation; ////
380
//// either version 2.1 of the License, or (at your option) any   ////
381
//// later version.                                               ////
382
////                                                              ////
383
//// This source is distributed in the hope that it will be       ////
384
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
385
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
386
//// PURPOSE.  See the GNU Lesser General Public License for more ////
387
//// details.                                                     ////
388
////                                                              ////
389
//// You should have received a copy of the GNU Lesser General    ////
390
//// Public License along with this source; if not, download it   ////
391
//// from http://www.opencores.org/lgpl.shtml                     ////
392
////                                                              ////
393
//////////////////////////////////////////////////////////////////////
394
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
395
parameter width = 32;
396
parameter nr_of_ports = 4;
397
input [width-1:0] a3, a2, a1, a0;
398
input [nr_of_ports-1:0] sel;
399 22 unneback
output [width-1:0] dout;
400 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
401 18 unneback
integer i;
402
// and
403
assign tmp[0] = {width{sel[0]}} & a0;
404
assign tmp[1] = {width{sel[1]}} & a1;
405
assign tmp[2] = {width{sel[2]}} & a2;
406
assign tmp[3] = {width{sel[3]}} & a3;
407
// or
408
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
409
endmodule
410
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
411
parameter width = 32;
412
parameter nr_of_ports = 5;
413
input [width-1:0] a4, a3, a2, a1, a0;
414
input [nr_of_ports-1:0] sel;
415 22 unneback
output [width-1:0] dout;
416 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
417 18 unneback
integer i;
418
// and
419
assign tmp[0] = {width{sel[0]}} & a0;
420
assign tmp[1] = {width{sel[1]}} & a1;
421
assign tmp[2] = {width{sel[2]}} & a2;
422
assign tmp[3] = {width{sel[3]}} & a3;
423
assign tmp[4] = {width{sel[4]}} & a4;
424
// or
425
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
426
endmodule
427
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
428
parameter width = 32;
429
parameter nr_of_ports = 6;
430
input [width-1:0] a5, a4, a3, a2, a1, a0;
431
input [nr_of_ports-1:0] sel;
432 22 unneback
output [width-1:0] dout;
433 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
434 18 unneback
integer i;
435
// and
436
assign tmp[0] = {width{sel[0]}} & a0;
437
assign tmp[1] = {width{sel[1]}} & a1;
438
assign tmp[2] = {width{sel[2]}} & a2;
439
assign tmp[3] = {width{sel[3]}} & a3;
440
assign tmp[4] = {width{sel[4]}} & a4;
441
assign tmp[5] = {width{sel[5]}} & a5;
442
// or
443
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
444
endmodule
445
//////////////////////////////////////////////////////////////////////
446
////                                                              ////
447 6 unneback
////  Versatile counter                                           ////
448
////                                                              ////
449
////  Description                                                 ////
450
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
451
////  counter                                                     ////
452
////                                                              ////
453
////  To Do:                                                      ////
454
////   - add LFSR with more taps                                  ////
455
////                                                              ////
456
////  Author(s):                                                  ////
457
////      - Michael Unneback, unneback@opencores.org              ////
458
////        ORSoC AB                                              ////
459
////                                                              ////
460
//////////////////////////////////////////////////////////////////////
461
////                                                              ////
462
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
463
////                                                              ////
464
//// This source file may be used and distributed without         ////
465
//// restriction provided that this copyright statement is not    ////
466
//// removed from the file and that any derivative work contains  ////
467
//// the original copyright notice and the associated disclaimer. ////
468
////                                                              ////
469
//// This source file is free software; you can redistribute it   ////
470
//// and/or modify it under the terms of the GNU Lesser General   ////
471
//// Public License as published by the Free Software Foundation; ////
472
//// either version 2.1 of the License, or (at your option) any   ////
473
//// later version.                                               ////
474
////                                                              ////
475
//// This source is distributed in the hope that it will be       ////
476
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
477
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
478
//// PURPOSE.  See the GNU Lesser General Public License for more ////
479
//// details.                                                     ////
480
////                                                              ////
481
//// You should have received a copy of the GNU Lesser General    ////
482
//// Public License along with this source; if not, download it   ////
483
//// from http://www.opencores.org/lgpl.shtml                     ////
484
////                                                              ////
485
//////////////////////////////////////////////////////////////////////
486
// binary counter
487 22 unneback
module vl_cnt_bin ( q, rst, clk);
488
   parameter length = 4;
489
   output [length:1] q;
490
   input rst;
491
   input clk;
492
   parameter clear_value = 0;
493
   parameter set_value = 1;
494
   parameter wrap_value = 0;
495
   parameter level1_value = 15;
496
   reg  [length:1] qi;
497
   wire [length:1] q_next;
498
   assign q_next = qi + {{length-1{1'b0}},1'b1};
499
   always @ (posedge clk or posedge rst)
500
     if (rst)
501
       qi <= {length{1'b0}};
502
     else
503
       qi <= q_next;
504
   assign q = qi;
505
endmodule
506
//////////////////////////////////////////////////////////////////////
507
////                                                              ////
508
////  Versatile counter                                           ////
509
////                                                              ////
510
////  Description                                                 ////
511
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
512
////  counter                                                     ////
513
////                                                              ////
514
////  To Do:                                                      ////
515
////   - add LFSR with more taps                                  ////
516
////                                                              ////
517
////  Author(s):                                                  ////
518
////      - Michael Unneback, unneback@opencores.org              ////
519
////        ORSoC AB                                              ////
520
////                                                              ////
521
//////////////////////////////////////////////////////////////////////
522
////                                                              ////
523
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
524
////                                                              ////
525
//// This source file may be used and distributed without         ////
526
//// restriction provided that this copyright statement is not    ////
527
//// removed from the file and that any derivative work contains  ////
528
//// the original copyright notice and the associated disclaimer. ////
529
////                                                              ////
530
//// This source file is free software; you can redistribute it   ////
531
//// and/or modify it under the terms of the GNU Lesser General   ////
532
//// Public License as published by the Free Software Foundation; ////
533
//// either version 2.1 of the License, or (at your option) any   ////
534
//// later version.                                               ////
535
////                                                              ////
536
//// This source is distributed in the hope that it will be       ////
537
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
538
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
539
//// PURPOSE.  See the GNU Lesser General Public License for more ////
540
//// details.                                                     ////
541
////                                                              ////
542
//// You should have received a copy of the GNU Lesser General    ////
543
//// Public License along with this source; if not, download it   ////
544
//// from http://www.opencores.org/lgpl.shtml                     ////
545
////                                                              ////
546
//////////////////////////////////////////////////////////////////////
547
// binary counter
548
module vl_cnt_bin_clear ( clear, q, rst, clk);
549
   parameter length = 4;
550
   input clear;
551
   output [length:1] q;
552
   input rst;
553
   input clk;
554
   parameter clear_value = 0;
555
   parameter set_value = 1;
556
   parameter wrap_value = 0;
557
   parameter level1_value = 15;
558
   reg  [length:1] qi;
559
   wire [length:1] q_next;
560
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
561
   always @ (posedge clk or posedge rst)
562
     if (rst)
563
       qi <= {length{1'b0}};
564
     else
565
       qi <= q_next;
566
   assign q = qi;
567
endmodule
568
//////////////////////////////////////////////////////////////////////
569
////                                                              ////
570
////  Versatile counter                                           ////
571
////                                                              ////
572
////  Description                                                 ////
573
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
574
////  counter                                                     ////
575
////                                                              ////
576
////  To Do:                                                      ////
577
////   - add LFSR with more taps                                  ////
578
////                                                              ////
579
////  Author(s):                                                  ////
580
////      - Michael Unneback, unneback@opencores.org              ////
581
////        ORSoC AB                                              ////
582
////                                                              ////
583
//////////////////////////////////////////////////////////////////////
584
////                                                              ////
585
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
586
////                                                              ////
587
//// This source file may be used and distributed without         ////
588
//// restriction provided that this copyright statement is not    ////
589
//// removed from the file and that any derivative work contains  ////
590
//// the original copyright notice and the associated disclaimer. ////
591
////                                                              ////
592
//// This source file is free software; you can redistribute it   ////
593
//// and/or modify it under the terms of the GNU Lesser General   ////
594
//// Public License as published by the Free Software Foundation; ////
595
//// either version 2.1 of the License, or (at your option) any   ////
596
//// later version.                                               ////
597
////                                                              ////
598
//// This source is distributed in the hope that it will be       ////
599
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
600
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
601
//// PURPOSE.  See the GNU Lesser General Public License for more ////
602
//// details.                                                     ////
603
////                                                              ////
604
//// You should have received a copy of the GNU Lesser General    ////
605
//// Public License along with this source; if not, download it   ////
606
//// from http://www.opencores.org/lgpl.shtml                     ////
607
////                                                              ////
608
//////////////////////////////////////////////////////////////////////
609
// binary counter
610 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
611 6 unneback
   parameter length = 4;
612
   input cke;
613
   output [length:1] q;
614
   input rst;
615
   input clk;
616
   parameter clear_value = 0;
617
   parameter set_value = 1;
618
   parameter wrap_value = 0;
619
   parameter level1_value = 15;
620
   reg  [length:1] qi;
621
   wire [length:1] q_next;
622
   assign q_next = qi + {{length-1{1'b0}},1'b1};
623
   always @ (posedge clk or posedge rst)
624
     if (rst)
625
       qi <= {length{1'b0}};
626
     else
627
     if (cke)
628
       qi <= q_next;
629
   assign q = qi;
630
endmodule
631
//////////////////////////////////////////////////////////////////////
632
////                                                              ////
633
////  Versatile counter                                           ////
634
////                                                              ////
635
////  Description                                                 ////
636
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
637
////  counter                                                     ////
638
////                                                              ////
639
////  To Do:                                                      ////
640
////   - add LFSR with more taps                                  ////
641
////                                                              ////
642
////  Author(s):                                                  ////
643
////      - Michael Unneback, unneback@opencores.org              ////
644
////        ORSoC AB                                              ////
645
////                                                              ////
646
//////////////////////////////////////////////////////////////////////
647
////                                                              ////
648
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
649
////                                                              ////
650
//// This source file may be used and distributed without         ////
651
//// restriction provided that this copyright statement is not    ////
652
//// removed from the file and that any derivative work contains  ////
653
//// the original copyright notice and the associated disclaimer. ////
654
////                                                              ////
655
//// This source file is free software; you can redistribute it   ////
656
//// and/or modify it under the terms of the GNU Lesser General   ////
657
//// Public License as published by the Free Software Foundation; ////
658
//// either version 2.1 of the License, or (at your option) any   ////
659
//// later version.                                               ////
660
////                                                              ////
661
//// This source is distributed in the hope that it will be       ////
662
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
663
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
664
//// PURPOSE.  See the GNU Lesser General Public License for more ////
665
//// details.                                                     ////
666
////                                                              ////
667
//// You should have received a copy of the GNU Lesser General    ////
668
//// Public License along with this source; if not, download it   ////
669
//// from http://www.opencores.org/lgpl.shtml                     ////
670
////                                                              ////
671
//////////////////////////////////////////////////////////////////////
672
// binary counter
673 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
674 6 unneback
   parameter length = 4;
675
   input clear;
676
   input cke;
677
   output [length:1] q;
678
   input rst;
679
   input clk;
680
   parameter clear_value = 0;
681
   parameter set_value = 1;
682
   parameter wrap_value = 0;
683
   parameter level1_value = 15;
684
   reg  [length:1] qi;
685
   wire [length:1] q_next;
686
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
687
   always @ (posedge clk or posedge rst)
688
     if (rst)
689
       qi <= {length{1'b0}};
690
     else
691
     if (cke)
692
       qi <= q_next;
693
   assign q = qi;
694
endmodule
695
//////////////////////////////////////////////////////////////////////
696
////                                                              ////
697
////  Versatile counter                                           ////
698
////                                                              ////
699
////  Description                                                 ////
700
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
701
////  counter                                                     ////
702
////                                                              ////
703
////  To Do:                                                      ////
704
////   - add LFSR with more taps                                  ////
705
////                                                              ////
706
////  Author(s):                                                  ////
707
////      - Michael Unneback, unneback@opencores.org              ////
708
////        ORSoC AB                                              ////
709
////                                                              ////
710
//////////////////////////////////////////////////////////////////////
711
////                                                              ////
712
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
713
////                                                              ////
714
//// This source file may be used and distributed without         ////
715
//// restriction provided that this copyright statement is not    ////
716
//// removed from the file and that any derivative work contains  ////
717
//// the original copyright notice and the associated disclaimer. ////
718
////                                                              ////
719
//// This source file is free software; you can redistribute it   ////
720
//// and/or modify it under the terms of the GNU Lesser General   ////
721
//// Public License as published by the Free Software Foundation; ////
722
//// either version 2.1 of the License, or (at your option) any   ////
723
//// later version.                                               ////
724
////                                                              ////
725
//// This source is distributed in the hope that it will be       ////
726
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
727
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
728
//// PURPOSE.  See the GNU Lesser General Public License for more ////
729
//// details.                                                     ////
730
////                                                              ////
731
//// You should have received a copy of the GNU Lesser General    ////
732
//// Public License along with this source; if not, download it   ////
733
//// from http://www.opencores.org/lgpl.shtml                     ////
734
////                                                              ////
735
//////////////////////////////////////////////////////////////////////
736
// binary counter
737 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
738 6 unneback
   parameter length = 4;
739
   input clear;
740
   input set;
741
   input cke;
742
   input rew;
743
   output [length:1] q;
744
   input rst;
745
   input clk;
746
   parameter clear_value = 0;
747
   parameter set_value = 1;
748
   parameter wrap_value = 0;
749
   parameter level1_value = 15;
750
   reg  [length:1] qi;
751
   wire  [length:1] q_next, q_next_fw, q_next_rew;
752
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
753
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
754
   assign q_next = rew ? q_next_rew : q_next_fw;
755
   always @ (posedge clk or posedge rst)
756
     if (rst)
757
       qi <= {length{1'b0}};
758
     else
759
     if (cke)
760
       qi <= q_next;
761
   assign q = qi;
762
endmodule
763
//////////////////////////////////////////////////////////////////////
764
////                                                              ////
765
////  Versatile counter                                           ////
766
////                                                              ////
767
////  Description                                                 ////
768
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
769
////  counter                                                     ////
770
////                                                              ////
771
////  To Do:                                                      ////
772
////   - add LFSR with more taps                                  ////
773
////                                                              ////
774
////  Author(s):                                                  ////
775
////      - Michael Unneback, unneback@opencores.org              ////
776
////        ORSoC AB                                              ////
777
////                                                              ////
778
//////////////////////////////////////////////////////////////////////
779
////                                                              ////
780
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
781
////                                                              ////
782
//// This source file may be used and distributed without         ////
783
//// restriction provided that this copyright statement is not    ////
784
//// removed from the file and that any derivative work contains  ////
785
//// the original copyright notice and the associated disclaimer. ////
786
////                                                              ////
787
//// This source file is free software; you can redistribute it   ////
788
//// and/or modify it under the terms of the GNU Lesser General   ////
789
//// Public License as published by the Free Software Foundation; ////
790
//// either version 2.1 of the License, or (at your option) any   ////
791
//// later version.                                               ////
792
////                                                              ////
793
//// This source is distributed in the hope that it will be       ////
794
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
795
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
796
//// PURPOSE.  See the GNU Lesser General Public License for more ////
797
//// details.                                                     ////
798
////                                                              ////
799
//// You should have received a copy of the GNU Lesser General    ////
800
//// Public License along with this source; if not, download it   ////
801
//// from http://www.opencores.org/lgpl.shtml                     ////
802
////                                                              ////
803
//////////////////////////////////////////////////////////////////////
804
// binary counter
805 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
806 6 unneback
   parameter length = 4;
807
   input cke;
808
   input rew;
809
   output reg level1;
810
   input rst;
811
   input clk;
812
   parameter clear_value = 0;
813
   parameter set_value = 1;
814
   parameter wrap_value = 1;
815
   parameter level1_value = 15;
816
   reg  [length:1] qi;
817
   wire  [length:1] q_next, q_next_fw, q_next_rew;
818
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
819
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
820
   assign q_next = rew ? q_next_rew : q_next_fw;
821
   always @ (posedge clk or posedge rst)
822
     if (rst)
823
       qi <= {length{1'b0}};
824
     else
825
     if (cke)
826
       qi <= q_next;
827
    always @ (posedge clk or posedge rst)
828
    if (rst)
829
        level1 <= 1'b0;
830
    else
831
    if (cke)
832
    if (q_next == level1_value)
833
        level1 <= 1'b1;
834
    else if (qi == level1_value & rew)
835
        level1 <= 1'b0;
836
endmodule
837
//////////////////////////////////////////////////////////////////////
838
////                                                              ////
839
////  Versatile counter                                           ////
840
////                                                              ////
841
////  Description                                                 ////
842
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
843
////  counter                                                     ////
844
////                                                              ////
845
////  To Do:                                                      ////
846
////   - add LFSR with more taps                                  ////
847
////                                                              ////
848
////  Author(s):                                                  ////
849
////      - Michael Unneback, unneback@opencores.org              ////
850
////        ORSoC AB                                              ////
851
////                                                              ////
852
//////////////////////////////////////////////////////////////////////
853
////                                                              ////
854
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
855
////                                                              ////
856
//// This source file may be used and distributed without         ////
857
//// restriction provided that this copyright statement is not    ////
858
//// removed from the file and that any derivative work contains  ////
859
//// the original copyright notice and the associated disclaimer. ////
860
////                                                              ////
861
//// This source file is free software; you can redistribute it   ////
862
//// and/or modify it under the terms of the GNU Lesser General   ////
863
//// Public License as published by the Free Software Foundation; ////
864
//// either version 2.1 of the License, or (at your option) any   ////
865
//// later version.                                               ////
866
////                                                              ////
867
//// This source is distributed in the hope that it will be       ////
868
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
869
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
870
//// PURPOSE.  See the GNU Lesser General Public License for more ////
871
//// details.                                                     ////
872
////                                                              ////
873
//// You should have received a copy of the GNU Lesser General    ////
874
//// Public License along with this source; if not, download it   ////
875
//// from http://www.opencores.org/lgpl.shtml                     ////
876
////                                                              ////
877
//////////////////////////////////////////////////////////////////////
878 25 unneback
// binary counter
879
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
880
   parameter length = 4;
881
   input cke;
882
   input rew;
883
   output reg zq;
884
   output reg level1;
885
   input rst;
886
   input clk;
887
   parameter clear_value = 0;
888
   parameter set_value = 1;
889
   parameter wrap_value = 1;
890
   parameter level1_value = 15;
891
   reg  [length:1] qi;
892
   wire  [length:1] q_next, q_next_fw, q_next_rew;
893
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
894
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
895
   assign q_next = rew ? q_next_rew : q_next_fw;
896
   always @ (posedge clk or posedge rst)
897
     if (rst)
898
       qi <= {length{1'b0}};
899
     else
900
     if (cke)
901
       qi <= q_next;
902
   always @ (posedge clk or posedge rst)
903
     if (rst)
904
       zq <= 1'b1;
905
     else
906
     if (cke)
907
       zq <= q_next == {length{1'b0}};
908
    always @ (posedge clk or posedge rst)
909
    if (rst)
910
        level1 <= 1'b0;
911
    else
912
    if (cke)
913
    if (q_next == level1_value)
914
        level1 <= 1'b1;
915
    else if (qi == level1_value & rew)
916
        level1 <= 1'b0;
917
endmodule
918
//////////////////////////////////////////////////////////////////////
919
////                                                              ////
920
////  Versatile counter                                           ////
921
////                                                              ////
922
////  Description                                                 ////
923
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
924
////  counter                                                     ////
925
////                                                              ////
926
////  To Do:                                                      ////
927
////   - add LFSR with more taps                                  ////
928
////                                                              ////
929
////  Author(s):                                                  ////
930
////      - Michael Unneback, unneback@opencores.org              ////
931
////        ORSoC AB                                              ////
932
////                                                              ////
933
//////////////////////////////////////////////////////////////////////
934
////                                                              ////
935
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
936
////                                                              ////
937
//// This source file may be used and distributed without         ////
938
//// restriction provided that this copyright statement is not    ////
939
//// removed from the file and that any derivative work contains  ////
940
//// the original copyright notice and the associated disclaimer. ////
941
////                                                              ////
942
//// This source file is free software; you can redistribute it   ////
943
//// and/or modify it under the terms of the GNU Lesser General   ////
944
//// Public License as published by the Free Software Foundation; ////
945
//// either version 2.1 of the License, or (at your option) any   ////
946
//// later version.                                               ////
947
////                                                              ////
948
//// This source is distributed in the hope that it will be       ////
949
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
950
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
951
//// PURPOSE.  See the GNU Lesser General Public License for more ////
952
//// details.                                                     ////
953
////                                                              ////
954
//// You should have received a copy of the GNU Lesser General    ////
955
//// Public License along with this source; if not, download it   ////
956
//// from http://www.opencores.org/lgpl.shtml                     ////
957
////                                                              ////
958
//////////////////////////////////////////////////////////////////////
959
// binary counter
960
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
961
   parameter length = 4;
962
   input cke;
963
   input rew;
964
   output [length:1] q;
965
   output reg zq;
966
   output reg level1;
967
   input rst;
968
   input clk;
969
   parameter clear_value = 0;
970
   parameter set_value = 1;
971
   parameter wrap_value = 1;
972
   parameter level1_value = 15;
973
   reg  [length:1] qi;
974
   wire  [length:1] q_next, q_next_fw, q_next_rew;
975
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
976
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
977
   assign q_next = rew ? q_next_rew : q_next_fw;
978
   always @ (posedge clk or posedge rst)
979
     if (rst)
980
       qi <= {length{1'b0}};
981
     else
982
     if (cke)
983
       qi <= q_next;
984
   assign q = qi;
985
   always @ (posedge clk or posedge rst)
986
     if (rst)
987
       zq <= 1'b1;
988
     else
989
     if (cke)
990
       zq <= q_next == {length{1'b0}};
991
    always @ (posedge clk or posedge rst)
992
    if (rst)
993
        level1 <= 1'b0;
994
    else
995
    if (cke)
996
    if (q_next == level1_value)
997
        level1 <= 1'b1;
998
    else if (qi == level1_value & rew)
999
        level1 <= 1'b0;
1000
endmodule
1001
//////////////////////////////////////////////////////////////////////
1002
////                                                              ////
1003
////  Versatile counter                                           ////
1004
////                                                              ////
1005
////  Description                                                 ////
1006
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1007
////  counter                                                     ////
1008
////                                                              ////
1009
////  To Do:                                                      ////
1010
////   - add LFSR with more taps                                  ////
1011
////                                                              ////
1012
////  Author(s):                                                  ////
1013
////      - Michael Unneback, unneback@opencores.org              ////
1014
////        ORSoC AB                                              ////
1015
////                                                              ////
1016
//////////////////////////////////////////////////////////////////////
1017
////                                                              ////
1018
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1019
////                                                              ////
1020
//// This source file may be used and distributed without         ////
1021
//// restriction provided that this copyright statement is not    ////
1022
//// removed from the file and that any derivative work contains  ////
1023
//// the original copyright notice and the associated disclaimer. ////
1024
////                                                              ////
1025
//// This source file is free software; you can redistribute it   ////
1026
//// and/or modify it under the terms of the GNU Lesser General   ////
1027
//// Public License as published by the Free Software Foundation; ////
1028
//// either version 2.1 of the License, or (at your option) any   ////
1029
//// later version.                                               ////
1030
////                                                              ////
1031
//// This source is distributed in the hope that it will be       ////
1032
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1033
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1034
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1035
//// details.                                                     ////
1036
////                                                              ////
1037
//// You should have received a copy of the GNU Lesser General    ////
1038
//// Public License along with this source; if not, download it   ////
1039
//// from http://www.opencores.org/lgpl.shtml                     ////
1040
////                                                              ////
1041
//////////////////////////////////////////////////////////////////////
1042 6 unneback
// LFSR counter
1043 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1044 6 unneback
   parameter length = 4;
1045
   output reg zq;
1046
   input rst;
1047
   input clk;
1048
   parameter clear_value = 0;
1049
   parameter set_value = 1;
1050
   parameter wrap_value = 8;
1051
   parameter level1_value = 15;
1052
   reg  [length:1] qi;
1053
   reg lfsr_fb;
1054
   wire [length:1] q_next;
1055
   reg [32:1] polynom;
1056
   integer i;
1057
   always @ (qi)
1058
   begin
1059
        case (length)
1060
         2: polynom = 32'b11;                               // 0x3
1061
         3: polynom = 32'b110;                              // 0x6
1062
         4: polynom = 32'b1100;                             // 0xC
1063
         5: polynom = 32'b10100;                            // 0x14
1064
         6: polynom = 32'b110000;                           // 0x30
1065
         7: polynom = 32'b1100000;                          // 0x60
1066
         8: polynom = 32'b10111000;                         // 0xb8
1067
         9: polynom = 32'b100010000;                        // 0x110
1068
        10: polynom = 32'b1001000000;                       // 0x240
1069
        11: polynom = 32'b10100000000;                      // 0x500
1070
        12: polynom = 32'b100000101001;                     // 0x829
1071
        13: polynom = 32'b1000000001100;                    // 0x100C
1072
        14: polynom = 32'b10000000010101;                   // 0x2015
1073
        15: polynom = 32'b110000000000000;                  // 0x6000
1074
        16: polynom = 32'b1101000000001000;                 // 0xD008
1075
        17: polynom = 32'b10010000000000000;                // 0x12000
1076
        18: polynom = 32'b100000010000000000;               // 0x20400
1077
        19: polynom = 32'b1000000000000100011;              // 0x40023
1078
        20: polynom = 32'b10000010000000000000;             // 0x82000
1079
        21: polynom = 32'b101000000000000000000;            // 0x140000
1080
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1081
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1082
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1083
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1084
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1085
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1086
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1087
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1088
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1089
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1090
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1091
        default: polynom = 32'b0;
1092
        endcase
1093
        lfsr_fb = qi[length];
1094
        for (i=length-1; i>=1; i=i-1) begin
1095
            if (polynom[i])
1096
                lfsr_fb = lfsr_fb  ~^ qi[i];
1097
        end
1098
    end
1099
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1100
   always @ (posedge clk or posedge rst)
1101
     if (rst)
1102
       qi <= {length{1'b0}};
1103
     else
1104
       qi <= q_next;
1105
   always @ (posedge clk or posedge rst)
1106
     if (rst)
1107
       zq <= 1'b1;
1108
     else
1109
       zq <= q_next == {length{1'b0}};
1110
endmodule
1111
//////////////////////////////////////////////////////////////////////
1112
////                                                              ////
1113
////  Versatile counter                                           ////
1114
////                                                              ////
1115
////  Description                                                 ////
1116
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1117
////  counter                                                     ////
1118
////                                                              ////
1119
////  To Do:                                                      ////
1120
////   - add LFSR with more taps                                  ////
1121
////                                                              ////
1122
////  Author(s):                                                  ////
1123
////      - Michael Unneback, unneback@opencores.org              ////
1124
////        ORSoC AB                                              ////
1125
////                                                              ////
1126
//////////////////////////////////////////////////////////////////////
1127
////                                                              ////
1128
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1129
////                                                              ////
1130
//// This source file may be used and distributed without         ////
1131
//// restriction provided that this copyright statement is not    ////
1132
//// removed from the file and that any derivative work contains  ////
1133
//// the original copyright notice and the associated disclaimer. ////
1134
////                                                              ////
1135
//// This source file is free software; you can redistribute it   ////
1136
//// and/or modify it under the terms of the GNU Lesser General   ////
1137
//// Public License as published by the Free Software Foundation; ////
1138
//// either version 2.1 of the License, or (at your option) any   ////
1139
//// later version.                                               ////
1140
////                                                              ////
1141
//// This source is distributed in the hope that it will be       ////
1142
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1143
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1144
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1145
//// details.                                                     ////
1146
////                                                              ////
1147
//// You should have received a copy of the GNU Lesser General    ////
1148
//// Public License along with this source; if not, download it   ////
1149
//// from http://www.opencores.org/lgpl.shtml                     ////
1150
////                                                              ////
1151
//////////////////////////////////////////////////////////////////////
1152
// LFSR counter
1153 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1154 6 unneback
   parameter length = 4;
1155
   input cke;
1156
   output reg zq;
1157
   input rst;
1158
   input clk;
1159
   parameter clear_value = 0;
1160
   parameter set_value = 1;
1161
   parameter wrap_value = 8;
1162
   parameter level1_value = 15;
1163
   reg  [length:1] qi;
1164
   reg lfsr_fb;
1165
   wire [length:1] q_next;
1166
   reg [32:1] polynom;
1167
   integer i;
1168
   always @ (qi)
1169
   begin
1170
        case (length)
1171
         2: polynom = 32'b11;                               // 0x3
1172
         3: polynom = 32'b110;                              // 0x6
1173
         4: polynom = 32'b1100;                             // 0xC
1174
         5: polynom = 32'b10100;                            // 0x14
1175
         6: polynom = 32'b110000;                           // 0x30
1176
         7: polynom = 32'b1100000;                          // 0x60
1177
         8: polynom = 32'b10111000;                         // 0xb8
1178
         9: polynom = 32'b100010000;                        // 0x110
1179
        10: polynom = 32'b1001000000;                       // 0x240
1180
        11: polynom = 32'b10100000000;                      // 0x500
1181
        12: polynom = 32'b100000101001;                     // 0x829
1182
        13: polynom = 32'b1000000001100;                    // 0x100C
1183
        14: polynom = 32'b10000000010101;                   // 0x2015
1184
        15: polynom = 32'b110000000000000;                  // 0x6000
1185
        16: polynom = 32'b1101000000001000;                 // 0xD008
1186
        17: polynom = 32'b10010000000000000;                // 0x12000
1187
        18: polynom = 32'b100000010000000000;               // 0x20400
1188
        19: polynom = 32'b1000000000000100011;              // 0x40023
1189
        20: polynom = 32'b10000010000000000000;             // 0x82000
1190
        21: polynom = 32'b101000000000000000000;            // 0x140000
1191
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1192
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1193
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1194
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1195
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1196
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1197
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1198
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1199
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1200
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1201
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1202
        default: polynom = 32'b0;
1203
        endcase
1204
        lfsr_fb = qi[length];
1205
        for (i=length-1; i>=1; i=i-1) begin
1206
            if (polynom[i])
1207
                lfsr_fb = lfsr_fb  ~^ qi[i];
1208
        end
1209
    end
1210
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1211
   always @ (posedge clk or posedge rst)
1212
     if (rst)
1213
       qi <= {length{1'b0}};
1214
     else
1215
     if (cke)
1216
       qi <= q_next;
1217
   always @ (posedge clk or posedge rst)
1218
     if (rst)
1219
       zq <= 1'b1;
1220
     else
1221
     if (cke)
1222
       zq <= q_next == {length{1'b0}};
1223
endmodule
1224
//////////////////////////////////////////////////////////////////////
1225
////                                                              ////
1226
////  Versatile counter                                           ////
1227
////                                                              ////
1228
////  Description                                                 ////
1229
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1230
////  counter                                                     ////
1231
////                                                              ////
1232
////  To Do:                                                      ////
1233
////   - add LFSR with more taps                                  ////
1234
////                                                              ////
1235
////  Author(s):                                                  ////
1236
////      - Michael Unneback, unneback@opencores.org              ////
1237
////        ORSoC AB                                              ////
1238
////                                                              ////
1239
//////////////////////////////////////////////////////////////////////
1240
////                                                              ////
1241
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1242
////                                                              ////
1243
//// This source file may be used and distributed without         ////
1244
//// restriction provided that this copyright statement is not    ////
1245
//// removed from the file and that any derivative work contains  ////
1246
//// the original copyright notice and the associated disclaimer. ////
1247
////                                                              ////
1248
//// This source file is free software; you can redistribute it   ////
1249
//// and/or modify it under the terms of the GNU Lesser General   ////
1250
//// Public License as published by the Free Software Foundation; ////
1251
//// either version 2.1 of the License, or (at your option) any   ////
1252
//// later version.                                               ////
1253
////                                                              ////
1254
//// This source is distributed in the hope that it will be       ////
1255
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1256
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1257
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1258
//// details.                                                     ////
1259
////                                                              ////
1260
//// You should have received a copy of the GNU Lesser General    ////
1261
//// Public License along with this source; if not, download it   ////
1262
//// from http://www.opencores.org/lgpl.shtml                     ////
1263
////                                                              ////
1264
//////////////////////////////////////////////////////////////////////
1265
// LFSR counter
1266 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1267
   parameter length = 4;
1268
   input cke;
1269
   output [length:1] q;
1270
   output reg zq;
1271
   input rst;
1272
   input clk;
1273
   parameter clear_value = 0;
1274
   parameter set_value = 1;
1275
   parameter wrap_value = 8;
1276
   parameter level1_value = 15;
1277
   reg  [length:1] qi;
1278
   reg lfsr_fb;
1279
   wire [length:1] q_next;
1280
   reg [32:1] polynom;
1281
   integer i;
1282
   always @ (qi)
1283
   begin
1284
        case (length)
1285
         2: polynom = 32'b11;                               // 0x3
1286
         3: polynom = 32'b110;                              // 0x6
1287
         4: polynom = 32'b1100;                             // 0xC
1288
         5: polynom = 32'b10100;                            // 0x14
1289
         6: polynom = 32'b110000;                           // 0x30
1290
         7: polynom = 32'b1100000;                          // 0x60
1291
         8: polynom = 32'b10111000;                         // 0xb8
1292
         9: polynom = 32'b100010000;                        // 0x110
1293
        10: polynom = 32'b1001000000;                       // 0x240
1294
        11: polynom = 32'b10100000000;                      // 0x500
1295
        12: polynom = 32'b100000101001;                     // 0x829
1296
        13: polynom = 32'b1000000001100;                    // 0x100C
1297
        14: polynom = 32'b10000000010101;                   // 0x2015
1298
        15: polynom = 32'b110000000000000;                  // 0x6000
1299
        16: polynom = 32'b1101000000001000;                 // 0xD008
1300
        17: polynom = 32'b10010000000000000;                // 0x12000
1301
        18: polynom = 32'b100000010000000000;               // 0x20400
1302
        19: polynom = 32'b1000000000000100011;              // 0x40023
1303
        20: polynom = 32'b10000010000000000000;             // 0x82000
1304
        21: polynom = 32'b101000000000000000000;            // 0x140000
1305
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1306
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1307
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1308
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1309
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1310
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1311
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1312
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1313
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1314
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1315
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1316
        default: polynom = 32'b0;
1317
        endcase
1318
        lfsr_fb = qi[length];
1319
        for (i=length-1; i>=1; i=i-1) begin
1320
            if (polynom[i])
1321
                lfsr_fb = lfsr_fb  ~^ qi[i];
1322
        end
1323
    end
1324
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1325
   always @ (posedge clk or posedge rst)
1326
     if (rst)
1327
       qi <= {length{1'b0}};
1328
     else
1329
     if (cke)
1330
       qi <= q_next;
1331
   assign q = qi;
1332
   always @ (posedge clk or posedge rst)
1333
     if (rst)
1334
       zq <= 1'b1;
1335
     else
1336
     if (cke)
1337
       zq <= q_next == {length{1'b0}};
1338
endmodule
1339
//////////////////////////////////////////////////////////////////////
1340
////                                                              ////
1341
////  Versatile counter                                           ////
1342
////                                                              ////
1343
////  Description                                                 ////
1344
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1345
////  counter                                                     ////
1346
////                                                              ////
1347
////  To Do:                                                      ////
1348
////   - add LFSR with more taps                                  ////
1349
////                                                              ////
1350
////  Author(s):                                                  ////
1351
////      - Michael Unneback, unneback@opencores.org              ////
1352
////        ORSoC AB                                              ////
1353
////                                                              ////
1354
//////////////////////////////////////////////////////////////////////
1355
////                                                              ////
1356
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1357
////                                                              ////
1358
//// This source file may be used and distributed without         ////
1359
//// restriction provided that this copyright statement is not    ////
1360
//// removed from the file and that any derivative work contains  ////
1361
//// the original copyright notice and the associated disclaimer. ////
1362
////                                                              ////
1363
//// This source file is free software; you can redistribute it   ////
1364
//// and/or modify it under the terms of the GNU Lesser General   ////
1365
//// Public License as published by the Free Software Foundation; ////
1366
//// either version 2.1 of the License, or (at your option) any   ////
1367
//// later version.                                               ////
1368
////                                                              ////
1369
//// This source is distributed in the hope that it will be       ////
1370
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1371
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1372
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1373
//// details.                                                     ////
1374
////                                                              ////
1375
//// You should have received a copy of the GNU Lesser General    ////
1376
//// Public License along with this source; if not, download it   ////
1377
//// from http://www.opencores.org/lgpl.shtml                     ////
1378
////                                                              ////
1379
//////////////////////////////////////////////////////////////////////
1380
// LFSR counter
1381 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1382 6 unneback
   parameter length = 4;
1383
   input cke;
1384
   input rew;
1385
   output reg level1;
1386
   input rst;
1387
   input clk;
1388
   parameter clear_value = 0;
1389
   parameter set_value = 1;
1390
   parameter wrap_value = 8;
1391
   parameter level1_value = 15;
1392
   reg  [length:1] qi;
1393
   reg lfsr_fb, lfsr_fb_rew;
1394
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1395
   reg [32:1] polynom_rew;
1396
   integer j;
1397
   reg [32:1] polynom;
1398
   integer i;
1399
   always @ (qi)
1400
   begin
1401
        case (length)
1402
         2: polynom = 32'b11;                               // 0x3
1403
         3: polynom = 32'b110;                              // 0x6
1404
         4: polynom = 32'b1100;                             // 0xC
1405
         5: polynom = 32'b10100;                            // 0x14
1406
         6: polynom = 32'b110000;                           // 0x30
1407
         7: polynom = 32'b1100000;                          // 0x60
1408
         8: polynom = 32'b10111000;                         // 0xb8
1409
         9: polynom = 32'b100010000;                        // 0x110
1410
        10: polynom = 32'b1001000000;                       // 0x240
1411
        11: polynom = 32'b10100000000;                      // 0x500
1412
        12: polynom = 32'b100000101001;                     // 0x829
1413
        13: polynom = 32'b1000000001100;                    // 0x100C
1414
        14: polynom = 32'b10000000010101;                   // 0x2015
1415
        15: polynom = 32'b110000000000000;                  // 0x6000
1416
        16: polynom = 32'b1101000000001000;                 // 0xD008
1417
        17: polynom = 32'b10010000000000000;                // 0x12000
1418
        18: polynom = 32'b100000010000000000;               // 0x20400
1419
        19: polynom = 32'b1000000000000100011;              // 0x40023
1420
        20: polynom = 32'b10000010000000000000;             // 0x82000
1421
        21: polynom = 32'b101000000000000000000;            // 0x140000
1422
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1423
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1424
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1425
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1426
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1427
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1428
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1429
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1430
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1431
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1432
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1433
        default: polynom = 32'b0;
1434
        endcase
1435
        lfsr_fb = qi[length];
1436
        for (i=length-1; i>=1; i=i-1) begin
1437
            if (polynom[i])
1438
                lfsr_fb = lfsr_fb  ~^ qi[i];
1439
        end
1440
    end
1441
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1442
   always @ (qi)
1443
   begin
1444
        case (length)
1445
         2: polynom_rew = 32'b11;
1446
         3: polynom_rew = 32'b110;
1447
         4: polynom_rew = 32'b1100;
1448
         5: polynom_rew = 32'b10100;
1449
         6: polynom_rew = 32'b110000;
1450
         7: polynom_rew = 32'b1100000;
1451
         8: polynom_rew = 32'b10111000;
1452
         9: polynom_rew = 32'b100010000;
1453
        10: polynom_rew = 32'b1001000000;
1454
        11: polynom_rew = 32'b10100000000;
1455
        12: polynom_rew = 32'b100000101001;
1456
        13: polynom_rew = 32'b1000000001100;
1457
        14: polynom_rew = 32'b10000000010101;
1458
        15: polynom_rew = 32'b110000000000000;
1459
        16: polynom_rew = 32'b1101000000001000;
1460
        17: polynom_rew = 32'b10010000000000000;
1461
        18: polynom_rew = 32'b100000010000000000;
1462
        19: polynom_rew = 32'b1000000000000100011;
1463
        20: polynom_rew = 32'b10000010000000000000;
1464
        21: polynom_rew = 32'b101000000000000000000;
1465
        22: polynom_rew = 32'b1100000000000000000000;
1466
        23: polynom_rew = 32'b10000100000000000000000;
1467
        24: polynom_rew = 32'b111000010000000000000000;
1468
        25: polynom_rew = 32'b1001000000000000000000000;
1469
        26: polynom_rew = 32'b10000000000000000000100011;
1470
        27: polynom_rew = 32'b100000000000000000000010011;
1471
        28: polynom_rew = 32'b1100100000000000000000000000;
1472
        29: polynom_rew = 32'b10100000000000000000000000000;
1473
        30: polynom_rew = 32'b100000000000000000000000101001;
1474
        31: polynom_rew = 32'b1001000000000000000000000000000;
1475
        32: polynom_rew = 32'b10000000001000000000000000000011;
1476
        default: polynom_rew = 32'b0;
1477
        endcase
1478
        // rotate left
1479
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1480
        lfsr_fb_rew = qi[length];
1481
        for (i=length-1; i>=1; i=i-1) begin
1482
            if (polynom_rew[i])
1483
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1484
        end
1485
    end
1486
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1487
   assign q_next = rew ? q_next_rew : q_next_fw;
1488
   always @ (posedge clk or posedge rst)
1489
     if (rst)
1490
       qi <= {length{1'b0}};
1491
     else
1492
     if (cke)
1493
       qi <= q_next;
1494
    always @ (posedge clk or posedge rst)
1495
    if (rst)
1496
        level1 <= 1'b0;
1497
    else
1498
    if (cke)
1499
    if (q_next == level1_value)
1500
        level1 <= 1'b1;
1501
    else if (qi == level1_value & rew)
1502
        level1 <= 1'b0;
1503
endmodule
1504
//////////////////////////////////////////////////////////////////////
1505
////                                                              ////
1506
////  Versatile counter                                           ////
1507
////                                                              ////
1508
////  Description                                                 ////
1509
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1510
////  counter                                                     ////
1511
////                                                              ////
1512
////  To Do:                                                      ////
1513
////   - add LFSR with more taps                                  ////
1514
////                                                              ////
1515
////  Author(s):                                                  ////
1516
////      - Michael Unneback, unneback@opencores.org              ////
1517
////        ORSoC AB                                              ////
1518
////                                                              ////
1519
//////////////////////////////////////////////////////////////////////
1520
////                                                              ////
1521
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1522
////                                                              ////
1523
//// This source file may be used and distributed without         ////
1524
//// restriction provided that this copyright statement is not    ////
1525
//// removed from the file and that any derivative work contains  ////
1526
//// the original copyright notice and the associated disclaimer. ////
1527
////                                                              ////
1528
//// This source file is free software; you can redistribute it   ////
1529
//// and/or modify it under the terms of the GNU Lesser General   ////
1530
//// Public License as published by the Free Software Foundation; ////
1531
//// either version 2.1 of the License, or (at your option) any   ////
1532
//// later version.                                               ////
1533
////                                                              ////
1534
//// This source is distributed in the hope that it will be       ////
1535
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1536
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1537
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1538
//// details.                                                     ////
1539
////                                                              ////
1540
//// You should have received a copy of the GNU Lesser General    ////
1541
//// Public License along with this source; if not, download it   ////
1542
//// from http://www.opencores.org/lgpl.shtml                     ////
1543
////                                                              ////
1544
//////////////////////////////////////////////////////////////////////
1545
// GRAY counter
1546 18 unneback
module vl_cnt_gray ( q, rst, clk);
1547 6 unneback
   parameter length = 4;
1548
   output reg [length:1] q;
1549
   input rst;
1550
   input clk;
1551
   parameter clear_value = 0;
1552
   parameter set_value = 1;
1553
   parameter wrap_value = 8;
1554
   parameter level1_value = 15;
1555
   reg  [length:1] qi;
1556
   wire [length:1] q_next;
1557
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1558
   always @ (posedge clk or posedge rst)
1559
     if (rst)
1560
       qi <= {length{1'b0}};
1561
     else
1562
       qi <= q_next;
1563
   always @ (posedge clk or posedge rst)
1564
     if (rst)
1565
       q <= {length{1'b0}};
1566
     else
1567
         q <= (q_next>>1) ^ q_next;
1568
endmodule
1569
//////////////////////////////////////////////////////////////////////
1570
////                                                              ////
1571
////  Versatile counter                                           ////
1572
////                                                              ////
1573
////  Description                                                 ////
1574
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1575
////  counter                                                     ////
1576
////                                                              ////
1577
////  To Do:                                                      ////
1578
////   - add LFSR with more taps                                  ////
1579
////                                                              ////
1580
////  Author(s):                                                  ////
1581
////      - Michael Unneback, unneback@opencores.org              ////
1582
////        ORSoC AB                                              ////
1583
////                                                              ////
1584
//////////////////////////////////////////////////////////////////////
1585
////                                                              ////
1586
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1587
////                                                              ////
1588
//// This source file may be used and distributed without         ////
1589
//// restriction provided that this copyright statement is not    ////
1590
//// removed from the file and that any derivative work contains  ////
1591
//// the original copyright notice and the associated disclaimer. ////
1592
////                                                              ////
1593
//// This source file is free software; you can redistribute it   ////
1594
//// and/or modify it under the terms of the GNU Lesser General   ////
1595
//// Public License as published by the Free Software Foundation; ////
1596
//// either version 2.1 of the License, or (at your option) any   ////
1597
//// later version.                                               ////
1598
////                                                              ////
1599
//// This source is distributed in the hope that it will be       ////
1600
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1601
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1602
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1603
//// details.                                                     ////
1604
////                                                              ////
1605
//// You should have received a copy of the GNU Lesser General    ////
1606
//// Public License along with this source; if not, download it   ////
1607
//// from http://www.opencores.org/lgpl.shtml                     ////
1608
////                                                              ////
1609
//////////////////////////////////////////////////////////////////////
1610
// GRAY counter
1611 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1612 6 unneback
   parameter length = 4;
1613
   input cke;
1614
   output reg [length:1] q;
1615
   input rst;
1616
   input clk;
1617
   parameter clear_value = 0;
1618
   parameter set_value = 1;
1619
   parameter wrap_value = 8;
1620
   parameter level1_value = 15;
1621
   reg  [length:1] qi;
1622
   wire [length:1] q_next;
1623
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1624
   always @ (posedge clk or posedge rst)
1625
     if (rst)
1626
       qi <= {length{1'b0}};
1627
     else
1628
     if (cke)
1629
       qi <= q_next;
1630
   always @ (posedge clk or posedge rst)
1631
     if (rst)
1632
       q <= {length{1'b0}};
1633
     else
1634
       if (cke)
1635
         q <= (q_next>>1) ^ q_next;
1636
endmodule
1637
//////////////////////////////////////////////////////////////////////
1638
////                                                              ////
1639
////  Versatile counter                                           ////
1640
////                                                              ////
1641
////  Description                                                 ////
1642
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1643
////  counter                                                     ////
1644
////                                                              ////
1645
////  To Do:                                                      ////
1646
////   - add LFSR with more taps                                  ////
1647
////                                                              ////
1648
////  Author(s):                                                  ////
1649
////      - Michael Unneback, unneback@opencores.org              ////
1650
////        ORSoC AB                                              ////
1651
////                                                              ////
1652
//////////////////////////////////////////////////////////////////////
1653
////                                                              ////
1654
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1655
////                                                              ////
1656
//// This source file may be used and distributed without         ////
1657
//// restriction provided that this copyright statement is not    ////
1658
//// removed from the file and that any derivative work contains  ////
1659
//// the original copyright notice and the associated disclaimer. ////
1660
////                                                              ////
1661
//// This source file is free software; you can redistribute it   ////
1662
//// and/or modify it under the terms of the GNU Lesser General   ////
1663
//// Public License as published by the Free Software Foundation; ////
1664
//// either version 2.1 of the License, or (at your option) any   ////
1665
//// later version.                                               ////
1666
////                                                              ////
1667
//// This source is distributed in the hope that it will be       ////
1668
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1669
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1670
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1671
//// details.                                                     ////
1672
////                                                              ////
1673
//// You should have received a copy of the GNU Lesser General    ////
1674
//// Public License along with this source; if not, download it   ////
1675
//// from http://www.opencores.org/lgpl.shtml                     ////
1676
////                                                              ////
1677
//////////////////////////////////////////////////////////////////////
1678
// GRAY counter
1679 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1680 6 unneback
   parameter length = 4;
1681
   input cke;
1682
   output reg [length:1] q;
1683
   output [length:1] q_bin;
1684
   input rst;
1685
   input clk;
1686
   parameter clear_value = 0;
1687
   parameter set_value = 1;
1688
   parameter wrap_value = 8;
1689
   parameter level1_value = 15;
1690
   reg  [length:1] qi;
1691
   wire [length:1] q_next;
1692
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1693
   always @ (posedge clk or posedge rst)
1694
     if (rst)
1695
       qi <= {length{1'b0}};
1696
     else
1697
     if (cke)
1698
       qi <= q_next;
1699
   always @ (posedge clk or posedge rst)
1700
     if (rst)
1701
       q <= {length{1'b0}};
1702
     else
1703
       if (cke)
1704
         q <= (q_next>>1) ^ q_next;
1705
   assign q_bin = qi;
1706
endmodule
1707
//////////////////////////////////////////////////////////////////////
1708
////                                                              ////
1709
////  Versatile library, counters                                 ////
1710
////                                                              ////
1711
////  Description                                                 ////
1712
////  counters                                                    ////
1713
////                                                              ////
1714
////                                                              ////
1715
////  To Do:                                                      ////
1716
////   - add more counters                                        ////
1717
////                                                              ////
1718
////  Author(s):                                                  ////
1719
////      - Michael Unneback, unneback@opencores.org              ////
1720
////        ORSoC AB                                              ////
1721
////                                                              ////
1722
//////////////////////////////////////////////////////////////////////
1723
////                                                              ////
1724
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1725
////                                                              ////
1726
//// This source file may be used and distributed without         ////
1727
//// restriction provided that this copyright statement is not    ////
1728
//// removed from the file and that any derivative work contains  ////
1729
//// the original copyright notice and the associated disclaimer. ////
1730
////                                                              ////
1731
//// This source file is free software; you can redistribute it   ////
1732
//// and/or modify it under the terms of the GNU Lesser General   ////
1733
//// Public License as published by the Free Software Foundation; ////
1734
//// either version 2.1 of the License, or (at your option) any   ////
1735
//// later version.                                               ////
1736
////                                                              ////
1737
//// This source is distributed in the hope that it will be       ////
1738
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1739
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1740
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1741
//// details.                                                     ////
1742
////                                                              ////
1743
//// You should have received a copy of the GNU Lesser General    ////
1744
//// Public License along with this source; if not, download it   ////
1745
//// from http://www.opencores.org/lgpl.shtml                     ////
1746
////                                                              ////
1747
//////////////////////////////////////////////////////////////////////
1748 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1749 6 unneback
   parameter length = 4;
1750
   output reg [0:length-1] q;
1751
   input rst;
1752
   input clk;
1753
    always @ (posedge clk or posedge rst)
1754
    if (rst)
1755
        q <= {1'b1,{length-1{1'b0}}};
1756
    else
1757
        q <= {q[length-1],q[0:length-2]};
1758
endmodule
1759 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1760 6 unneback
   parameter length = 4;
1761
   input cke;
1762
   output reg [0:length-1] q;
1763
   input rst;
1764
   input clk;
1765
    always @ (posedge clk or posedge rst)
1766
    if (rst)
1767
        q <= {1'b1,{length-1{1'b0}}};
1768
    else
1769
        if (cke)
1770
            q <= {q[length-1],q[0:length-2]};
1771
endmodule
1772 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1773 6 unneback
   parameter length = 4;
1774
   input cke, clear;
1775
   output reg [0:length-1] q;
1776
   input rst;
1777
   input clk;
1778
    always @ (posedge clk or posedge rst)
1779
    if (rst)
1780
        q <= {1'b1,{length-1{1'b0}}};
1781
    else
1782
        if (cke)
1783
            if (clear)
1784
                q <= {1'b1,{length-1{1'b0}}};
1785
            else
1786
                q <= q >> 1;
1787
endmodule
1788 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1789 6 unneback
   parameter length = 4;
1790
   input cke, clear;
1791
   output reg [0:length-1] q;
1792
   input rst;
1793
   input clk;
1794
    always @ (posedge clk or posedge rst)
1795
    if (rst)
1796
        q <= {1'b1,{length-1{1'b0}}};
1797
    else
1798
        if (cke)
1799
            if (clear)
1800
                q <= {1'b1,{length-1{1'b0}}};
1801
            else
1802
            q <= {q[length-1],q[0:length-2]};
1803
endmodule
1804
//////////////////////////////////////////////////////////////////////
1805
////                                                              ////
1806
////  Versatile library, memories                                 ////
1807
////                                                              ////
1808
////  Description                                                 ////
1809
////  memories                                                    ////
1810
////                                                              ////
1811
////                                                              ////
1812
////  To Do:                                                      ////
1813
////   - add more memory types                                    ////
1814
////                                                              ////
1815
////  Author(s):                                                  ////
1816
////      - Michael Unneback, unneback@opencores.org              ////
1817
////        ORSoC AB                                              ////
1818
////                                                              ////
1819
//////////////////////////////////////////////////////////////////////
1820
////                                                              ////
1821
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1822
////                                                              ////
1823
//// This source file may be used and distributed without         ////
1824
//// restriction provided that this copyright statement is not    ////
1825
//// removed from the file and that any derivative work contains  ////
1826
//// the original copyright notice and the associated disclaimer. ////
1827
////                                                              ////
1828
//// This source file is free software; you can redistribute it   ////
1829
//// and/or modify it under the terms of the GNU Lesser General   ////
1830
//// Public License as published by the Free Software Foundation; ////
1831
//// either version 2.1 of the License, or (at your option) any   ////
1832
//// later version.                                               ////
1833
////                                                              ////
1834
//// This source is distributed in the hope that it will be       ////
1835
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1836
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1837
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1838
//// details.                                                     ////
1839
////                                                              ////
1840
//// You should have received a copy of the GNU Lesser General    ////
1841
//// Public License along with this source; if not, download it   ////
1842
//// from http://www.opencores.org/lgpl.shtml                     ////
1843
////                                                              ////
1844
//////////////////////////////////////////////////////////////////////
1845
/// ROM
1846 7 unneback
module vl_rom_init ( adr, q, clk);
1847
   parameter data_width = 32;
1848
   parameter addr_width = 8;
1849
   input [(addr_width-1):0]       adr;
1850
   output reg [(data_width-1):0] q;
1851
   input                         clk;
1852
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1853
   parameter memory_file = "vl_rom.vmem";
1854
   initial
1855
     begin
1856
        $readmemh(memory_file, rom);
1857
     end
1858
   always @ (posedge clk)
1859
     q <= rom[adr];
1860
endmodule
1861 14 unneback
/*
1862 7 unneback
module vl_rom ( adr, q, clk);
1863 6 unneback
parameter data_width = 32;
1864
parameter addr_width = 4;
1865
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1866
    {32'h18000000},
1867
    {32'hA8200000},
1868
    {32'hA8200000},
1869
    {32'hA8200000},
1870
    {32'h44003000},
1871
    {32'h15000000},
1872
    {32'h15000000},
1873
    {32'h15000000},
1874
    {32'h15000000},
1875
    {32'h15000000},
1876
    {32'h15000000},
1877
    {32'h15000000},
1878
    {32'h15000000},
1879
    {32'h15000000},
1880
    {32'h15000000},
1881
    {32'h15000000}};
1882 7 unneback
input [addr_width-1:0] adr;
1883 6 unneback
output reg [data_width-1:0] q;
1884
input clk;
1885
always @ (posedge clk)
1886 7 unneback
    q <= data[adr];
1887 6 unneback
endmodule
1888 14 unneback
*/
1889 6 unneback
// Single port RAM
1890
module vl_ram ( d, adr, we, q, clk);
1891
   parameter data_width = 32;
1892
   parameter addr_width = 8;
1893
   input [(data_width-1):0]      d;
1894
   input [(addr_width-1):0]       adr;
1895
   input                         we;
1896 7 unneback
   output reg [(data_width-1):0] q;
1897 6 unneback
   input                         clk;
1898
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1899 7 unneback
   parameter init = 0;
1900
   parameter memory_file = "vl_ram.vmem";
1901
   generate if (init) begin : init_mem
1902
   initial
1903
     begin
1904
        $readmemh(memory_file, ram);
1905
     end
1906
   end
1907
   endgenerate
1908 6 unneback
   always @ (posedge clk)
1909
   begin
1910
   if (we)
1911
     ram[adr] <= d;
1912
   q <= ram[adr];
1913
   end
1914
endmodule
1915 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1916
   parameter data_width = 32;
1917
   parameter addr_width = 8;
1918
   input [(data_width-1):0]      d;
1919
   input [(addr_width-1):0]       adr;
1920
   input [(addr_width/4)-1:0]    be;
1921
   input                         we;
1922
   output reg [(data_width-1):0] q;
1923
   input                         clk;
1924
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1925
   parameter init = 0;
1926
   parameter memory_file = "vl_ram.vmem";
1927
   generate if (init) begin : init_mem
1928
   initial
1929
     begin
1930
        $readmemh(memory_file, ram);
1931
     end
1932
   end
1933
   endgenerate
1934
   genvar i;
1935
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1936
      always @ (posedge clk)
1937
      if (we & be[i])
1938
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1939
   end
1940
   endgenerate
1941
   always @ (posedge clk)
1942
      q <= ram[adr];
1943
endmodule
1944 6 unneback
// Dual port RAM
1945
// ACTEL FPGA should not use logic to handle rw collision
1946 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1947 6 unneback
   parameter data_width = 32;
1948
   parameter addr_width = 8;
1949
   input [(data_width-1):0]      d_a;
1950
   input [(addr_width-1):0]       adr_a;
1951
   input [(addr_width-1):0]       adr_b;
1952
   input                         we_a;
1953
   output [(data_width-1):0]      q_b;
1954
   input                         clk_a, clk_b;
1955
   reg [(addr_width-1):0]         adr_b_reg;
1956
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1957 7 unneback
   parameter init = 0;
1958
   parameter memory_file = "vl_ram.vmem";
1959
   generate if (init) begin : init_mem
1960
   initial
1961
     begin
1962
        $readmemh(memory_file, ram);
1963
     end
1964
   end
1965
   endgenerate
1966 6 unneback
   always @ (posedge clk_a)
1967
   if (we_a)
1968
     ram[adr_a] <= d_a;
1969
   always @ (posedge clk_b)
1970
   adr_b_reg <= adr_b;
1971
   assign q_b = ram[adr_b_reg];
1972
endmodule
1973 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1974 6 unneback
   parameter data_width = 32;
1975
   parameter addr_width = 8;
1976
   input [(data_width-1):0]      d_a;
1977
   input [(addr_width-1):0]       adr_a;
1978
   input [(addr_width-1):0]       adr_b;
1979
   input                         we_a;
1980
   output [(data_width-1):0]      q_b;
1981
   output reg [(data_width-1):0] q_a;
1982
   input                         clk_a, clk_b;
1983
   reg [(data_width-1):0]         q_b;
1984
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1985 7 unneback
   parameter init = 0;
1986
   parameter memory_file = "vl_ram.vmem";
1987
   generate if (init) begin : init_mem
1988
   initial
1989
     begin
1990
        $readmemh(memory_file, ram);
1991
     end
1992
   end
1993
   endgenerate
1994 6 unneback
   always @ (posedge clk_a)
1995
     begin
1996
        q_a <= ram[adr_a];
1997
        if (we_a)
1998
             ram[adr_a] <= d_a;
1999
     end
2000
   always @ (posedge clk_b)
2001
          q_b <= ram[adr_b];
2002
endmodule
2003 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2004 6 unneback
   parameter data_width = 32;
2005
   parameter addr_width = 8;
2006
   input [(data_width-1):0]      d_a;
2007
   input [(addr_width-1):0]       adr_a;
2008
   input [(addr_width-1):0]       adr_b;
2009
   input                         we_a;
2010
   output [(data_width-1):0]      q_b;
2011
   input [(data_width-1):0]       d_b;
2012
   output reg [(data_width-1):0] q_a;
2013
   input                         we_b;
2014
   input                         clk_a, clk_b;
2015
   reg [(data_width-1):0]         q_b;
2016
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2017 7 unneback
   parameter init = 0;
2018
   parameter memory_file = "vl_ram.vmem";
2019
   generate if (init) begin : init_mem
2020
   initial
2021
     begin
2022
        $readmemh(memory_file, ram);
2023
     end
2024
   end
2025
   endgenerate
2026 6 unneback
   always @ (posedge clk_a)
2027
     begin
2028
        q_a <= ram[adr_a];
2029
        if (we_a)
2030
             ram[adr_a] <= d_a;
2031
     end
2032
   always @ (posedge clk_b)
2033
     begin
2034
        q_b <= ram[adr_b];
2035
        if (we_b)
2036
          ram[adr_b] <= d_b;
2037
     end
2038
endmodule
2039
// Content addresable memory, CAM
2040
// FIFO
2041 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2042
    d, wr, fifo_full,
2043
    q, rd, fifo_empty,
2044
    fill_level,
2045
    clk, rst
2046
    );
2047
parameter data_width = 18;
2048
parameter addr_width = 4;
2049
// write side
2050
input  [data_width-1:0] d;
2051
input                   wr;
2052
output                  fifo_full;
2053
// read side
2054
output [data_width-1:0] q;
2055
input                   rd;
2056
output                  fifo_empty;
2057
// common
2058
output [addr_width:0]   fill_level;
2059
input rst, clk;
2060
wire [addr_width:1] wadr, radr;
2061
vl_cnt_bin_ce
2062
    # ( .length(addr_width))
2063
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2064
vl_cnt_bin_ce
2065
    # (.length(addr_width))
2066
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2067
vl_dpram_1r1w
2068
    # (.data_width(data_width), .addr_width(addr_width))
2069
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2070
vl_cnt_bin_ce_rew_zq_l1
2071
    # (.length(addr_width+1), .level1(1<<add_width))
2072
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2073
endmodule
2074 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2075 11 unneback
   parameter addr_width = 4;
2076
   parameter N = addr_width-1;
2077 6 unneback
   parameter Q1 = 2'b00;
2078
   parameter Q2 = 2'b01;
2079
   parameter Q3 = 2'b11;
2080
   parameter Q4 = 2'b10;
2081
   parameter going_empty = 1'b0;
2082
   parameter going_full  = 1'b1;
2083
   input [N:0]  wptr, rptr;
2084 14 unneback
   output       fifo_empty;
2085 6 unneback
   output       fifo_full;
2086
   input        wclk, rclk, rst;
2087
   wire direction;
2088
   reg  direction_set, direction_clr;
2089
   wire async_empty, async_full;
2090
   wire fifo_full2;
2091 14 unneback
   wire fifo_empty2;
2092 6 unneback
   // direction_set
2093
   always @ (wptr[N:N-1] or rptr[N:N-1])
2094
     case ({wptr[N:N-1],rptr[N:N-1]})
2095
       {Q1,Q2} : direction_set <= 1'b1;
2096
       {Q2,Q3} : direction_set <= 1'b1;
2097
       {Q3,Q4} : direction_set <= 1'b1;
2098
       {Q4,Q1} : direction_set <= 1'b1;
2099
       default : direction_set <= 1'b0;
2100
     endcase
2101
   // direction_clear
2102
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2103
     if (rst)
2104
       direction_clr <= 1'b1;
2105
     else
2106
       case ({wptr[N:N-1],rptr[N:N-1]})
2107
         {Q2,Q1} : direction_clr <= 1'b1;
2108
         {Q3,Q2} : direction_clr <= 1'b1;
2109
         {Q4,Q3} : direction_clr <= 1'b1;
2110
         {Q1,Q4} : direction_clr <= 1'b1;
2111
         default : direction_clr <= 1'b0;
2112
       endcase
2113 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2114 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2115
   assign async_full  = (wptr == rptr) && (direction==going_full);
2116 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2117
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2118 6 unneback
/*
2119
   always @ (posedge wclk or posedge rst or posedge async_full)
2120
     if (rst)
2121
       {fifo_full, fifo_full2} <= 2'b00;
2122
     else if (async_full)
2123
       {fifo_full, fifo_full2} <= 2'b11;
2124
     else
2125
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2126
*/
2127 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2128 6 unneback
     if (async_empty)
2129
       {fifo_empty, fifo_empty2} <= 2'b11;
2130
     else
2131 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2132 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2133
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2134 6 unneback
endmodule // async_comp
2135
module vl_fifo_1r1w_async (
2136
    d, wr, fifo_full, wr_clk, wr_rst,
2137
    q, rd, fifo_empty, rd_clk, rd_rst
2138
    );
2139
parameter data_width = 18;
2140
parameter addr_width = 4;
2141
// write side
2142
input  [data_width-1:0] d;
2143
input                   wr;
2144
output                  fifo_full;
2145
input                   wr_clk;
2146
input                   wr_rst;
2147
// read side
2148
output [data_width-1:0] q;
2149
input                   rd;
2150
output                  fifo_empty;
2151
input                   rd_clk;
2152
input                   rd_rst;
2153
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2154 18 unneback
vl_cnt_gray_ce_bin
2155 6 unneback
    # ( .length(addr_width))
2156
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2157 18 unneback
vl_cnt_gray_ce_bin
2158 6 unneback
    # (.length(addr_width))
2159 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2160 7 unneback
vl_dpram_1r1w
2161 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2162
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2163
vl_fifo_cmp_async
2164
    # (.addr_width(addr_width))
2165
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2166
endmodule
2167 8 unneback
module vl_fifo_2r2w_async (
2168 6 unneback
    // a side
2169
    a_d, a_wr, a_fifo_full,
2170
    a_q, a_rd, a_fifo_empty,
2171
    a_clk, a_rst,
2172
    // b side
2173
    b_d, b_wr, b_fifo_full,
2174
    b_q, b_rd, b_fifo_empty,
2175
    b_clk, b_rst
2176
    );
2177
parameter data_width = 18;
2178
parameter addr_width = 4;
2179
// a side
2180
input  [data_width-1:0] a_d;
2181
input                   a_wr;
2182
output                  a_fifo_full;
2183
output [data_width-1:0] a_q;
2184
input                   a_rd;
2185
output                  a_fifo_empty;
2186
input                   a_clk;
2187
input                   a_rst;
2188
// b side
2189
input  [data_width-1:0] b_d;
2190
input                   b_wr;
2191
output                  b_fifo_full;
2192
output [data_width-1:0] b_q;
2193
input                   b_rd;
2194
output                  b_fifo_empty;
2195
input                   b_clk;
2196
input                   b_rst;
2197
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2198
vl_fifo_1r1w_async_a (
2199
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2200
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2201
    );
2202
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2203
vl_fifo_1r1w_async_b (
2204
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2205
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2206
    );
2207
endmodule
2208 8 unneback
module vl_fifo_2r2w_async_simplex (
2209 6 unneback
    // a side
2210
    a_d, a_wr, a_fifo_full,
2211
    a_q, a_rd, a_fifo_empty,
2212
    a_clk, a_rst,
2213
    // b side
2214
    b_d, b_wr, b_fifo_full,
2215
    b_q, b_rd, b_fifo_empty,
2216
    b_clk, b_rst
2217
    );
2218
parameter data_width = 18;
2219
parameter addr_width = 4;
2220
// a side
2221
input  [data_width-1:0] a_d;
2222
input                   a_wr;
2223
output                  a_fifo_full;
2224
output [data_width-1:0] a_q;
2225
input                   a_rd;
2226
output                  a_fifo_empty;
2227
input                   a_clk;
2228
input                   a_rst;
2229
// b side
2230
input  [data_width-1:0] b_d;
2231
input                   b_wr;
2232
output                  b_fifo_full;
2233
output [data_width-1:0] b_q;
2234
input                   b_rd;
2235
output                  b_fifo_empty;
2236
input                   b_clk;
2237
input                   b_rst;
2238
// adr_gen
2239
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2240
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2241
// dpram
2242
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2243 18 unneback
vl_cnt_gray_ce_bin
2244 6 unneback
    # ( .length(addr_width))
2245
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2246 18 unneback
vl_cnt_gray_ce_bin
2247 6 unneback
    # (.length(addr_width))
2248
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2249 18 unneback
vl_cnt_gray_ce_bin
2250 6 unneback
    # ( .length(addr_width))
2251
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2252 18 unneback
vl_cnt_gray_ce_bin
2253 6 unneback
    # (.length(addr_width))
2254
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2255
// mux read or write adr to DPRAM
2256
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2257
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2258 11 unneback
vl_dpram_2r2w
2259 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2260
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2261
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2262 11 unneback
vl_fifo_cmp_async
2263 6 unneback
    # (.addr_width(addr_width))
2264
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2265 11 unneback
vl_fifo_cmp_async
2266 6 unneback
    # (.addr_width(addr_width))
2267
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2268
endmodule
2269 12 unneback
//////////////////////////////////////////////////////////////////////
2270
////                                                              ////
2271
////  Versatile library, wishbone stuff                           ////
2272
////                                                              ////
2273
////  Description                                                 ////
2274
////  Wishbone compliant modules                                  ////
2275
////                                                              ////
2276
////                                                              ////
2277
////  To Do:                                                      ////
2278
////   -                                                          ////
2279
////                                                              ////
2280
////  Author(s):                                                  ////
2281
////      - Michael Unneback, unneback@opencores.org              ////
2282
////        ORSoC AB                                              ////
2283
////                                                              ////
2284
//////////////////////////////////////////////////////////////////////
2285
////                                                              ////
2286
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2287
////                                                              ////
2288
//// This source file may be used and distributed without         ////
2289
//// restriction provided that this copyright statement is not    ////
2290
//// removed from the file and that any derivative work contains  ////
2291
//// the original copyright notice and the associated disclaimer. ////
2292
////                                                              ////
2293
//// This source file is free software; you can redistribute it   ////
2294
//// and/or modify it under the terms of the GNU Lesser General   ////
2295
//// Public License as published by the Free Software Foundation; ////
2296
//// either version 2.1 of the License, or (at your option) any   ////
2297
//// later version.                                               ////
2298
////                                                              ////
2299
//// This source is distributed in the hope that it will be       ////
2300
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2301
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2302
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2303
//// details.                                                     ////
2304
////                                                              ////
2305
//// You should have received a copy of the GNU Lesser General    ////
2306
//// Public License along with this source; if not, download it   ////
2307
//// from http://www.opencores.org/lgpl.shtml                     ////
2308
////                                                              ////
2309
//////////////////////////////////////////////////////////////////////
2310
// async wb3 - wb3 bridge
2311
`timescale 1ns/1ns
2312 18 unneback
module vl_wb3wb3_bridge (
2313 12 unneback
        // wishbone slave side
2314
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2315
        // wishbone master side
2316
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2317
input [31:0] wbs_dat_i;
2318
input [31:2] wbs_adr_i;
2319
input [3:0]  wbs_sel_i;
2320
input [1:0]  wbs_bte_i;
2321
input [2:0]  wbs_cti_i;
2322
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2323
output [31:0] wbs_dat_o;
2324 14 unneback
output wbs_ack_o;
2325 12 unneback
input wbs_clk, wbs_rst;
2326
output [31:0] wbm_dat_o;
2327
output reg [31:2] wbm_adr_o;
2328
output [3:0]  wbm_sel_o;
2329
output reg [1:0]  wbm_bte_o;
2330
output reg [2:0]  wbm_cti_o;
2331 14 unneback
output reg wbm_we_o;
2332
output wbm_cyc_o;
2333 12 unneback
output wbm_stb_o;
2334
input [31:0]  wbm_dat_i;
2335
input wbm_ack_i;
2336
input wbm_clk, wbm_rst;
2337
parameter addr_width = 4;
2338
// bte
2339
parameter linear       = 2'b00;
2340
parameter wrap4        = 2'b01;
2341
parameter wrap8        = 2'b10;
2342
parameter wrap16       = 2'b11;
2343
// cti
2344
parameter classic      = 3'b000;
2345
parameter incburst     = 3'b010;
2346
parameter endofburst   = 3'b111;
2347
parameter wbs_adr  = 1'b0;
2348
parameter wbs_data = 1'b1;
2349
parameter wbm_adr0 = 2'b00;
2350
parameter wbm_adr1 = 2'b01;
2351
parameter wbm_data = 2'b10;
2352
reg [1:0] wbs_bte_reg;
2353
reg wbs;
2354
wire wbs_eoc_alert, wbm_eoc_alert;
2355
reg wbs_eoc, wbm_eoc;
2356
reg [1:0] wbm;
2357 14 unneback
wire [1:16] wbs_count, wbm_count;
2358 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2359
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2360
reg a_rd_reg;
2361
wire b_rd_adr, b_rd_data;
2362 14 unneback
wire b_rd_data_reg;
2363
wire [35:0] temp;
2364 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2365
always @ (posedge wbs_clk or posedge wbs_rst)
2366
if (wbs_rst)
2367
        wbs_eoc <= 1'b0;
2368
else
2369
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2370
                wbs_eoc <= wbs_bte_i==linear;
2371
        else if (wbs_eoc_alert & (a_rd | a_wr))
2372
                wbs_eoc <= 1'b1;
2373 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2374 12 unneback
    cnt0 (
2375
        .cke(wbs_ack_o),
2376
        .clear(wbs_eoc),
2377
        .q(wbs_count),
2378
        .rst(wbs_rst),
2379
        .clk(wbs_clk));
2380
always @ (posedge wbs_clk or posedge wbs_rst)
2381
if (wbs_rst)
2382
        wbs <= wbs_adr;
2383
else
2384
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2385
                wbs <= wbs_data;
2386
        else if (wbs_eoc & wbs_ack_o)
2387
                wbs <= wbs_adr;
2388
// wbs FIFO
2389
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2390
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2391
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2392
              1'b0;
2393
assign a_rd = !a_fifo_empty;
2394
always @ (posedge wbs_clk or posedge wbs_rst)
2395
if (wbs_rst)
2396
        a_rd_reg <= 1'b0;
2397
else
2398
        a_rd_reg <= a_rd;
2399
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2400
assign wbs_dat_o = a_q[35:4];
2401
always @ (posedge wbs_clk or posedge wbs_rst)
2402
if (wbs_rst)
2403 13 unneback
        wbs_bte_reg <= 2'b00;
2404 12 unneback
else
2405 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2406 12 unneback
// wbm FIFO
2407
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2408
always @ (posedge wbm_clk or posedge wbm_rst)
2409
if (wbm_rst)
2410
        wbm_eoc <= 1'b0;
2411
else
2412
        if (wbm==wbm_adr0 & !b_fifo_empty)
2413
                wbm_eoc <= b_q[4:3] == linear;
2414
        else if (wbm_eoc_alert & wbm_ack_i)
2415
                wbm_eoc <= 1'b1;
2416
always @ (posedge wbm_clk or posedge wbm_rst)
2417
if (wbm_rst)
2418
        wbm <= wbm_adr0;
2419
else
2420
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2421
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2422
        (wbm==wbm_adr1 & !wbm_we_o) |
2423
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2424
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2425
assign b_d = {wbm_dat_i,4'b1111};
2426
assign b_wr = !wbm_we_o & wbm_ack_i;
2427
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2428
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2429
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2430
                   1'b0;
2431
assign b_rd = b_rd_adr | b_rd_data;
2432 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2433
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2434 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2435 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2436 12 unneback
    cnt1 (
2437
        .cke(wbm_ack_i),
2438
        .clear(wbm_eoc),
2439
        .q(wbm_count),
2440
        .rst(wbm_rst),
2441
        .clk(wbm_clk));
2442
assign wbm_cyc_o = wbm==wbm_data;
2443
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2444
                   (wbm==wbm_data) ? 1'b1 :
2445
                   1'b0;
2446
always @ (posedge wbm_clk or posedge wbm_rst)
2447
if (wbm_rst)
2448
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2449
else begin
2450
        if (wbm==wbm_adr0 & !b_fifo_empty)
2451
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2452
        else if (wbm_eoc_alert & wbm_ack_i)
2453
                wbm_cti_o <= endofburst;
2454
end
2455
//async_fifo_dw_simplex_top
2456
vl_fifo_2r2w_async_simplex
2457
# ( .data_width(36), .addr_width(addr_width))
2458
fifo (
2459
    // a side
2460
    .a_d(a_d),
2461
    .a_wr(a_wr),
2462
    .a_fifo_full(a_fifo_full),
2463
    .a_q(a_q),
2464
    .a_rd(a_rd),
2465
    .a_fifo_empty(a_fifo_empty),
2466
    .a_clk(wbs_clk),
2467
    .a_rst(wbs_rst),
2468
    // b side
2469
    .b_d(b_d),
2470
    .b_wr(b_wr),
2471
    .b_fifo_full(b_fifo_full),
2472
    .b_q(b_q),
2473
    .b_rd(b_rd),
2474
    .b_fifo_empty(b_fifo_empty),
2475
    .b_clk(wbm_clk),
2476
    .b_rst(wbm_rst)
2477
    );
2478
endmodule
2479 17 unneback
// WB ROM
2480 18 unneback
module vl_wb_boot_rom (
2481 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2482 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2483
    parameter adr_hi = 31;
2484
    parameter adr_lo = 28;
2485
    parameter adr_sel = 4'hf;
2486
    parameter addr_width = 5;
2487 17 unneback
//E2_ifndef BOOT_ROM
2488
//E2_define BOOT_ROM "boot_rom.v"
2489
//E2_endif
2490 18 unneback
    input [adr_hi:2]    wb_adr_i;
2491
    input               wb_stb_i;
2492
    input               wb_cyc_i;
2493
    output [31:0]        wb_dat_o;
2494
    output              wb_ack_o;
2495
    output              hit_o;
2496
    input               wb_clk;
2497
    input               wb_rst;
2498
    wire hit;
2499
    reg [31:0] wb_dat;
2500
    reg wb_ack;
2501
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2502 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2503
    if (wb_rst)
2504 18 unneback
        wb_dat <= 32'h15000000;
2505 17 unneback
    else
2506 18 unneback
         case (wb_adr_i[addr_width-1:2])
2507 17 unneback
//E2_include `BOOT_ROM
2508
           /*
2509
            // Zero r0 and jump to 0x00000100
2510 18 unneback
 
2511
            1 : wb_dat <= 32'hA8200000;
2512
            2 : wb_dat <= 32'hA8C00100;
2513
            3 : wb_dat <= 32'h44003000;
2514
            4 : wb_dat <= 32'h15000000;
2515 17 unneback
            */
2516
           default:
2517 18 unneback
             wb_dat <= 32'h00000000;
2518 17 unneback
         endcase // case (wb_adr_i)
2519
always @ (posedge wb_clk or posedge wb_rst)
2520
    if (wb_rst)
2521 18 unneback
        wb_ack <= 1'b0;
2522 17 unneback
    else
2523 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2524
assign hit_o = hit;
2525
assign wb_dat_o = wb_dat & {32{wb_ack}};
2526
assign wb_ack_o = wb_ack;
2527 17 unneback
endmodule
2528 18 unneback
//////////////////////////////////////////////////////////////////////
2529
////                                                              ////
2530
////  Arithmetic functions                                        ////
2531
////                                                              ////
2532
////  Description                                                 ////
2533
////  Arithmetic functions for ALU and DSP                        ////
2534
////                                                              ////
2535
////                                                              ////
2536
////  To Do:                                                      ////
2537
////   -                                                          ////
2538
////                                                              ////
2539
////  Author(s):                                                  ////
2540
////      - Michael Unneback, unneback@opencores.org              ////
2541
////        ORSoC AB                                              ////
2542
////                                                              ////
2543
//////////////////////////////////////////////////////////////////////
2544
////                                                              ////
2545
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2546
////                                                              ////
2547
//// This source file may be used and distributed without         ////
2548
//// restriction provided that this copyright statement is not    ////
2549
//// removed from the file and that any derivative work contains  ////
2550
//// the original copyright notice and the associated disclaimer. ////
2551
////                                                              ////
2552
//// This source file is free software; you can redistribute it   ////
2553
//// and/or modify it under the terms of the GNU Lesser General   ////
2554
//// Public License as published by the Free Software Foundation; ////
2555
//// either version 2.1 of the License, or (at your option) any   ////
2556
//// later version.                                               ////
2557
////                                                              ////
2558
//// This source is distributed in the hope that it will be       ////
2559
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2560
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2561
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2562
//// details.                                                     ////
2563
////                                                              ////
2564
//// You should have received a copy of the GNU Lesser General    ////
2565
//// Public License along with this source; if not, download it   ////
2566
//// from http://www.opencores.org/lgpl.shtml                     ////
2567
////                                                              ////
2568
//////////////////////////////////////////////////////////////////////
2569
// signed multiplication
2570
module vl_mults (a,b,p);
2571
parameter operand_a_width = 18;
2572
parameter operand_b_width = 18;
2573
parameter result_hi = 35;
2574
parameter result_lo = 0;
2575
input [operand_a_width-1:0] a;
2576
input [operand_b_width-1:0] b;
2577
output [result_hi:result_lo] p;
2578
wire signed [operand_a_width-1:0] ai;
2579
wire signed [operand_b_width-1:0] bi;
2580
wire signed [operand_a_width+operand_b_width-1:0] result;
2581
    assign ai = a;
2582
    assign bi = b;
2583
    assign result = ai * bi;
2584
    assign p = result[result_hi:result_lo];
2585
endmodule
2586
module vl_mults18x18 (a,b,p);
2587
input [17:0] a,b;
2588
output [35:0] p;
2589
vl_mult
2590
    # (.operand_a_width(18), .operand_b_width(18))
2591
    mult0 (.a(a), .b(b), .p(p));
2592
endmodule
2593
// unsigned multiplication
2594
module vl_mult (a,b,p);
2595
parameter operand_a_width = 18;
2596
parameter operand_b_width = 18;
2597
parameter result_hi = 35;
2598
parameter result_lo = 0;
2599
input [operand_a_width-1:0] a;
2600
input [operand_b_width-1:0] b;
2601
output [result_hi:result_hi] p;
2602
wire [operand_a_width+operand_b_width-1:0] result;
2603
    assign result = a * b;
2604
    assign p = result[result_hi:result_lo];
2605
endmodule
2606
// shift unit
2607
// supporting the following shift functions
2608
//   SLL
2609
//   SRL
2610
//   SRA
2611
module vl_shift_unit_32( din, s, dout, opcode);
2612
input [31:0] din; // data in operand
2613
input [4:0] s; // shift operand
2614
input [1:0] opcode;
2615
output [31:0] dout;
2616
parameter opcode_sll = 2'b00;
2617
//parameter opcode_srl = 2'b01;
2618
parameter opcode_sra = 2'b10