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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 6 unneback
 // ALTERA
47
 //ACTEL
48
// sync reset
49 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
50 6 unneback
// output active high global reset sync with two DFFs 
51
`timescale 1 ns/100 ps
52
module vl_sync_rst ( rst_n_i, rst_o, clk);
53
input rst_n_i, clk;
54
output rst_o;
55 18 unneback
reg [1:0] tmp;
56 6 unneback
always @ (posedge clk or negedge rst_n_i)
57
if (!rst_n_i)
58 17 unneback
        tmp <= 2'b11;
59 6 unneback
else
60 17 unneback
        tmp <= {1'b0,tmp[0]};
61
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
62 6 unneback
endmodule
63
// vl_pll
64
 //altera
65
 //actel
66
//////////////////////////////////////////////////////////////////////
67
////                                                              ////
68
////  Versatile library, registers                                ////
69
////                                                              ////
70
////  Description                                                 ////
71
////  Different type of registers                                 ////
72
////                                                              ////
73
////                                                              ////
74
////  To Do:                                                      ////
75
////   - add more different registers                             ////
76
////                                                              ////
77
////  Author(s):                                                  ////
78
////      - Michael Unneback, unneback@opencores.org              ////
79
////        ORSoC AB                                              ////
80
////                                                              ////
81
//////////////////////////////////////////////////////////////////////
82
////                                                              ////
83
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84
////                                                              ////
85
//// This source file may be used and distributed without         ////
86
//// restriction provided that this copyright statement is not    ////
87
//// removed from the file and that any derivative work contains  ////
88
//// the original copyright notice and the associated disclaimer. ////
89
////                                                              ////
90
//// This source file is free software; you can redistribute it   ////
91
//// and/or modify it under the terms of the GNU Lesser General   ////
92
//// Public License as published by the Free Software Foundation; ////
93
//// either version 2.1 of the License, or (at your option) any   ////
94
//// later version.                                               ////
95
////                                                              ////
96
//// This source is distributed in the hope that it will be       ////
97
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100
//// details.                                                     ////
101
////                                                              ////
102
//// You should have received a copy of the GNU Lesser General    ////
103
//// Public License along with this source; if not, download it   ////
104
//// from http://www.opencores.org/lgpl.shtml                     ////
105
////                                                              ////
106
//////////////////////////////////////////////////////////////////////
107 18 unneback
module vl_dff ( d, q, clk, rst);
108 6 unneback
        parameter width = 1;
109
        parameter reset_value = 0;
110
        input [width-1:0] d;
111
        input clk, rst;
112
        output reg [width-1:0] q;
113
        always @ (posedge clk or posedge rst)
114
        if (rst)
115
                q <= reset_value;
116
        else
117
                q <= d;
118
endmodule
119 18 unneback
module vl_dff_array ( d, q, clk, rst);
120 6 unneback
        parameter width = 1;
121
        parameter depth = 2;
122
        parameter reset_value = 1'b0;
123
        input [width-1:0] d;
124
        input clk, rst;
125
        output [width-1:0] q;
126
        reg  [0:depth-1] q_tmp [width-1:0];
127
        integer i;
128
        always @ (posedge clk or posedge rst)
129
        if (rst) begin
130
            for (i=0;i<depth;i=i+1)
131
                q_tmp[i] <= {width{reset_value}};
132
        end else begin
133
            q_tmp[0] <= d;
134
            for (i=1;i<depth;i=i+1)
135
                q_tmp[i] <= q_tmp[i-1];
136
        end
137
    assign q = q_tmp[depth-1];
138
endmodule
139 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
140 6 unneback
        parameter width = 1;
141
        parameter reset_value = 0;
142
        input [width-1:0] d;
143
        input ce, clk, rst;
144
        output reg [width-1:0] q;
145
        always @ (posedge clk or posedge rst)
146
        if (rst)
147
                q <= reset_value;
148
        else
149
                if (ce)
150
                        q <= d;
151
endmodule
152 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
153 8 unneback
        parameter width = 1;
154
        parameter reset_value = 0;
155
        input [width-1:0] d;
156 10 unneback
        input ce, clear, clk, rst;
157 8 unneback
        output reg [width-1:0] q;
158
        always @ (posedge clk or posedge rst)
159
        if (rst)
160
            q <= reset_value;
161
        else
162
            if (ce)
163
                if (clear)
164
                    q <= {width{1'b0}};
165
                else
166
                    q <= d;
167
endmodule
168 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
169
        parameter width = 1;
170
        parameter reset_value = 0;
171
        input [width-1:0] d;
172
        input ce, set, clk, rst;
173
        output reg [width-1:0] q;
174
        always @ (posedge clk or posedge rst)
175
        if (rst)
176
            q <= reset_value;
177
        else
178
            if (ce)
179
                if (set)
180
                    q <= {width{1'b1}};
181
                else
182
                    q <= d;
183
endmodule
184 6 unneback
// megafunction wizard: %LPM_FF%
185
// GENERATION: STANDARD
186
// VERSION: WM1.0
187
// MODULE: lpm_ff 
188
// ============================================================
189
// File Name: dff_sr.v
190
// Megafunction Name(s):
191
//                      lpm_ff
192
//
193
// Simulation Library Files(s):
194
//                      lpm
195
// ============================================================
196
// ************************************************************
197
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
198
//
199
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
200
// ************************************************************
201
//Copyright (C) 1991-2010 Altera Corporation
202
//Your use of Altera Corporation's design tools, logic functions 
203
//and other software and tools, and its AMPP partner logic 
204
//functions, and any output files from any of the foregoing 
205
//(including device programming or simulation files), and any 
206
//associated documentation or information are expressly subject 
207
//to the terms and conditions of the Altera Program License 
208
//Subscription Agreement, Altera MegaCore Function License 
209
//Agreement, or other applicable license agreement, including, 
210
//without limitation, that your use is for the sole purpose of 
211
//programming logic devices manufactured by Altera and sold by 
212
//Altera or its authorized distributors.  Please refer to the 
213
//applicable agreement for further details.
214
// synopsys translate_off
215
`timescale 1 ps / 1 ps
216
// synopsys translate_on
217 18 unneback
module vl_dff_sr (
218 6 unneback
        aclr,
219
        aset,
220
        clock,
221
        data,
222
        q);
223
        input     aclr;
224
        input     aset;
225
        input     clock;
226
        input     data;
227
        output    q;
228
        wire [0:0] sub_wire0;
229
        wire [0:0] sub_wire1 = sub_wire0[0:0];
230
        wire  q = sub_wire1;
231
        wire  sub_wire2 = data;
232
        wire  sub_wire3 = sub_wire2;
233
        lpm_ff  lpm_ff_component (
234
                                .aclr (aclr),
235
                                .clock (clock),
236
                                .data (sub_wire3),
237
                                .aset (aset),
238
                                .q (sub_wire0)
239
                                // synopsys translate_off
240
                                ,
241
                                .aload (),
242
                                .enable (),
243
                                .sclr (),
244
                                .sload (),
245
                                .sset ()
246
                                // synopsys translate_on
247
                                );
248
        defparam
249
                lpm_ff_component.lpm_fftype = "DFF",
250
                lpm_ff_component.lpm_type = "LPM_FF",
251
                lpm_ff_component.lpm_width = 1;
252
endmodule
253
// ============================================================
254
// CNX file retrieval info
255
// ============================================================
256
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
257
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
258
// Retrieval info: PRIVATE: ASET NUMERIC "1"
259
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
260
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
261
// Retrieval info: PRIVATE: DFF NUMERIC "1"
262
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
263
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
264
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
265
// Retrieval info: PRIVATE: SSET NUMERIC "0"
266
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
267
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
268
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
269
// Retrieval info: PRIVATE: nBit NUMERIC "1"
270
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
271
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
272
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
273
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
274
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
275
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
276
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
277
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
278
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
279
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
280
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
281
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
282
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
283
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
284
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
285
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
286
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
287
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
288
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
289
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
290
// Retrieval info: LIB_FILE: lpm
291
// LATCH
292
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
293 18 unneback
module vl_latch ( d, le, q, clk);
294 6 unneback
input d, le;
295
output q;
296
input clk;
297
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
298
endmodule
299 18 unneback
module vl_shreg ( d, q, clk, rst);
300 17 unneback
parameter depth = 10;
301
input d;
302
output q;
303
input clk, rst;
304
reg [1:depth] dffs;
305
always @ (posedge clk or posedge rst)
306
if (rst)
307
    dffs <= {depth{1'b0}};
308
else
309
    dffs <= {d,dffs[1:depth-1]};
310
assign q = dffs[depth];
311
endmodule
312 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
313 17 unneback
parameter depth = 10;
314
input d, ce;
315
output q;
316
input clk, rst;
317
reg [1:depth] dffs;
318
always @ (posedge clk or posedge rst)
319
if (rst)
320
    dffs <= {depth{1'b0}};
321
else
322
    if (ce)
323
        dffs <= {d,dffs[1:depth-1]};
324
assign q = dffs[depth];
325
endmodule
326 18 unneback
module vl_delay ( d, q, clk, rst);
327 15 unneback
parameter depth = 10;
328
input d;
329
output q;
330
input clk, rst;
331
reg [1:depth] dffs;
332
always @ (posedge clk or posedge rst)
333
if (rst)
334
    dffs <= {depth{1'b0}};
335
else
336
    dffs <= {d,dffs[1:depth-1]};
337
assign q = dffs[depth];
338
endmodule
339 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
340 17 unneback
parameter depth = 10;
341
input d;
342
output q, emptyflag;
343
input clk, rst;
344
reg [1:depth] dffs;
345
always @ (posedge clk or posedge rst)
346
if (rst)
347
    dffs <= {depth{1'b0}};
348
else
349
    dffs <= {d,dffs[1:depth-1]};
350
assign q = dffs[depth];
351
assign emptyflag = !(|dffs);
352
endmodule
353 6 unneback
//////////////////////////////////////////////////////////////////////
354
////                                                              ////
355 18 unneback
////  Logic functions                                             ////
356
////                                                              ////
357
////  Description                                                 ////
358
////  Logic functions such as multiplexers                        ////
359
////                                                              ////
360
////                                                              ////
361
////  To Do:                                                      ////
362
////   -                                                          ////
363
////                                                              ////
364
////  Author(s):                                                  ////
365
////      - Michael Unneback, unneback@opencores.org              ////
366
////        ORSoC AB                                              ////
367
////                                                              ////
368
//////////////////////////////////////////////////////////////////////
369
////                                                              ////
370
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
371
////                                                              ////
372
//// This source file may be used and distributed without         ////
373
//// restriction provided that this copyright statement is not    ////
374
//// removed from the file and that any derivative work contains  ////
375
//// the original copyright notice and the associated disclaimer. ////
376
////                                                              ////
377
//// This source file is free software; you can redistribute it   ////
378
//// and/or modify it under the terms of the GNU Lesser General   ////
379
//// Public License as published by the Free Software Foundation; ////
380
//// either version 2.1 of the License, or (at your option) any   ////
381
//// later version.                                               ////
382
////                                                              ////
383
//// This source is distributed in the hope that it will be       ////
384
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
385
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
386
//// PURPOSE.  See the GNU Lesser General Public License for more ////
387
//// details.                                                     ////
388
////                                                              ////
389
//// You should have received a copy of the GNU Lesser General    ////
390
//// Public License along with this source; if not, download it   ////
391
//// from http://www.opencores.org/lgpl.shtml                     ////
392
////                                                              ////
393
//////////////////////////////////////////////////////////////////////
394
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
395
parameter width = 32;
396
parameter nr_of_ports = 4;
397
input [width-1:0] a3, a2, a1, a0;
398
input [nr_of_ports-1:0] sel;
399 22 unneback
output [width-1:0] dout;
400 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
401 18 unneback
integer i;
402
// and
403
assign tmp[0] = {width{sel[0]}} & a0;
404
assign tmp[1] = {width{sel[1]}} & a1;
405
assign tmp[2] = {width{sel[2]}} & a2;
406
assign tmp[3] = {width{sel[3]}} & a3;
407
// or
408
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
409
endmodule
410
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
411
parameter width = 32;
412
parameter nr_of_ports = 5;
413
input [width-1:0] a4, a3, a2, a1, a0;
414
input [nr_of_ports-1:0] sel;
415 22 unneback
output [width-1:0] dout;
416 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
417 18 unneback
integer i;
418
// and
419
assign tmp[0] = {width{sel[0]}} & a0;
420
assign tmp[1] = {width{sel[1]}} & a1;
421
assign tmp[2] = {width{sel[2]}} & a2;
422
assign tmp[3] = {width{sel[3]}} & a3;
423
assign tmp[4] = {width{sel[4]}} & a4;
424
// or
425
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
426
endmodule
427
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
428
parameter width = 32;
429
parameter nr_of_ports = 6;
430
input [width-1:0] a5, a4, a3, a2, a1, a0;
431
input [nr_of_ports-1:0] sel;
432 22 unneback
output [width-1:0] dout;
433 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
434 18 unneback
integer i;
435
// and
436
assign tmp[0] = {width{sel[0]}} & a0;
437
assign tmp[1] = {width{sel[1]}} & a1;
438
assign tmp[2] = {width{sel[2]}} & a2;
439
assign tmp[3] = {width{sel[3]}} & a3;
440
assign tmp[4] = {width{sel[4]}} & a4;
441
assign tmp[5] = {width{sel[5]}} & a5;
442
// or
443
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
444
endmodule
445
//////////////////////////////////////////////////////////////////////
446
////                                                              ////
447 6 unneback
////  Versatile counter                                           ////
448
////                                                              ////
449
////  Description                                                 ////
450
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
451
////  counter                                                     ////
452
////                                                              ////
453
////  To Do:                                                      ////
454
////   - add LFSR with more taps                                  ////
455
////                                                              ////
456
////  Author(s):                                                  ////
457
////      - Michael Unneback, unneback@opencores.org              ////
458
////        ORSoC AB                                              ////
459
////                                                              ////
460
//////////////////////////////////////////////////////////////////////
461
////                                                              ////
462
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
463
////                                                              ////
464
//// This source file may be used and distributed without         ////
465
//// restriction provided that this copyright statement is not    ////
466
//// removed from the file and that any derivative work contains  ////
467
//// the original copyright notice and the associated disclaimer. ////
468
////                                                              ////
469
//// This source file is free software; you can redistribute it   ////
470
//// and/or modify it under the terms of the GNU Lesser General   ////
471
//// Public License as published by the Free Software Foundation; ////
472
//// either version 2.1 of the License, or (at your option) any   ////
473
//// later version.                                               ////
474
////                                                              ////
475
//// This source is distributed in the hope that it will be       ////
476
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
477
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
478
//// PURPOSE.  See the GNU Lesser General Public License for more ////
479
//// details.                                                     ////
480
////                                                              ////
481
//// You should have received a copy of the GNU Lesser General    ////
482
//// Public License along with this source; if not, download it   ////
483
//// from http://www.opencores.org/lgpl.shtml                     ////
484
////                                                              ////
485
//////////////////////////////////////////////////////////////////////
486
// binary counter
487 22 unneback
module vl_cnt_bin ( q, rst, clk);
488
   parameter length = 4;
489
   output [length:1] q;
490
   input rst;
491
   input clk;
492
   parameter clear_value = 0;
493
   parameter set_value = 1;
494
   parameter wrap_value = 0;
495
   parameter level1_value = 15;
496
   reg  [length:1] qi;
497
   wire [length:1] q_next;
498
   assign q_next = qi + {{length-1{1'b0}},1'b1};
499
   always @ (posedge clk or posedge rst)
500
     if (rst)
501
       qi <= {length{1'b0}};
502
     else
503
       qi <= q_next;
504
   assign q = qi;
505
endmodule
506
//////////////////////////////////////////////////////////////////////
507
////                                                              ////
508
////  Versatile counter                                           ////
509
////                                                              ////
510
////  Description                                                 ////
511
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
512
////  counter                                                     ////
513
////                                                              ////
514
////  To Do:                                                      ////
515
////   - add LFSR with more taps                                  ////
516
////                                                              ////
517
////  Author(s):                                                  ////
518
////      - Michael Unneback, unneback@opencores.org              ////
519
////        ORSoC AB                                              ////
520
////                                                              ////
521
//////////////////////////////////////////////////////////////////////
522
////                                                              ////
523
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
524
////                                                              ////
525
//// This source file may be used and distributed without         ////
526
//// restriction provided that this copyright statement is not    ////
527
//// removed from the file and that any derivative work contains  ////
528
//// the original copyright notice and the associated disclaimer. ////
529
////                                                              ////
530
//// This source file is free software; you can redistribute it   ////
531
//// and/or modify it under the terms of the GNU Lesser General   ////
532
//// Public License as published by the Free Software Foundation; ////
533
//// either version 2.1 of the License, or (at your option) any   ////
534
//// later version.                                               ////
535
////                                                              ////
536
//// This source is distributed in the hope that it will be       ////
537
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
538
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
539
//// PURPOSE.  See the GNU Lesser General Public License for more ////
540
//// details.                                                     ////
541
////                                                              ////
542
//// You should have received a copy of the GNU Lesser General    ////
543
//// Public License along with this source; if not, download it   ////
544
//// from http://www.opencores.org/lgpl.shtml                     ////
545
////                                                              ////
546
//////////////////////////////////////////////////////////////////////
547
// binary counter
548
module vl_cnt_bin_clear ( clear, q, rst, clk);
549
   parameter length = 4;
550
   input clear;
551
   output [length:1] q;
552
   input rst;
553
   input clk;
554
   parameter clear_value = 0;
555
   parameter set_value = 1;
556
   parameter wrap_value = 0;
557
   parameter level1_value = 15;
558
   reg  [length:1] qi;
559
   wire [length:1] q_next;
560
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
561
   always @ (posedge clk or posedge rst)
562
     if (rst)
563
       qi <= {length{1'b0}};
564
     else
565
       qi <= q_next;
566
   assign q = qi;
567
endmodule
568
//////////////////////////////////////////////////////////////////////
569
////                                                              ////
570
////  Versatile counter                                           ////
571
////                                                              ////
572
////  Description                                                 ////
573
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
574
////  counter                                                     ////
575
////                                                              ////
576
////  To Do:                                                      ////
577
////   - add LFSR with more taps                                  ////
578
////                                                              ////
579
////  Author(s):                                                  ////
580
////      - Michael Unneback, unneback@opencores.org              ////
581
////        ORSoC AB                                              ////
582
////                                                              ////
583
//////////////////////////////////////////////////////////////////////
584
////                                                              ////
585
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
586
////                                                              ////
587
//// This source file may be used and distributed without         ////
588
//// restriction provided that this copyright statement is not    ////
589
//// removed from the file and that any derivative work contains  ////
590
//// the original copyright notice and the associated disclaimer. ////
591
////                                                              ////
592
//// This source file is free software; you can redistribute it   ////
593
//// and/or modify it under the terms of the GNU Lesser General   ////
594
//// Public License as published by the Free Software Foundation; ////
595
//// either version 2.1 of the License, or (at your option) any   ////
596
//// later version.                                               ////
597
////                                                              ////
598
//// This source is distributed in the hope that it will be       ////
599
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
600
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
601
//// PURPOSE.  See the GNU Lesser General Public License for more ////
602
//// details.                                                     ////
603
////                                                              ////
604
//// You should have received a copy of the GNU Lesser General    ////
605
//// Public License along with this source; if not, download it   ////
606
//// from http://www.opencores.org/lgpl.shtml                     ////
607
////                                                              ////
608
//////////////////////////////////////////////////////////////////////
609
// binary counter
610 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
611 6 unneback
   parameter length = 4;
612
   input cke;
613
   output [length:1] q;
614
   input rst;
615
   input clk;
616
   parameter clear_value = 0;
617
   parameter set_value = 1;
618
   parameter wrap_value = 0;
619
   parameter level1_value = 15;
620
   reg  [length:1] qi;
621
   wire [length:1] q_next;
622
   assign q_next = qi + {{length-1{1'b0}},1'b1};
623
   always @ (posedge clk or posedge rst)
624
     if (rst)
625
       qi <= {length{1'b0}};
626
     else
627
     if (cke)
628
       qi <= q_next;
629
   assign q = qi;
630
endmodule
631
//////////////////////////////////////////////////////////////////////
632
////                                                              ////
633
////  Versatile counter                                           ////
634
////                                                              ////
635
////  Description                                                 ////
636
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
637
////  counter                                                     ////
638
////                                                              ////
639
////  To Do:                                                      ////
640
////   - add LFSR with more taps                                  ////
641
////                                                              ////
642
////  Author(s):                                                  ////
643
////      - Michael Unneback, unneback@opencores.org              ////
644
////        ORSoC AB                                              ////
645
////                                                              ////
646
//////////////////////////////////////////////////////////////////////
647
////                                                              ////
648
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
649
////                                                              ////
650
//// This source file may be used and distributed without         ////
651
//// restriction provided that this copyright statement is not    ////
652
//// removed from the file and that any derivative work contains  ////
653
//// the original copyright notice and the associated disclaimer. ////
654
////                                                              ////
655
//// This source file is free software; you can redistribute it   ////
656
//// and/or modify it under the terms of the GNU Lesser General   ////
657
//// Public License as published by the Free Software Foundation; ////
658
//// either version 2.1 of the License, or (at your option) any   ////
659
//// later version.                                               ////
660
////                                                              ////
661
//// This source is distributed in the hope that it will be       ////
662
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
663
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
664
//// PURPOSE.  See the GNU Lesser General Public License for more ////
665
//// details.                                                     ////
666
////                                                              ////
667
//// You should have received a copy of the GNU Lesser General    ////
668
//// Public License along with this source; if not, download it   ////
669
//// from http://www.opencores.org/lgpl.shtml                     ////
670
////                                                              ////
671
//////////////////////////////////////////////////////////////////////
672
// binary counter
673 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
674 6 unneback
   parameter length = 4;
675
   input clear;
676
   input cke;
677
   output [length:1] q;
678
   input rst;
679
   input clk;
680
   parameter clear_value = 0;
681
   parameter set_value = 1;
682
   parameter wrap_value = 0;
683
   parameter level1_value = 15;
684
   reg  [length:1] qi;
685
   wire [length:1] q_next;
686
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
687
   always @ (posedge clk or posedge rst)
688
     if (rst)
689
       qi <= {length{1'b0}};
690
     else
691
     if (cke)
692
       qi <= q_next;
693
   assign q = qi;
694
endmodule
695
//////////////////////////////////////////////////////////////////////
696
////                                                              ////
697
////  Versatile counter                                           ////
698
////                                                              ////
699
////  Description                                                 ////
700
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
701
////  counter                                                     ////
702
////                                                              ////
703
////  To Do:                                                      ////
704
////   - add LFSR with more taps                                  ////
705
////                                                              ////
706
////  Author(s):                                                  ////
707
////      - Michael Unneback, unneback@opencores.org              ////
708
////        ORSoC AB                                              ////
709
////                                                              ////
710
//////////////////////////////////////////////////////////////////////
711
////                                                              ////
712
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
713
////                                                              ////
714
//// This source file may be used and distributed without         ////
715
//// restriction provided that this copyright statement is not    ////
716
//// removed from the file and that any derivative work contains  ////
717
//// the original copyright notice and the associated disclaimer. ////
718
////                                                              ////
719
//// This source file is free software; you can redistribute it   ////
720
//// and/or modify it under the terms of the GNU Lesser General   ////
721
//// Public License as published by the Free Software Foundation; ////
722
//// either version 2.1 of the License, or (at your option) any   ////
723
//// later version.                                               ////
724
////                                                              ////
725
//// This source is distributed in the hope that it will be       ////
726
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
727
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
728
//// PURPOSE.  See the GNU Lesser General Public License for more ////
729
//// details.                                                     ////
730
////                                                              ////
731
//// You should have received a copy of the GNU Lesser General    ////
732
//// Public License along with this source; if not, download it   ////
733
//// from http://www.opencores.org/lgpl.shtml                     ////
734
////                                                              ////
735
//////////////////////////////////////////////////////////////////////
736
// binary counter
737 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
738 6 unneback
   parameter length = 4;
739
   input clear;
740
   input set;
741
   input cke;
742
   input rew;
743
   output [length:1] q;
744
   input rst;
745
   input clk;
746
   parameter clear_value = 0;
747
   parameter set_value = 1;
748
   parameter wrap_value = 0;
749
   parameter level1_value = 15;
750
   reg  [length:1] qi;
751
   wire  [length:1] q_next, q_next_fw, q_next_rew;
752
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
753
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
754
   assign q_next = rew ? q_next_rew : q_next_fw;
755
   always @ (posedge clk or posedge rst)
756
     if (rst)
757
       qi <= {length{1'b0}};
758
     else
759
     if (cke)
760
       qi <= q_next;
761
   assign q = qi;
762
endmodule
763
//////////////////////////////////////////////////////////////////////
764
////                                                              ////
765
////  Versatile counter                                           ////
766
////                                                              ////
767
////  Description                                                 ////
768
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
769
////  counter                                                     ////
770
////                                                              ////
771
////  To Do:                                                      ////
772
////   - add LFSR with more taps                                  ////
773
////                                                              ////
774
////  Author(s):                                                  ////
775
////      - Michael Unneback, unneback@opencores.org              ////
776
////        ORSoC AB                                              ////
777
////                                                              ////
778
//////////////////////////////////////////////////////////////////////
779
////                                                              ////
780
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
781
////                                                              ////
782
//// This source file may be used and distributed without         ////
783
//// restriction provided that this copyright statement is not    ////
784
//// removed from the file and that any derivative work contains  ////
785
//// the original copyright notice and the associated disclaimer. ////
786
////                                                              ////
787
//// This source file is free software; you can redistribute it   ////
788
//// and/or modify it under the terms of the GNU Lesser General   ////
789
//// Public License as published by the Free Software Foundation; ////
790
//// either version 2.1 of the License, or (at your option) any   ////
791
//// later version.                                               ////
792
////                                                              ////
793
//// This source is distributed in the hope that it will be       ////
794
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
795
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
796
//// PURPOSE.  See the GNU Lesser General Public License for more ////
797
//// details.                                                     ////
798
////                                                              ////
799
//// You should have received a copy of the GNU Lesser General    ////
800
//// Public License along with this source; if not, download it   ////
801
//// from http://www.opencores.org/lgpl.shtml                     ////
802
////                                                              ////
803
//////////////////////////////////////////////////////////////////////
804
// binary counter
805 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
806 6 unneback
   parameter length = 4;
807
   input cke;
808
   input rew;
809
   output reg level1;
810
   input rst;
811
   input clk;
812
   parameter clear_value = 0;
813
   parameter set_value = 1;
814
   parameter wrap_value = 1;
815
   parameter level1_value = 15;
816
   reg  [length:1] qi;
817
   wire  [length:1] q_next, q_next_fw, q_next_rew;
818
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
819
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
820
   assign q_next = rew ? q_next_rew : q_next_fw;
821
   always @ (posedge clk or posedge rst)
822
     if (rst)
823
       qi <= {length{1'b0}};
824
     else
825
     if (cke)
826
       qi <= q_next;
827
    always @ (posedge clk or posedge rst)
828
    if (rst)
829
        level1 <= 1'b0;
830
    else
831
    if (cke)
832
    if (q_next == level1_value)
833
        level1 <= 1'b1;
834
    else if (qi == level1_value & rew)
835
        level1 <= 1'b0;
836
endmodule
837
//////////////////////////////////////////////////////////////////////
838
////                                                              ////
839
////  Versatile counter                                           ////
840
////                                                              ////
841
////  Description                                                 ////
842
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
843
////  counter                                                     ////
844
////                                                              ////
845
////  To Do:                                                      ////
846
////   - add LFSR with more taps                                  ////
847
////                                                              ////
848
////  Author(s):                                                  ////
849
////      - Michael Unneback, unneback@opencores.org              ////
850
////        ORSoC AB                                              ////
851
////                                                              ////
852
//////////////////////////////////////////////////////////////////////
853
////                                                              ////
854
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
855
////                                                              ////
856
//// This source file may be used and distributed without         ////
857
//// restriction provided that this copyright statement is not    ////
858
//// removed from the file and that any derivative work contains  ////
859
//// the original copyright notice and the associated disclaimer. ////
860
////                                                              ////
861
//// This source file is free software; you can redistribute it   ////
862
//// and/or modify it under the terms of the GNU Lesser General   ////
863
//// Public License as published by the Free Software Foundation; ////
864
//// either version 2.1 of the License, or (at your option) any   ////
865
//// later version.                                               ////
866
////                                                              ////
867
//// This source is distributed in the hope that it will be       ////
868
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
869
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
870
//// PURPOSE.  See the GNU Lesser General Public License for more ////
871
//// details.                                                     ////
872
////                                                              ////
873
//// You should have received a copy of the GNU Lesser General    ////
874
//// Public License along with this source; if not, download it   ////
875
//// from http://www.opencores.org/lgpl.shtml                     ////
876
////                                                              ////
877
//////////////////////////////////////////////////////////////////////
878 25 unneback
// binary counter
879
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
880
   parameter length = 4;
881
   input cke;
882
   input rew;
883
   output reg zq;
884
   output reg level1;
885
   input rst;
886
   input clk;
887
   parameter clear_value = 0;
888
   parameter set_value = 1;
889
   parameter wrap_value = 1;
890
   parameter level1_value = 15;
891
   reg  [length:1] qi;
892
   wire  [length:1] q_next, q_next_fw, q_next_rew;
893
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
894
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
895
   assign q_next = rew ? q_next_rew : q_next_fw;
896
   always @ (posedge clk or posedge rst)
897
     if (rst)
898
       qi <= {length{1'b0}};
899
     else
900
     if (cke)
901
       qi <= q_next;
902
   always @ (posedge clk or posedge rst)
903
     if (rst)
904
       zq <= 1'b1;
905
     else
906
     if (cke)
907
       zq <= q_next == {length{1'b0}};
908
    always @ (posedge clk or posedge rst)
909
    if (rst)
910
        level1 <= 1'b0;
911
    else
912
    if (cke)
913
    if (q_next == level1_value)
914
        level1 <= 1'b1;
915
    else if (qi == level1_value & rew)
916
        level1 <= 1'b0;
917
endmodule
918
//////////////////////////////////////////////////////////////////////
919
////                                                              ////
920
////  Versatile counter                                           ////
921
////                                                              ////
922
////  Description                                                 ////
923
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
924
////  counter                                                     ////
925
////                                                              ////
926
////  To Do:                                                      ////
927
////   - add LFSR with more taps                                  ////
928
////                                                              ////
929
////  Author(s):                                                  ////
930
////      - Michael Unneback, unneback@opencores.org              ////
931
////        ORSoC AB                                              ////
932
////                                                              ////
933
//////////////////////////////////////////////////////////////////////
934
////                                                              ////
935
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
936
////                                                              ////
937
//// This source file may be used and distributed without         ////
938
//// restriction provided that this copyright statement is not    ////
939
//// removed from the file and that any derivative work contains  ////
940
//// the original copyright notice and the associated disclaimer. ////
941
////                                                              ////
942
//// This source file is free software; you can redistribute it   ////
943
//// and/or modify it under the terms of the GNU Lesser General   ////
944
//// Public License as published by the Free Software Foundation; ////
945
//// either version 2.1 of the License, or (at your option) any   ////
946
//// later version.                                               ////
947
////                                                              ////
948
//// This source is distributed in the hope that it will be       ////
949
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
950
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
951
//// PURPOSE.  See the GNU Lesser General Public License for more ////
952
//// details.                                                     ////
953
////                                                              ////
954
//// You should have received a copy of the GNU Lesser General    ////
955
//// Public License along with this source; if not, download it   ////
956
//// from http://www.opencores.org/lgpl.shtml                     ////
957
////                                                              ////
958
//////////////////////////////////////////////////////////////////////
959
// binary counter
960
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
961
   parameter length = 4;
962
   input cke;
963
   input rew;
964
   output [length:1] q;
965
   output reg zq;
966
   output reg level1;
967
   input rst;
968
   input clk;
969
   parameter clear_value = 0;
970
   parameter set_value = 1;
971
   parameter wrap_value = 1;
972
   parameter level1_value = 15;
973
   reg  [length:1] qi;
974
   wire  [length:1] q_next, q_next_fw, q_next_rew;
975
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
976
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
977
   assign q_next = rew ? q_next_rew : q_next_fw;
978
   always @ (posedge clk or posedge rst)
979
     if (rst)
980
       qi <= {length{1'b0}};
981
     else
982
     if (cke)
983
       qi <= q_next;
984
   assign q = qi;
985
   always @ (posedge clk or posedge rst)
986
     if (rst)
987
       zq <= 1'b1;
988
     else
989
     if (cke)
990
       zq <= q_next == {length{1'b0}};
991
    always @ (posedge clk or posedge rst)
992
    if (rst)
993
        level1 <= 1'b0;
994
    else
995
    if (cke)
996
    if (q_next == level1_value)
997
        level1 <= 1'b1;
998
    else if (qi == level1_value & rew)
999
        level1 <= 1'b0;
1000
endmodule
1001
//////////////////////////////////////////////////////////////////////
1002
////                                                              ////
1003
////  Versatile counter                                           ////
1004
////                                                              ////
1005
////  Description                                                 ////
1006
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1007
////  counter                                                     ////
1008
////                                                              ////
1009
////  To Do:                                                      ////
1010
////   - add LFSR with more taps                                  ////
1011
////                                                              ////
1012
////  Author(s):                                                  ////
1013
////      - Michael Unneback, unneback@opencores.org              ////
1014
////        ORSoC AB                                              ////
1015
////                                                              ////
1016
//////////////////////////////////////////////////////////////////////
1017
////                                                              ////
1018
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1019
////                                                              ////
1020
//// This source file may be used and distributed without         ////
1021
//// restriction provided that this copyright statement is not    ////
1022
//// removed from the file and that any derivative work contains  ////
1023
//// the original copyright notice and the associated disclaimer. ////
1024
////                                                              ////
1025
//// This source file is free software; you can redistribute it   ////
1026
//// and/or modify it under the terms of the GNU Lesser General   ////
1027
//// Public License as published by the Free Software Foundation; ////
1028
//// either version 2.1 of the License, or (at your option) any   ////
1029
//// later version.                                               ////
1030
////                                                              ////
1031
//// This source is distributed in the hope that it will be       ////
1032
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1033
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1034
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1035
//// details.                                                     ////
1036
////                                                              ////
1037
//// You should have received a copy of the GNU Lesser General    ////
1038
//// Public License along with this source; if not, download it   ////
1039
//// from http://www.opencores.org/lgpl.shtml                     ////
1040
////                                                              ////
1041
//////////////////////////////////////////////////////////////////////
1042 6 unneback
// LFSR counter
1043 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1044 6 unneback
   parameter length = 4;
1045
   output reg zq;
1046
   input rst;
1047
   input clk;
1048
   parameter clear_value = 0;
1049
   parameter set_value = 1;
1050
   parameter wrap_value = 8;
1051
   parameter level1_value = 15;
1052
   reg  [length:1] qi;
1053
   reg lfsr_fb;
1054
   wire [length:1] q_next;
1055
   reg [32:1] polynom;
1056
   integer i;
1057
   always @ (qi)
1058
   begin
1059
        case (length)
1060
         2: polynom = 32'b11;                               // 0x3
1061
         3: polynom = 32'b110;                              // 0x6
1062
         4: polynom = 32'b1100;                             // 0xC
1063
         5: polynom = 32'b10100;                            // 0x14
1064
         6: polynom = 32'b110000;                           // 0x30
1065
         7: polynom = 32'b1100000;                          // 0x60
1066
         8: polynom = 32'b10111000;                         // 0xb8
1067
         9: polynom = 32'b100010000;                        // 0x110
1068
        10: polynom = 32'b1001000000;                       // 0x240
1069
        11: polynom = 32'b10100000000;                      // 0x500
1070
        12: polynom = 32'b100000101001;                     // 0x829
1071
        13: polynom = 32'b1000000001100;                    // 0x100C
1072
        14: polynom = 32'b10000000010101;                   // 0x2015
1073
        15: polynom = 32'b110000000000000;                  // 0x6000
1074
        16: polynom = 32'b1101000000001000;                 // 0xD008
1075
        17: polynom = 32'b10010000000000000;                // 0x12000
1076
        18: polynom = 32'b100000010000000000;               // 0x20400
1077
        19: polynom = 32'b1000000000000100011;              // 0x40023
1078
        20: polynom = 32'b10000010000000000000;             // 0x82000
1079
        21: polynom = 32'b101000000000000000000;            // 0x140000
1080
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1081
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1082
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1083
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1084
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1085
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1086
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1087
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1088
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1089
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1090
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1091
        default: polynom = 32'b0;
1092
        endcase
1093
        lfsr_fb = qi[length];
1094
        for (i=length-1; i>=1; i=i-1) begin
1095
            if (polynom[i])
1096
                lfsr_fb = lfsr_fb  ~^ qi[i];
1097
        end
1098
    end
1099
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1100
   always @ (posedge clk or posedge rst)
1101
     if (rst)
1102
       qi <= {length{1'b0}};
1103
     else
1104
       qi <= q_next;
1105
   always @ (posedge clk or posedge rst)
1106
     if (rst)
1107
       zq <= 1'b1;
1108
     else
1109
       zq <= q_next == {length{1'b0}};
1110
endmodule
1111
//////////////////////////////////////////////////////////////////////
1112
////                                                              ////
1113
////  Versatile counter                                           ////
1114
////                                                              ////
1115
////  Description                                                 ////
1116
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1117
////  counter                                                     ////
1118
////                                                              ////
1119
////  To Do:                                                      ////
1120
////   - add LFSR with more taps                                  ////
1121
////                                                              ////
1122
////  Author(s):                                                  ////
1123
////      - Michael Unneback, unneback@opencores.org              ////
1124
////        ORSoC AB                                              ////
1125
////                                                              ////
1126
//////////////////////////////////////////////////////////////////////
1127
////                                                              ////
1128
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1129
////                                                              ////
1130
//// This source file may be used and distributed without         ////
1131
//// restriction provided that this copyright statement is not    ////
1132
//// removed from the file and that any derivative work contains  ////
1133
//// the original copyright notice and the associated disclaimer. ////
1134
////                                                              ////
1135
//// This source file is free software; you can redistribute it   ////
1136
//// and/or modify it under the terms of the GNU Lesser General   ////
1137
//// Public License as published by the Free Software Foundation; ////
1138
//// either version 2.1 of the License, or (at your option) any   ////
1139
//// later version.                                               ////
1140
////                                                              ////
1141
//// This source is distributed in the hope that it will be       ////
1142
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1143
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1144
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1145
//// details.                                                     ////
1146
////                                                              ////
1147
//// You should have received a copy of the GNU Lesser General    ////
1148
//// Public License along with this source; if not, download it   ////
1149
//// from http://www.opencores.org/lgpl.shtml                     ////
1150
////                                                              ////
1151
//////////////////////////////////////////////////////////////////////
1152
// LFSR counter
1153 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1154 6 unneback
   parameter length = 4;
1155
   input cke;
1156
   output reg zq;
1157
   input rst;
1158
   input clk;
1159
   parameter clear_value = 0;
1160
   parameter set_value = 1;
1161
   parameter wrap_value = 8;
1162
   parameter level1_value = 15;
1163
   reg  [length:1] qi;
1164
   reg lfsr_fb;
1165
   wire [length:1] q_next;
1166
   reg [32:1] polynom;
1167
   integer i;
1168
   always @ (qi)
1169
   begin
1170
        case (length)
1171
         2: polynom = 32'b11;                               // 0x3
1172
         3: polynom = 32'b110;                              // 0x6
1173
         4: polynom = 32'b1100;                             // 0xC
1174
         5: polynom = 32'b10100;                            // 0x14
1175
         6: polynom = 32'b110000;                           // 0x30
1176
         7: polynom = 32'b1100000;                          // 0x60
1177
         8: polynom = 32'b10111000;                         // 0xb8
1178
         9: polynom = 32'b100010000;                        // 0x110
1179
        10: polynom = 32'b1001000000;                       // 0x240
1180
        11: polynom = 32'b10100000000;                      // 0x500
1181
        12: polynom = 32'b100000101001;                     // 0x829
1182
        13: polynom = 32'b1000000001100;                    // 0x100C
1183
        14: polynom = 32'b10000000010101;                   // 0x2015
1184
        15: polynom = 32'b110000000000000;                  // 0x6000
1185
        16: polynom = 32'b1101000000001000;                 // 0xD008
1186
        17: polynom = 32'b10010000000000000;                // 0x12000
1187
        18: polynom = 32'b100000010000000000;               // 0x20400
1188
        19: polynom = 32'b1000000000000100011;              // 0x40023
1189
        20: polynom = 32'b10000010000000000000;             // 0x82000
1190
        21: polynom = 32'b101000000000000000000;            // 0x140000
1191
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1192
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1193
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1194
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1195
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1196
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1197
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1198
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1199
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1200
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1201
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1202
        default: polynom = 32'b0;
1203
        endcase
1204
        lfsr_fb = qi[length];
1205
        for (i=length-1; i>=1; i=i-1) begin
1206
            if (polynom[i])
1207
                lfsr_fb = lfsr_fb  ~^ qi[i];
1208
        end
1209
    end
1210
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1211
   always @ (posedge clk or posedge rst)
1212
     if (rst)
1213
       qi <= {length{1'b0}};
1214
     else
1215
     if (cke)
1216
       qi <= q_next;
1217
   always @ (posedge clk or posedge rst)
1218
     if (rst)
1219
       zq <= 1'b1;
1220
     else
1221
     if (cke)
1222
       zq <= q_next == {length{1'b0}};
1223
endmodule
1224
//////////////////////////////////////////////////////////////////////
1225
////                                                              ////
1226
////  Versatile counter                                           ////
1227
////                                                              ////
1228
////  Description                                                 ////
1229
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1230
////  counter                                                     ////
1231
////                                                              ////
1232
////  To Do:                                                      ////
1233
////   - add LFSR with more taps                                  ////
1234
////                                                              ////
1235
////  Author(s):                                                  ////
1236
////      - Michael Unneback, unneback@opencores.org              ////
1237
////        ORSoC AB                                              ////
1238
////                                                              ////
1239
//////////////////////////////////////////////////////////////////////
1240
////                                                              ////
1241
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1242
////                                                              ////
1243
//// This source file may be used and distributed without         ////
1244
//// restriction provided that this copyright statement is not    ////
1245
//// removed from the file and that any derivative work contains  ////
1246
//// the original copyright notice and the associated disclaimer. ////
1247
////                                                              ////
1248
//// This source file is free software; you can redistribute it   ////
1249
//// and/or modify it under the terms of the GNU Lesser General   ////
1250
//// Public License as published by the Free Software Foundation; ////
1251
//// either version 2.1 of the License, or (at your option) any   ////
1252
//// later version.                                               ////
1253
////                                                              ////
1254
//// This source is distributed in the hope that it will be       ////
1255
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1256
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1257
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1258
//// details.                                                     ////
1259
////                                                              ////
1260
//// You should have received a copy of the GNU Lesser General    ////
1261
//// Public License along with this source; if not, download it   ////
1262
//// from http://www.opencores.org/lgpl.shtml                     ////
1263
////                                                              ////
1264
//////////////////////////////////////////////////////////////////////
1265
// LFSR counter
1266 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1267
   parameter length = 4;
1268
   input cke;
1269
   output [length:1] q;
1270
   input rst;
1271
   input clk;
1272
   parameter clear_value = 0;
1273
   parameter set_value = 1;
1274
   parameter wrap_value = 8;
1275
   parameter level1_value = 15;
1276
   reg  [length:1] qi;
1277
   reg lfsr_fb;
1278
   wire [length:1] q_next;
1279
   reg [32:1] polynom;
1280
   integer i;
1281
   always @ (qi)
1282
   begin
1283
        case (length)
1284
         2: polynom = 32'b11;                               // 0x3
1285
         3: polynom = 32'b110;                              // 0x6
1286
         4: polynom = 32'b1100;                             // 0xC
1287
         5: polynom = 32'b10100;                            // 0x14
1288
         6: polynom = 32'b110000;                           // 0x30
1289
         7: polynom = 32'b1100000;                          // 0x60
1290
         8: polynom = 32'b10111000;                         // 0xb8
1291
         9: polynom = 32'b100010000;                        // 0x110
1292
        10: polynom = 32'b1001000000;                       // 0x240
1293
        11: polynom = 32'b10100000000;                      // 0x500
1294
        12: polynom = 32'b100000101001;                     // 0x829
1295
        13: polynom = 32'b1000000001100;                    // 0x100C
1296
        14: polynom = 32'b10000000010101;                   // 0x2015
1297
        15: polynom = 32'b110000000000000;                  // 0x6000
1298
        16: polynom = 32'b1101000000001000;                 // 0xD008
1299
        17: polynom = 32'b10010000000000000;                // 0x12000
1300
        18: polynom = 32'b100000010000000000;               // 0x20400
1301
        19: polynom = 32'b1000000000000100011;              // 0x40023
1302
        20: polynom = 32'b10000010000000000000;             // 0x82000
1303
        21: polynom = 32'b101000000000000000000;            // 0x140000
1304
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1305
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1306
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1307
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1308
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1309
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1310
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1311
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1312
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1313
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1314
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1315
        default: polynom = 32'b0;
1316
        endcase
1317
        lfsr_fb = qi[length];
1318
        for (i=length-1; i>=1; i=i-1) begin
1319
            if (polynom[i])
1320
                lfsr_fb = lfsr_fb  ~^ qi[i];
1321
        end
1322
    end
1323
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1324
   always @ (posedge clk or posedge rst)
1325
     if (rst)
1326
       qi <= {length{1'b0}};
1327
     else
1328
     if (cke)
1329
       qi <= q_next;
1330
   assign q = qi;
1331
endmodule
1332
//////////////////////////////////////////////////////////////////////
1333
////                                                              ////
1334
////  Versatile counter                                           ////
1335
////                                                              ////
1336
////  Description                                                 ////
1337
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1338
////  counter                                                     ////
1339
////                                                              ////
1340
////  To Do:                                                      ////
1341
////   - add LFSR with more taps                                  ////
1342
////                                                              ////
1343
////  Author(s):                                                  ////
1344
////      - Michael Unneback, unneback@opencores.org              ////
1345
////        ORSoC AB                                              ////
1346
////                                                              ////
1347
//////////////////////////////////////////////////////////////////////
1348
////                                                              ////
1349
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1350
////                                                              ////
1351
//// This source file may be used and distributed without         ////
1352
//// restriction provided that this copyright statement is not    ////
1353
//// removed from the file and that any derivative work contains  ////
1354
//// the original copyright notice and the associated disclaimer. ////
1355
////                                                              ////
1356
//// This source file is free software; you can redistribute it   ////
1357
//// and/or modify it under the terms of the GNU Lesser General   ////
1358
//// Public License as published by the Free Software Foundation; ////
1359
//// either version 2.1 of the License, or (at your option) any   ////
1360
//// later version.                                               ////
1361
////                                                              ////
1362
//// This source is distributed in the hope that it will be       ////
1363
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1364
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1365
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1366
//// details.                                                     ////
1367
////                                                              ////
1368
//// You should have received a copy of the GNU Lesser General    ////
1369
//// Public License along with this source; if not, download it   ////
1370
//// from http://www.opencores.org/lgpl.shtml                     ////
1371
////                                                              ////
1372
//////////////////////////////////////////////////////////////////////
1373
// LFSR counter
1374
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1375
   parameter length = 4;
1376
   input clear;
1377
   input cke;
1378
   output [length:1] q;
1379
   input rst;
1380
   input clk;
1381
   parameter clear_value = 0;
1382
   parameter set_value = 1;
1383
   parameter wrap_value = 8;
1384
   parameter level1_value = 15;
1385
   reg  [length:1] qi;
1386
   reg lfsr_fb;
1387
   wire [length:1] q_next;
1388
   reg [32:1] polynom;
1389
   integer i;
1390
   always @ (qi)
1391
   begin
1392
        case (length)
1393
         2: polynom = 32'b11;                               // 0x3
1394
         3: polynom = 32'b110;                              // 0x6
1395
         4: polynom = 32'b1100;                             // 0xC
1396
         5: polynom = 32'b10100;                            // 0x14
1397
         6: polynom = 32'b110000;                           // 0x30
1398
         7: polynom = 32'b1100000;                          // 0x60
1399
         8: polynom = 32'b10111000;                         // 0xb8
1400
         9: polynom = 32'b100010000;                        // 0x110
1401
        10: polynom = 32'b1001000000;                       // 0x240
1402
        11: polynom = 32'b10100000000;                      // 0x500
1403
        12: polynom = 32'b100000101001;                     // 0x829
1404
        13: polynom = 32'b1000000001100;                    // 0x100C
1405
        14: polynom = 32'b10000000010101;                   // 0x2015
1406
        15: polynom = 32'b110000000000000;                  // 0x6000
1407
        16: polynom = 32'b1101000000001000;                 // 0xD008
1408
        17: polynom = 32'b10010000000000000;                // 0x12000
1409
        18: polynom = 32'b100000010000000000;               // 0x20400
1410
        19: polynom = 32'b1000000000000100011;              // 0x40023
1411
        20: polynom = 32'b10000010000000000000;             // 0x82000
1412
        21: polynom = 32'b101000000000000000000;            // 0x140000
1413
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1414
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1415
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1416
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1417
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1418
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1419
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1420
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1421
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1422
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1423
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1424
        default: polynom = 32'b0;
1425
        endcase
1426
        lfsr_fb = qi[length];
1427
        for (i=length-1; i>=1; i=i-1) begin
1428
            if (polynom[i])
1429
                lfsr_fb = lfsr_fb  ~^ qi[i];
1430
        end
1431
    end
1432
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1433
   always @ (posedge clk or posedge rst)
1434
     if (rst)
1435
       qi <= {length{1'b0}};
1436
     else
1437
     if (cke)
1438
       qi <= q_next;
1439
   assign q = qi;
1440
endmodule
1441
//////////////////////////////////////////////////////////////////////
1442
////                                                              ////
1443
////  Versatile counter                                           ////
1444
////                                                              ////
1445
////  Description                                                 ////
1446
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1447
////  counter                                                     ////
1448
////                                                              ////
1449
////  To Do:                                                      ////
1450
////   - add LFSR with more taps                                  ////
1451
////                                                              ////
1452
////  Author(s):                                                  ////
1453
////      - Michael Unneback, unneback@opencores.org              ////
1454
////        ORSoC AB                                              ////
1455
////                                                              ////
1456
//////////////////////////////////////////////////////////////////////
1457
////                                                              ////
1458
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1459
////                                                              ////
1460
//// This source file may be used and distributed without         ////
1461
//// restriction provided that this copyright statement is not    ////
1462
//// removed from the file and that any derivative work contains  ////
1463
//// the original copyright notice and the associated disclaimer. ////
1464
////                                                              ////
1465
//// This source file is free software; you can redistribute it   ////
1466
//// and/or modify it under the terms of the GNU Lesser General   ////
1467
//// Public License as published by the Free Software Foundation; ////
1468
//// either version 2.1 of the License, or (at your option) any   ////
1469
//// later version.                                               ////
1470
////                                                              ////
1471
//// This source is distributed in the hope that it will be       ////
1472
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1473
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1474
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1475
//// details.                                                     ////
1476
////                                                              ////
1477
//// You should have received a copy of the GNU Lesser General    ////
1478
//// Public License along with this source; if not, download it   ////
1479
//// from http://www.opencores.org/lgpl.shtml                     ////
1480
////                                                              ////
1481
//////////////////////////////////////////////////////////////////////
1482
// LFSR counter
1483 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1484
   parameter length = 4;
1485
   input cke;
1486
   output [length:1] q;
1487
   output reg zq;
1488
   input rst;
1489
   input clk;
1490
   parameter clear_value = 0;
1491
   parameter set_value = 1;
1492
   parameter wrap_value = 8;
1493
   parameter level1_value = 15;
1494
   reg  [length:1] qi;
1495
   reg lfsr_fb;
1496
   wire [length:1] q_next;
1497
   reg [32:1] polynom;
1498
   integer i;
1499
   always @ (qi)
1500
   begin
1501
        case (length)
1502
         2: polynom = 32'b11;                               // 0x3
1503
         3: polynom = 32'b110;                              // 0x6
1504
         4: polynom = 32'b1100;                             // 0xC
1505
         5: polynom = 32'b10100;                            // 0x14
1506
         6: polynom = 32'b110000;                           // 0x30
1507
         7: polynom = 32'b1100000;                          // 0x60
1508
         8: polynom = 32'b10111000;                         // 0xb8
1509
         9: polynom = 32'b100010000;                        // 0x110
1510
        10: polynom = 32'b1001000000;                       // 0x240
1511
        11: polynom = 32'b10100000000;                      // 0x500
1512
        12: polynom = 32'b100000101001;                     // 0x829
1513
        13: polynom = 32'b1000000001100;                    // 0x100C
1514
        14: polynom = 32'b10000000010101;                   // 0x2015
1515
        15: polynom = 32'b110000000000000;                  // 0x6000
1516
        16: polynom = 32'b1101000000001000;                 // 0xD008
1517
        17: polynom = 32'b10010000000000000;                // 0x12000
1518
        18: polynom = 32'b100000010000000000;               // 0x20400
1519
        19: polynom = 32'b1000000000000100011;              // 0x40023
1520
        20: polynom = 32'b10000010000000000000;             // 0x82000
1521
        21: polynom = 32'b101000000000000000000;            // 0x140000
1522
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1523
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1524
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1525
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1526
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1527
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1528
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1529
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1530
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1531
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1532
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1533
        default: polynom = 32'b0;
1534
        endcase
1535
        lfsr_fb = qi[length];
1536
        for (i=length-1; i>=1; i=i-1) begin
1537
            if (polynom[i])
1538
                lfsr_fb = lfsr_fb  ~^ qi[i];
1539
        end
1540
    end
1541
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1542
   always @ (posedge clk or posedge rst)
1543
     if (rst)
1544
       qi <= {length{1'b0}};
1545
     else
1546
     if (cke)
1547
       qi <= q_next;
1548
   assign q = qi;
1549
   always @ (posedge clk or posedge rst)
1550
     if (rst)
1551
       zq <= 1'b1;
1552
     else
1553
     if (cke)
1554
       zq <= q_next == {length{1'b0}};
1555
endmodule
1556
//////////////////////////////////////////////////////////////////////
1557
////                                                              ////
1558
////  Versatile counter                                           ////
1559
////                                                              ////
1560
////  Description                                                 ////
1561
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1562
////  counter                                                     ////
1563
////                                                              ////
1564
////  To Do:                                                      ////
1565
////   - add LFSR with more taps                                  ////
1566
////                                                              ////
1567
////  Author(s):                                                  ////
1568
////      - Michael Unneback, unneback@opencores.org              ////
1569
////        ORSoC AB                                              ////
1570
////                                                              ////
1571
//////////////////////////////////////////////////////////////////////
1572
////                                                              ////
1573
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1574
////                                                              ////
1575
//// This source file may be used and distributed without         ////
1576
//// restriction provided that this copyright statement is not    ////
1577
//// removed from the file and that any derivative work contains  ////
1578
//// the original copyright notice and the associated disclaimer. ////
1579
////                                                              ////
1580
//// This source file is free software; you can redistribute it   ////
1581
//// and/or modify it under the terms of the GNU Lesser General   ////
1582
//// Public License as published by the Free Software Foundation; ////
1583
//// either version 2.1 of the License, or (at your option) any   ////
1584
//// later version.                                               ////
1585
////                                                              ////
1586
//// This source is distributed in the hope that it will be       ////
1587
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1588
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1589
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1590
//// details.                                                     ////
1591
////                                                              ////
1592
//// You should have received a copy of the GNU Lesser General    ////
1593
//// Public License along with this source; if not, download it   ////
1594
//// from http://www.opencores.org/lgpl.shtml                     ////
1595
////                                                              ////
1596
//////////////////////////////////////////////////////////////////////
1597
// LFSR counter
1598 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1599 6 unneback
   parameter length = 4;
1600
   input cke;
1601
   input rew;
1602
   output reg level1;
1603
   input rst;
1604
   input clk;
1605
   parameter clear_value = 0;
1606
   parameter set_value = 1;
1607
   parameter wrap_value = 8;
1608
   parameter level1_value = 15;
1609
   reg  [length:1] qi;
1610
   reg lfsr_fb, lfsr_fb_rew;
1611
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1612
   reg [32:1] polynom_rew;
1613
   integer j;
1614
   reg [32:1] polynom;
1615
   integer i;
1616
   always @ (qi)
1617
   begin
1618
        case (length)
1619
         2: polynom = 32'b11;                               // 0x3
1620
         3: polynom = 32'b110;                              // 0x6
1621
         4: polynom = 32'b1100;                             // 0xC
1622
         5: polynom = 32'b10100;                            // 0x14
1623
         6: polynom = 32'b110000;                           // 0x30
1624
         7: polynom = 32'b1100000;                          // 0x60
1625
         8: polynom = 32'b10111000;                         // 0xb8
1626
         9: polynom = 32'b100010000;                        // 0x110
1627
        10: polynom = 32'b1001000000;                       // 0x240
1628
        11: polynom = 32'b10100000000;                      // 0x500
1629
        12: polynom = 32'b100000101001;                     // 0x829
1630
        13: polynom = 32'b1000000001100;                    // 0x100C
1631
        14: polynom = 32'b10000000010101;                   // 0x2015
1632
        15: polynom = 32'b110000000000000;                  // 0x6000
1633
        16: polynom = 32'b1101000000001000;                 // 0xD008
1634
        17: polynom = 32'b10010000000000000;                // 0x12000
1635
        18: polynom = 32'b100000010000000000;               // 0x20400
1636
        19: polynom = 32'b1000000000000100011;              // 0x40023
1637
        20: polynom = 32'b10000010000000000000;             // 0x82000
1638
        21: polynom = 32'b101000000000000000000;            // 0x140000
1639
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1640
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1641
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1642
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1643
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1644
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1645
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1646
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1647
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1648
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1649
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1650
        default: polynom = 32'b0;
1651
        endcase
1652
        lfsr_fb = qi[length];
1653
        for (i=length-1; i>=1; i=i-1) begin
1654
            if (polynom[i])
1655
                lfsr_fb = lfsr_fb  ~^ qi[i];
1656
        end
1657
    end
1658
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1659
   always @ (qi)
1660
   begin
1661
        case (length)
1662
         2: polynom_rew = 32'b11;
1663
         3: polynom_rew = 32'b110;
1664
         4: polynom_rew = 32'b1100;
1665
         5: polynom_rew = 32'b10100;
1666
         6: polynom_rew = 32'b110000;
1667
         7: polynom_rew = 32'b1100000;
1668
         8: polynom_rew = 32'b10111000;
1669
         9: polynom_rew = 32'b100010000;
1670
        10: polynom_rew = 32'b1001000000;
1671
        11: polynom_rew = 32'b10100000000;
1672
        12: polynom_rew = 32'b100000101001;
1673
        13: polynom_rew = 32'b1000000001100;
1674
        14: polynom_rew = 32'b10000000010101;
1675
        15: polynom_rew = 32'b110000000000000;
1676
        16: polynom_rew = 32'b1101000000001000;
1677
        17: polynom_rew = 32'b10010000000000000;
1678
        18: polynom_rew = 32'b100000010000000000;
1679
        19: polynom_rew = 32'b1000000000000100011;
1680
        20: polynom_rew = 32'b10000010000000000000;
1681
        21: polynom_rew = 32'b101000000000000000000;
1682
        22: polynom_rew = 32'b1100000000000000000000;
1683
        23: polynom_rew = 32'b10000100000000000000000;
1684
        24: polynom_rew = 32'b111000010000000000000000;
1685
        25: polynom_rew = 32'b1001000000000000000000000;
1686
        26: polynom_rew = 32'b10000000000000000000100011;
1687
        27: polynom_rew = 32'b100000000000000000000010011;
1688
        28: polynom_rew = 32'b1100100000000000000000000000;
1689
        29: polynom_rew = 32'b10100000000000000000000000000;
1690
        30: polynom_rew = 32'b100000000000000000000000101001;
1691
        31: polynom_rew = 32'b1001000000000000000000000000000;
1692
        32: polynom_rew = 32'b10000000001000000000000000000011;
1693
        default: polynom_rew = 32'b0;
1694
        endcase
1695
        // rotate left
1696
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1697
        lfsr_fb_rew = qi[length];
1698
        for (i=length-1; i>=1; i=i-1) begin
1699
            if (polynom_rew[i])
1700
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1701
        end
1702
    end
1703
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1704
   assign q_next = rew ? q_next_rew : q_next_fw;
1705
   always @ (posedge clk or posedge rst)
1706
     if (rst)
1707
       qi <= {length{1'b0}};
1708
     else
1709
     if (cke)
1710
       qi <= q_next;
1711
    always @ (posedge clk or posedge rst)
1712
    if (rst)
1713
        level1 <= 1'b0;
1714
    else
1715
    if (cke)
1716
    if (q_next == level1_value)
1717
        level1 <= 1'b1;
1718
    else if (qi == level1_value & rew)
1719
        level1 <= 1'b0;
1720
endmodule
1721
//////////////////////////////////////////////////////////////////////
1722
////                                                              ////
1723
////  Versatile counter                                           ////
1724
////                                                              ////
1725
////  Description                                                 ////
1726
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1727
////  counter                                                     ////
1728
////                                                              ////
1729
////  To Do:                                                      ////
1730
////   - add LFSR with more taps                                  ////
1731
////                                                              ////
1732
////  Author(s):                                                  ////
1733
////      - Michael Unneback, unneback@opencores.org              ////
1734
////        ORSoC AB                                              ////
1735
////                                                              ////
1736
//////////////////////////////////////////////////////////////////////
1737
////                                                              ////
1738
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1739
////                                                              ////
1740
//// This source file may be used and distributed without         ////
1741
//// restriction provided that this copyright statement is not    ////
1742
//// removed from the file and that any derivative work contains  ////
1743
//// the original copyright notice and the associated disclaimer. ////
1744
////                                                              ////
1745
//// This source file is free software; you can redistribute it   ////
1746
//// and/or modify it under the terms of the GNU Lesser General   ////
1747
//// Public License as published by the Free Software Foundation; ////
1748
//// either version 2.1 of the License, or (at your option) any   ////
1749
//// later version.                                               ////
1750
////                                                              ////
1751
//// This source is distributed in the hope that it will be       ////
1752
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1753
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1754
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1755
//// details.                                                     ////
1756
////                                                              ////
1757
//// You should have received a copy of the GNU Lesser General    ////
1758
//// Public License along with this source; if not, download it   ////
1759
//// from http://www.opencores.org/lgpl.shtml                     ////
1760
////                                                              ////
1761
//////////////////////////////////////////////////////////////////////
1762
// GRAY counter
1763 18 unneback
module vl_cnt_gray ( q, rst, clk);
1764 6 unneback
   parameter length = 4;
1765
   output reg [length:1] q;
1766
   input rst;
1767
   input clk;
1768
   parameter clear_value = 0;
1769
   parameter set_value = 1;
1770
   parameter wrap_value = 8;
1771
   parameter level1_value = 15;
1772
   reg  [length:1] qi;
1773
   wire [length:1] q_next;
1774
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1775
   always @ (posedge clk or posedge rst)
1776
     if (rst)
1777
       qi <= {length{1'b0}};
1778
     else
1779
       qi <= q_next;
1780
   always @ (posedge clk or posedge rst)
1781
     if (rst)
1782
       q <= {length{1'b0}};
1783
     else
1784
         q <= (q_next>>1) ^ q_next;
1785
endmodule
1786
//////////////////////////////////////////////////////////////////////
1787
////                                                              ////
1788
////  Versatile counter                                           ////
1789
////                                                              ////
1790
////  Description                                                 ////
1791
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1792
////  counter                                                     ////
1793
////                                                              ////
1794
////  To Do:                                                      ////
1795
////   - add LFSR with more taps                                  ////
1796
////                                                              ////
1797
////  Author(s):                                                  ////
1798
////      - Michael Unneback, unneback@opencores.org              ////
1799
////        ORSoC AB                                              ////
1800
////                                                              ////
1801
//////////////////////////////////////////////////////////////////////
1802
////                                                              ////
1803
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1804
////                                                              ////
1805
//// This source file may be used and distributed without         ////
1806
//// restriction provided that this copyright statement is not    ////
1807
//// removed from the file and that any derivative work contains  ////
1808
//// the original copyright notice and the associated disclaimer. ////
1809
////                                                              ////
1810
//// This source file is free software; you can redistribute it   ////
1811
//// and/or modify it under the terms of the GNU Lesser General   ////
1812
//// Public License as published by the Free Software Foundation; ////
1813
//// either version 2.1 of the License, or (at your option) any   ////
1814
//// later version.                                               ////
1815
////                                                              ////
1816
//// This source is distributed in the hope that it will be       ////
1817
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1818
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1819
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1820
//// details.                                                     ////
1821
////                                                              ////
1822
//// You should have received a copy of the GNU Lesser General    ////
1823
//// Public License along with this source; if not, download it   ////
1824
//// from http://www.opencores.org/lgpl.shtml                     ////
1825
////                                                              ////
1826
//////////////////////////////////////////////////////////////////////
1827
// GRAY counter
1828 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1829 6 unneback
   parameter length = 4;
1830
   input cke;
1831
   output reg [length:1] q;
1832
   input rst;
1833
   input clk;
1834
   parameter clear_value = 0;
1835
   parameter set_value = 1;
1836
   parameter wrap_value = 8;
1837
   parameter level1_value = 15;
1838
   reg  [length:1] qi;
1839
   wire [length:1] q_next;
1840
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1841
   always @ (posedge clk or posedge rst)
1842
     if (rst)
1843
       qi <= {length{1'b0}};
1844
     else
1845
     if (cke)
1846
       qi <= q_next;
1847
   always @ (posedge clk or posedge rst)
1848
     if (rst)
1849
       q <= {length{1'b0}};
1850
     else
1851
       if (cke)
1852
         q <= (q_next>>1) ^ q_next;
1853
endmodule
1854
//////////////////////////////////////////////////////////////////////
1855
////                                                              ////
1856
////  Versatile counter                                           ////
1857
////                                                              ////
1858
////  Description                                                 ////
1859
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1860
////  counter                                                     ////
1861
////                                                              ////
1862
////  To Do:                                                      ////
1863
////   - add LFSR with more taps                                  ////
1864
////                                                              ////
1865
////  Author(s):                                                  ////
1866
////      - Michael Unneback, unneback@opencores.org              ////
1867
////        ORSoC AB                                              ////
1868
////                                                              ////
1869
//////////////////////////////////////////////////////////////////////
1870
////                                                              ////
1871
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1872
////                                                              ////
1873
//// This source file may be used and distributed without         ////
1874
//// restriction provided that this copyright statement is not    ////
1875
//// removed from the file and that any derivative work contains  ////
1876
//// the original copyright notice and the associated disclaimer. ////
1877
////                                                              ////
1878
//// This source file is free software; you can redistribute it   ////
1879
//// and/or modify it under the terms of the GNU Lesser General   ////
1880
//// Public License as published by the Free Software Foundation; ////
1881
//// either version 2.1 of the License, or (at your option) any   ////
1882
//// later version.                                               ////
1883
////                                                              ////
1884
//// This source is distributed in the hope that it will be       ////
1885
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1886
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1887
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1888
//// details.                                                     ////
1889
////                                                              ////
1890
//// You should have received a copy of the GNU Lesser General    ////
1891
//// Public License along with this source; if not, download it   ////
1892
//// from http://www.opencores.org/lgpl.shtml                     ////
1893
////                                                              ////
1894
//////////////////////////////////////////////////////////////////////
1895
// GRAY counter
1896 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1897 6 unneback
   parameter length = 4;
1898
   input cke;
1899
   output reg [length:1] q;
1900
   output [length:1] q_bin;
1901
   input rst;
1902
   input clk;
1903
   parameter clear_value = 0;
1904
   parameter set_value = 1;
1905
   parameter wrap_value = 8;
1906
   parameter level1_value = 15;
1907
   reg  [length:1] qi;
1908
   wire [length:1] q_next;
1909
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1910
   always @ (posedge clk or posedge rst)
1911
     if (rst)
1912
       qi <= {length{1'b0}};
1913
     else
1914
     if (cke)
1915
       qi <= q_next;
1916
   always @ (posedge clk or posedge rst)
1917
     if (rst)
1918
       q <= {length{1'b0}};
1919
     else
1920
       if (cke)
1921
         q <= (q_next>>1) ^ q_next;
1922
   assign q_bin = qi;
1923
endmodule
1924
//////////////////////////////////////////////////////////////////////
1925
////                                                              ////
1926
////  Versatile library, counters                                 ////
1927
////                                                              ////
1928
////  Description                                                 ////
1929
////  counters                                                    ////
1930
////                                                              ////
1931
////                                                              ////
1932
////  To Do:                                                      ////
1933
////   - add more counters                                        ////
1934
////                                                              ////
1935
////  Author(s):                                                  ////
1936
////      - Michael Unneback, unneback@opencores.org              ////
1937
////        ORSoC AB                                              ////
1938
////                                                              ////
1939
//////////////////////////////////////////////////////////////////////
1940
////                                                              ////
1941
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1942
////                                                              ////
1943
//// This source file may be used and distributed without         ////
1944
//// restriction provided that this copyright statement is not    ////
1945
//// removed from the file and that any derivative work contains  ////
1946
//// the original copyright notice and the associated disclaimer. ////
1947
////                                                              ////
1948
//// This source file is free software; you can redistribute it   ////
1949
//// and/or modify it under the terms of the GNU Lesser General   ////
1950
//// Public License as published by the Free Software Foundation; ////
1951
//// either version 2.1 of the License, or (at your option) any   ////
1952
//// later version.                                               ////
1953
////                                                              ////
1954
//// This source is distributed in the hope that it will be       ////
1955
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1956
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1957
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1958
//// details.                                                     ////
1959
////                                                              ////
1960
//// You should have received a copy of the GNU Lesser General    ////
1961
//// Public License along with this source; if not, download it   ////
1962
//// from http://www.opencores.org/lgpl.shtml                     ////
1963
////                                                              ////
1964
//////////////////////////////////////////////////////////////////////
1965 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1966 6 unneback
   parameter length = 4;
1967
   output reg [0:length-1] q;
1968
   input rst;
1969
   input clk;
1970
    always @ (posedge clk or posedge rst)
1971
    if (rst)
1972
        q <= {1'b1,{length-1{1'b0}}};
1973
    else
1974
        q <= {q[length-1],q[0:length-2]};
1975
endmodule
1976 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1977 6 unneback
   parameter length = 4;
1978
   input cke;
1979
   output reg [0:length-1] q;
1980
   input rst;
1981
   input clk;
1982
    always @ (posedge clk or posedge rst)
1983
    if (rst)
1984
        q <= {1'b1,{length-1{1'b0}}};
1985
    else
1986
        if (cke)
1987
            q <= {q[length-1],q[0:length-2]};
1988
endmodule
1989 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1990 6 unneback
   parameter length = 4;
1991
   input cke, clear;
1992
   output reg [0:length-1] q;
1993
   input rst;
1994
   input clk;
1995
    always @ (posedge clk or posedge rst)
1996
    if (rst)
1997
        q <= {1'b1,{length-1{1'b0}}};
1998
    else
1999
        if (cke)
2000
            if (clear)
2001
                q <= {1'b1,{length-1{1'b0}}};
2002
            else
2003
                q <= q >> 1;
2004
endmodule
2005 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2006 6 unneback
   parameter length = 4;
2007
   input cke, clear;
2008
   output reg [0:length-1] q;
2009
   input rst;
2010
   input clk;
2011
    always @ (posedge clk or posedge rst)
2012
    if (rst)
2013
        q <= {1'b1,{length-1{1'b0}}};
2014
    else
2015
        if (cke)
2016
            if (clear)
2017
                q <= {1'b1,{length-1{1'b0}}};
2018
            else
2019
            q <= {q[length-1],q[0:length-2]};
2020
endmodule
2021
//////////////////////////////////////////////////////////////////////
2022
////                                                              ////
2023
////  Versatile library, memories                                 ////
2024
////                                                              ////
2025
////  Description                                                 ////
2026
////  memories                                                    ////
2027
////                                                              ////
2028
////                                                              ////
2029
////  To Do:                                                      ////
2030
////   - add more memory types                                    ////
2031
////                                                              ////
2032
////  Author(s):                                                  ////
2033
////      - Michael Unneback, unneback@opencores.org              ////
2034
////        ORSoC AB                                              ////
2035
////                                                              ////
2036
//////////////////////////////////////////////////////////////////////
2037
////                                                              ////
2038
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2039
////                                                              ////
2040
//// This source file may be used and distributed without         ////
2041
//// restriction provided that this copyright statement is not    ////
2042
//// removed from the file and that any derivative work contains  ////
2043
//// the original copyright notice and the associated disclaimer. ////
2044
////                                                              ////
2045
//// This source file is free software; you can redistribute it   ////
2046
//// and/or modify it under the terms of the GNU Lesser General   ////
2047
//// Public License as published by the Free Software Foundation; ////
2048
//// either version 2.1 of the License, or (at your option) any   ////
2049
//// later version.                                               ////
2050
////                                                              ////
2051
//// This source is distributed in the hope that it will be       ////
2052
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2053
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2054
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2055
//// details.                                                     ////
2056
////                                                              ////
2057
//// You should have received a copy of the GNU Lesser General    ////
2058
//// Public License along with this source; if not, download it   ////
2059
//// from http://www.opencores.org/lgpl.shtml                     ////
2060
////                                                              ////
2061
//////////////////////////////////////////////////////////////////////
2062
/// ROM
2063 7 unneback
module vl_rom_init ( adr, q, clk);
2064
   parameter data_width = 32;
2065
   parameter addr_width = 8;
2066
   input [(addr_width-1):0]       adr;
2067
   output reg [(data_width-1):0] q;
2068
   input                         clk;
2069
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2070
   parameter memory_file = "vl_rom.vmem";
2071
   initial
2072
     begin
2073
        $readmemh(memory_file, rom);
2074
     end
2075
   always @ (posedge clk)
2076
     q <= rom[adr];
2077
endmodule
2078 14 unneback
/*
2079 7 unneback
module vl_rom ( adr, q, clk);
2080 6 unneback
parameter data_width = 32;
2081
parameter addr_width = 4;
2082
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2083
    {32'h18000000},
2084
    {32'hA8200000},
2085
    {32'hA8200000},
2086
    {32'hA8200000},
2087
    {32'h44003000},
2088
    {32'h15000000},
2089
    {32'h15000000},
2090
    {32'h15000000},
2091
    {32'h15000000},
2092
    {32'h15000000},
2093
    {32'h15000000},
2094
    {32'h15000000},
2095
    {32'h15000000},
2096
    {32'h15000000},
2097
    {32'h15000000},
2098
    {32'h15000000}};
2099 7 unneback
input [addr_width-1:0] adr;
2100 6 unneback
output reg [data_width-1:0] q;
2101
input clk;
2102
always @ (posedge clk)
2103 7 unneback
    q <= data[adr];
2104 6 unneback
endmodule
2105 14 unneback
*/
2106 6 unneback
// Single port RAM
2107
module vl_ram ( d, adr, we, q, clk);
2108
   parameter data_width = 32;
2109
   parameter addr_width = 8;
2110
   input [(data_width-1):0]      d;
2111
   input [(addr_width-1):0]       adr;
2112
   input                         we;
2113 7 unneback
   output reg [(data_width-1):0] q;
2114 6 unneback
   input                         clk;
2115
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2116 7 unneback
   parameter init = 0;
2117
   parameter memory_file = "vl_ram.vmem";
2118
   generate if (init) begin : init_mem
2119
   initial
2120
     begin
2121
        $readmemh(memory_file, ram);
2122
     end
2123
   end
2124
   endgenerate
2125 6 unneback
   always @ (posedge clk)
2126
   begin
2127
   if (we)
2128
     ram[adr] <= d;
2129
   q <= ram[adr];
2130
   end
2131
endmodule
2132 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2133
   parameter data_width = 32;
2134
   parameter addr_width = 8;
2135
   input [(data_width-1):0]      d;
2136
   input [(addr_width-1):0]       adr;
2137
   input [(addr_width/4)-1:0]    be;
2138
   input                         we;
2139
   output reg [(data_width-1):0] q;
2140
   input                         clk;
2141
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2142
   parameter init = 0;
2143
   parameter memory_file = "vl_ram.vmem";
2144
   generate if (init) begin : init_mem
2145
   initial
2146
     begin
2147
        $readmemh(memory_file, ram);
2148
     end
2149
   end
2150
   endgenerate
2151
   genvar i;
2152
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2153
      always @ (posedge clk)
2154
      if (we & be[i])
2155
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2156
   end
2157
   endgenerate
2158
   always @ (posedge clk)
2159
      q <= ram[adr];
2160
endmodule
2161 6 unneback
// Dual port RAM
2162
// ACTEL FPGA should not use logic to handle rw collision
2163 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2164 6 unneback
   parameter data_width = 32;
2165
   parameter addr_width = 8;
2166
   input [(data_width-1):0]      d_a;
2167
   input [(addr_width-1):0]       adr_a;
2168
   input [(addr_width-1):0]       adr_b;
2169
   input                         we_a;
2170
   output [(data_width-1):0]      q_b;
2171
   input                         clk_a, clk_b;
2172
   reg [(addr_width-1):0]         adr_b_reg;
2173
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2174 7 unneback
   parameter init = 0;
2175
   parameter memory_file = "vl_ram.vmem";
2176
   generate if (init) begin : init_mem
2177
   initial
2178
     begin
2179
        $readmemh(memory_file, ram);
2180
     end
2181
   end
2182
   endgenerate
2183 6 unneback
   always @ (posedge clk_a)
2184
   if (we_a)
2185
     ram[adr_a] <= d_a;
2186
   always @ (posedge clk_b)
2187
   adr_b_reg <= adr_b;
2188
   assign q_b = ram[adr_b_reg];
2189
endmodule
2190 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2191 6 unneback
   parameter data_width = 32;
2192
   parameter addr_width = 8;
2193
   input [(data_width-1):0]      d_a;
2194
   input [(addr_width-1):0]       adr_a;
2195
   input [(addr_width-1):0]       adr_b;
2196
   input                         we_a;
2197
   output [(data_width-1):0]      q_b;
2198
   output reg [(data_width-1):0] q_a;
2199
   input                         clk_a, clk_b;
2200
   reg [(data_width-1):0]         q_b;
2201
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2202 7 unneback
   parameter init = 0;
2203
   parameter memory_file = "vl_ram.vmem";
2204
   generate if (init) begin : init_mem
2205
   initial
2206
     begin
2207
        $readmemh(memory_file, ram);
2208
     end
2209
   end
2210
   endgenerate
2211 6 unneback
   always @ (posedge clk_a)
2212
     begin
2213
        q_a <= ram[adr_a];
2214
        if (we_a)
2215
             ram[adr_a] <= d_a;
2216
     end
2217
   always @ (posedge clk_b)
2218
          q_b <= ram[adr_b];
2219
endmodule
2220 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2221 6 unneback
   parameter data_width = 32;
2222
   parameter addr_width = 8;
2223
   input [(data_width-1):0]      d_a;
2224
   input [(addr_width-1):0]       adr_a;
2225
   input [(addr_width-1):0]       adr_b;
2226
   input                         we_a;
2227
   output [(data_width-1):0]      q_b;
2228
   input [(data_width-1):0]       d_b;
2229
   output reg [(data_width-1):0] q_a;
2230
   input                         we_b;
2231
   input                         clk_a, clk_b;
2232
   reg [(data_width-1):0]         q_b;
2233
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2234 7 unneback
   parameter init = 0;
2235
   parameter memory_file = "vl_ram.vmem";
2236
   generate if (init) begin : init_mem
2237
   initial
2238
     begin
2239
        $readmemh(memory_file, ram);
2240
     end
2241
   end
2242
   endgenerate
2243 6 unneback
   always @ (posedge clk_a)
2244
     begin
2245
        q_a <= ram[adr_a];
2246
        if (we_a)
2247
             ram[adr_a] <= d_a;
2248
     end
2249
   always @ (posedge clk_b)
2250
     begin
2251
        q_b <= ram[adr_b];
2252
        if (we_b)
2253
          ram[adr_b] <= d_b;
2254
     end
2255
endmodule
2256
// Content addresable memory, CAM
2257
// FIFO
2258 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2259
    d, wr, fifo_full,
2260
    q, rd, fifo_empty,
2261
    fill_level,
2262
    clk, rst
2263
    );
2264
parameter data_width = 18;
2265
parameter addr_width = 4;
2266
// write side
2267
input  [data_width-1:0] d;
2268
input                   wr;
2269
output                  fifo_full;
2270
// read side
2271
output [data_width-1:0] q;
2272
input                   rd;
2273
output                  fifo_empty;
2274
// common
2275
output [addr_width:0]   fill_level;
2276
input rst, clk;
2277
wire [addr_width:1] wadr, radr;
2278
vl_cnt_bin_ce
2279
    # ( .length(addr_width))
2280
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2281
vl_cnt_bin_ce
2282
    # (.length(addr_width))
2283
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2284
vl_dpram_1r1w
2285
    # (.data_width(data_width), .addr_width(addr_width))
2286
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2287
vl_cnt_bin_ce_rew_zq_l1
2288 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2289 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2290
endmodule
2291 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2292
// RAM is supposed to be larger than the two FIFOs
2293
// LFSR counters used adr pointers
2294
module vl_fifo_2r2w_sync_simplex (
2295
    // a side
2296
    a_d, a_wr, a_fifo_full,
2297
    a_q, a_rd, a_fifo_empty,
2298
    a_fill_level,
2299
    // b side
2300
    b_d, b_wr, b_fifo_full,
2301
    b_q, b_rd, b_fifo_empty,
2302
    b_fill_level,
2303
    // common
2304
    clk, rst
2305
    );
2306
parameter data_width = 8;
2307
parameter addr_width = 5;
2308
parameter fifo_full_level = (1<<addr_width)-1;
2309
// a side
2310
input  [data_width-1:0] a_d;
2311
input                   a_wr;
2312
output                  a_fifo_full;
2313
output [data_width-1:0] a_q;
2314
input                   a_rd;
2315
output                  a_fifo_empty;
2316
output [addr_width-1:0] a_fill_level;
2317
// b side
2318
input  [data_width-1:0] b_d;
2319
input                   b_wr;
2320
output                  b_fifo_full;
2321
output [data_width-1:0] b_q;
2322
input                   b_rd;
2323
output                  b_fifo_empty;
2324
output [addr_width-1:0] b_fill_level;
2325
input                   clk;
2326
input                   rst;
2327
// adr_gen
2328
wire [addr_width:1] a_wadr, a_radr;
2329
wire [addr_width:1] b_wadr, b_radr;
2330
// dpram
2331
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2332
vl_cnt_lfsr_ce
2333
    # ( .length(addr_width))
2334
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2335
vl_cnt_lfsr_ce
2336
    # (.length(addr_width))
2337
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2338
vl_cnt_lfsr_ce
2339
    # ( .length(addr_width))
2340
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2341
vl_cnt_lfsr_ce
2342
    # (.length(addr_width))
2343
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2344
// mux read or write adr to DPRAM
2345
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2346
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2347
vl_dpram_2r2w
2348
    # (.data_width(data_width), .addr_width(addr_width+1))
2349
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2350
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2351
vl_cnt_bin_ce_rew_zq_l1
2352
    # (.length(addr_width+1), .level1_value(fifo_full_level))
2353
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2354
vl_cnt_bin_ce_rew_zq_l1
2355
    # (.length(addr_width+1), .level1_value(fifo_full_level))
2356
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2357
endmodule
2358 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2359 11 unneback
   parameter addr_width = 4;
2360
   parameter N = addr_width-1;
2361 6 unneback
   parameter Q1 = 2'b00;
2362
   parameter Q2 = 2'b01;
2363
   parameter Q3 = 2'b11;
2364
   parameter Q4 = 2'b10;
2365
   parameter going_empty = 1'b0;
2366
   parameter going_full  = 1'b1;
2367
   input [N:0]  wptr, rptr;
2368 14 unneback
   output       fifo_empty;
2369 6 unneback
   output       fifo_full;
2370
   input        wclk, rclk, rst;
2371
   wire direction;
2372
   reg  direction_set, direction_clr;
2373
   wire async_empty, async_full;
2374
   wire fifo_full2;
2375 14 unneback
   wire fifo_empty2;
2376 6 unneback
   // direction_set
2377
   always @ (wptr[N:N-1] or rptr[N:N-1])
2378
     case ({wptr[N:N-1],rptr[N:N-1]})
2379
       {Q1,Q2} : direction_set <= 1'b1;
2380
       {Q2,Q3} : direction_set <= 1'b1;
2381
       {Q3,Q4} : direction_set <= 1'b1;
2382
       {Q4,Q1} : direction_set <= 1'b1;
2383
       default : direction_set <= 1'b0;
2384
     endcase
2385
   // direction_clear
2386
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2387
     if (rst)
2388
       direction_clr <= 1'b1;
2389
     else
2390
       case ({wptr[N:N-1],rptr[N:N-1]})
2391
         {Q2,Q1} : direction_clr <= 1'b1;
2392
         {Q3,Q2} : direction_clr <= 1'b1;
2393
         {Q4,Q3} : direction_clr <= 1'b1;
2394
         {Q1,Q4} : direction_clr <= 1'b1;
2395
         default : direction_clr <= 1'b0;
2396
       endcase
2397 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2398 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2399
   assign async_full  = (wptr == rptr) && (direction==going_full);
2400 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2401
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2402 6 unneback
/*
2403
   always @ (posedge wclk or posedge rst or posedge async_full)
2404
     if (rst)
2405
       {fifo_full, fifo_full2} <= 2'b00;
2406
     else if (async_full)
2407
       {fifo_full, fifo_full2} <= 2'b11;
2408
     else
2409
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2410
*/
2411 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2412 6 unneback
     if (async_empty)
2413
       {fifo_empty, fifo_empty2} <= 2'b11;
2414
     else
2415 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2416 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2417
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2418 27 unneback
endmodule // async_compb
2419 6 unneback
module vl_fifo_1r1w_async (
2420
    d, wr, fifo_full, wr_clk, wr_rst,
2421
    q, rd, fifo_empty, rd_clk, rd_rst
2422
    );
2423
parameter data_width = 18;
2424
parameter addr_width = 4;
2425
// write side
2426
input  [data_width-1:0] d;
2427
input                   wr;
2428
output                  fifo_full;
2429
input                   wr_clk;
2430
input                   wr_rst;
2431
// read side
2432
output [data_width-1:0] q;
2433
input                   rd;
2434
output                  fifo_empty;
2435
input                   rd_clk;
2436
input                   rd_rst;
2437
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2438 18 unneback
vl_cnt_gray_ce_bin
2439 6 unneback
    # ( .length(addr_width))
2440
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2441 18 unneback
vl_cnt_gray_ce_bin
2442 6 unneback
    # (.length(addr_width))
2443 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2444 7 unneback
vl_dpram_1r1w
2445 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2446
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2447
vl_fifo_cmp_async
2448
    # (.addr_width(addr_width))
2449
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2450
endmodule
2451 8 unneback
module vl_fifo_2r2w_async (
2452 6 unneback
    // a side
2453
    a_d, a_wr, a_fifo_full,
2454
    a_q, a_rd, a_fifo_empty,
2455
    a_clk, a_rst,
2456
    // b side
2457
    b_d, b_wr, b_fifo_full,
2458
    b_q, b_rd, b_fifo_empty,
2459
    b_clk, b_rst
2460
    );
2461
parameter data_width = 18;
2462
parameter addr_width = 4;
2463
// a side
2464
input  [data_width-1:0] a_d;
2465
input                   a_wr;
2466
output                  a_fifo_full;
2467
output [data_width-1:0] a_q;
2468
input                   a_rd;
2469
output                  a_fifo_empty;
2470
input                   a_clk;
2471
input                   a_rst;
2472
// b side
2473
input  [data_width-1:0] b_d;
2474
input                   b_wr;
2475
output                  b_fifo_full;
2476
output [data_width-1:0] b_q;
2477
input                   b_rd;
2478
output                  b_fifo_empty;
2479
input                   b_clk;
2480
input                   b_rst;
2481
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2482
vl_fifo_1r1w_async_a (
2483
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2484
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2485
    );
2486
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2487
vl_fifo_1r1w_async_b (
2488
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2489
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2490
    );
2491
endmodule
2492 8 unneback
module vl_fifo_2r2w_async_simplex (
2493 6 unneback
    // a side
2494
    a_d, a_wr, a_fifo_full,
2495
    a_q, a_rd, a_fifo_empty,
2496
    a_clk, a_rst,
2497
    // b side
2498
    b_d, b_wr, b_fifo_full,
2499
    b_q, b_rd, b_fifo_empty,
2500
    b_clk, b_rst
2501
    );
2502
parameter data_width = 18;
2503
parameter addr_width = 4;
2504
// a side
2505
input  [data_width-1:0] a_d;
2506
input                   a_wr;
2507
output                  a_fifo_full;
2508
output [data_width-1:0] a_q;
2509
input                   a_rd;
2510
output                  a_fifo_empty;
2511
input                   a_clk;
2512
input                   a_rst;
2513
// b side
2514
input  [data_width-1:0] b_d;
2515
input                   b_wr;
2516
output                  b_fifo_full;
2517
output [data_width-1:0] b_q;
2518
input                   b_rd;
2519
output                  b_fifo_empty;
2520
input                   b_clk;
2521
input                   b_rst;
2522
// adr_gen
2523
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2524
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2525
// dpram
2526
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2527 18 unneback
vl_cnt_gray_ce_bin
2528 6 unneback
    # ( .length(addr_width))
2529
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2530 18 unneback
vl_cnt_gray_ce_bin
2531 6 unneback
    # (.length(addr_width))
2532
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2533 18 unneback
vl_cnt_gray_ce_bin
2534 6 unneback
    # ( .length(addr_width))
2535
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2536 18 unneback
vl_cnt_gray_ce_bin
2537 6 unneback
    # (.length(addr_width))
2538
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2539
// mux read or write adr to DPRAM
2540
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2541
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2542 11 unneback
vl_dpram_2r2w
2543 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2544
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2545
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2546 11 unneback
vl_fifo_cmp_async
2547 6 unneback
    # (.addr_width(addr_width))
2548
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2549 11 unneback
vl_fifo_cmp_async
2550 6 unneback
    # (.addr_width(addr_width))
2551
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2552
endmodule
2553 12 unneback
//////////////////////////////////////////////////////////////////////
2554
////                                                              ////
2555
////  Versatile library, wishbone stuff                           ////
2556
////                                                              ////
2557
////  Description                                                 ////
2558
////  Wishbone compliant modules                                  ////
2559
////                                                              ////
2560
////                                                              ////
2561
////  To Do:                                                      ////
2562
////   -                                                          ////
2563
////                                                              ////
2564
////  Author(s):                                                  ////
2565
////      - Michael Unneback, unneback@opencores.org              ////
2566
////        ORSoC AB                                              ////
2567
////                                                              ////
2568
//////////////////////////////////////////////////////////////////////
2569
////                                                              ////
2570
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2571
////                                                              ////
2572
//// This source file may be used and distributed without         ////
2573
//// restriction provided that this copyright statement is not    ////
2574
//// removed from the file and that any derivative work contains  ////
2575
//// the original copyright notice and the associated disclaimer. ////
2576
////                                                              ////
2577
//// This source file is free software; you can redistribute it   ////
2578
//// and/or modify it under the terms of the GNU Lesser General   ////
2579
//// Public License as published by the Free Software Foundation; ////
2580
//// either version 2.1 of the License, or (at your option) any   ////
2581
//// later version.                                               ////
2582
////                                                              ////
2583
//// This source is distributed in the hope that it will be       ////
2584
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2585
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2586
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2587
//// details.                                                     ////
2588
////                                                              ////
2589
//// You should have received a copy of the GNU Lesser General    ////
2590
//// Public License along with this source; if not, download it   ////
2591
//// from http://www.opencores.org/lgpl.shtml                     ////
2592
////                                                              ////
2593
//////////////////////////////////////////////////////////////////////
2594
// async wb3 - wb3 bridge
2595
`timescale 1ns/1ns
2596 18 unneback
module vl_wb3wb3_bridge (
2597 12 unneback
        // wishbone slave side
2598
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2599
        // wishbone master side
2600
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2601
input [31:0] wbs_dat_i;
2602
input [31:2] wbs_adr_i;
2603
input [3:0]  wbs_sel_i;
2604
input [1:0]  wbs_bte_i;
2605
input [2:0]  wbs_cti_i;
2606
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2607
output [31:0] wbs_dat_o;
2608 14 unneback
output wbs_ack_o;
2609 12 unneback
input wbs_clk, wbs_rst;
2610
output [31:0] wbm_dat_o;
2611
output reg [31:2] wbm_adr_o;
2612
output [3:0</