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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 6 unneback
 // ALTERA
47
 //ACTEL
48
// sync reset
49 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
50 6 unneback
// output active high global reset sync with two DFFs 
51
`timescale 1 ns/100 ps
52
module vl_sync_rst ( rst_n_i, rst_o, clk);
53
input rst_n_i, clk;
54
output rst_o;
55 18 unneback
reg [1:0] tmp;
56 6 unneback
always @ (posedge clk or negedge rst_n_i)
57
if (!rst_n_i)
58 17 unneback
        tmp <= 2'b11;
59 6 unneback
else
60 17 unneback
        tmp <= {1'b0,tmp[0]};
61
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
62 6 unneback
endmodule
63
// vl_pll
64
 //altera
65
 //actel
66
//////////////////////////////////////////////////////////////////////
67
////                                                              ////
68
////  Versatile library, registers                                ////
69
////                                                              ////
70
////  Description                                                 ////
71
////  Different type of registers                                 ////
72
////                                                              ////
73
////                                                              ////
74
////  To Do:                                                      ////
75
////   - add more different registers                             ////
76
////                                                              ////
77
////  Author(s):                                                  ////
78
////      - Michael Unneback, unneback@opencores.org              ////
79
////        ORSoC AB                                              ////
80
////                                                              ////
81
//////////////////////////////////////////////////////////////////////
82
////                                                              ////
83
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84
////                                                              ////
85
//// This source file may be used and distributed without         ////
86
//// restriction provided that this copyright statement is not    ////
87
//// removed from the file and that any derivative work contains  ////
88
//// the original copyright notice and the associated disclaimer. ////
89
////                                                              ////
90
//// This source file is free software; you can redistribute it   ////
91
//// and/or modify it under the terms of the GNU Lesser General   ////
92
//// Public License as published by the Free Software Foundation; ////
93
//// either version 2.1 of the License, or (at your option) any   ////
94
//// later version.                                               ////
95
////                                                              ////
96
//// This source is distributed in the hope that it will be       ////
97
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100
//// details.                                                     ////
101
////                                                              ////
102
//// You should have received a copy of the GNU Lesser General    ////
103
//// Public License along with this source; if not, download it   ////
104
//// from http://www.opencores.org/lgpl.shtml                     ////
105
////                                                              ////
106
//////////////////////////////////////////////////////////////////////
107 18 unneback
module vl_dff ( d, q, clk, rst);
108 6 unneback
        parameter width = 1;
109
        parameter reset_value = 0;
110
        input [width-1:0] d;
111
        input clk, rst;
112
        output reg [width-1:0] q;
113
        always @ (posedge clk or posedge rst)
114
        if (rst)
115
                q <= reset_value;
116
        else
117
                q <= d;
118
endmodule
119 18 unneback
module vl_dff_array ( d, q, clk, rst);
120 6 unneback
        parameter width = 1;
121
        parameter depth = 2;
122
        parameter reset_value = 1'b0;
123
        input [width-1:0] d;
124
        input clk, rst;
125
        output [width-1:0] q;
126
        reg  [0:depth-1] q_tmp [width-1:0];
127
        integer i;
128
        always @ (posedge clk or posedge rst)
129
        if (rst) begin
130
            for (i=0;i<depth;i=i+1)
131
                q_tmp[i] <= {width{reset_value}};
132
        end else begin
133
            q_tmp[0] <= d;
134
            for (i=1;i<depth;i=i+1)
135
                q_tmp[i] <= q_tmp[i-1];
136
        end
137
    assign q = q_tmp[depth-1];
138
endmodule
139 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
140 6 unneback
        parameter width = 1;
141
        parameter reset_value = 0;
142
        input [width-1:0] d;
143
        input ce, clk, rst;
144
        output reg [width-1:0] q;
145
        always @ (posedge clk or posedge rst)
146
        if (rst)
147
                q <= reset_value;
148
        else
149
                if (ce)
150
                        q <= d;
151
endmodule
152 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
153 8 unneback
        parameter width = 1;
154
        parameter reset_value = 0;
155
        input [width-1:0] d;
156 10 unneback
        input ce, clear, clk, rst;
157 8 unneback
        output reg [width-1:0] q;
158
        always @ (posedge clk or posedge rst)
159
        if (rst)
160
            q <= reset_value;
161
        else
162
            if (ce)
163
                if (clear)
164
                    q <= {width{1'b0}};
165
                else
166
                    q <= d;
167
endmodule
168 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
169
        parameter width = 1;
170
        parameter reset_value = 0;
171
        input [width-1:0] d;
172
        input ce, set, clk, rst;
173
        output reg [width-1:0] q;
174
        always @ (posedge clk or posedge rst)
175
        if (rst)
176
            q <= reset_value;
177
        else
178
            if (ce)
179
                if (set)
180
                    q <= {width{1'b1}};
181
                else
182
                    q <= d;
183
endmodule
184 29 unneback
module vl_spr ( sp, r, q, clk, rst);
185
        parameter width = 1;
186
        parameter reset_value = 0;
187
        input sp, r;
188
        output reg q;
189
        input clk, rst;
190
        always @ (posedge clk or posedge rst)
191
        if (rst)
192
            q <= reset_value;
193
        else
194
            if (sp)
195
                q <= 1'b1;
196
            else if (r)
197
                q <= 1'b0;
198
endmodule
199
module vl_srp ( s, rp, q, clk, rst);
200
        parameter width = 1;
201
        parameter reset_value = 0;
202
        input s, rp;
203
        output reg q;
204
        input clk, rst;
205
        always @ (posedge clk or posedge rst)
206
        if (rst)
207
            q <= reset_value;
208
        else
209
            if (rp)
210
                q <= 1'b0;
211
            else if (s)
212
                q <= 1'b1;
213
endmodule
214 6 unneback
// megafunction wizard: %LPM_FF%
215
// GENERATION: STANDARD
216
// VERSION: WM1.0
217
// MODULE: lpm_ff 
218
// ============================================================
219
// File Name: dff_sr.v
220
// Megafunction Name(s):
221
//                      lpm_ff
222
//
223
// Simulation Library Files(s):
224
//                      lpm
225
// ============================================================
226
// ************************************************************
227
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
228
//
229
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
230
// ************************************************************
231
//Copyright (C) 1991-2010 Altera Corporation
232
//Your use of Altera Corporation's design tools, logic functions 
233
//and other software and tools, and its AMPP partner logic 
234
//functions, and any output files from any of the foregoing 
235
//(including device programming or simulation files), and any 
236
//associated documentation or information are expressly subject 
237
//to the terms and conditions of the Altera Program License 
238
//Subscription Agreement, Altera MegaCore Function License 
239
//Agreement, or other applicable license agreement, including, 
240
//without limitation, that your use is for the sole purpose of 
241
//programming logic devices manufactured by Altera and sold by 
242
//Altera or its authorized distributors.  Please refer to the 
243
//applicable agreement for further details.
244
// synopsys translate_off
245
`timescale 1 ps / 1 ps
246
// synopsys translate_on
247 18 unneback
module vl_dff_sr (
248 6 unneback
        aclr,
249
        aset,
250
        clock,
251
        data,
252
        q);
253
        input     aclr;
254
        input     aset;
255
        input     clock;
256
        input     data;
257
        output    q;
258
        wire [0:0] sub_wire0;
259
        wire [0:0] sub_wire1 = sub_wire0[0:0];
260
        wire  q = sub_wire1;
261
        wire  sub_wire2 = data;
262
        wire  sub_wire3 = sub_wire2;
263
        lpm_ff  lpm_ff_component (
264
                                .aclr (aclr),
265
                                .clock (clock),
266
                                .data (sub_wire3),
267
                                .aset (aset),
268
                                .q (sub_wire0)
269
                                // synopsys translate_off
270
                                ,
271
                                .aload (),
272
                                .enable (),
273
                                .sclr (),
274
                                .sload (),
275
                                .sset ()
276
                                // synopsys translate_on
277
                                );
278
        defparam
279
                lpm_ff_component.lpm_fftype = "DFF",
280
                lpm_ff_component.lpm_type = "LPM_FF",
281
                lpm_ff_component.lpm_width = 1;
282
endmodule
283
// ============================================================
284
// CNX file retrieval info
285
// ============================================================
286
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
287
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
288
// Retrieval info: PRIVATE: ASET NUMERIC "1"
289
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
290
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
291
// Retrieval info: PRIVATE: DFF NUMERIC "1"
292
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
293
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
294
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
295
// Retrieval info: PRIVATE: SSET NUMERIC "0"
296
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
297
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
298
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
299
// Retrieval info: PRIVATE: nBit NUMERIC "1"
300
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
301
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
302
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
303
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
304
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
305
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
306
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
307
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
308
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
309
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
310
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
311
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
312
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
313
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
314
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
315
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
316
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
317
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
318
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
319
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
320
// Retrieval info: LIB_FILE: lpm
321
// LATCH
322
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
323 18 unneback
module vl_latch ( d, le, q, clk);
324 6 unneback
input d, le;
325
output q;
326
input clk;
327
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
328
endmodule
329 18 unneback
module vl_shreg ( d, q, clk, rst);
330 17 unneback
parameter depth = 10;
331
input d;
332
output q;
333
input clk, rst;
334
reg [1:depth] dffs;
335
always @ (posedge clk or posedge rst)
336
if (rst)
337
    dffs <= {depth{1'b0}};
338
else
339
    dffs <= {d,dffs[1:depth-1]};
340
assign q = dffs[depth];
341
endmodule
342 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
343 17 unneback
parameter depth = 10;
344
input d, ce;
345
output q;
346
input clk, rst;
347
reg [1:depth] dffs;
348
always @ (posedge clk or posedge rst)
349
if (rst)
350
    dffs <= {depth{1'b0}};
351
else
352
    if (ce)
353
        dffs <= {d,dffs[1:depth-1]};
354
assign q = dffs[depth];
355
endmodule
356 18 unneback
module vl_delay ( d, q, clk, rst);
357 15 unneback
parameter depth = 10;
358
input d;
359
output q;
360
input clk, rst;
361
reg [1:depth] dffs;
362
always @ (posedge clk or posedge rst)
363
if (rst)
364
    dffs <= {depth{1'b0}};
365
else
366
    dffs <= {d,dffs[1:depth-1]};
367
assign q = dffs[depth];
368
endmodule
369 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
370 17 unneback
parameter depth = 10;
371
input d;
372
output q, emptyflag;
373
input clk, rst;
374
reg [1:depth] dffs;
375
always @ (posedge clk or posedge rst)
376
if (rst)
377
    dffs <= {depth{1'b0}};
378
else
379
    dffs <= {d,dffs[1:depth-1]};
380
assign q = dffs[depth];
381
assign emptyflag = !(|dffs);
382
endmodule
383 6 unneback
//////////////////////////////////////////////////////////////////////
384
////                                                              ////
385 18 unneback
////  Logic functions                                             ////
386
////                                                              ////
387
////  Description                                                 ////
388
////  Logic functions such as multiplexers                        ////
389
////                                                              ////
390
////                                                              ////
391
////  To Do:                                                      ////
392
////   -                                                          ////
393
////                                                              ////
394
////  Author(s):                                                  ////
395
////      - Michael Unneback, unneback@opencores.org              ////
396
////        ORSoC AB                                              ////
397
////                                                              ////
398
//////////////////////////////////////////////////////////////////////
399
////                                                              ////
400
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
401
////                                                              ////
402
//// This source file may be used and distributed without         ////
403
//// restriction provided that this copyright statement is not    ////
404
//// removed from the file and that any derivative work contains  ////
405
//// the original copyright notice and the associated disclaimer. ////
406
////                                                              ////
407
//// This source file is free software; you can redistribute it   ////
408
//// and/or modify it under the terms of the GNU Lesser General   ////
409
//// Public License as published by the Free Software Foundation; ////
410
//// either version 2.1 of the License, or (at your option) any   ////
411
//// later version.                                               ////
412
////                                                              ////
413
//// This source is distributed in the hope that it will be       ////
414
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
415
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
416
//// PURPOSE.  See the GNU Lesser General Public License for more ////
417
//// details.                                                     ////
418
////                                                              ////
419
//// You should have received a copy of the GNU Lesser General    ////
420
//// Public License along with this source; if not, download it   ////
421
//// from http://www.opencores.org/lgpl.shtml                     ////
422
////                                                              ////
423
//////////////////////////////////////////////////////////////////////
424
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
425
parameter width = 32;
426
parameter nr_of_ports = 4;
427
input [width-1:0] a3, a2, a1, a0;
428
input [nr_of_ports-1:0] sel;
429 22 unneback
output [width-1:0] dout;
430 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
431 18 unneback
integer i;
432
// and
433
assign tmp[0] = {width{sel[0]}} & a0;
434
assign tmp[1] = {width{sel[1]}} & a1;
435
assign tmp[2] = {width{sel[2]}} & a2;
436
assign tmp[3] = {width{sel[3]}} & a3;
437
// or
438
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
439
endmodule
440
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
441
parameter width = 32;
442
parameter nr_of_ports = 5;
443
input [width-1:0] a4, a3, a2, a1, a0;
444
input [nr_of_ports-1:0] sel;
445 22 unneback
output [width-1:0] dout;
446 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
447 18 unneback
integer i;
448
// and
449
assign tmp[0] = {width{sel[0]}} & a0;
450
assign tmp[1] = {width{sel[1]}} & a1;
451
assign tmp[2] = {width{sel[2]}} & a2;
452
assign tmp[3] = {width{sel[3]}} & a3;
453
assign tmp[4] = {width{sel[4]}} & a4;
454
// or
455
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
456
endmodule
457
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
458
parameter width = 32;
459
parameter nr_of_ports = 6;
460
input [width-1:0] a5, a4, a3, a2, a1, a0;
461
input [nr_of_ports-1:0] sel;
462 22 unneback
output [width-1:0] dout;
463 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
464 18 unneback
integer i;
465
// and
466
assign tmp[0] = {width{sel[0]}} & a0;
467
assign tmp[1] = {width{sel[1]}} & a1;
468
assign tmp[2] = {width{sel[2]}} & a2;
469
assign tmp[3] = {width{sel[3]}} & a3;
470
assign tmp[4] = {width{sel[4]}} & a4;
471
assign tmp[5] = {width{sel[5]}} & a5;
472
// or
473
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
474
endmodule
475
//////////////////////////////////////////////////////////////////////
476
////                                                              ////
477 6 unneback
////  Versatile counter                                           ////
478
////                                                              ////
479
////  Description                                                 ////
480
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
481
////  counter                                                     ////
482
////                                                              ////
483
////  To Do:                                                      ////
484
////   - add LFSR with more taps                                  ////
485
////                                                              ////
486
////  Author(s):                                                  ////
487
////      - Michael Unneback, unneback@opencores.org              ////
488
////        ORSoC AB                                              ////
489
////                                                              ////
490
//////////////////////////////////////////////////////////////////////
491
////                                                              ////
492
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
493
////                                                              ////
494
//// This source file may be used and distributed without         ////
495
//// restriction provided that this copyright statement is not    ////
496
//// removed from the file and that any derivative work contains  ////
497
//// the original copyright notice and the associated disclaimer. ////
498
////                                                              ////
499
//// This source file is free software; you can redistribute it   ////
500
//// and/or modify it under the terms of the GNU Lesser General   ////
501
//// Public License as published by the Free Software Foundation; ////
502
//// either version 2.1 of the License, or (at your option) any   ////
503
//// later version.                                               ////
504
////                                                              ////
505
//// This source is distributed in the hope that it will be       ////
506
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
507
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
508
//// PURPOSE.  See the GNU Lesser General Public License for more ////
509
//// details.                                                     ////
510
////                                                              ////
511
//// You should have received a copy of the GNU Lesser General    ////
512
//// Public License along with this source; if not, download it   ////
513
//// from http://www.opencores.org/lgpl.shtml                     ////
514
////                                                              ////
515
//////////////////////////////////////////////////////////////////////
516
// binary counter
517 22 unneback
module vl_cnt_bin ( q, rst, clk);
518
   parameter length = 4;
519
   output [length:1] q;
520
   input rst;
521
   input clk;
522
   parameter clear_value = 0;
523
   parameter set_value = 1;
524
   parameter wrap_value = 0;
525
   parameter level1_value = 15;
526
   reg  [length:1] qi;
527
   wire [length:1] q_next;
528
   assign q_next = qi + {{length-1{1'b0}},1'b1};
529
   always @ (posedge clk or posedge rst)
530
     if (rst)
531
       qi <= {length{1'b0}};
532
     else
533
       qi <= q_next;
534
   assign q = qi;
535
endmodule
536
//////////////////////////////////////////////////////////////////////
537
////                                                              ////
538
////  Versatile counter                                           ////
539
////                                                              ////
540
////  Description                                                 ////
541
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
542
////  counter                                                     ////
543
////                                                              ////
544
////  To Do:                                                      ////
545
////   - add LFSR with more taps                                  ////
546
////                                                              ////
547
////  Author(s):                                                  ////
548
////      - Michael Unneback, unneback@opencores.org              ////
549
////        ORSoC AB                                              ////
550
////                                                              ////
551
//////////////////////////////////////////////////////////////////////
552
////                                                              ////
553
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
554
////                                                              ////
555
//// This source file may be used and distributed without         ////
556
//// restriction provided that this copyright statement is not    ////
557
//// removed from the file and that any derivative work contains  ////
558
//// the original copyright notice and the associated disclaimer. ////
559
////                                                              ////
560
//// This source file is free software; you can redistribute it   ////
561
//// and/or modify it under the terms of the GNU Lesser General   ////
562
//// Public License as published by the Free Software Foundation; ////
563
//// either version 2.1 of the License, or (at your option) any   ////
564
//// later version.                                               ////
565
////                                                              ////
566
//// This source is distributed in the hope that it will be       ////
567
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
568
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
569
//// PURPOSE.  See the GNU Lesser General Public License for more ////
570
//// details.                                                     ////
571
////                                                              ////
572
//// You should have received a copy of the GNU Lesser General    ////
573
//// Public License along with this source; if not, download it   ////
574
//// from http://www.opencores.org/lgpl.shtml                     ////
575
////                                                              ////
576
//////////////////////////////////////////////////////////////////////
577
// binary counter
578
module vl_cnt_bin_clear ( clear, q, rst, clk);
579
   parameter length = 4;
580
   input clear;
581
   output [length:1] q;
582
   input rst;
583
   input clk;
584
   parameter clear_value = 0;
585
   parameter set_value = 1;
586
   parameter wrap_value = 0;
587
   parameter level1_value = 15;
588
   reg  [length:1] qi;
589
   wire [length:1] q_next;
590
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
591
   always @ (posedge clk or posedge rst)
592
     if (rst)
593
       qi <= {length{1'b0}};
594
     else
595
       qi <= q_next;
596
   assign q = qi;
597
endmodule
598
//////////////////////////////////////////////////////////////////////
599
////                                                              ////
600
////  Versatile counter                                           ////
601
////                                                              ////
602
////  Description                                                 ////
603
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
604
////  counter                                                     ////
605
////                                                              ////
606
////  To Do:                                                      ////
607
////   - add LFSR with more taps                                  ////
608
////                                                              ////
609
////  Author(s):                                                  ////
610
////      - Michael Unneback, unneback@opencores.org              ////
611
////        ORSoC AB                                              ////
612
////                                                              ////
613
//////////////////////////////////////////////////////////////////////
614
////                                                              ////
615
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
616
////                                                              ////
617
//// This source file may be used and distributed without         ////
618
//// restriction provided that this copyright statement is not    ////
619
//// removed from the file and that any derivative work contains  ////
620
//// the original copyright notice and the associated disclaimer. ////
621
////                                                              ////
622
//// This source file is free software; you can redistribute it   ////
623
//// and/or modify it under the terms of the GNU Lesser General   ////
624
//// Public License as published by the Free Software Foundation; ////
625
//// either version 2.1 of the License, or (at your option) any   ////
626
//// later version.                                               ////
627
////                                                              ////
628
//// This source is distributed in the hope that it will be       ////
629
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
630
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
631
//// PURPOSE.  See the GNU Lesser General Public License for more ////
632
//// details.                                                     ////
633
////                                                              ////
634
//// You should have received a copy of the GNU Lesser General    ////
635
//// Public License along with this source; if not, download it   ////
636
//// from http://www.opencores.org/lgpl.shtml                     ////
637
////                                                              ////
638
//////////////////////////////////////////////////////////////////////
639
// binary counter
640 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
641 6 unneback
   parameter length = 4;
642
   input cke;
643
   output [length:1] q;
644
   input rst;
645
   input clk;
646
   parameter clear_value = 0;
647
   parameter set_value = 1;
648
   parameter wrap_value = 0;
649
   parameter level1_value = 15;
650
   reg  [length:1] qi;
651
   wire [length:1] q_next;
652
   assign q_next = qi + {{length-1{1'b0}},1'b1};
653
   always @ (posedge clk or posedge rst)
654
     if (rst)
655
       qi <= {length{1'b0}};
656
     else
657
     if (cke)
658
       qi <= q_next;
659
   assign q = qi;
660
endmodule
661
//////////////////////////////////////////////////////////////////////
662
////                                                              ////
663
////  Versatile counter                                           ////
664
////                                                              ////
665
////  Description                                                 ////
666
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
667
////  counter                                                     ////
668
////                                                              ////
669
////  To Do:                                                      ////
670
////   - add LFSR with more taps                                  ////
671
////                                                              ////
672
////  Author(s):                                                  ////
673
////      - Michael Unneback, unneback@opencores.org              ////
674
////        ORSoC AB                                              ////
675
////                                                              ////
676
//////////////////////////////////////////////////////////////////////
677
////                                                              ////
678
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
679
////                                                              ////
680
//// This source file may be used and distributed without         ////
681
//// restriction provided that this copyright statement is not    ////
682
//// removed from the file and that any derivative work contains  ////
683
//// the original copyright notice and the associated disclaimer. ////
684
////                                                              ////
685
//// This source file is free software; you can redistribute it   ////
686
//// and/or modify it under the terms of the GNU Lesser General   ////
687
//// Public License as published by the Free Software Foundation; ////
688
//// either version 2.1 of the License, or (at your option) any   ////
689
//// later version.                                               ////
690
////                                                              ////
691
//// This source is distributed in the hope that it will be       ////
692
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
693
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
694
//// PURPOSE.  See the GNU Lesser General Public License for more ////
695
//// details.                                                     ////
696
////                                                              ////
697
//// You should have received a copy of the GNU Lesser General    ////
698
//// Public License along with this source; if not, download it   ////
699
//// from http://www.opencores.org/lgpl.shtml                     ////
700
////                                                              ////
701
//////////////////////////////////////////////////////////////////////
702
// binary counter
703 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
704 6 unneback
   parameter length = 4;
705
   input clear;
706
   input cke;
707
   output [length:1] q;
708
   input rst;
709
   input clk;
710
   parameter clear_value = 0;
711
   parameter set_value = 1;
712
   parameter wrap_value = 0;
713
   parameter level1_value = 15;
714
   reg  [length:1] qi;
715
   wire [length:1] q_next;
716
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
717
   always @ (posedge clk or posedge rst)
718
     if (rst)
719
       qi <= {length{1'b0}};
720
     else
721
     if (cke)
722
       qi <= q_next;
723
   assign q = qi;
724
endmodule
725
//////////////////////////////////////////////////////////////////////
726
////                                                              ////
727
////  Versatile counter                                           ////
728
////                                                              ////
729
////  Description                                                 ////
730
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
731
////  counter                                                     ////
732
////                                                              ////
733
////  To Do:                                                      ////
734
////   - add LFSR with more taps                                  ////
735
////                                                              ////
736
////  Author(s):                                                  ////
737
////      - Michael Unneback, unneback@opencores.org              ////
738
////        ORSoC AB                                              ////
739
////                                                              ////
740
//////////////////////////////////////////////////////////////////////
741
////                                                              ////
742
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
743
////                                                              ////
744
//// This source file may be used and distributed without         ////
745
//// restriction provided that this copyright statement is not    ////
746
//// removed from the file and that any derivative work contains  ////
747
//// the original copyright notice and the associated disclaimer. ////
748
////                                                              ////
749
//// This source file is free software; you can redistribute it   ////
750
//// and/or modify it under the terms of the GNU Lesser General   ////
751
//// Public License as published by the Free Software Foundation; ////
752
//// either version 2.1 of the License, or (at your option) any   ////
753
//// later version.                                               ////
754
////                                                              ////
755
//// This source is distributed in the hope that it will be       ////
756
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
757
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
758
//// PURPOSE.  See the GNU Lesser General Public License for more ////
759
//// details.                                                     ////
760
////                                                              ////
761
//// You should have received a copy of the GNU Lesser General    ////
762
//// Public License along with this source; if not, download it   ////
763
//// from http://www.opencores.org/lgpl.shtml                     ////
764
////                                                              ////
765
//////////////////////////////////////////////////////////////////////
766
// binary counter
767 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
768
   parameter length = 4;
769
   input clear;
770
   input cke;
771
   output [length:1] q;
772
   output reg level1;
773
   output reg level2;
774
   input rst;
775
   input clk;
776
   parameter clear_value = 0;
777
   parameter set_value = 1;
778
   parameter wrap_value = 7;
779
   parameter level1_value = 15;
780
   wire rew;
781
   assign rew=1'b0;
782
   reg  [length:1] qi;
783
   wire [length:1] q_next;
784
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
785
   always @ (posedge clk or posedge rst)
786
     if (rst)
787
       qi <= {length{1'b0}};
788
     else
789
     if (cke)
790
       qi <= q_next;
791
   assign q = qi;
792
    always @ (posedge clk or posedge rst)
793
    if (rst)
794
        level1 <= 1'b0;
795
    else
796
    if (cke)
797
    if (clear)
798
        level1 <= 1'b0;
799
    else if (q_next == level1_value)
800
        level1 <= 1'b1;
801
    else if (qi == level1_value & rew)
802
        level1 <= 1'b0;
803
    always @ (posedge clk or posedge rst)
804
    if (rst)
805
        level2 <= 1'b0;
806
    else
807
    if (cke)
808
    if (clear)
809
        level2 <= 1'b0;
810
    else if (q_next == level2_value)
811
        level2 <= 1'b1;
812
    else if (qi == level2_value & rew)
813
        level2 <= 1'b0;
814
endmodule
815
//////////////////////////////////////////////////////////////////////
816
////                                                              ////
817
////  Versatile counter                                           ////
818
////                                                              ////
819
////  Description                                                 ////
820
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
821
////  counter                                                     ////
822
////                                                              ////
823
////  To Do:                                                      ////
824
////   - add LFSR with more taps                                  ////
825
////                                                              ////
826
////  Author(s):                                                  ////
827
////      - Michael Unneback, unneback@opencores.org              ////
828
////        ORSoC AB                                              ////
829
////                                                              ////
830
//////////////////////////////////////////////////////////////////////
831
////                                                              ////
832
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
833
////                                                              ////
834
//// This source file may be used and distributed without         ////
835
//// restriction provided that this copyright statement is not    ////
836
//// removed from the file and that any derivative work contains  ////
837
//// the original copyright notice and the associated disclaimer. ////
838
////                                                              ////
839
//// This source file is free software; you can redistribute it   ////
840
//// and/or modify it under the terms of the GNU Lesser General   ////
841
//// Public License as published by the Free Software Foundation; ////
842
//// either version 2.1 of the License, or (at your option) any   ////
843
//// later version.                                               ////
844
////                                                              ////
845
//// This source is distributed in the hope that it will be       ////
846
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
847
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
848
//// PURPOSE.  See the GNU Lesser General Public License for more ////
849
//// details.                                                     ////
850
////                                                              ////
851
//// You should have received a copy of the GNU Lesser General    ////
852
//// Public License along with this source; if not, download it   ////
853
//// from http://www.opencores.org/lgpl.shtml                     ////
854
////                                                              ////
855
//////////////////////////////////////////////////////////////////////
856
// binary counter
857 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
858 6 unneback
   parameter length = 4;
859
   input clear;
860
   input set;
861
   input cke;
862
   input rew;
863
   output [length:1] q;
864
   input rst;
865
   input clk;
866
   parameter clear_value = 0;
867
   parameter set_value = 1;
868
   parameter wrap_value = 0;
869
   parameter level1_value = 15;
870
   reg  [length:1] qi;
871
   wire  [length:1] q_next, q_next_fw, q_next_rew;
872
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
873
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
874
   assign q_next = rew ? q_next_rew : q_next_fw;
875
   always @ (posedge clk or posedge rst)
876
     if (rst)
877
       qi <= {length{1'b0}};
878
     else
879
     if (cke)
880
       qi <= q_next;
881
   assign q = qi;
882
endmodule
883
//////////////////////////////////////////////////////////////////////
884
////                                                              ////
885
////  Versatile counter                                           ////
886
////                                                              ////
887
////  Description                                                 ////
888
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
889
////  counter                                                     ////
890
////                                                              ////
891
////  To Do:                                                      ////
892
////   - add LFSR with more taps                                  ////
893
////                                                              ////
894
////  Author(s):                                                  ////
895
////      - Michael Unneback, unneback@opencores.org              ////
896
////        ORSoC AB                                              ////
897
////                                                              ////
898
//////////////////////////////////////////////////////////////////////
899
////                                                              ////
900
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
901
////                                                              ////
902
//// This source file may be used and distributed without         ////
903
//// restriction provided that this copyright statement is not    ////
904
//// removed from the file and that any derivative work contains  ////
905
//// the original copyright notice and the associated disclaimer. ////
906
////                                                              ////
907
//// This source file is free software; you can redistribute it   ////
908
//// and/or modify it under the terms of the GNU Lesser General   ////
909
//// Public License as published by the Free Software Foundation; ////
910
//// either version 2.1 of the License, or (at your option) any   ////
911
//// later version.                                               ////
912
////                                                              ////
913
//// This source is distributed in the hope that it will be       ////
914
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
915
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
916
//// PURPOSE.  See the GNU Lesser General Public License for more ////
917
//// details.                                                     ////
918
////                                                              ////
919
//// You should have received a copy of the GNU Lesser General    ////
920
//// Public License along with this source; if not, download it   ////
921
//// from http://www.opencores.org/lgpl.shtml                     ////
922
////                                                              ////
923
//////////////////////////////////////////////////////////////////////
924
// binary counter
925 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
926 6 unneback
   parameter length = 4;
927
   input cke;
928
   input rew;
929
   output reg level1;
930
   input rst;
931
   input clk;
932
   parameter clear_value = 0;
933
   parameter set_value = 1;
934
   parameter wrap_value = 1;
935
   parameter level1_value = 15;
936 29 unneback
   wire clear;
937
   assign clear=1'b0;
938 6 unneback
   reg  [length:1] qi;
939
   wire  [length:1] q_next, q_next_fw, q_next_rew;
940
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
941
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
942
   assign q_next = rew ? q_next_rew : q_next_fw;
943
   always @ (posedge clk or posedge rst)
944
     if (rst)
945
       qi <= {length{1'b0}};
946
     else
947
     if (cke)
948
       qi <= q_next;
949
    always @ (posedge clk or posedge rst)
950
    if (rst)
951
        level1 <= 1'b0;
952
    else
953
    if (cke)
954 29 unneback
    if (clear)
955
        level1 <= 1'b0;
956
    else if (q_next == level1_value)
957 6 unneback
        level1 <= 1'b1;
958
    else if (qi == level1_value & rew)
959
        level1 <= 1'b0;
960
endmodule
961
//////////////////////////////////////////////////////////////////////
962
////                                                              ////
963
////  Versatile counter                                           ////
964
////                                                              ////
965
////  Description                                                 ////
966
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
967
////  counter                                                     ////
968
////                                                              ////
969
////  To Do:                                                      ////
970
////   - add LFSR with more taps                                  ////
971
////                                                              ////
972
////  Author(s):                                                  ////
973
////      - Michael Unneback, unneback@opencores.org              ////
974
////        ORSoC AB                                              ////
975
////                                                              ////
976
//////////////////////////////////////////////////////////////////////
977
////                                                              ////
978
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
979
////                                                              ////
980
//// This source file may be used and distributed without         ////
981
//// restriction provided that this copyright statement is not    ////
982
//// removed from the file and that any derivative work contains  ////
983
//// the original copyright notice and the associated disclaimer. ////
984
////                                                              ////
985
//// This source file is free software; you can redistribute it   ////
986
//// and/or modify it under the terms of the GNU Lesser General   ////
987
//// Public License as published by the Free Software Foundation; ////
988
//// either version 2.1 of the License, or (at your option) any   ////
989
//// later version.                                               ////
990
////                                                              ////
991
//// This source is distributed in the hope that it will be       ////
992
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
993
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
994
//// PURPOSE.  See the GNU Lesser General Public License for more ////
995
//// details.                                                     ////
996
////                                                              ////
997
//// You should have received a copy of the GNU Lesser General    ////
998
//// Public License along with this source; if not, download it   ////
999
//// from http://www.opencores.org/lgpl.shtml                     ////
1000
////                                                              ////
1001
//////////////////////////////////////////////////////////////////////
1002 25 unneback
// binary counter
1003
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1004
   parameter length = 4;
1005
   input cke;
1006
   input rew;
1007
   output reg zq;
1008
   output reg level1;
1009
   input rst;
1010
   input clk;
1011
   parameter clear_value = 0;
1012
   parameter set_value = 1;
1013
   parameter wrap_value = 1;
1014
   parameter level1_value = 15;
1015 29 unneback
   wire clear;
1016
   assign clear=1'b0;
1017 25 unneback
   reg  [length:1] qi;
1018
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1019
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1020
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1021
   assign q_next = rew ? q_next_rew : q_next_fw;
1022
   always @ (posedge clk or posedge rst)
1023
     if (rst)
1024
       qi <= {length{1'b0}};
1025
     else
1026
     if (cke)
1027
       qi <= q_next;
1028
   always @ (posedge clk or posedge rst)
1029
     if (rst)
1030
       zq <= 1'b1;
1031
     else
1032
     if (cke)
1033
       zq <= q_next == {length{1'b0}};
1034
    always @ (posedge clk or posedge rst)
1035
    if (rst)
1036
        level1 <= 1'b0;
1037
    else
1038
    if (cke)
1039 29 unneback
    if (clear)
1040
        level1 <= 1'b0;
1041
    else if (q_next == level1_value)
1042 25 unneback
        level1 <= 1'b1;
1043
    else if (qi == level1_value & rew)
1044
        level1 <= 1'b0;
1045
endmodule
1046
//////////////////////////////////////////////////////////////////////
1047
////                                                              ////
1048
////  Versatile counter                                           ////
1049
////                                                              ////
1050
////  Description                                                 ////
1051
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1052
////  counter                                                     ////
1053
////                                                              ////
1054
////  To Do:                                                      ////
1055
////   - add LFSR with more taps                                  ////
1056
////                                                              ////
1057
////  Author(s):                                                  ////
1058
////      - Michael Unneback, unneback@opencores.org              ////
1059
////        ORSoC AB                                              ////
1060
////                                                              ////
1061
//////////////////////////////////////////////////////////////////////
1062
////                                                              ////
1063
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1064
////                                                              ////
1065
//// This source file may be used and distributed without         ////
1066
//// restriction provided that this copyright statement is not    ////
1067
//// removed from the file and that any derivative work contains  ////
1068
//// the original copyright notice and the associated disclaimer. ////
1069
////                                                              ////
1070
//// This source file is free software; you can redistribute it   ////
1071
//// and/or modify it under the terms of the GNU Lesser General   ////
1072
//// Public License as published by the Free Software Foundation; ////
1073
//// either version 2.1 of the License, or (at your option) any   ////
1074
//// later version.                                               ////
1075
////                                                              ////
1076
//// This source is distributed in the hope that it will be       ////
1077
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1078
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1079
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1080
//// details.                                                     ////
1081
////                                                              ////
1082
//// You should have received a copy of the GNU Lesser General    ////
1083
//// Public License along with this source; if not, download it   ////
1084
//// from http://www.opencores.org/lgpl.shtml                     ////
1085
////                                                              ////
1086
//////////////////////////////////////////////////////////////////////
1087
// binary counter
1088
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1089
   parameter length = 4;
1090
   input cke;
1091
   input rew;
1092
   output [length:1] q;
1093
   output reg zq;
1094
   output reg level1;
1095
   input rst;
1096
   input clk;
1097
   parameter clear_value = 0;
1098
   parameter set_value = 1;
1099
   parameter wrap_value = 1;
1100
   parameter level1_value = 15;
1101 29 unneback
   wire clear;
1102
   assign clear=1'b0;
1103 25 unneback
   reg  [length:1] qi;
1104
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1105
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1106
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1107
   assign q_next = rew ? q_next_rew : q_next_fw;
1108
   always @ (posedge clk or posedge rst)
1109
     if (rst)
1110
       qi <= {length{1'b0}};
1111
     else
1112
     if (cke)
1113
       qi <= q_next;
1114
   assign q = qi;
1115
   always @ (posedge clk or posedge rst)
1116
     if (rst)
1117
       zq <= 1'b1;
1118
     else
1119
     if (cke)
1120
       zq <= q_next == {length{1'b0}};
1121
    always @ (posedge clk or posedge rst)
1122
    if (rst)
1123
        level1 <= 1'b0;
1124
    else
1125
    if (cke)
1126 29 unneback
    if (clear)
1127
        level1 <= 1'b0;
1128
    else if (q_next == level1_value)
1129 25 unneback
        level1 <= 1'b1;
1130
    else if (qi == level1_value & rew)
1131
        level1 <= 1'b0;
1132
endmodule
1133
//////////////////////////////////////////////////////////////////////
1134
////                                                              ////
1135
////  Versatile counter                                           ////
1136
////                                                              ////
1137
////  Description                                                 ////
1138
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1139
////  counter                                                     ////
1140
////                                                              ////
1141
////  To Do:                                                      ////
1142
////   - add LFSR with more taps                                  ////
1143
////                                                              ////
1144
////  Author(s):                                                  ////
1145
////      - Michael Unneback, unneback@opencores.org              ////
1146
////        ORSoC AB                                              ////
1147
////                                                              ////
1148
//////////////////////////////////////////////////////////////////////
1149
////                                                              ////
1150
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1151
////                                                              ////
1152
//// This source file may be used and distributed without         ////
1153
//// restriction provided that this copyright statement is not    ////
1154
//// removed from the file and that any derivative work contains  ////
1155
//// the original copyright notice and the associated disclaimer. ////
1156
////                                                              ////
1157
//// This source file is free software; you can redistribute it   ////
1158
//// and/or modify it under the terms of the GNU Lesser General   ////
1159
//// Public License as published by the Free Software Foundation; ////
1160
//// either version 2.1 of the License, or (at your option) any   ////
1161
//// later version.                                               ////
1162
////                                                              ////
1163
//// This source is distributed in the hope that it will be       ////
1164
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1165
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1166
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1167
//// details.                                                     ////
1168
////                                                              ////
1169
//// You should have received a copy of the GNU Lesser General    ////
1170
//// Public License along with this source; if not, download it   ////
1171
//// from http://www.opencores.org/lgpl.shtml                     ////
1172
////                                                              ////
1173
//////////////////////////////////////////////////////////////////////
1174 6 unneback
// LFSR counter
1175 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1176 6 unneback
   parameter length = 4;
1177
   output reg zq;
1178
   input rst;
1179
   input clk;
1180
   parameter clear_value = 0;
1181
   parameter set_value = 1;
1182
   parameter wrap_value = 8;
1183
   parameter level1_value = 15;
1184
   reg  [length:1] qi;
1185
   reg lfsr_fb;
1186
   wire [length:1] q_next;
1187
   reg [32:1] polynom;
1188
   integer i;
1189
   always @ (qi)
1190
   begin
1191
        case (length)
1192
         2: polynom = 32'b11;                               // 0x3
1193
         3: polynom = 32'b110;                              // 0x6
1194
         4: polynom = 32'b1100;                             // 0xC
1195
         5: polynom = 32'b10100;                            // 0x14
1196
         6: polynom = 32'b110000;                           // 0x30
1197
         7: polynom = 32'b1100000;                          // 0x60
1198
         8: polynom = 32'b10111000;                         // 0xb8
1199
         9: polynom = 32'b100010000;                        // 0x110
1200
        10: polynom = 32'b1001000000;                       // 0x240
1201
        11: polynom = 32'b10100000000;                      // 0x500
1202
        12: polynom = 32'b100000101001;                     // 0x829
1203
        13: polynom = 32'b1000000001100;                    // 0x100C
1204
        14: polynom = 32'b10000000010101;                   // 0x2015
1205
        15: polynom = 32'b110000000000000;                  // 0x6000
1206
        16: polynom = 32'b1101000000001000;                 // 0xD008
1207
        17: polynom = 32'b10010000000000000;                // 0x12000
1208
        18: polynom = 32'b100000010000000000;               // 0x20400
1209
        19: polynom = 32'b1000000000000100011;              // 0x40023
1210
        20: polynom = 32'b10000010000000000000;             // 0x82000
1211
        21: polynom = 32'b101000000000000000000;            // 0x140000
1212
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1213
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1214
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1215
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1216
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1217
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1218
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1219
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1220
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1221
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1222
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1223
        default: polynom = 32'b0;
1224
        endcase
1225
        lfsr_fb = qi[length];
1226
        for (i=length-1; i>=1; i=i-1) begin
1227
            if (polynom[i])
1228
                lfsr_fb = lfsr_fb  ~^ qi[i];
1229
        end
1230
    end
1231
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1232
   always @ (posedge clk or posedge rst)
1233
     if (rst)
1234
       qi <= {length{1'b0}};
1235
     else
1236
       qi <= q_next;
1237
   always @ (posedge clk or posedge rst)
1238
     if (rst)
1239
       zq <= 1'b1;
1240
     else
1241
       zq <= q_next == {length{1'b0}};
1242
endmodule
1243
//////////////////////////////////////////////////////////////////////
1244
////                                                              ////
1245
////  Versatile counter                                           ////
1246
////                                                              ////
1247
////  Description                                                 ////
1248
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1249
////  counter                                                     ////
1250
////                                                              ////
1251
////  To Do:                                                      ////
1252
////   - add LFSR with more taps                                  ////
1253
////                                                              ////
1254
////  Author(s):                                                  ////
1255
////      - Michael Unneback, unneback@opencores.org              ////
1256
////        ORSoC AB                                              ////
1257
////                                                              ////
1258
//////////////////////////////////////////////////////////////////////
1259
////                                                              ////
1260
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1261
////                                                              ////
1262
//// This source file may be used and distributed without         ////
1263
//// restriction provided that this copyright statement is not    ////
1264
//// removed from the file and that any derivative work contains  ////
1265
//// the original copyright notice and the associated disclaimer. ////
1266
////                                                              ////
1267
//// This source file is free software; you can redistribute it   ////
1268
//// and/or modify it under the terms of the GNU Lesser General   ////
1269
//// Public License as published by the Free Software Foundation; ////
1270
//// either version 2.1 of the License, or (at your option) any   ////
1271
//// later version.                                               ////
1272
////                                                              ////
1273
//// This source is distributed in the hope that it will be       ////
1274
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1275
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1276
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1277
//// details.                                                     ////
1278
////                                                              ////
1279
//// You should have received a copy of the GNU Lesser General    ////
1280
//// Public License along with this source; if not, download it   ////
1281
//// from http://www.opencores.org/lgpl.shtml                     ////
1282
////                                                              ////
1283
//////////////////////////////////////////////////////////////////////
1284
// LFSR counter
1285 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1286 6 unneback
   parameter length = 4;
1287
   input cke;
1288
   output reg zq;
1289
   input rst;
1290
   input clk;
1291
   parameter clear_value = 0;
1292
   parameter set_value = 1;
1293
   parameter wrap_value = 8;
1294
   parameter level1_value = 15;
1295
   reg  [length:1] qi;
1296
   reg lfsr_fb;
1297
   wire [length:1] q_next;
1298
   reg [32:1] polynom;
1299
   integer i;
1300
   always @ (qi)
1301
   begin
1302
        case (length)
1303
         2: polynom = 32'b11;                               // 0x3
1304
         3: polynom = 32'b110;                              // 0x6
1305
         4: polynom = 32'b1100;                             // 0xC
1306
         5: polynom = 32'b10100;                            // 0x14
1307
         6: polynom = 32'b110000;                           // 0x30
1308
         7: polynom = 32'b1100000;                          // 0x60
1309
         8: polynom = 32'b10111000;                         // 0xb8
1310
         9: polynom = 32'b100010000;                        // 0x110
1311
        10: polynom = 32'b1001000000;                       // 0x240
1312
        11: polynom = 32'b10100000000;                      // 0x500
1313
        12: polynom = 32'b100000101001;                     // 0x829
1314
        13: polynom = 32'b1000000001100;                    // 0x100C
1315
        14: polynom = 32'b10000000010101;                   // 0x2015
1316
        15: polynom = 32'b110000000000000;                  // 0x6000
1317
        16: polynom = 32'b1101000000001000;                 // 0xD008
1318
        17: polynom = 32'b10010000000000000;                // 0x12000
1319
        18: polynom = 32'b100000010000000000;               // 0x20400
1320
        19: polynom = 32'b1000000000000100011;              // 0x40023
1321
        20: polynom = 32'b10000010000000000000;             // 0x82000
1322
        21: polynom = 32'b101000000000000000000;            // 0x140000
1323
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1324
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1325
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1326
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1327
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1328
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1329
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1330
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1331
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1332
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1333
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1334
        default: polynom = 32'b0;
1335
        endcase
1336
        lfsr_fb = qi[length];
1337
        for (i=length-1; i>=1; i=i-1) begin
1338
            if (polynom[i])
1339
                lfsr_fb = lfsr_fb  ~^ qi[i];
1340
        end
1341
    end
1342
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1343
   always @ (posedge clk or posedge rst)
1344
     if (rst)
1345
       qi <= {length{1'b0}};
1346
     else
1347
     if (cke)
1348
       qi <= q_next;
1349
   always @ (posedge clk or posedge rst)
1350
     if (rst)
1351
       zq <= 1'b1;
1352
     else
1353
     if (cke)
1354
       zq <= q_next == {length{1'b0}};
1355
endmodule
1356
//////////////////////////////////////////////////////////////////////
1357
////                                                              ////
1358
////  Versatile counter                                           ////
1359
////                                                              ////
1360
////  Description                                                 ////
1361
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1362
////  counter                                                     ////
1363
////                                                              ////
1364
////  To Do:                                                      ////
1365
////   - add LFSR with more taps                                  ////
1366
////                                                              ////
1367
////  Author(s):                                                  ////
1368
////      - Michael Unneback, unneback@opencores.org              ////
1369
////        ORSoC AB                                              ////
1370
////                                                              ////
1371
//////////////////////////////////////////////////////////////////////
1372
////                                                              ////
1373
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1374
////                                                              ////
1375
//// This source file may be used and distributed without         ////
1376
//// restriction provided that this copyright statement is not    ////
1377
//// removed from the file and that any derivative work contains  ////
1378
//// the original copyright notice and the associated disclaimer. ////
1379
////                                                              ////
1380
//// This source file is free software; you can redistribute it   ////
1381
//// and/or modify it under the terms of the GNU Lesser General   ////
1382
//// Public License as published by the Free Software Foundation; ////
1383
//// either version 2.1 of the License, or (at your option) any   ////
1384
//// later version.                                               ////
1385
////                                                              ////
1386
//// This source is distributed in the hope that it will be       ////
1387
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1388
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1389
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1390
//// details.                                                     ////
1391
////                                                              ////
1392
//// You should have received a copy of the GNU Lesser General    ////
1393
//// Public License along with this source; if not, download it   ////
1394
//// from http://www.opencores.org/lgpl.shtml                     ////
1395
////                                                              ////
1396
//////////////////////////////////////////////////////////////////////
1397
// LFSR counter
1398 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1399
   parameter length = 4;
1400
   input cke;
1401
   output [length:1] q;
1402
   input rst;
1403
   input clk;
1404
   parameter clear_value = 0;
1405
   parameter set_value = 1;
1406
   parameter wrap_value = 8;
1407
   parameter level1_value = 15;
1408
   reg  [length:1] qi;
1409
   reg lfsr_fb;
1410
   wire [length:1] q_next;
1411
   reg [32:1] polynom;
1412
   integer i;
1413
   always @ (qi)
1414
   begin
1415
        case (length)
1416
         2: polynom = 32'b11;                               // 0x3
1417
         3: polynom = 32'b110;                              // 0x6
1418
         4: polynom = 32'b1100;                             // 0xC
1419
         5: polynom = 32'b10100;                            // 0x14
1420
         6: polynom = 32'b110000;                           // 0x30
1421
         7: polynom = 32'b1100000;                          // 0x60
1422
         8: polynom = 32'b10111000;                         // 0xb8
1423
         9: polynom = 32'b100010000;                        // 0x110
1424
        10: polynom = 32'b1001000000;                       // 0x240
1425
        11: polynom = 32'b10100000000;                      // 0x500
1426
        12: polynom = 32'b100000101001;                     // 0x829
1427
        13: polynom = 32'b1000000001100;                    // 0x100C
1428
        14: polynom = 32'b10000000010101;                   // 0x2015
1429
        15: polynom = 32'b110000000000000;                  // 0x6000
1430
        16: polynom = 32'b1101000000001000;                 // 0xD008
1431
        17: polynom = 32'b10010000000000000;                // 0x12000
1432
        18: polynom = 32'b100000010000000000;               // 0x20400
1433
        19: polynom = 32'b1000000000000100011;              // 0x40023
1434
        20: polynom = 32'b10000010000000000000;             // 0x82000
1435
        21: polynom = 32'b101000000000000000000;            // 0x140000
1436
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1437
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1438
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1439
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1440
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1441
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1442
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1443
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1444
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1445
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1446
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1447
        default: polynom = 32'b0;
1448
        endcase
1449
        lfsr_fb = qi[length];
1450
        for (i=length-1; i>=1; i=i-1) begin
1451
            if (polynom[i])
1452
                lfsr_fb = lfsr_fb  ~^ qi[i];
1453
        end
1454
    end
1455
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1456
   always @ (posedge clk or posedge rst)
1457
     if (rst)
1458
       qi <= {length{1'b0}};
1459
     else
1460
     if (cke)
1461
       qi <= q_next;
1462
   assign q = qi;
1463
endmodule
1464
//////////////////////////////////////////////////////////////////////
1465
////                                                              ////
1466
////  Versatile counter                                           ////
1467
////                                                              ////
1468
////  Description                                                 ////
1469
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1470
////  counter                                                     ////
1471
////                                                              ////
1472
////  To Do:                                                      ////
1473
////   - add LFSR with more taps                                  ////
1474
////                                                              ////
1475
////  Author(s):                                                  ////
1476
////      - Michael Unneback, unneback@opencores.org              ////
1477
////        ORSoC AB                                              ////
1478
////                                                              ////
1479
//////////////////////////////////////////////////////////////////////
1480
////                                                              ////
1481
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1482
////                                                              ////
1483
//// This source file may be used and distributed without         ////
1484
//// restriction provided that this copyright statement is not    ////
1485
//// removed from the file and that any derivative work contains  ////
1486
//// the original copyright notice and the associated disclaimer. ////
1487
////                                                              ////
1488
//// This source file is free software; you can redistribute it   ////
1489
//// and/or modify it under the terms of the GNU Lesser General   ////
1490
//// Public License as published by the Free Software Foundation; ////
1491
//// either version 2.1 of the License, or (at your option) any   ////
1492
//// later version.                                               ////
1493
////                                                              ////
1494
//// This source is distributed in the hope that it will be       ////
1495
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1496
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1497
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1498
//// details.                                                     ////
1499
////                                                              ////
1500
//// You should have received a copy of the GNU Lesser General    ////
1501
//// Public License along with this source; if not, download it   ////
1502
//// from http://www.opencores.org/lgpl.shtml                     ////
1503
////                                                              ////
1504
//////////////////////////////////////////////////////////////////////
1505
// LFSR counter
1506
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1507
   parameter length = 4;
1508
   input clear;
1509
   input cke;
1510
   output [length:1] q;
1511
   input rst;
1512
   input clk;
1513
   parameter clear_value = 0;
1514
   parameter set_value = 1;
1515
   parameter wrap_value = 8;
1516
   parameter level1_value = 15;
1517
   reg  [length:1] qi;
1518
   reg lfsr_fb;
1519
   wire [length:1] q_next;
1520
   reg [32:1] polynom;
1521
   integer i;
1522
   always @ (qi)
1523
   begin
1524
        case (length)
1525
         2: polynom = 32'b11;                               // 0x3
1526
         3: polynom = 32'b110;                              // 0x6
1527
         4: polynom = 32'b1100;                             // 0xC
1528
         5: polynom = 32'b10100;                            // 0x14
1529
         6: polynom = 32'b110000;                           // 0x30
1530
         7: polynom = 32'b1100000;                          // 0x60
1531
         8: polynom = 32'b10111000;                         // 0xb8
1532
         9: polynom = 32'b100010000;                        // 0x110
1533
        10: polynom = 32'b1001000000;                       // 0x240
1534
        11: polynom = 32'b10100000000;                      // 0x500
1535
        12: polynom = 32'b100000101001;                     // 0x829
1536
        13: polynom = 32'b1000000001100;                    // 0x100C
1537
        14: polynom = 32'b10000000010101;                   // 0x2015
1538
        15: polynom = 32'b110000000000000;                  // 0x6000
1539
        16: polynom = 32'b1101000000001000;                 // 0xD008
1540
        17: polynom = 32'b10010000000000000;                // 0x12000
1541
        18: polynom = 32'b100000010000000000;               // 0x20400
1542
        19: polynom = 32'b1000000000000100011;              // 0x40023
1543
        20: polynom = 32'b10000010000000000000;             // 0x82000
1544
        21: polynom = 32'b101000000000000000000;            // 0x140000
1545
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1546
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1547
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1548
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1549
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1550
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1551
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1552
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1553
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1554
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1555
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1556
        default: polynom = 32'b0;
1557
        endcase
1558
        lfsr_fb = qi[length];
1559
        for (i=length-1; i>=1; i=i-1) begin
1560
            if (polynom[i])
1561
                lfsr_fb = lfsr_fb  ~^ qi[i];
1562
        end
1563
    end
1564
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1565
   always @ (posedge clk or posedge rst)
1566
     if (rst)
1567
       qi <= {length{1'b0}};
1568
     else
1569
     if (cke)
1570
       qi <= q_next;
1571
   assign q = qi;
1572
endmodule
1573
//////////////////////////////////////////////////////////////////////
1574
////                                                              ////
1575
////  Versatile counter                                           ////
1576
////                                                              ////
1577
////  Description                                                 ////
1578
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1579
////  counter                                                     ////
1580
////                                                              ////
1581
////  To Do:                                                      ////
1582
////   - add LFSR with more taps                                  ////
1583
////                                                              ////
1584
////  Author(s):                                                  ////
1585
////      - Michael Unneback, unneback@opencores.org              ////
1586
////        ORSoC AB                                              ////
1587
////                                                              ////
1588
//////////////////////////////////////////////////////////////////////
1589
////                                                              ////
1590
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1591
////                                                              ////
1592
//// This source file may be used and distributed without         ////
1593
//// restriction provided that this copyright statement is not    ////
1594
//// removed from the file and that any derivative work contains  ////
1595
//// the original copyright notice and the associated disclaimer. ////
1596
////                                                              ////
1597
//// This source file is free software; you can redistribute it   ////
1598
//// and/or modify it under the terms of the GNU Lesser General   ////
1599
//// Public License as published by the Free Software Foundation; ////
1600
//// either version 2.1 of the License, or (at your option) any   ////
1601
//// later version.                                               ////
1602
////                                                              ////
1603
//// This source is distributed in the hope that it will be       ////
1604
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1605
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1606
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1607
//// details.                                                     ////
1608
////                                                              ////
1609
//// You should have received a copy of the GNU Lesser General    ////
1610
//// Public License along with this source; if not, download it   ////
1611
//// from http://www.opencores.org/lgpl.shtml                     ////
1612
////                                                              ////
1613
//////////////////////////////////////////////////////////////////////
1614
// LFSR counter
1615 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1616
   parameter length = 4;
1617
   input cke;
1618
   output [length:1] q;
1619
   output reg zq;
1620
   input rst;
1621
   input clk;
1622
   parameter clear_value = 0;
1623
   parameter set_value = 1;
1624
   parameter wrap_value = 8;
1625
   parameter level1_value = 15;
1626
   reg  [length:1] qi;
1627
   reg lfsr_fb;
1628
   wire [length:1] q_next;
1629
   reg [32:1] polynom;
1630
   integer i;
1631
   always @ (qi)
1632
   begin
1633
        case (length)
1634
         2: polynom = 32'b11;                               // 0x3
1635
         3: polynom = 32'b110;                              // 0x6
1636
         4: polynom = 32'b1100;                             // 0xC
1637
         5: polynom = 32'b10100;                            // 0x14
1638
         6: polynom = 32'b110000;                           // 0x30
1639
         7: polynom = 32'b1100000;                          // 0x60
1640
         8: polynom = 32'b10111000;                         // 0xb8
1641
         9: polynom = 32'b100010000;                        // 0x110
1642
        10: polynom = 32'b1001000000;                       // 0x240
1643
        11: polynom = 32'b10100000000;                      // 0x500
1644
        12: polynom = 32'b100000101001;                     // 0x829
1645
        13: polynom = 32'b1000000001100;                    // 0x100C
1646
        14: polynom = 32'b10000000010101;                   // 0x2015
1647
        15: polynom = 32'b110000000000000;                  // 0x6000
1648
        16: polynom = 32'b1101000000001000;                 // 0xD008
1649
        17: polynom = 32'b10010000000000000;                // 0x12000
1650
        18: polynom = 32'b100000010000000000;               // 0x20400
1651
        19: polynom = 32'b1000000000000100011;              // 0x40023
1652
        20: polynom = 32'b10000010000000000000;             // 0x82000
1653
        21: polynom = 32'b101000000000000000000;            // 0x140000
1654
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1655
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1656
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1657
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1658
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1659
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1660
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1661
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1662
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1663
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1664
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1665
        default: polynom = 32'b0;
1666
        endcase
1667
        lfsr_fb = qi[length];
1668
        for (i=length-1; i>=1; i=i-1) begin
1669
            if (polynom[i])
1670
                lfsr_fb = lfsr_fb  ~^ qi[i];
1671
        end
1672
    end
1673
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1674
   always @ (posedge clk or posedge rst)
1675
     if (rst)
1676
       qi <= {length{1'b0}};
1677
     else
1678
     if (cke)
1679
       qi <= q_next;
1680
   assign q = qi;
1681
   always @ (posedge clk or posedge rst)
1682
     if (rst)
1683
       zq <= 1'b1;
1684
     else
1685
     if (cke)
1686
       zq <= q_next == {length{1'b0}};
1687
endmodule
1688
//////////////////////////////////////////////////////////////////////
1689
////                                                              ////
1690
////  Versatile counter                                           ////
1691
////                                                              ////
1692
////  Description                                                 ////
1693
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1694
////  counter                                                     ////
1695
////                                                              ////
1696
////  To Do:                                                      ////
1697
////   - add LFSR with more taps                                  ////
1698
////                                                              ////
1699
////  Author(s):                                                  ////
1700
////      - Michael Unneback, unneback@opencores.org              ////
1701
////        ORSoC AB                                              ////
1702
////                                                              ////
1703
//////////////////////////////////////////////////////////////////////
1704
////                                                              ////
1705
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1706
////                                                              ////
1707
//// This source file may be used and distributed without         ////
1708
//// restriction provided that this copyright statement is not    ////
1709
//// removed from the file and that any derivative work contains  ////
1710
//// the original copyright notice and the associated disclaimer. ////
1711
////                                                              ////
1712
//// This source file is free software; you can redistribute it   ////
1713
//// and/or modify it under the terms of the GNU Lesser General   ////
1714
//// Public License as published by the Free Software Foundation; ////
1715
//// either version 2.1 of the License, or (at your option) any   ////
1716
//// later version.                                               ////
1717
////                                                              ////
1718
//// This source is distributed in the hope that it will be       ////
1719
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1720
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1721
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1722
//// details.                                                     ////
1723
////                                                              ////
1724
//// You should have received a copy of the GNU Lesser General    ////
1725
//// Public License along with this source; if not, download it   ////
1726
//// from http://www.opencores.org/lgpl.shtml                     ////
1727
////                                                              ////
1728
//////////////////////////////////////////////////////////////////////
1729
// LFSR counter
1730 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1731 6 unneback
   parameter length = 4;
1732
   input cke;
1733
   input rew;
1734
   output reg level1;
1735
   input rst;
1736
   input clk;
1737
   parameter clear_value = 0;
1738
   parameter set_value = 1;
1739
   parameter wrap_value = 8;
1740
   parameter level1_value = 15;
1741 29 unneback
   wire clear;
1742
   assign clear=1'b0;
1743 6 unneback
   reg  [length:1] qi;
1744
   reg lfsr_fb, lfsr_fb_rew;
1745
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1746
   reg [32:1] polynom_rew;
1747
   integer j;
1748
   reg [32:1] polynom;
1749
   integer i;
1750
   always @ (qi)
1751
   begin
1752
        case (length)
1753
         2: polynom = 32'b11;                               // 0x3
1754
         3: polynom = 32'b110;                              // 0x6
1755
         4: polynom = 32'b1100;                             // 0xC
1756
         5: polynom = 32'b10100;                            // 0x14
1757
         6: polynom = 32'b110000;                           // 0x30
1758
         7: polynom = 32'b1100000;                          // 0x60
1759
         8: polynom = 32'b10111000;                         // 0xb8
1760
         9: polynom = 32'b100010000;                        // 0x110
1761
        10: polynom = 32'b1001000000;                       // 0x240
1762
        11: polynom = 32'b10100000000;                      // 0x500
1763
        12: polynom = 32'b100000101001;                     // 0x829
1764
        13: polynom = 32'b1000000001100;                    // 0x100C
1765
        14: polynom = 32'b10000000010101;                   // 0x2015
1766
        15: polynom = 32'b110000000000000;                  // 0x6000
1767
        16: polynom = 32'b1101000000001000;                 // 0xD008
1768
        17: polynom = 32'b10010000000000000;                // 0x12000
1769
        18: polynom = 32'b100000010000000000;               // 0x20400
1770
        19: polynom = 32'b1000000000000100011;              // 0x40023
1771
        20: polynom = 32'b10000010000000000000;             // 0x82000
1772
        21: polynom = 32'b101000000000000000000;            // 0x140000
1773
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1774
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1775
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1776
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1777
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1778
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1779
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1780
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1781
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1782
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1783
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1784
        default: polynom = 32'b0;
1785
        endcase
1786
        lfsr_fb = qi[length];
1787
        for (i=length-1; i>=1; i=i-1) begin
1788
            if (polynom[i])
1789
                lfsr_fb = lfsr_fb  ~^ qi[i];
1790
        end
1791
    end
1792
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1793
   always @ (qi)
1794
   begin
1795
        case (length)
1796
         2: polynom_rew = 32'b11;
1797
         3: polynom_rew = 32'b110;
1798
         4: polynom_rew = 32'b1100;
1799
         5: polynom_rew = 32'b10100;
1800
         6: polynom_rew = 32'b110000;
1801
         7: polynom_rew = 32'b1100000;
1802
         8: polynom_rew = 32'b10111000;
1803
         9: polynom_rew = 32'b100010000;
1804
        10: polynom_rew = 32'b1001000000;
1805
        11: polynom_rew = 32'b10100000000;
1806
        12: polynom_rew = 32'b100000101001;
1807
        13: polynom_rew = 32'b1000000001100;
1808
        14: polynom_rew = 32'b10000000010101;
1809
        15: polynom_rew = 32'b110000000000000;
1810
        16: polynom_rew = 32'b1101000000001000;
1811
        17: polynom_rew = 32'b10010000000000000;
1812
        18: polynom_rew = 32'b100000010000000000;
1813
        19: polynom_rew = 32'b1000000000000100011;
1814
        20: polynom_rew = 32'b10000010000000000000;
1815
        21: polynom_rew = 32'b101000000000000000000;
1816
        22: polynom_rew = 32'b1100000000000000000000;
1817
        23: polynom_rew = 32'b10000100000000000000000;
1818
        24: polynom_rew = 32'b111000010000000000000000;
1819
        25: polynom_rew = 32'b1001000000000000000000000;
1820
        26: polynom_rew = 32'b10000000000000000000100011;
1821
        27: polynom_rew = 32'b100000000000000000000010011;
1822
        28: polynom_rew = 32'b1100100000000000000000000000;
1823
        29: polynom_rew = 32'b10100000000000000000000000000;
1824
        30: polynom_rew = 32'b100000000000000000000000101001;
1825
        31: polynom_rew = 32'b1001000000000000000000000000000;
1826
        32: polynom_rew = 32'b10000000001000000000000000000011;
1827
        default: polynom_rew = 32'b0;
1828
        endcase
1829
        // rotate left
1830
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1831
        lfsr_fb_rew = qi[length];
1832
        for (i=length-1; i>=1; i=i-1) begin
1833
            if (polynom_rew[i])
1834
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1835
        end
1836
    end
1837
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1838
   assign q_next = rew ? q_next_rew : q_next_fw;
1839
   always @ (posedge clk or posedge rst)
1840
     if (rst)
1841
       qi <= {length{1'b0}};
1842
     else
1843
     if (cke)
1844
       qi <= q_next;
1845
    always @ (posedge clk or posedge rst)
1846
    if (rst)
1847
        level1 <= 1'b0;
1848
    else
1849
    if (cke)
1850 29 unneback
    if (clear)
1851
        level1 <= 1'b0;
1852
    else if (q_next == level1_value)
1853 6 unneback
        level1 <= 1'b1;
1854
    else if (qi == level1_value & rew)
1855
        level1 <= 1'b0;
1856
endmodule
1857
//////////////////////////////////////////////////////////////////////
1858
////                                                              ////
1859
////  Versatile counter                                           ////
1860
////                                                              ////
1861
////  Description                                                 ////
1862
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1863
////  counter                                                     ////
1864
////                                                              ////
1865
////  To Do:                                                      ////
1866
////   - add LFSR with more taps                                  ////
1867
////                                                              ////
1868
////  Author(s):                                                  ////
1869
////      - Michael Unneback, unneback@opencores.org              ////
1870
////        ORSoC AB                                              ////
1871
////                                                              ////
1872
//////////////////////////////////////////////////////////////////////
1873
////                                                              ////
1874
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1875
////                                                              ////
1876
//// This source file may be used and distributed without         ////
1877
//// restriction provided that this copyright statement is not    ////
1878
//// removed from the file and that any derivative work contains  ////
1879
//// the original copyright notice and the associated disclaimer. ////
1880
////                                                              ////
1881
//// This source file is free software; you can redistribute it   ////
1882
//// and/or modify it under the terms of the GNU Lesser General   ////
1883
//// Public License as published by the Free Software Foundation; ////
1884
//// either version 2.1 of the License, or (at your option) any   ////
1885
//// later version.                                               ////
1886
////                                                              ////
1887
//// This source is distributed in the hope that it will be       ////
1888
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1889
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1890
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1891
//// details.                                                     ////
1892
////                                                              ////
1893
//// You should have received a copy of the GNU Lesser General    ////
1894
//// Public License along with this source; if not, download it   ////
1895
//// from http://www.opencores.org/lgpl.shtml                     ////
1896
////                                                              ////
1897
//////////////////////////////////////////////////////////////////////
1898
// GRAY counter
1899 18 unneback
module vl_cnt_gray ( q, rst, clk);
1900 6 unneback
   parameter length = 4;
1901
   output reg [length:1] q;
1902
   input rst;
1903
   input clk;
1904
   parameter clear_value = 0;
1905
   parameter set_value = 1;
1906
   parameter wrap_value = 8;
1907
   parameter level1_value = 15;
1908
   reg  [length:1] qi;
1909
   wire [length:1] q_next;
1910
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1911
   always @ (posedge clk or posedge rst)
1912
     if (rst)
1913
       qi <= {length{1'b0}};
1914
     else
1915
       qi <= q_next;
1916
   always @ (posedge clk or posedge rst)
1917
     if (rst)
1918
       q <= {length{1'b0}};
1919
     else
1920
         q <= (q_next>>1) ^ q_next;
1921
endmodule
1922
//////////////////////////////////////////////////////////////////////
1923
////                                                              ////
1924
////  Versatile counter                                           ////
1925
////                                                              ////
1926
////  Description                                                 ////
1927
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1928
////  counter                                                     ////
1929
////                                                              ////
1930
////  To Do:                                                      ////
1931
////   - add LFSR with more taps                                  ////
1932
////                                                              ////
1933
////  Author(s):                                                  ////
1934
////      - Michael Unneback, unneback@opencores.org              ////
1935
////        ORSoC AB                                              ////
1936
////                                                              ////
1937
//////////////////////////////////////////////////////////////////////
1938
////                                                              ////
1939
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1940
////                                                              ////
1941
//// This source file may be used and distributed without         ////
1942
//// restriction provided that this copyright statement is not    ////
1943
//// removed from the file and that any derivative work contains  ////
1944
//// the original copyright notice and the associated disclaimer. ////
1945
////                                                              ////
1946
//// This source file is free software; you can redistribute it   ////
1947
//// and/or modify it under the terms of the GNU Lesser General   ////
1948
//// Public License as published by the Free Software Foundation; ////
1949
//// either version 2.1 of the License, or (at your option) any   ////
1950
//// later version.                                               ////
1951
////                                                              ////
1952
//// This source is distributed in the hope that it will be       ////
1953
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1954
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1955
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1956
//// details.                                                     ////
1957
////                                                              ////
1958
//// You should have received a copy of the GNU Lesser General    ////
1959
//// Public License along with this source; if not, download it   ////
1960
//// from http://www.opencores.org/lgpl.shtml                     ////
1961
////                                                              ////
1962
//////////////////////////////////////////////////////////////////////
1963
// GRAY counter
1964 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1965 6 unneback
   parameter length = 4;
1966
   input cke;
1967
   output reg [length:1] q;
1968
   input rst;
1969
   input clk;
1970
   parameter clear_value = 0;
1971
   parameter set_value = 1;
1972
   parameter wrap_value = 8;
1973
   parameter level1_value = 15;
1974
   reg  [length:1] qi;
1975
   wire [length:1] q_next;
1976
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1977
   always @ (posedge clk or posedge rst)
1978
     if (rst)
1979
       qi <= {length{1'b0}};
1980
     else
1981
     if (cke)
1982
       qi <= q_next;
1983
   always @ (posedge clk or posedge rst)
1984
     if (rst)
1985
       q <= {length{1'b0}};
1986
     else
1987
       if (cke)
1988
         q <= (q_next>>1) ^ q_next;
1989
endmodule
1990
//////////////////////////////////////////////////////////////////////
1991
////                                                              ////
1992
////  Versatile counter                                           ////
1993
////                                                              ////
1994
////  Description                                                 ////
1995
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1996
////  counter                                                     ////
1997
////                                                              ////
1998
////  To Do:                                                      ////
1999
////   - add LFSR with more taps                                  ////
2000
////                                                              ////
2001
////  Author(s):                                                  ////
2002
////      - Michael Unneback, unneback@opencores.org              ////
2003
////        ORSoC AB                                              ////
2004
////                                                              ////
2005
//////////////////////////////////////////////////////////////////////
2006
////                                                              ////
2007
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2008
////                                                              ////
2009
//// This source file may be used and distributed without         ////
2010
//// restriction provided that this copyright statement is not    ////
2011
//// removed from the file and that any derivative work contains  ////
2012
//// the original copyright notice and the associated disclaimer. ////
2013
////                                                              ////
2014
//// This source file is free software; you can redistribute it   ////
2015
//// and/or modify it under the terms of the GNU Lesser General   ////
2016
//// Public License as published by the Free Software Foundation; ////
2017
//// either version 2.1 of the License, or (at your option) any   ////
2018
//// later version.                                               ////
2019
////                                                              ////
2020
//// This source is distributed in the hope that it will be       ////
2021
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2022
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2023
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2024
//// details.                                                     ////
2025
////                                                              ////
2026
//// You should have received a copy of the GNU Lesser General    ////
2027
//// Public License along with this source; if not, download it   ////
2028
//// from http://www.opencores.org/lgpl.shtml                     ////
2029
////                                                              ////
2030
//////////////////////////////////////////////////////////////////////
2031
// GRAY counter
2032 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2033 6 unneback
   parameter length = 4;
2034
   input cke;
2035
   output reg [length:1] q;
2036
   output [length:1] q_bin;
2037
   input rst;
2038
   input clk;
2039
   parameter clear_value = 0;
2040
   parameter set_value = 1;
2041
   parameter wrap_value = 8;
2042
   parameter level1_value = 15;
2043
   reg  [length:1] qi;
2044
   wire [length:1] q_next;
2045
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2046
   always @ (posedge clk or posedge rst)
2047
     if (rst)
2048
       qi <= {length{1'b0}};
2049
     else
2050
     if (cke)
2051
       qi <= q_next;
2052
   always @ (posedge clk or posedge rst)
2053
     if (rst)
2054
       q <= {length{1'b0}};
2055
     else
2056
       if (cke)
2057
         q <= (q_next>>1) ^ q_next;
2058
   assign q_bin = qi;
2059
endmodule
2060
//////////////////////////////////////////////////////////////////////
2061
////                                                              ////
2062
////  Versatile library, counters                                 ////
2063
////                                                              ////
2064
////  Description                                                 ////
2065
////  counters                                                    ////
2066
////                                                              ////
2067
////                                                              ////
2068
////  To Do:                                                      ////
2069
////   - add more counters                                        ////
2070
////                                                              ////
2071
////  Author(s):                                                  ////
2072
////      - Michael Unneback, unneback@opencores.org              ////
2073
////        ORSoC AB                                              ////
2074
////                                                              ////
2075
//////////////////////////////////////////////////////////////////////
2076
////                                                              ////
2077
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2078
////                                                              ////
2079
//// This source file may be used and distributed without         ////
2080
//// restriction provided that this copyright statement is not    ////
2081
//// removed from the file and that any derivative work contains  ////
2082
//// the original copyright notice and the associated disclaimer. ////
2083
////                                                              ////
2084
//// This source file is free software; you can redistribute it   ////
2085
//// and/or modify it under the terms of the GNU Lesser General   ////
2086
//// Public License as published by the Free Software Foundation; ////
2087
//// either version 2.1 of the License, or (at your option) any   ////
2088
//// later version.                                               ////
2089
////                                                              ////
2090
//// This source is distributed in the hope that it will be       ////
2091
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2092
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2093
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2094
//// details.                                                     ////
2095
////                                                              ////
2096
//// You should have received a copy of the GNU Lesser General    ////
2097
//// Public License along with this source; if not, download it   ////
2098
//// from http://www.opencores.org/lgpl.shtml                     ////
2099
////                                                              ////
2100
//////////////////////////////////////////////////////////////////////
2101 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2102 6 unneback
   parameter length = 4;
2103
   output reg [0:length-1] q;
2104
   input rst;
2105
   input clk;
2106
    always @ (posedge clk or posedge rst)
2107
    if (rst)
2108
        q <= {1'b1,{length-1{1'b0}}};
2109
    else
2110
        q <= {q[length-1],q[0:length-2]};
2111
endmodule
2112 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2113 6 unneback
   parameter length = 4;
2114
   input cke;
2115
   output reg [0:length-1] q;
2116
   input rst;
2117
   input clk;
2118
    always @ (posedge clk or posedge rst)
2119
    if (rst)
2120
        q <= {1'b1,{length-1{1'b0}}};
2121
    else
2122
        if (cke)
2123
            q <= {q[length-1],q[0:length-2]};
2124
endmodule
2125 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2126 6 unneback
   parameter length = 4;
2127
   input cke, clear;
2128
   output reg [0:length-1] q;
2129
   input rst;
2130
   input clk;
2131
    always @ (posedge clk or posedge rst)
2132
    if (rst)
2133
        q <= {1'b1,{length-1{1'b0}}};
2134
    else
2135
        if (cke)
2136
            if (clear)
2137
                q <= {1'b1,{length-1{1'b0}}};
2138
            else
2139
                q <= q >> 1;
2140
endmodule
2141 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2142 6 unneback
   parameter length = 4;
2143
   input cke, clear;
2144
   output reg [0:length-1] q;
2145
   input rst;
2146
   input clk;
2147
    always @ (posedge clk or posedge rst)
2148
    if (rst)
2149
        q <= {1'b1,{length-1{1'b0}}};
2150
    else
2151
        if (cke)
2152
            if (clear)
2153
                q <= {1'b1,{length-1{1'b0}}};
2154
            else
2155
            q <= {q[length-1],q[0:length-2]};
2156
endmodule
2157
//////////////////////////////////////////////////////////////////////
2158
////                                                              ////
2159
////  Versatile library, memories                                 ////
2160
////                                                              ////
2161
////  Description                                                 ////
2162
////  memories                                                    ////
2163
////                                                              ////
2164
////                                                              ////
2165
////  To Do:                                                      ////
2166
////   - add more memory types                                    ////
2167
////                                                              ////
2168
////  Author(s):                                                  ////
2169
////      - Michael Unneback, unneback@opencores.org              ////
2170
////        ORSoC AB                                              ////
2171
////                                                              ////
2172
//////////////////////////////////////////////////////////////////////
2173
////                                                              ////
2174
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2175
////                                                              ////
2176
//// This source file may be used and distributed without         ////
2177
//// restriction provided that this copyright statement is not    ////
2178
//// removed from the file and that any derivative work contains  ////
2179
//// the original copyright notice and the associated disclaimer. ////
2180
////                                                              ////
2181
//// This source file is free software; you can redistribute it   ////
2182
//// and/or modify it under the terms of the GNU Lesser General   ////
2183
//// Public License as published by the Free Software Foundation; ////
2184
//// either version 2.1 of the License, or (at your option) any   ////
2185
//// later version.                                               ////
2186
////                                                              ////
2187
//// This source is distributed in the hope that it will be       ////
2188
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2189
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2190
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2191
//// details.                                                     ////
2192
////                                                              ////
2193
//// You should have received a copy of the GNU Lesser General    ////
2194
//// Public License along with this source; if not, download it   ////
2195
//// from http://www.opencores.org/lgpl.shtml                     ////
2196
////                                                              ////
2197
//////////////////////////////////////////////////////////////////////
2198
/// ROM
2199 7 unneback
module vl_rom_init ( adr, q, clk);
2200
   parameter data_width = 32;
2201
   parameter addr_width = 8;
2202
   input [(addr_width-1):0]       adr;
2203
   output reg [(data_width-1):0] q;
2204
   input                         clk;
2205
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2206
   parameter memory_file = "vl_rom.vmem";
2207
   initial
2208
     begin
2209
        $readmemh(memory_file, rom);
2210
     end
2211
   always @ (posedge clk)
2212
     q <= rom[adr];
2213
endmodule
2214 14 unneback
/*
2215 7 unneback
module vl_rom ( adr, q, clk);
2216 6 unneback
parameter data_width = 32;
2217
parameter addr_width = 4;
2218
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2219
    {32'h18000000},
2220
    {32'hA8200000},
2221
    {32'hA8200000},
2222
    {32'hA8200000},
2223
    {32'h44003000},
2224
    {32'h15000000},
2225
    {32'h15000000},
2226
    {32'h15000000},
2227
    {32'h15000000},
2228
    {32'h15000000},
2229
    {32'h15000000},
2230
    {32'h15000000},
2231
    {32'h15000000},
2232
    {32'h15000000},
2233
    {32'h15000000},
2234
    {32'h15000000}};
2235 7 unneback
input [addr_width-1:0] adr;
2236 6 unneback
output reg [data_width-1:0] q;
2237
input clk;
2238
always @ (posedge clk)
2239 7 unneback
    q <= data[adr];
2240 6 unneback
endmodule
2241 14 unneback
*/
2242 6 unneback
// Single port RAM
2243
module vl_ram ( d, adr, we, q, clk);
2244
   parameter data_width = 32;
2245
   parameter addr_width = 8;
2246
   input [(data_width-1):0]      d;
2247
   input [(addr_width-1):0]       adr;
2248
   input                         we;
2249 7 unneback
   output reg [(data_width-1):0] q;
2250 6 unneback
   input                         clk;
2251
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2252 7 unneback
   parameter init = 0;
2253
   parameter memory_file = "vl_ram.vmem";
2254
   generate if (init) begin : init_mem
2255
   initial
2256
     begin
2257
        $readmemh(memory_file, ram);
2258
     end
2259
   end
2260
   endgenerate
2261 6 unneback
   always @ (posedge clk)
2262
   begin
2263
   if (we)
2264
     ram[adr] <= d;
2265
   q <= ram[adr];
2266
   end
2267
endmodule
2268 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2269
   parameter data_width = 32;
2270
   parameter addr_width = 8;
2271
   input [(data_width-1):0]      d;
2272
   input [(addr_width-1):0]       adr;
2273
   input [(addr_width/4)-1:0]    be;
2274
   input                         we;
2275
   output reg [(data_width-1):0] q;
2276
   input                         clk;
2277
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2278
   parameter init = 0;
2279
   parameter memory_file = "vl_ram.vmem";
2280
   generate if (init) begin : init_mem
2281
   initial
2282
     begin
2283
        $readmemh(memory_file, ram);
2284
     end
2285
   end
2286
   endgenerate
2287
   genvar i;
2288
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2289
      always @ (posedge clk)
2290
      if (we & be[i])
2291
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2292
   end
2293
   endgenerate
2294
   always @ (posedge clk)
2295
      q <= ram[adr];
2296
endmodule
2297 6 unneback
// Dual port RAM
2298
// ACTEL FPGA should not use logic to handle rw collision
2299 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2300 6 unneback
   parameter data_width = 32;
2301
   parameter addr_width = 8;
2302
   input [(data_width-1):0]      d_a;
2303
   input [(addr_width-1):0]       adr_a;
2304
   input [(addr_width-1):0]       adr_b;
2305
   input                         we_a;
2306
   output [(data_width-1):0]      q_b;
2307
   input                         clk_a, clk_b;
2308
   reg [(addr_width-1):0]         adr_b_reg;
2309
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2310 7 unneback
   parameter init = 0;
2311
   parameter memory_file = "vl_ram.vmem";
2312
   generate if (init) begin : init_mem
2313
   initial
2314
     begin
2315
        $readmemh(memory_file, ram);
2316
     end
2317
   end
2318
   endgenerate
2319 6 unneback
   always @ (posedge clk_a)
2320
   if (we_a)
2321
     ram[adr_a] <= d_a;
2322
   always @ (posedge clk_b)
2323
   adr_b_reg <= adr_b;
2324
   assign q_b = ram[adr_b_reg];
2325
endmodule
2326 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2327 6 unneback
   parameter data_width = 32;
2328
   parameter addr_width = 8;
2329
   input [(data_width-1):0]      d_a;
2330
   input [(addr_width-1):0]       adr_a;
2331
   input [(addr_width-1):0]       adr_b;
2332
   input                         we_a;
2333
   output [(data_width-1):0]      q_b;
2334
   output reg [(data_width-1):0] q_a;
2335
   input                         clk_a, clk_b;
2336
   reg [(data_width-1):0]         q_b;
2337
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2338 7 unneback
   parameter init = 0;
2339
   parameter memory_file = "vl_ram.vmem";
2340
   generate if (init) begin : init_mem
2341
   initial
2342
     begin
2343
        $readmemh(memory_file, ram);
2344
     end
2345
   end
2346
   endgenerate
2347 6 unneback
   always @ (posedge clk_a)
2348
     begin
2349
        q_a <= ram[adr_a];
2350
        if (we_a)
2351
             ram[adr_a] <= d_a;
2352
     end
2353
   always @ (posedge clk_b)
2354
          q_b <= ram[adr_b];
2355
endmodule
2356 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2357 6 unneback
   parameter data_width = 32;
2358
   parameter addr_width = 8;
2359
   input [(data_width-1):0]      d_a;
2360
   input [(addr_width-1):0]       adr_a;
2361
   input [(addr_width-1):0]       adr_b;
2362
   input                         we_a;
2363
   output [(data_width-1):0]      q_b;
2364
   input [(data_width-1):0]       d_b;
2365
   output reg [(data_width-1):0] q_a;
2366
   input                         we_b;
2367
   input                         clk_a, clk_b;
2368
   reg [(data_width-1):0]         q_b;
2369
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2370 7 unneback
   parameter init = 0;
2371
   parameter memory_file = "vl_ram.vmem";
2372
   generate if (init) begin : init_mem
2373
   initial
2374
     begin
2375
        $readmemh(memory_file, ram);
2376
     end
2377
   end
2378
   endgenerate
2379 6 unneback
   always @ (posedge clk_a)
2380
     begin
2381
        q_a <= ram[adr_a];
2382
        if (we_a)
2383
             ram[adr_a] <= d_a;
2384
     end
2385
   always @ (posedge clk_b)
2386
     begin
2387
        q_b <= ram[adr_b];
2388
        if (we_b)
2389
          ram[adr_b] <= d_b;
2390
     end
2391
endmodule
2392
// Content addresable memory, CAM
2393
// FIFO
2394 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2395
    d, wr, fifo_full,
2396
    q, rd, fifo_empty,
2397
    fill_level,
2398
    clk, rst
2399
    );
2400
parameter data_width = 18;
2401
parameter addr_width = 4;
2402
// write side
2403
input  [data_width-1:0] d;
2404
input                   wr;
2405
output                  fifo_full;
2406
// read side
2407
output [data_width-1:0] q;
2408
input                   rd;
2409
output                  fifo_empty;
2410
// common
2411
output [addr_width:0]   fill_level;
2412
input rst, clk;
2413
wire [addr_width:1] wadr, radr;
2414
vl_cnt_bin_ce
2415
    # ( .length(addr_width))
2416
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2417
vl_cnt_bin_ce
2418
    # (.length(addr_width))
2419
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2420
vl_dpram_1r1w
2421
    # (.data_width(data_width), .addr_width(addr_width))
2422
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2423
vl_cnt_bin_ce_rew_zq_l1
2424 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2425 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2426
endmodule
2427 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2428
// RAM is supposed to be larger than the two FIFOs
2429
// LFSR counters used adr pointers
2430
module vl_fifo_2r2w_sync_simplex (
2431
    // a side
2432
    a_d, a_wr, a_fifo_full,
2433
    a_q, a_rd, a_fifo_empty,
2434
    a_fill_level,
2435
    // b side
2436
    b_d, b_wr, b_fifo_full,
2437
    b_q, b_rd, b_fifo_empty,
2438
    b_fill_level,
2439
    // common
2440
    clk, rst
2441
    );
2442
parameter data_width = 8;
2443
parameter addr_width = 5;
2444
parameter fifo_full_level = (1<<addr_width)-1;
2445
// a side
2446
input  [data_width-1:0] a_d;
2447
input                   a_wr;
2448
output                  a_fifo_full;
2449
output [data_width-1:0] a_q;
2450
input                   a_rd;
2451
output                  a_fifo_empty;
2452
output [addr_width-1:0] a_fill_level;
2453
// b side
2454
input  [data_width-1:0] b_d;
2455
input                   b_wr;
2456
output                  b_fifo_full;
2457
output [data_width-1:0] b_q;
2458
input                   b_rd;
2459
output                  b_fifo_empty;
2460
output [addr_width-1:0] b_fill_level;
2461
input                   clk;
2462
input                   rst;
2463
// adr_gen
2464
wire [addr_width:1] a_wadr, a_radr;
2465
wire [addr_width:1] b_wadr, b_radr;
2466
// dpram
2467
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2468
vl_cnt_lfsr_ce
2469
    # ( .length(addr_width))
2470
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2471
vl_cnt_lfsr_ce
2472
    # (.length(addr_width))
2473
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2474
vl_cnt_lfsr_ce
2475
    # ( .length(addr_width))
2476
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2477
vl_cnt_lfsr_ce
2478
    # (.length(addr_width))
2479
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2480
// mux read or write adr to DPRAM
2481
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2482
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2483
vl_dpram_2r2w
2484
    # (.data_width(data_width), .addr_width(addr_width+1))
2485
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2486
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2487
vl_cnt_bin_ce_rew_zq_l1
2488 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2489 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2490
vl_cnt_bin_ce_rew_zq_l1
2491 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2492 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2493
endmodule
2494 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2495 11 unneback
   parameter addr_width = 4;
2496
   parameter N = addr_width-1;
2497 6 unneback
   parameter Q1 = 2'b00;
2498
   parameter Q2 = 2'b01;
2499
   parameter Q3 = 2'b11;
2500
   parameter Q4 = 2'b10;
2501
   parameter going_empty = 1'b0;
2502
   parameter going_full  = 1'b1;
2503
   input [N:0]  wptr, rptr;
2504 14 unneback
   output       fifo_empty;
2505 6 unneback
   output       fifo_full;
2506
   input        wclk, rclk, rst;
2507
   wire direction;
2508
   reg  direction_set, direction_clr;
2509
   wire async_empty, async_full;
2510
   wire fifo_full2;
2511 14 unneback
   wire fifo_empty2;
2512 6 unneback
   // direction_set
2513
   always @ (wptr[N:N-1] or rptr[N:N-1])
2514
     case ({wptr[N:N-1],rptr[N:N-1]})
2515
       {Q1,Q2} : direction_set <= 1'b1;
2516
       {Q2,Q3} : direction_set <= 1'b1;
2517
       {Q3,Q4} : direction_set <= 1'b1;
2518
       {Q4,Q1} : direction_set <= 1'b1;
2519
       default : direction_set <= 1'b0;
2520
     endcase
2521
   // direction_clear
2522
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2523
     if (rst)
2524
       direction_clr <= 1'b1;
2525
     else
2526
       case ({wptr[N:N-1],rptr[N:N-1]})
2527
         {Q2,Q1} : direction_clr <= 1'b1;
2528
         {Q3,Q2} : direction_clr <= 1'b1;
2529
         {Q4,Q3} : direction_clr <= 1'b1;
2530
         {Q1,Q4} : direction_clr <= 1'b1;
2531
         default : direction_clr <= 1'b0;
2532
       endcase
2533 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2534 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2535
   assign async_full  = (wptr == rptr) && (direction==going_full);
2536 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2537
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2538 6 unneback
/*
2539
   always @ (posedge wclk or posedge rst or posedge async_full)
2540
     if (rst)
2541
       {fifo_full, fifo_full2} <= 2'b00;
2542
     else if (async_full)
2543
       {fifo_full, fifo_full2} <= 2'b11;
2544
     else
2545
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2546
*/
2547 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2548 6 unneback
     if (async_empty)
2549
       {fifo_empty, fifo_empty2} <= 2'b11;
2550
     else
2551 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2552 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2553
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2554 27 unneback
endmodule // async_compb
2555 6 unneback
module vl_fifo_1r1w_async (
2556
    d, wr, fifo_full, wr_clk, wr_rst,
2557
    q, rd, fifo_empty, rd_clk, rd_rst
2558
    );
2559
parameter data_width = 18;
2560
parameter addr_width = 4;
2561
// write side
2562
input  [data_width-1:0] d;
2563
input                   wr;
2564
output                  fifo_full;
2565
input                   wr_clk;
2566
input                   wr_rst;
2567
// read side
2568
output [data_width-1:0] q;
2569
input                   rd;
2570
output                  fifo_empty;
2571
input                   rd_clk;
2572
input                   rd_rst;
2573
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2574 18 unneback
vl_cnt_gray_ce_bin
2575 6 unneback
    # ( .length(addr_width))
2576
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2577 18 unneback
vl_cnt_gray_ce_bin
2578 6 unneback
    # (.length(addr_width))
2579 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2580 7 unneback
vl_dpram_1r1w
2581 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2582
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2583
vl_fifo_cmp_async
2584
    # (.addr_width(addr_width))
2585
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2586
endmodule
2587 8 unneback
module vl_fifo_2r2w_async (
2588 6 unneback
    // a side
2589
    a_d, a_wr, a_fifo_full,
2590
    a_q, a_rd, a_fifo_empty,
2591
    a_clk, a_rst,
2592
    // b side
2593
    b_d, b_wr, b_fifo_full,
2594
    b_q, b_rd, b_fifo_empty,
2595
    b_clk, b_rst
2596
    );
2597
parameter data_width = 18;
2598
parameter addr_width = 4;
2599
// a side
2600
input  [data_width-1:0] a_d;
2601
input                   a_wr;
2602
output                  a_fifo_full;
2603
output [data_width-1:0] a_q;
2604
input                   a_rd;
2605
output                  a_fifo_empty;
2606
input                   a_clk;
2607
input                   a_rst;
2608
// b side
2609
input  [data_width-1:0] b_d;
2610
input                   b_wr;
2611
output                  b_fifo_full;
2612
output [data_width-1:0] b_q;
2613
input                   b_rd;
2614
output                  b_fifo_empty;
2615
input                   b_clk;
2616
input                   b_rst;
2617
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2618
vl_fifo_1r1w_async_a (
2619
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2620
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2621
    );
2622
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2623
vl_fifo_1r1w_async_b (
2624
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2625
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2626