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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 6 unneback
 // ALTERA
47
 //ACTEL
48
// sync reset
49 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
50 6 unneback
// output active high global reset sync with two DFFs 
51
`timescale 1 ns/100 ps
52
module vl_sync_rst ( rst_n_i, rst_o, clk);
53
input rst_n_i, clk;
54
output rst_o;
55 18 unneback
reg [1:0] tmp;
56 6 unneback
always @ (posedge clk or negedge rst_n_i)
57
if (!rst_n_i)
58 17 unneback
        tmp <= 2'b11;
59 6 unneback
else
60 17 unneback
        tmp <= {1'b0,tmp[0]};
61
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
62 6 unneback
endmodule
63
// vl_pll
64
 //altera
65
 //actel
66
//////////////////////////////////////////////////////////////////////
67
////                                                              ////
68
////  Versatile library, registers                                ////
69
////                                                              ////
70
////  Description                                                 ////
71
////  Different type of registers                                 ////
72
////                                                              ////
73
////                                                              ////
74
////  To Do:                                                      ////
75
////   - add more different registers                             ////
76
////                                                              ////
77
////  Author(s):                                                  ////
78
////      - Michael Unneback, unneback@opencores.org              ////
79
////        ORSoC AB                                              ////
80
////                                                              ////
81
//////////////////////////////////////////////////////////////////////
82
////                                                              ////
83
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84
////                                                              ////
85
//// This source file may be used and distributed without         ////
86
//// restriction provided that this copyright statement is not    ////
87
//// removed from the file and that any derivative work contains  ////
88
//// the original copyright notice and the associated disclaimer. ////
89
////                                                              ////
90
//// This source file is free software; you can redistribute it   ////
91
//// and/or modify it under the terms of the GNU Lesser General   ////
92
//// Public License as published by the Free Software Foundation; ////
93
//// either version 2.1 of the License, or (at your option) any   ////
94
//// later version.                                               ////
95
////                                                              ////
96
//// This source is distributed in the hope that it will be       ////
97
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100
//// details.                                                     ////
101
////                                                              ////
102
//// You should have received a copy of the GNU Lesser General    ////
103
//// Public License along with this source; if not, download it   ////
104
//// from http://www.opencores.org/lgpl.shtml                     ////
105
////                                                              ////
106
//////////////////////////////////////////////////////////////////////
107 18 unneback
module vl_dff ( d, q, clk, rst);
108 6 unneback
        parameter width = 1;
109
        parameter reset_value = 0;
110
        input [width-1:0] d;
111
        input clk, rst;
112
        output reg [width-1:0] q;
113
        always @ (posedge clk or posedge rst)
114
        if (rst)
115
                q <= reset_value;
116
        else
117
                q <= d;
118
endmodule
119 18 unneback
module vl_dff_array ( d, q, clk, rst);
120 6 unneback
        parameter width = 1;
121
        parameter depth = 2;
122
        parameter reset_value = 1'b0;
123
        input [width-1:0] d;
124
        input clk, rst;
125
        output [width-1:0] q;
126
        reg  [0:depth-1] q_tmp [width-1:0];
127
        integer i;
128
        always @ (posedge clk or posedge rst)
129
        if (rst) begin
130
            for (i=0;i<depth;i=i+1)
131
                q_tmp[i] <= {width{reset_value}};
132
        end else begin
133
            q_tmp[0] <= d;
134
            for (i=1;i<depth;i=i+1)
135
                q_tmp[i] <= q_tmp[i-1];
136
        end
137
    assign q = q_tmp[depth-1];
138
endmodule
139 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
140 6 unneback
        parameter width = 1;
141
        parameter reset_value = 0;
142
        input [width-1:0] d;
143
        input ce, clk, rst;
144
        output reg [width-1:0] q;
145
        always @ (posedge clk or posedge rst)
146
        if (rst)
147
                q <= reset_value;
148
        else
149
                if (ce)
150
                        q <= d;
151
endmodule
152 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
153 8 unneback
        parameter width = 1;
154
        parameter reset_value = 0;
155
        input [width-1:0] d;
156 10 unneback
        input ce, clear, clk, rst;
157 8 unneback
        output reg [width-1:0] q;
158
        always @ (posedge clk or posedge rst)
159
        if (rst)
160
            q <= reset_value;
161
        else
162
            if (ce)
163
                if (clear)
164
                    q <= {width{1'b0}};
165
                else
166
                    q <= d;
167
endmodule
168 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
169
        parameter width = 1;
170
        parameter reset_value = 0;
171
        input [width-1:0] d;
172
        input ce, set, clk, rst;
173
        output reg [width-1:0] q;
174
        always @ (posedge clk or posedge rst)
175
        if (rst)
176
            q <= reset_value;
177
        else
178
            if (ce)
179
                if (set)
180
                    q <= {width{1'b1}};
181
                else
182
                    q <= d;
183
endmodule
184 29 unneback
module vl_spr ( sp, r, q, clk, rst);
185
        parameter width = 1;
186
        parameter reset_value = 0;
187
        input sp, r;
188
        output reg q;
189
        input clk, rst;
190
        always @ (posedge clk or posedge rst)
191
        if (rst)
192
            q <= reset_value;
193
        else
194
            if (sp)
195
                q <= 1'b1;
196
            else if (r)
197
                q <= 1'b0;
198
endmodule
199
module vl_srp ( s, rp, q, clk, rst);
200
        parameter width = 1;
201
        parameter reset_value = 0;
202
        input s, rp;
203
        output reg q;
204
        input clk, rst;
205
        always @ (posedge clk or posedge rst)
206
        if (rst)
207
            q <= reset_value;
208
        else
209
            if (rp)
210
                q <= 1'b0;
211
            else if (s)
212
                q <= 1'b1;
213
endmodule
214 6 unneback
// megafunction wizard: %LPM_FF%
215
// GENERATION: STANDARD
216
// VERSION: WM1.0
217
// MODULE: lpm_ff 
218
// ============================================================
219
// File Name: dff_sr.v
220
// Megafunction Name(s):
221
//                      lpm_ff
222
//
223
// Simulation Library Files(s):
224
//                      lpm
225
// ============================================================
226
// ************************************************************
227
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
228
//
229
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
230
// ************************************************************
231
//Copyright (C) 1991-2010 Altera Corporation
232
//Your use of Altera Corporation's design tools, logic functions 
233
//and other software and tools, and its AMPP partner logic 
234
//functions, and any output files from any of the foregoing 
235
//(including device programming or simulation files), and any 
236
//associated documentation or information are expressly subject 
237
//to the terms and conditions of the Altera Program License 
238
//Subscription Agreement, Altera MegaCore Function License 
239
//Agreement, or other applicable license agreement, including, 
240
//without limitation, that your use is for the sole purpose of 
241
//programming logic devices manufactured by Altera and sold by 
242
//Altera or its authorized distributors.  Please refer to the 
243
//applicable agreement for further details.
244
// synopsys translate_off
245
`timescale 1 ps / 1 ps
246
// synopsys translate_on
247 18 unneback
module vl_dff_sr (
248 6 unneback
        aclr,
249
        aset,
250
        clock,
251
        data,
252
        q);
253
        input     aclr;
254
        input     aset;
255
        input     clock;
256
        input     data;
257
        output    q;
258
        wire [0:0] sub_wire0;
259
        wire [0:0] sub_wire1 = sub_wire0[0:0];
260
        wire  q = sub_wire1;
261
        wire  sub_wire2 = data;
262
        wire  sub_wire3 = sub_wire2;
263
        lpm_ff  lpm_ff_component (
264
                                .aclr (aclr),
265
                                .clock (clock),
266
                                .data (sub_wire3),
267
                                .aset (aset),
268
                                .q (sub_wire0)
269
                                // synopsys translate_off
270
                                ,
271
                                .aload (),
272
                                .enable (),
273
                                .sclr (),
274
                                .sload (),
275
                                .sset ()
276
                                // synopsys translate_on
277
                                );
278
        defparam
279
                lpm_ff_component.lpm_fftype = "DFF",
280
                lpm_ff_component.lpm_type = "LPM_FF",
281
                lpm_ff_component.lpm_width = 1;
282
endmodule
283
// ============================================================
284
// CNX file retrieval info
285
// ============================================================
286
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
287
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
288
// Retrieval info: PRIVATE: ASET NUMERIC "1"
289
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
290
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
291
// Retrieval info: PRIVATE: DFF NUMERIC "1"
292
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
293
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
294
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
295
// Retrieval info: PRIVATE: SSET NUMERIC "0"
296
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
297
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
298
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
299
// Retrieval info: PRIVATE: nBit NUMERIC "1"
300
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
301
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
302
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
303
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
304
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
305
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
306
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
307
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
308
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
309
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
310
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
311
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
312
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
313
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
314
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
315
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
316
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
317
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
318
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
319
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
320
// Retrieval info: LIB_FILE: lpm
321
// LATCH
322
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
323 18 unneback
module vl_latch ( d, le, q, clk);
324 6 unneback
input d, le;
325
output q;
326
input clk;
327
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
328
endmodule
329 18 unneback
module vl_shreg ( d, q, clk, rst);
330 17 unneback
parameter depth = 10;
331
input d;
332
output q;
333
input clk, rst;
334
reg [1:depth] dffs;
335
always @ (posedge clk or posedge rst)
336
if (rst)
337
    dffs <= {depth{1'b0}};
338
else
339
    dffs <= {d,dffs[1:depth-1]};
340
assign q = dffs[depth];
341
endmodule
342 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
343 17 unneback
parameter depth = 10;
344
input d, ce;
345
output q;
346
input clk, rst;
347
reg [1:depth] dffs;
348
always @ (posedge clk or posedge rst)
349
if (rst)
350
    dffs <= {depth{1'b0}};
351
else
352
    if (ce)
353
        dffs <= {d,dffs[1:depth-1]};
354
assign q = dffs[depth];
355
endmodule
356 18 unneback
module vl_delay ( d, q, clk, rst);
357 15 unneback
parameter depth = 10;
358
input d;
359
output q;
360
input clk, rst;
361
reg [1:depth] dffs;
362
always @ (posedge clk or posedge rst)
363
if (rst)
364
    dffs <= {depth{1'b0}};
365
else
366
    dffs <= {d,dffs[1:depth-1]};
367
assign q = dffs[depth];
368
endmodule
369 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
370 17 unneback
parameter depth = 10;
371
input d;
372
output q, emptyflag;
373
input clk, rst;
374
reg [1:depth] dffs;
375
always @ (posedge clk or posedge rst)
376
if (rst)
377
    dffs <= {depth{1'b0}};
378
else
379
    dffs <= {d,dffs[1:depth-1]};
380
assign q = dffs[depth];
381
assign emptyflag = !(|dffs);
382
endmodule
383 6 unneback
//////////////////////////////////////////////////////////////////////
384
////                                                              ////
385 18 unneback
////  Logic functions                                             ////
386
////                                                              ////
387
////  Description                                                 ////
388
////  Logic functions such as multiplexers                        ////
389
////                                                              ////
390
////                                                              ////
391
////  To Do:                                                      ////
392
////   -                                                          ////
393
////                                                              ////
394
////  Author(s):                                                  ////
395
////      - Michael Unneback, unneback@opencores.org              ////
396
////        ORSoC AB                                              ////
397
////                                                              ////
398
//////////////////////////////////////////////////////////////////////
399
////                                                              ////
400
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
401
////                                                              ////
402
//// This source file may be used and distributed without         ////
403
//// restriction provided that this copyright statement is not    ////
404
//// removed from the file and that any derivative work contains  ////
405
//// the original copyright notice and the associated disclaimer. ////
406
////                                                              ////
407
//// This source file is free software; you can redistribute it   ////
408
//// and/or modify it under the terms of the GNU Lesser General   ////
409
//// Public License as published by the Free Software Foundation; ////
410
//// either version 2.1 of the License, or (at your option) any   ////
411
//// later version.                                               ////
412
////                                                              ////
413
//// This source is distributed in the hope that it will be       ////
414
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
415
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
416
//// PURPOSE.  See the GNU Lesser General Public License for more ////
417
//// details.                                                     ////
418
////                                                              ////
419
//// You should have received a copy of the GNU Lesser General    ////
420
//// Public License along with this source; if not, download it   ////
421
//// from http://www.opencores.org/lgpl.shtml                     ////
422
////                                                              ////
423
//////////////////////////////////////////////////////////////////////
424
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
425
parameter width = 32;
426
parameter nr_of_ports = 4;
427
input [width-1:0] a3, a2, a1, a0;
428
input [nr_of_ports-1:0] sel;
429 22 unneback
output [width-1:0] dout;
430 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
431 18 unneback
integer i;
432
// and
433
assign tmp[0] = {width{sel[0]}} & a0;
434
assign tmp[1] = {width{sel[1]}} & a1;
435
assign tmp[2] = {width{sel[2]}} & a2;
436
assign tmp[3] = {width{sel[3]}} & a3;
437
// or
438
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
439
endmodule
440
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
441
parameter width = 32;
442
parameter nr_of_ports = 5;
443
input [width-1:0] a4, a3, a2, a1, a0;
444
input [nr_of_ports-1:0] sel;
445 22 unneback
output [width-1:0] dout;
446 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
447 18 unneback
integer i;
448
// and
449
assign tmp[0] = {width{sel[0]}} & a0;
450
assign tmp[1] = {width{sel[1]}} & a1;
451
assign tmp[2] = {width{sel[2]}} & a2;
452
assign tmp[3] = {width{sel[3]}} & a3;
453
assign tmp[4] = {width{sel[4]}} & a4;
454
// or
455
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
456
endmodule
457
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
458
parameter width = 32;
459
parameter nr_of_ports = 6;
460
input [width-1:0] a5, a4, a3, a2, a1, a0;
461
input [nr_of_ports-1:0] sel;
462 22 unneback
output [width-1:0] dout;
463 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
464 18 unneback
integer i;
465
// and
466
assign tmp[0] = {width{sel[0]}} & a0;
467
assign tmp[1] = {width{sel[1]}} & a1;
468
assign tmp[2] = {width{sel[2]}} & a2;
469
assign tmp[3] = {width{sel[3]}} & a3;
470
assign tmp[4] = {width{sel[4]}} & a4;
471
assign tmp[5] = {width{sel[5]}} & a5;
472
// or
473
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
474
endmodule
475
//////////////////////////////////////////////////////////////////////
476
////                                                              ////
477 6 unneback
////  Versatile counter                                           ////
478
////                                                              ////
479
////  Description                                                 ////
480
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
481
////  counter                                                     ////
482
////                                                              ////
483
////  To Do:                                                      ////
484
////   - add LFSR with more taps                                  ////
485
////                                                              ////
486
////  Author(s):                                                  ////
487
////      - Michael Unneback, unneback@opencores.org              ////
488
////        ORSoC AB                                              ////
489
////                                                              ////
490
//////////////////////////////////////////////////////////////////////
491
////                                                              ////
492
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
493
////                                                              ////
494
//// This source file may be used and distributed without         ////
495
//// restriction provided that this copyright statement is not    ////
496
//// removed from the file and that any derivative work contains  ////
497
//// the original copyright notice and the associated disclaimer. ////
498
////                                                              ////
499
//// This source file is free software; you can redistribute it   ////
500
//// and/or modify it under the terms of the GNU Lesser General   ////
501
//// Public License as published by the Free Software Foundation; ////
502
//// either version 2.1 of the License, or (at your option) any   ////
503
//// later version.                                               ////
504
////                                                              ////
505
//// This source is distributed in the hope that it will be       ////
506
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
507
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
508
//// PURPOSE.  See the GNU Lesser General Public License for more ////
509
//// details.                                                     ////
510
////                                                              ////
511
//// You should have received a copy of the GNU Lesser General    ////
512
//// Public License along with this source; if not, download it   ////
513
//// from http://www.opencores.org/lgpl.shtml                     ////
514
////                                                              ////
515
//////////////////////////////////////////////////////////////////////
516
// binary counter
517 22 unneback
module vl_cnt_bin ( q, rst, clk);
518
   parameter length = 4;
519
   output [length:1] q;
520
   input rst;
521
   input clk;
522
   parameter clear_value = 0;
523
   parameter set_value = 1;
524
   parameter wrap_value = 0;
525
   parameter level1_value = 15;
526
   reg  [length:1] qi;
527
   wire [length:1] q_next;
528
   assign q_next = qi + {{length-1{1'b0}},1'b1};
529
   always @ (posedge clk or posedge rst)
530
     if (rst)
531
       qi <= {length{1'b0}};
532
     else
533
       qi <= q_next;
534
   assign q = qi;
535
endmodule
536
//////////////////////////////////////////////////////////////////////
537
////                                                              ////
538
////  Versatile counter                                           ////
539
////                                                              ////
540
////  Description                                                 ////
541
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
542
////  counter                                                     ////
543
////                                                              ////
544
////  To Do:                                                      ////
545
////   - add LFSR with more taps                                  ////
546
////                                                              ////
547
////  Author(s):                                                  ////
548
////      - Michael Unneback, unneback@opencores.org              ////
549
////        ORSoC AB                                              ////
550
////                                                              ////
551
//////////////////////////////////////////////////////////////////////
552
////                                                              ////
553
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
554
////                                                              ////
555
//// This source file may be used and distributed without         ////
556
//// restriction provided that this copyright statement is not    ////
557
//// removed from the file and that any derivative work contains  ////
558
//// the original copyright notice and the associated disclaimer. ////
559
////                                                              ////
560
//// This source file is free software; you can redistribute it   ////
561
//// and/or modify it under the terms of the GNU Lesser General   ////
562
//// Public License as published by the Free Software Foundation; ////
563
//// either version 2.1 of the License, or (at your option) any   ////
564
//// later version.                                               ////
565
////                                                              ////
566
//// This source is distributed in the hope that it will be       ////
567
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
568
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
569
//// PURPOSE.  See the GNU Lesser General Public License for more ////
570
//// details.                                                     ////
571
////                                                              ////
572
//// You should have received a copy of the GNU Lesser General    ////
573
//// Public License along with this source; if not, download it   ////
574
//// from http://www.opencores.org/lgpl.shtml                     ////
575
////                                                              ////
576
//////////////////////////////////////////////////////////////////////
577
// binary counter
578
module vl_cnt_bin_clear ( clear, q, rst, clk);
579
   parameter length = 4;
580
   input clear;
581
   output [length:1] q;
582
   input rst;
583
   input clk;
584
   parameter clear_value = 0;
585
   parameter set_value = 1;
586
   parameter wrap_value = 0;
587
   parameter level1_value = 15;
588
   reg  [length:1] qi;
589
   wire [length:1] q_next;
590
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
591
   always @ (posedge clk or posedge rst)
592
     if (rst)
593
       qi <= {length{1'b0}};
594
     else
595
       qi <= q_next;
596
   assign q = qi;
597
endmodule
598
//////////////////////////////////////////////////////////////////////
599
////                                                              ////
600
////  Versatile counter                                           ////
601
////                                                              ////
602
////  Description                                                 ////
603
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
604
////  counter                                                     ////
605
////                                                              ////
606
////  To Do:                                                      ////
607
////   - add LFSR with more taps                                  ////
608
////                                                              ////
609
////  Author(s):                                                  ////
610
////      - Michael Unneback, unneback@opencores.org              ////
611
////        ORSoC AB                                              ////
612
////                                                              ////
613
//////////////////////////////////////////////////////////////////////
614
////                                                              ////
615
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
616
////                                                              ////
617
//// This source file may be used and distributed without         ////
618
//// restriction provided that this copyright statement is not    ////
619
//// removed from the file and that any derivative work contains  ////
620
//// the original copyright notice and the associated disclaimer. ////
621
////                                                              ////
622
//// This source file is free software; you can redistribute it   ////
623
//// and/or modify it under the terms of the GNU Lesser General   ////
624
//// Public License as published by the Free Software Foundation; ////
625
//// either version 2.1 of the License, or (at your option) any   ////
626
//// later version.                                               ////
627
////                                                              ////
628
//// This source is distributed in the hope that it will be       ////
629
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
630
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
631
//// PURPOSE.  See the GNU Lesser General Public License for more ////
632
//// details.                                                     ////
633
////                                                              ////
634
//// You should have received a copy of the GNU Lesser General    ////
635
//// Public License along with this source; if not, download it   ////
636
//// from http://www.opencores.org/lgpl.shtml                     ////
637
////                                                              ////
638
//////////////////////////////////////////////////////////////////////
639
// binary counter
640 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
641 6 unneback
   parameter length = 4;
642
   input cke;
643
   output [length:1] q;
644
   input rst;
645
   input clk;
646
   parameter clear_value = 0;
647
   parameter set_value = 1;
648
   parameter wrap_value = 0;
649
   parameter level1_value = 15;
650
   reg  [length:1] qi;
651
   wire [length:1] q_next;
652
   assign q_next = qi + {{length-1{1'b0}},1'b1};
653
   always @ (posedge clk or posedge rst)
654
     if (rst)
655
       qi <= {length{1'b0}};
656
     else
657
     if (cke)
658
       qi <= q_next;
659
   assign q = qi;
660
endmodule
661
//////////////////////////////////////////////////////////////////////
662
////                                                              ////
663
////  Versatile counter                                           ////
664
////                                                              ////
665
////  Description                                                 ////
666
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
667
////  counter                                                     ////
668
////                                                              ////
669
////  To Do:                                                      ////
670
////   - add LFSR with more taps                                  ////
671
////                                                              ////
672
////  Author(s):                                                  ////
673
////      - Michael Unneback, unneback@opencores.org              ////
674
////        ORSoC AB                                              ////
675
////                                                              ////
676
//////////////////////////////////////////////////////////////////////
677
////                                                              ////
678
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
679
////                                                              ////
680
//// This source file may be used and distributed without         ////
681
//// restriction provided that this copyright statement is not    ////
682
//// removed from the file and that any derivative work contains  ////
683
//// the original copyright notice and the associated disclaimer. ////
684
////                                                              ////
685
//// This source file is free software; you can redistribute it   ////
686
//// and/or modify it under the terms of the GNU Lesser General   ////
687
//// Public License as published by the Free Software Foundation; ////
688
//// either version 2.1 of the License, or (at your option) any   ////
689
//// later version.                                               ////
690
////                                                              ////
691
//// This source is distributed in the hope that it will be       ////
692
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
693
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
694
//// PURPOSE.  See the GNU Lesser General Public License for more ////
695
//// details.                                                     ////
696
////                                                              ////
697
//// You should have received a copy of the GNU Lesser General    ////
698
//// Public License along with this source; if not, download it   ////
699
//// from http://www.opencores.org/lgpl.shtml                     ////
700
////                                                              ////
701
//////////////////////////////////////////////////////////////////////
702
// binary counter
703 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
704 6 unneback
   parameter length = 4;
705
   input clear;
706
   input cke;
707
   output [length:1] q;
708
   input rst;
709
   input clk;
710
   parameter clear_value = 0;
711
   parameter set_value = 1;
712
   parameter wrap_value = 0;
713
   parameter level1_value = 15;
714
   reg  [length:1] qi;
715
   wire [length:1] q_next;
716
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
717
   always @ (posedge clk or posedge rst)
718
     if (rst)
719
       qi <= {length{1'b0}};
720
     else
721
     if (cke)
722
       qi <= q_next;
723
   assign q = qi;
724
endmodule
725
//////////////////////////////////////////////////////////////////////
726
////                                                              ////
727
////  Versatile counter                                           ////
728
////                                                              ////
729
////  Description                                                 ////
730
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
731
////  counter                                                     ////
732
////                                                              ////
733
////  To Do:                                                      ////
734
////   - add LFSR with more taps                                  ////
735
////                                                              ////
736
////  Author(s):                                                  ////
737
////      - Michael Unneback, unneback@opencores.org              ////
738
////        ORSoC AB                                              ////
739
////                                                              ////
740
//////////////////////////////////////////////////////////////////////
741
////                                                              ////
742
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
743
////                                                              ////
744
//// This source file may be used and distributed without         ////
745
//// restriction provided that this copyright statement is not    ////
746
//// removed from the file and that any derivative work contains  ////
747
//// the original copyright notice and the associated disclaimer. ////
748
////                                                              ////
749
//// This source file is free software; you can redistribute it   ////
750
//// and/or modify it under the terms of the GNU Lesser General   ////
751
//// Public License as published by the Free Software Foundation; ////
752
//// either version 2.1 of the License, or (at your option) any   ////
753
//// later version.                                               ////
754
////                                                              ////
755
//// This source is distributed in the hope that it will be       ////
756
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
757
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
758
//// PURPOSE.  See the GNU Lesser General Public License for more ////
759
//// details.                                                     ////
760
////                                                              ////
761
//// You should have received a copy of the GNU Lesser General    ////
762
//// Public License along with this source; if not, download it   ////
763
//// from http://www.opencores.org/lgpl.shtml                     ////
764
////                                                              ////
765
//////////////////////////////////////////////////////////////////////
766
// binary counter
767 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
768
   parameter length = 4;
769
   input clear;
770
   input cke;
771
   output [length:1] q;
772
   output reg level1;
773
   output reg level2;
774
   input rst;
775
   input clk;
776
   parameter clear_value = 0;
777
   parameter set_value = 1;
778 30 unneback
   parameter wrap_value = 15;
779
   parameter level1_value = 8;
780
   parameter level2_value = 15;
781 29 unneback
   wire rew;
782 30 unneback
   assign rew = 1'b0;
783 29 unneback
   reg  [length:1] qi;
784
   wire [length:1] q_next;
785
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
786
   always @ (posedge clk or posedge rst)
787
     if (rst)
788
       qi <= {length{1'b0}};
789
     else
790
     if (cke)
791
       qi <= q_next;
792
   assign q = qi;
793
    always @ (posedge clk or posedge rst)
794
    if (rst)
795
        level1 <= 1'b0;
796
    else
797
    if (cke)
798
    if (clear)
799
        level1 <= 1'b0;
800
    else if (q_next == level1_value)
801
        level1 <= 1'b1;
802
    else if (qi == level1_value & rew)
803
        level1 <= 1'b0;
804
    always @ (posedge clk or posedge rst)
805
    if (rst)
806
        level2 <= 1'b0;
807
    else
808
    if (cke)
809
    if (clear)
810
        level2 <= 1'b0;
811
    else if (q_next == level2_value)
812
        level2 <= 1'b1;
813
    else if (qi == level2_value & rew)
814
        level2 <= 1'b0;
815
endmodule
816
//////////////////////////////////////////////////////////////////////
817
////                                                              ////
818
////  Versatile counter                                           ////
819
////                                                              ////
820
////  Description                                                 ////
821
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
822
////  counter                                                     ////
823
////                                                              ////
824
////  To Do:                                                      ////
825
////   - add LFSR with more taps                                  ////
826
////                                                              ////
827
////  Author(s):                                                  ////
828
////      - Michael Unneback, unneback@opencores.org              ////
829
////        ORSoC AB                                              ////
830
////                                                              ////
831
//////////////////////////////////////////////////////////////////////
832
////                                                              ////
833
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
834
////                                                              ////
835
//// This source file may be used and distributed without         ////
836
//// restriction provided that this copyright statement is not    ////
837
//// removed from the file and that any derivative work contains  ////
838
//// the original copyright notice and the associated disclaimer. ////
839
////                                                              ////
840
//// This source file is free software; you can redistribute it   ////
841
//// and/or modify it under the terms of the GNU Lesser General   ////
842
//// Public License as published by the Free Software Foundation; ////
843
//// either version 2.1 of the License, or (at your option) any   ////
844
//// later version.                                               ////
845
////                                                              ////
846
//// This source is distributed in the hope that it will be       ////
847
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
848
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
849
//// PURPOSE.  See the GNU Lesser General Public License for more ////
850
//// details.                                                     ////
851
////                                                              ////
852
//// You should have received a copy of the GNU Lesser General    ////
853
//// Public License along with this source; if not, download it   ////
854
//// from http://www.opencores.org/lgpl.shtml                     ////
855
////                                                              ////
856
//////////////////////////////////////////////////////////////////////
857
// binary counter
858 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
859 6 unneback
   parameter length = 4;
860
   input clear;
861
   input set;
862
   input cke;
863
   input rew;
864
   output [length:1] q;
865
   input rst;
866
   input clk;
867
   parameter clear_value = 0;
868
   parameter set_value = 1;
869
   parameter wrap_value = 0;
870
   parameter level1_value = 15;
871
   reg  [length:1] qi;
872
   wire  [length:1] q_next, q_next_fw, q_next_rew;
873
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
874
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
875
   assign q_next = rew ? q_next_rew : q_next_fw;
876
   always @ (posedge clk or posedge rst)
877
     if (rst)
878
       qi <= {length{1'b0}};
879
     else
880
     if (cke)
881
       qi <= q_next;
882
   assign q = qi;
883
endmodule
884
//////////////////////////////////////////////////////////////////////
885
////                                                              ////
886
////  Versatile counter                                           ////
887
////                                                              ////
888
////  Description                                                 ////
889
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
890
////  counter                                                     ////
891
////                                                              ////
892
////  To Do:                                                      ////
893
////   - add LFSR with more taps                                  ////
894
////                                                              ////
895
////  Author(s):                                                  ////
896
////      - Michael Unneback, unneback@opencores.org              ////
897
////        ORSoC AB                                              ////
898
////                                                              ////
899
//////////////////////////////////////////////////////////////////////
900
////                                                              ////
901
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
902
////                                                              ////
903
//// This source file may be used and distributed without         ////
904
//// restriction provided that this copyright statement is not    ////
905
//// removed from the file and that any derivative work contains  ////
906
//// the original copyright notice and the associated disclaimer. ////
907
////                                                              ////
908
//// This source file is free software; you can redistribute it   ////
909
//// and/or modify it under the terms of the GNU Lesser General   ////
910
//// Public License as published by the Free Software Foundation; ////
911
//// either version 2.1 of the License, or (at your option) any   ////
912
//// later version.                                               ////
913
////                                                              ////
914
//// This source is distributed in the hope that it will be       ////
915
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
916
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
917
//// PURPOSE.  See the GNU Lesser General Public License for more ////
918
//// details.                                                     ////
919
////                                                              ////
920
//// You should have received a copy of the GNU Lesser General    ////
921
//// Public License along with this source; if not, download it   ////
922
//// from http://www.opencores.org/lgpl.shtml                     ////
923
////                                                              ////
924
//////////////////////////////////////////////////////////////////////
925
// binary counter
926 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
927 6 unneback
   parameter length = 4;
928
   input cke;
929
   input rew;
930
   output reg level1;
931
   input rst;
932
   input clk;
933
   parameter clear_value = 0;
934
   parameter set_value = 1;
935
   parameter wrap_value = 1;
936
   parameter level1_value = 15;
937 29 unneback
   wire clear;
938 30 unneback
   assign clear = 1'b0;
939 6 unneback
   reg  [length:1] qi;
940
   wire  [length:1] q_next, q_next_fw, q_next_rew;
941
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
942
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
943
   assign q_next = rew ? q_next_rew : q_next_fw;
944
   always @ (posedge clk or posedge rst)
945
     if (rst)
946
       qi <= {length{1'b0}};
947
     else
948
     if (cke)
949
       qi <= q_next;
950
    always @ (posedge clk or posedge rst)
951
    if (rst)
952
        level1 <= 1'b0;
953
    else
954
    if (cke)
955 29 unneback
    if (clear)
956
        level1 <= 1'b0;
957
    else if (q_next == level1_value)
958 6 unneback
        level1 <= 1'b1;
959
    else if (qi == level1_value & rew)
960
        level1 <= 1'b0;
961
endmodule
962
//////////////////////////////////////////////////////////////////////
963
////                                                              ////
964
////  Versatile counter                                           ////
965
////                                                              ////
966
////  Description                                                 ////
967
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
968
////  counter                                                     ////
969
////                                                              ////
970
////  To Do:                                                      ////
971
////   - add LFSR with more taps                                  ////
972
////                                                              ////
973
////  Author(s):                                                  ////
974
////      - Michael Unneback, unneback@opencores.org              ////
975
////        ORSoC AB                                              ////
976
////                                                              ////
977
//////////////////////////////////////////////////////////////////////
978
////                                                              ////
979
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
980
////                                                              ////
981
//// This source file may be used and distributed without         ////
982
//// restriction provided that this copyright statement is not    ////
983
//// removed from the file and that any derivative work contains  ////
984
//// the original copyright notice and the associated disclaimer. ////
985
////                                                              ////
986
//// This source file is free software; you can redistribute it   ////
987
//// and/or modify it under the terms of the GNU Lesser General   ////
988
//// Public License as published by the Free Software Foundation; ////
989
//// either version 2.1 of the License, or (at your option) any   ////
990
//// later version.                                               ////
991
////                                                              ////
992
//// This source is distributed in the hope that it will be       ////
993
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
994
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
995
//// PURPOSE.  See the GNU Lesser General Public License for more ////
996
//// details.                                                     ////
997
////                                                              ////
998
//// You should have received a copy of the GNU Lesser General    ////
999
//// Public License along with this source; if not, download it   ////
1000
//// from http://www.opencores.org/lgpl.shtml                     ////
1001
////                                                              ////
1002
//////////////////////////////////////////////////////////////////////
1003 25 unneback
// binary counter
1004
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1005
   parameter length = 4;
1006
   input cke;
1007
   input rew;
1008
   output reg zq;
1009
   output reg level1;
1010
   input rst;
1011
   input clk;
1012
   parameter clear_value = 0;
1013
   parameter set_value = 1;
1014
   parameter wrap_value = 1;
1015
   parameter level1_value = 15;
1016 29 unneback
   wire clear;
1017 30 unneback
   assign clear = 1'b0;
1018 25 unneback
   reg  [length:1] qi;
1019
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1020
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1021
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1022
   assign q_next = rew ? q_next_rew : q_next_fw;
1023
   always @ (posedge clk or posedge rst)
1024
     if (rst)
1025
       qi <= {length{1'b0}};
1026
     else
1027
     if (cke)
1028
       qi <= q_next;
1029
   always @ (posedge clk or posedge rst)
1030
     if (rst)
1031
       zq <= 1'b1;
1032
     else
1033
     if (cke)
1034
       zq <= q_next == {length{1'b0}};
1035
    always @ (posedge clk or posedge rst)
1036
    if (rst)
1037
        level1 <= 1'b0;
1038
    else
1039
    if (cke)
1040 29 unneback
    if (clear)
1041
        level1 <= 1'b0;
1042
    else if (q_next == level1_value)
1043 25 unneback
        level1 <= 1'b1;
1044
    else if (qi == level1_value & rew)
1045
        level1 <= 1'b0;
1046
endmodule
1047
//////////////////////////////////////////////////////////////////////
1048
////                                                              ////
1049
////  Versatile counter                                           ////
1050
////                                                              ////
1051
////  Description                                                 ////
1052
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1053
////  counter                                                     ////
1054
////                                                              ////
1055
////  To Do:                                                      ////
1056
////   - add LFSR with more taps                                  ////
1057
////                                                              ////
1058
////  Author(s):                                                  ////
1059
////      - Michael Unneback, unneback@opencores.org              ////
1060
////        ORSoC AB                                              ////
1061
////                                                              ////
1062
//////////////////////////////////////////////////////////////////////
1063
////                                                              ////
1064
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1065
////                                                              ////
1066
//// This source file may be used and distributed without         ////
1067
//// restriction provided that this copyright statement is not    ////
1068
//// removed from the file and that any derivative work contains  ////
1069
//// the original copyright notice and the associated disclaimer. ////
1070
////                                                              ////
1071
//// This source file is free software; you can redistribute it   ////
1072
//// and/or modify it under the terms of the GNU Lesser General   ////
1073
//// Public License as published by the Free Software Foundation; ////
1074
//// either version 2.1 of the License, or (at your option) any   ////
1075
//// later version.                                               ////
1076
////                                                              ////
1077
//// This source is distributed in the hope that it will be       ////
1078
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1079
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1080
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1081
//// details.                                                     ////
1082
////                                                              ////
1083
//// You should have received a copy of the GNU Lesser General    ////
1084
//// Public License along with this source; if not, download it   ////
1085
//// from http://www.opencores.org/lgpl.shtml                     ////
1086
////                                                              ////
1087
//////////////////////////////////////////////////////////////////////
1088
// binary counter
1089
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1090
   parameter length = 4;
1091
   input cke;
1092
   input rew;
1093
   output [length:1] q;
1094
   output reg zq;
1095
   output reg level1;
1096
   input rst;
1097
   input clk;
1098
   parameter clear_value = 0;
1099
   parameter set_value = 1;
1100
   parameter wrap_value = 1;
1101
   parameter level1_value = 15;
1102 29 unneback
   wire clear;
1103 30 unneback
   assign clear = 1'b0;
1104 25 unneback
   reg  [length:1] qi;
1105
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1106
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1107
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1108
   assign q_next = rew ? q_next_rew : q_next_fw;
1109
   always @ (posedge clk or posedge rst)
1110
     if (rst)
1111
       qi <= {length{1'b0}};
1112
     else
1113
     if (cke)
1114
       qi <= q_next;
1115
   assign q = qi;
1116
   always @ (posedge clk or posedge rst)
1117
     if (rst)
1118
       zq <= 1'b1;
1119
     else
1120
     if (cke)
1121
       zq <= q_next == {length{1'b0}};
1122
    always @ (posedge clk or posedge rst)
1123
    if (rst)
1124
        level1 <= 1'b0;
1125
    else
1126
    if (cke)
1127 29 unneback
    if (clear)
1128
        level1 <= 1'b0;
1129
    else if (q_next == level1_value)
1130 25 unneback
        level1 <= 1'b1;
1131
    else if (qi == level1_value & rew)
1132
        level1 <= 1'b0;
1133
endmodule
1134
//////////////////////////////////////////////////////////////////////
1135
////                                                              ////
1136
////  Versatile counter                                           ////
1137
////                                                              ////
1138
////  Description                                                 ////
1139
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1140
////  counter                                                     ////
1141
////                                                              ////
1142
////  To Do:                                                      ////
1143
////   - add LFSR with more taps                                  ////
1144
////                                                              ////
1145
////  Author(s):                                                  ////
1146
////      - Michael Unneback, unneback@opencores.org              ////
1147
////        ORSoC AB                                              ////
1148
////                                                              ////
1149
//////////////////////////////////////////////////////////////////////
1150
////                                                              ////
1151
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1152
////                                                              ////
1153
//// This source file may be used and distributed without         ////
1154
//// restriction provided that this copyright statement is not    ////
1155
//// removed from the file and that any derivative work contains  ////
1156
//// the original copyright notice and the associated disclaimer. ////
1157
////                                                              ////
1158
//// This source file is free software; you can redistribute it   ////
1159
//// and/or modify it under the terms of the GNU Lesser General   ////
1160
//// Public License as published by the Free Software Foundation; ////
1161
//// either version 2.1 of the License, or (at your option) any   ////
1162
//// later version.                                               ////
1163
////                                                              ////
1164
//// This source is distributed in the hope that it will be       ////
1165
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1166
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1167
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1168
//// details.                                                     ////
1169
////                                                              ////
1170
//// You should have received a copy of the GNU Lesser General    ////
1171
//// Public License along with this source; if not, download it   ////
1172
//// from http://www.opencores.org/lgpl.shtml                     ////
1173
////                                                              ////
1174
//////////////////////////////////////////////////////////////////////
1175 6 unneback
// LFSR counter
1176 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1177 6 unneback
   parameter length = 4;
1178
   output reg zq;
1179
   input rst;
1180
   input clk;
1181
   parameter clear_value = 0;
1182
   parameter set_value = 1;
1183
   parameter wrap_value = 8;
1184
   parameter level1_value = 15;
1185
   reg  [length:1] qi;
1186
   reg lfsr_fb;
1187
   wire [length:1] q_next;
1188
   reg [32:1] polynom;
1189
   integer i;
1190
   always @ (qi)
1191
   begin
1192
        case (length)
1193
         2: polynom = 32'b11;                               // 0x3
1194
         3: polynom = 32'b110;                              // 0x6
1195
         4: polynom = 32'b1100;                             // 0xC
1196
         5: polynom = 32'b10100;                            // 0x14
1197
         6: polynom = 32'b110000;                           // 0x30
1198
         7: polynom = 32'b1100000;                          // 0x60
1199
         8: polynom = 32'b10111000;                         // 0xb8
1200
         9: polynom = 32'b100010000;                        // 0x110
1201
        10: polynom = 32'b1001000000;                       // 0x240
1202
        11: polynom = 32'b10100000000;                      // 0x500
1203
        12: polynom = 32'b100000101001;                     // 0x829
1204
        13: polynom = 32'b1000000001100;                    // 0x100C
1205
        14: polynom = 32'b10000000010101;                   // 0x2015
1206
        15: polynom = 32'b110000000000000;                  // 0x6000
1207
        16: polynom = 32'b1101000000001000;                 // 0xD008
1208
        17: polynom = 32'b10010000000000000;                // 0x12000
1209
        18: polynom = 32'b100000010000000000;               // 0x20400
1210
        19: polynom = 32'b1000000000000100011;              // 0x40023
1211
        20: polynom = 32'b10000010000000000000;             // 0x82000
1212
        21: polynom = 32'b101000000000000000000;            // 0x140000
1213
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1214
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1215
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1216
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1217
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1218
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1219
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1220
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1221
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1222
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1223
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1224
        default: polynom = 32'b0;
1225
        endcase
1226
        lfsr_fb = qi[length];
1227
        for (i=length-1; i>=1; i=i-1) begin
1228
            if (polynom[i])
1229
                lfsr_fb = lfsr_fb  ~^ qi[i];
1230
        end
1231
    end
1232
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1233
   always @ (posedge clk or posedge rst)
1234
     if (rst)
1235
       qi <= {length{1'b0}};
1236
     else
1237
       qi <= q_next;
1238
   always @ (posedge clk or posedge rst)
1239
     if (rst)
1240
       zq <= 1'b1;
1241
     else
1242
       zq <= q_next == {length{1'b0}};
1243
endmodule
1244
//////////////////////////////////////////////////////////////////////
1245
////                                                              ////
1246
////  Versatile counter                                           ////
1247
////                                                              ////
1248
////  Description                                                 ////
1249
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1250
////  counter                                                     ////
1251
////                                                              ////
1252
////  To Do:                                                      ////
1253
////   - add LFSR with more taps                                  ////
1254
////                                                              ////
1255
////  Author(s):                                                  ////
1256
////      - Michael Unneback, unneback@opencores.org              ////
1257
////        ORSoC AB                                              ////
1258
////                                                              ////
1259
//////////////////////////////////////////////////////////////////////
1260
////                                                              ////
1261
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1262
////                                                              ////
1263
//// This source file may be used and distributed without         ////
1264
//// restriction provided that this copyright statement is not    ////
1265
//// removed from the file and that any derivative work contains  ////
1266
//// the original copyright notice and the associated disclaimer. ////
1267
////                                                              ////
1268
//// This source file is free software; you can redistribute it   ////
1269
//// and/or modify it under the terms of the GNU Lesser General   ////
1270
//// Public License as published by the Free Software Foundation; ////
1271
//// either version 2.1 of the License, or (at your option) any   ////
1272
//// later version.                                               ////
1273
////                                                              ////
1274
//// This source is distributed in the hope that it will be       ////
1275
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1276
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1277
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1278
//// details.                                                     ////
1279
////                                                              ////
1280
//// You should have received a copy of the GNU Lesser General    ////
1281
//// Public License along with this source; if not, download it   ////
1282
//// from http://www.opencores.org/lgpl.shtml                     ////
1283
////                                                              ////
1284
//////////////////////////////////////////////////////////////////////
1285
// LFSR counter
1286 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1287 6 unneback
   parameter length = 4;
1288
   input cke;
1289
   output reg zq;
1290
   input rst;
1291
   input clk;
1292
   parameter clear_value = 0;
1293
   parameter set_value = 1;
1294
   parameter wrap_value = 8;
1295
   parameter level1_value = 15;
1296
   reg  [length:1] qi;
1297
   reg lfsr_fb;
1298
   wire [length:1] q_next;
1299
   reg [32:1] polynom;
1300
   integer i;
1301
   always @ (qi)
1302
   begin
1303
        case (length)
1304
         2: polynom = 32'b11;                               // 0x3
1305
         3: polynom = 32'b110;                              // 0x6
1306
         4: polynom = 32'b1100;                             // 0xC
1307
         5: polynom = 32'b10100;                            // 0x14
1308
         6: polynom = 32'b110000;                           // 0x30
1309
         7: polynom = 32'b1100000;                          // 0x60
1310
         8: polynom = 32'b10111000;                         // 0xb8
1311
         9: polynom = 32'b100010000;                        // 0x110
1312
        10: polynom = 32'b1001000000;                       // 0x240
1313
        11: polynom = 32'b10100000000;                      // 0x500
1314
        12: polynom = 32'b100000101001;                     // 0x829
1315
        13: polynom = 32'b1000000001100;                    // 0x100C
1316
        14: polynom = 32'b10000000010101;                   // 0x2015
1317
        15: polynom = 32'b110000000000000;                  // 0x6000
1318
        16: polynom = 32'b1101000000001000;                 // 0xD008
1319
        17: polynom = 32'b10010000000000000;                // 0x12000
1320
        18: polynom = 32'b100000010000000000;               // 0x20400
1321
        19: polynom = 32'b1000000000000100011;              // 0x40023
1322
        20: polynom = 32'b10000010000000000000;             // 0x82000
1323
        21: polynom = 32'b101000000000000000000;            // 0x140000
1324
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1325
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1326
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1327
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1328
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1329
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1330
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1331
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1332
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1333
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1334
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1335
        default: polynom = 32'b0;
1336
        endcase
1337
        lfsr_fb = qi[length];
1338
        for (i=length-1; i>=1; i=i-1) begin
1339
            if (polynom[i])
1340
                lfsr_fb = lfsr_fb  ~^ qi[i];
1341
        end
1342
    end
1343
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1344
   always @ (posedge clk or posedge rst)
1345
     if (rst)
1346
       qi <= {length{1'b0}};
1347
     else
1348
     if (cke)
1349
       qi <= q_next;
1350
   always @ (posedge clk or posedge rst)
1351
     if (rst)
1352
       zq <= 1'b1;
1353
     else
1354
     if (cke)
1355
       zq <= q_next == {length{1'b0}};
1356
endmodule
1357
//////////////////////////////////////////////////////////////////////
1358
////                                                              ////
1359
////  Versatile counter                                           ////
1360
////                                                              ////
1361
////  Description                                                 ////
1362
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1363
////  counter                                                     ////
1364
////                                                              ////
1365
////  To Do:                                                      ////
1366
////   - add LFSR with more taps                                  ////
1367
////                                                              ////
1368
////  Author(s):                                                  ////
1369
////      - Michael Unneback, unneback@opencores.org              ////
1370
////        ORSoC AB                                              ////
1371
////                                                              ////
1372
//////////////////////////////////////////////////////////////////////
1373
////                                                              ////
1374
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1375
////                                                              ////
1376
//// This source file may be used and distributed without         ////
1377
//// restriction provided that this copyright statement is not    ////
1378
//// removed from the file and that any derivative work contains  ////
1379
//// the original copyright notice and the associated disclaimer. ////
1380
////                                                              ////
1381
//// This source file is free software; you can redistribute it   ////
1382
//// and/or modify it under the terms of the GNU Lesser General   ////
1383
//// Public License as published by the Free Software Foundation; ////
1384
//// either version 2.1 of the License, or (at your option) any   ////
1385
//// later version.                                               ////
1386
////                                                              ////
1387
//// This source is distributed in the hope that it will be       ////
1388
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1389
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1390
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1391
//// details.                                                     ////
1392
////                                                              ////
1393
//// You should have received a copy of the GNU Lesser General    ////
1394
//// Public License along with this source; if not, download it   ////
1395
//// from http://www.opencores.org/lgpl.shtml                     ////
1396
////                                                              ////
1397
//////////////////////////////////////////////////////////////////////
1398
// LFSR counter
1399 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1400
   parameter length = 4;
1401
   input cke;
1402
   output [length:1] q;
1403
   input rst;
1404
   input clk;
1405
   parameter clear_value = 0;
1406
   parameter set_value = 1;
1407
   parameter wrap_value = 8;
1408
   parameter level1_value = 15;
1409
   reg  [length:1] qi;
1410
   reg lfsr_fb;
1411
   wire [length:1] q_next;
1412
   reg [32:1] polynom;
1413
   integer i;
1414
   always @ (qi)
1415
   begin
1416
        case (length)
1417
         2: polynom = 32'b11;                               // 0x3
1418
         3: polynom = 32'b110;                              // 0x6
1419
         4: polynom = 32'b1100;                             // 0xC
1420
         5: polynom = 32'b10100;                            // 0x14
1421
         6: polynom = 32'b110000;                           // 0x30
1422
         7: polynom = 32'b1100000;                          // 0x60
1423
         8: polynom = 32'b10111000;                         // 0xb8
1424
         9: polynom = 32'b100010000;                        // 0x110
1425
        10: polynom = 32'b1001000000;                       // 0x240
1426
        11: polynom = 32'b10100000000;                      // 0x500
1427
        12: polynom = 32'b100000101001;                     // 0x829
1428
        13: polynom = 32'b1000000001100;                    // 0x100C
1429
        14: polynom = 32'b10000000010101;                   // 0x2015
1430
        15: polynom = 32'b110000000000000;                  // 0x6000
1431
        16: polynom = 32'b1101000000001000;                 // 0xD008
1432
        17: polynom = 32'b10010000000000000;                // 0x12000
1433
        18: polynom = 32'b100000010000000000;               // 0x20400
1434
        19: polynom = 32'b1000000000000100011;              // 0x40023
1435
        20: polynom = 32'b10000010000000000000;             // 0x82000
1436
        21: polynom = 32'b101000000000000000000;            // 0x140000
1437
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1438
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1439
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1440
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1441
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1442
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1443
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1444
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1445
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1446
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1447
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1448
        default: polynom = 32'b0;
1449
        endcase
1450
        lfsr_fb = qi[length];
1451
        for (i=length-1; i>=1; i=i-1) begin
1452
            if (polynom[i])
1453
                lfsr_fb = lfsr_fb  ~^ qi[i];
1454
        end
1455
    end
1456
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1457
   always @ (posedge clk or posedge rst)
1458
     if (rst)
1459
       qi <= {length{1'b0}};
1460
     else
1461
     if (cke)
1462
       qi <= q_next;
1463
   assign q = qi;
1464
endmodule
1465
//////////////////////////////////////////////////////////////////////
1466
////                                                              ////
1467
////  Versatile counter                                           ////
1468
////                                                              ////
1469
////  Description                                                 ////
1470
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1471
////  counter                                                     ////
1472
////                                                              ////
1473
////  To Do:                                                      ////
1474
////   - add LFSR with more taps                                  ////
1475
////                                                              ////
1476
////  Author(s):                                                  ////
1477
////      - Michael Unneback, unneback@opencores.org              ////
1478
////        ORSoC AB                                              ////
1479
////                                                              ////
1480
//////////////////////////////////////////////////////////////////////
1481
////                                                              ////
1482
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1483
////                                                              ////
1484
//// This source file may be used and distributed without         ////
1485
//// restriction provided that this copyright statement is not    ////
1486
//// removed from the file and that any derivative work contains  ////
1487
//// the original copyright notice and the associated disclaimer. ////
1488
////                                                              ////
1489
//// This source file is free software; you can redistribute it   ////
1490
//// and/or modify it under the terms of the GNU Lesser General   ////
1491
//// Public License as published by the Free Software Foundation; ////
1492
//// either version 2.1 of the License, or (at your option) any   ////
1493
//// later version.                                               ////
1494
////                                                              ////
1495
//// This source is distributed in the hope that it will be       ////
1496
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1497
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1498
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1499
//// details.                                                     ////
1500
////                                                              ////
1501
//// You should have received a copy of the GNU Lesser General    ////
1502
//// Public License along with this source; if not, download it   ////
1503
//// from http://www.opencores.org/lgpl.shtml                     ////
1504
////                                                              ////
1505
//////////////////////////////////////////////////////////////////////
1506
// LFSR counter
1507
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1508
   parameter length = 4;
1509
   input clear;
1510
   input cke;
1511
   output [length:1] q;
1512
   input rst;
1513
   input clk;
1514
   parameter clear_value = 0;
1515
   parameter set_value = 1;
1516
   parameter wrap_value = 8;
1517
   parameter level1_value = 15;
1518
   reg  [length:1] qi;
1519
   reg lfsr_fb;
1520
   wire [length:1] q_next;
1521
   reg [32:1] polynom;
1522
   integer i;
1523
   always @ (qi)
1524
   begin
1525
        case (length)
1526
         2: polynom = 32'b11;                               // 0x3
1527
         3: polynom = 32'b110;                              // 0x6
1528
         4: polynom = 32'b1100;                             // 0xC
1529
         5: polynom = 32'b10100;                            // 0x14
1530
         6: polynom = 32'b110000;                           // 0x30
1531
         7: polynom = 32'b1100000;                          // 0x60
1532
         8: polynom = 32'b10111000;                         // 0xb8
1533
         9: polynom = 32'b100010000;                        // 0x110
1534
        10: polynom = 32'b1001000000;                       // 0x240
1535
        11: polynom = 32'b10100000000;                      // 0x500
1536
        12: polynom = 32'b100000101001;                     // 0x829
1537
        13: polynom = 32'b1000000001100;                    // 0x100C
1538
        14: polynom = 32'b10000000010101;                   // 0x2015
1539
        15: polynom = 32'b110000000000000;                  // 0x6000
1540
        16: polynom = 32'b1101000000001000;                 // 0xD008
1541
        17: polynom = 32'b10010000000000000;                // 0x12000
1542
        18: polynom = 32'b100000010000000000;               // 0x20400
1543
        19: polynom = 32'b1000000000000100011;              // 0x40023
1544
        20: polynom = 32'b10000010000000000000;             // 0x82000
1545
        21: polynom = 32'b101000000000000000000;            // 0x140000
1546
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1547
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1548
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1549
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1550
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1551
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1552
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1553
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1554
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1555
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1556
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1557
        default: polynom = 32'b0;
1558
        endcase
1559
        lfsr_fb = qi[length];
1560
        for (i=length-1; i>=1; i=i-1) begin
1561
            if (polynom[i])
1562
                lfsr_fb = lfsr_fb  ~^ qi[i];
1563
        end
1564
    end
1565
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1566
   always @ (posedge clk or posedge rst)
1567
     if (rst)
1568
       qi <= {length{1'b0}};
1569
     else
1570
     if (cke)
1571
       qi <= q_next;
1572
   assign q = qi;
1573
endmodule
1574
//////////////////////////////////////////////////////////////////////
1575
////                                                              ////
1576
////  Versatile counter                                           ////
1577
////                                                              ////
1578
////  Description                                                 ////
1579
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1580
////  counter                                                     ////
1581
////                                                              ////
1582
////  To Do:                                                      ////
1583
////   - add LFSR with more taps                                  ////
1584
////                                                              ////
1585
////  Author(s):                                                  ////
1586
////      - Michael Unneback, unneback@opencores.org              ////
1587
////        ORSoC AB                                              ////
1588
////                                                              ////
1589
//////////////////////////////////////////////////////////////////////
1590
////                                                              ////
1591
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1592
////                                                              ////
1593
//// This source file may be used and distributed without         ////
1594
//// restriction provided that this copyright statement is not    ////
1595
//// removed from the file and that any derivative work contains  ////
1596
//// the original copyright notice and the associated disclaimer. ////
1597
////                                                              ////
1598
//// This source file is free software; you can redistribute it   ////
1599
//// and/or modify it under the terms of the GNU Lesser General   ////
1600
//// Public License as published by the Free Software Foundation; ////
1601
//// either version 2.1 of the License, or (at your option) any   ////
1602
//// later version.                                               ////
1603
////                                                              ////
1604
//// This source is distributed in the hope that it will be       ////
1605
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1606
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1607
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1608
//// details.                                                     ////
1609
////                                                              ////
1610
//// You should have received a copy of the GNU Lesser General    ////
1611
//// Public License along with this source; if not, download it   ////
1612
//// from http://www.opencores.org/lgpl.shtml                     ////
1613
////                                                              ////
1614
//////////////////////////////////////////////////////////////////////
1615
// LFSR counter
1616 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1617
   parameter length = 4;
1618
   input cke;
1619
   output [length:1] q;
1620
   output reg zq;
1621
   input rst;
1622
   input clk;
1623
   parameter clear_value = 0;
1624
   parameter set_value = 1;
1625
   parameter wrap_value = 8;
1626
   parameter level1_value = 15;
1627
   reg  [length:1] qi;
1628
   reg lfsr_fb;
1629
   wire [length:1] q_next;
1630
   reg [32:1] polynom;
1631
   integer i;
1632
   always @ (qi)
1633
   begin
1634
        case (length)
1635
         2: polynom = 32'b11;                               // 0x3
1636
         3: polynom = 32'b110;                              // 0x6
1637
         4: polynom = 32'b1100;                             // 0xC
1638
         5: polynom = 32'b10100;                            // 0x14
1639
         6: polynom = 32'b110000;                           // 0x30
1640
         7: polynom = 32'b1100000;                          // 0x60
1641
         8: polynom = 32'b10111000;                         // 0xb8
1642
         9: polynom = 32'b100010000;                        // 0x110
1643
        10: polynom = 32'b1001000000;                       // 0x240
1644
        11: polynom = 32'b10100000000;                      // 0x500
1645
        12: polynom = 32'b100000101001;                     // 0x829
1646
        13: polynom = 32'b1000000001100;                    // 0x100C
1647
        14: polynom = 32'b10000000010101;                   // 0x2015
1648
        15: polynom = 32'b110000000000000;                  // 0x6000
1649
        16: polynom = 32'b1101000000001000;                 // 0xD008
1650
        17: polynom = 32'b10010000000000000;                // 0x12000
1651
        18: polynom = 32'b100000010000000000;               // 0x20400
1652
        19: polynom = 32'b1000000000000100011;              // 0x40023
1653
        20: polynom = 32'b10000010000000000000;             // 0x82000
1654
        21: polynom = 32'b101000000000000000000;            // 0x140000
1655
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1656
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1657
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1658
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1659
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1660
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1661
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1662
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1663
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1664
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1665
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1666
        default: polynom = 32'b0;
1667
        endcase
1668
        lfsr_fb = qi[length];
1669
        for (i=length-1; i>=1; i=i-1) begin
1670
            if (polynom[i])
1671
                lfsr_fb = lfsr_fb  ~^ qi[i];
1672
        end
1673
    end
1674
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1675
   always @ (posedge clk or posedge rst)
1676
     if (rst)
1677
       qi <= {length{1'b0}};
1678
     else
1679
     if (cke)
1680
       qi <= q_next;
1681
   assign q = qi;
1682
   always @ (posedge clk or posedge rst)
1683
     if (rst)
1684
       zq <= 1'b1;
1685
     else
1686
     if (cke)
1687
       zq <= q_next == {length{1'b0}};
1688
endmodule
1689
//////////////////////////////////////////////////////////////////////
1690
////                                                              ////
1691
////  Versatile counter                                           ////
1692
////                                                              ////
1693
////  Description                                                 ////
1694
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1695
////  counter                                                     ////
1696
////                                                              ////
1697
////  To Do:                                                      ////
1698
////   - add LFSR with more taps                                  ////
1699
////                                                              ////
1700
////  Author(s):                                                  ////
1701
////      - Michael Unneback, unneback@opencores.org              ////
1702
////        ORSoC AB                                              ////
1703
////                                                              ////
1704
//////////////////////////////////////////////////////////////////////
1705
////                                                              ////
1706
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1707
////                                                              ////
1708
//// This source file may be used and distributed without         ////
1709
//// restriction provided that this copyright statement is not    ////
1710
//// removed from the file and that any derivative work contains  ////
1711
//// the original copyright notice and the associated disclaimer. ////
1712
////                                                              ////
1713
//// This source file is free software; you can redistribute it   ////
1714
//// and/or modify it under the terms of the GNU Lesser General   ////
1715
//// Public License as published by the Free Software Foundation; ////
1716
//// either version 2.1 of the License, or (at your option) any   ////
1717
//// later version.                                               ////
1718
////                                                              ////
1719
//// This source is distributed in the hope that it will be       ////
1720
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1721
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1722
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1723
//// details.                                                     ////
1724
////                                                              ////
1725
//// You should have received a copy of the GNU Lesser General    ////
1726
//// Public License along with this source; if not, download it   ////
1727
//// from http://www.opencores.org/lgpl.shtml                     ////
1728
////                                                              ////
1729
//////////////////////////////////////////////////////////////////////
1730
// LFSR counter
1731 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1732 6 unneback
   parameter length = 4;
1733
   input cke;
1734
   input rew;
1735
   output reg level1;
1736
   input rst;
1737
   input clk;
1738
   parameter clear_value = 0;
1739
   parameter set_value = 1;
1740
   parameter wrap_value = 8;
1741
   parameter level1_value = 15;
1742 29 unneback
   wire clear;
1743 30 unneback
   assign clear = 1'b0;
1744 6 unneback
   reg  [length:1] qi;
1745
   reg lfsr_fb, lfsr_fb_rew;
1746
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1747
   reg [32:1] polynom_rew;
1748
   integer j;
1749
   reg [32:1] polynom;
1750
   integer i;
1751
   always @ (qi)
1752
   begin
1753
        case (length)
1754
         2: polynom = 32'b11;                               // 0x3
1755
         3: polynom = 32'b110;                              // 0x6
1756
         4: polynom = 32'b1100;                             // 0xC
1757
         5: polynom = 32'b10100;                            // 0x14
1758
         6: polynom = 32'b110000;                           // 0x30
1759
         7: polynom = 32'b1100000;                          // 0x60
1760
         8: polynom = 32'b10111000;                         // 0xb8
1761
         9: polynom = 32'b100010000;                        // 0x110
1762
        10: polynom = 32'b1001000000;                       // 0x240
1763
        11: polynom = 32'b10100000000;                      // 0x500
1764
        12: polynom = 32'b100000101001;                     // 0x829
1765
        13: polynom = 32'b1000000001100;                    // 0x100C
1766
        14: polynom = 32'b10000000010101;                   // 0x2015
1767
        15: polynom = 32'b110000000000000;                  // 0x6000
1768
        16: polynom = 32'b1101000000001000;                 // 0xD008
1769
        17: polynom = 32'b10010000000000000;                // 0x12000
1770
        18: polynom = 32'b100000010000000000;               // 0x20400
1771
        19: polynom = 32'b1000000000000100011;              // 0x40023
1772
        20: polynom = 32'b10000010000000000000;             // 0x82000
1773
        21: polynom = 32'b101000000000000000000;            // 0x140000
1774
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1775
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1776
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1777
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1778
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1779
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1780
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1781
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1782
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1783
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1784
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1785
        default: polynom = 32'b0;
1786
        endcase
1787
        lfsr_fb = qi[length];
1788
        for (i=length-1; i>=1; i=i-1) begin
1789
            if (polynom[i])
1790
                lfsr_fb = lfsr_fb  ~^ qi[i];
1791
        end
1792
    end
1793
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1794
   always @ (qi)
1795
   begin
1796
        case (length)
1797
         2: polynom_rew = 32'b11;
1798
         3: polynom_rew = 32'b110;
1799
         4: polynom_rew = 32'b1100;
1800
         5: polynom_rew = 32'b10100;
1801
         6: polynom_rew = 32'b110000;
1802
         7: polynom_rew = 32'b1100000;
1803
         8: polynom_rew = 32'b10111000;
1804
         9: polynom_rew = 32'b100010000;
1805
        10: polynom_rew = 32'b1001000000;
1806
        11: polynom_rew = 32'b10100000000;
1807
        12: polynom_rew = 32'b100000101001;
1808
        13: polynom_rew = 32'b1000000001100;
1809
        14: polynom_rew = 32'b10000000010101;
1810
        15: polynom_rew = 32'b110000000000000;
1811
        16: polynom_rew = 32'b1101000000001000;
1812
        17: polynom_rew = 32'b10010000000000000;
1813
        18: polynom_rew = 32'b100000010000000000;
1814
        19: polynom_rew = 32'b1000000000000100011;
1815
        20: polynom_rew = 32'b10000010000000000000;
1816
        21: polynom_rew = 32'b101000000000000000000;
1817
        22: polynom_rew = 32'b1100000000000000000000;
1818
        23: polynom_rew = 32'b10000100000000000000000;
1819
        24: polynom_rew = 32'b111000010000000000000000;
1820
        25: polynom_rew = 32'b1001000000000000000000000;
1821
        26: polynom_rew = 32'b10000000000000000000100011;
1822
        27: polynom_rew = 32'b100000000000000000000010011;
1823
        28: polynom_rew = 32'b1100100000000000000000000000;
1824
        29: polynom_rew = 32'b10100000000000000000000000000;
1825
        30: polynom_rew = 32'b100000000000000000000000101001;
1826
        31: polynom_rew = 32'b1001000000000000000000000000000;
1827
        32: polynom_rew = 32'b10000000001000000000000000000011;
1828
        default: polynom_rew = 32'b0;
1829
        endcase
1830
        // rotate left
1831
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1832
        lfsr_fb_rew = qi[length];
1833
        for (i=length-1; i>=1; i=i-1) begin
1834
            if (polynom_rew[i])
1835
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1836
        end
1837
    end
1838
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1839
   assign q_next = rew ? q_next_rew : q_next_fw;
1840
   always @ (posedge clk or posedge rst)
1841
     if (rst)
1842
       qi <= {length{1'b0}};
1843
     else
1844
     if (cke)
1845
       qi <= q_next;
1846
    always @ (posedge clk or posedge rst)
1847
    if (rst)
1848
        level1 <= 1'b0;
1849
    else
1850
    if (cke)
1851 29 unneback
    if (clear)
1852
        level1 <= 1'b0;
1853
    else if (q_next == level1_value)
1854 6 unneback
        level1 <= 1'b1;
1855
    else if (qi == level1_value & rew)
1856
        level1 <= 1'b0;
1857
endmodule
1858
//////////////////////////////////////////////////////////////////////
1859
////                                                              ////
1860
////  Versatile counter                                           ////
1861
////                                                              ////
1862
////  Description                                                 ////
1863
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1864
////  counter                                                     ////
1865
////                                                              ////
1866
////  To Do:                                                      ////
1867
////   - add LFSR with more taps                                  ////
1868
////                                                              ////
1869
////  Author(s):                                                  ////
1870
////      - Michael Unneback, unneback@opencores.org              ////
1871
////        ORSoC AB                                              ////
1872
////                                                              ////
1873
//////////////////////////////////////////////////////////////////////
1874
////                                                              ////
1875
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1876
////                                                              ////
1877
//// This source file may be used and distributed without         ////
1878
//// restriction provided that this copyright statement is not    ////
1879
//// removed from the file and that any derivative work contains  ////
1880
//// the original copyright notice and the associated disclaimer. ////
1881
////                                                              ////
1882
//// This source file is free software; you can redistribute it   ////
1883
//// and/or modify it under the terms of the GNU Lesser General   ////
1884
//// Public License as published by the Free Software Foundation; ////
1885
//// either version 2.1 of the License, or (at your option) any   ////
1886
//// later version.                                               ////
1887
////                                                              ////
1888
//// This source is distributed in the hope that it will be       ////
1889
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1890
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1891
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1892
//// details.                                                     ////
1893
////                                                              ////
1894
//// You should have received a copy of the GNU Lesser General    ////
1895
//// Public License along with this source; if not, download it   ////
1896
//// from http://www.opencores.org/lgpl.shtml                     ////
1897
////                                                              ////
1898
//////////////////////////////////////////////////////////////////////
1899
// GRAY counter
1900 18 unneback
module vl_cnt_gray ( q, rst, clk);
1901 6 unneback
   parameter length = 4;
1902
   output reg [length:1] q;
1903
   input rst;
1904
   input clk;
1905
   parameter clear_value = 0;
1906
   parameter set_value = 1;
1907
   parameter wrap_value = 8;
1908
   parameter level1_value = 15;
1909
   reg  [length:1] qi;
1910
   wire [length:1] q_next;
1911
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1912
   always @ (posedge clk or posedge rst)
1913
     if (rst)
1914
       qi <= {length{1'b0}};
1915
     else
1916
       qi <= q_next;
1917
   always @ (posedge clk or posedge rst)
1918
     if (rst)
1919
       q <= {length{1'b0}};
1920
     else
1921
         q <= (q_next>>1) ^ q_next;
1922
endmodule
1923
//////////////////////////////////////////////////////////////////////
1924
////                                                              ////
1925
////  Versatile counter                                           ////
1926
////                                                              ////
1927
////  Description                                                 ////
1928
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1929
////  counter                                                     ////
1930
////                                                              ////
1931
////  To Do:                                                      ////
1932
////   - add LFSR with more taps                                  ////
1933
////                                                              ////
1934
////  Author(s):                                                  ////
1935
////      - Michael Unneback, unneback@opencores.org              ////
1936
////        ORSoC AB                                              ////
1937
////                                                              ////
1938
//////////////////////////////////////////////////////////////////////
1939
////                                                              ////
1940
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1941
////                                                              ////
1942
//// This source file may be used and distributed without         ////
1943
//// restriction provided that this copyright statement is not    ////
1944
//// removed from the file and that any derivative work contains  ////
1945
//// the original copyright notice and the associated disclaimer. ////
1946
////                                                              ////
1947
//// This source file is free software; you can redistribute it   ////
1948
//// and/or modify it under the terms of the GNU Lesser General   ////
1949
//// Public License as published by the Free Software Foundation; ////
1950
//// either version 2.1 of the License, or (at your option) any   ////
1951
//// later version.                                               ////
1952
////                                                              ////
1953
//// This source is distributed in the hope that it will be       ////
1954
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1955
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1956
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1957
//// details.                                                     ////
1958
////                                                              ////
1959
//// You should have received a copy of the GNU Lesser General    ////
1960
//// Public License along with this source; if not, download it   ////
1961
//// from http://www.opencores.org/lgpl.shtml                     ////
1962
////                                                              ////
1963
//////////////////////////////////////////////////////////////////////
1964
// GRAY counter
1965 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1966 6 unneback
   parameter length = 4;
1967
   input cke;
1968
   output reg [length:1] q;
1969
   input rst;
1970
   input clk;
1971
   parameter clear_value = 0;
1972
   parameter set_value = 1;
1973
   parameter wrap_value = 8;
1974
   parameter level1_value = 15;
1975
   reg  [length:1] qi;
1976
   wire [length:1] q_next;
1977
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1978
   always @ (posedge clk or posedge rst)
1979
     if (rst)
1980
       qi <= {length{1'b0}};
1981
     else
1982
     if (cke)
1983
       qi <= q_next;
1984
   always @ (posedge clk or posedge rst)
1985
     if (rst)
1986
       q <= {length{1'b0}};
1987
     else
1988
       if (cke)
1989
         q <= (q_next>>1) ^ q_next;
1990
endmodule
1991
//////////////////////////////////////////////////////////////////////
1992
////                                                              ////
1993
////  Versatile counter                                           ////
1994
////                                                              ////
1995
////  Description                                                 ////
1996
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1997
////  counter                                                     ////
1998
////                                                              ////
1999
////  To Do:                                                      ////
2000
////   - add LFSR with more taps                                  ////
2001
////                                                              ////
2002
////  Author(s):                                                  ////
2003
////      - Michael Unneback, unneback@opencores.org              ////
2004
////        ORSoC AB                                              ////
2005
////                                                              ////
2006
//////////////////////////////////////////////////////////////////////
2007
////                                                              ////
2008
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2009
////                                                              ////
2010
//// This source file may be used and distributed without         ////
2011
//// restriction provided that this copyright statement is not    ////
2012
//// removed from the file and that any derivative work contains  ////
2013
//// the original copyright notice and the associated disclaimer. ////
2014
////                                                              ////
2015
//// This source file is free software; you can redistribute it   ////
2016
//// and/or modify it under the terms of the GNU Lesser General   ////
2017
//// Public License as published by the Free Software Foundation; ////
2018
//// either version 2.1 of the License, or (at your option) any   ////
2019
//// later version.                                               ////
2020
////                                                              ////
2021
//// This source is distributed in the hope that it will be       ////
2022
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2023
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2024
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2025
//// details.                                                     ////
2026
////                                                              ////
2027
//// You should have received a copy of the GNU Lesser General    ////
2028
//// Public License along with this source; if not, download it   ////
2029
//// from http://www.opencores.org/lgpl.shtml                     ////
2030
////                                                              ////
2031
//////////////////////////////////////////////////////////////////////
2032
// GRAY counter
2033 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2034 6 unneback
   parameter length = 4;
2035
   input cke;
2036
   output reg [length:1] q;
2037
   output [length:1] q_bin;
2038
   input rst;
2039
   input clk;
2040
   parameter clear_value = 0;
2041
   parameter set_value = 1;
2042
   parameter wrap_value = 8;
2043
   parameter level1_value = 15;
2044
   reg  [length:1] qi;
2045
   wire [length:1] q_next;
2046
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2047
   always @ (posedge clk or posedge rst)
2048
     if (rst)
2049
       qi <= {length{1'b0}};
2050
     else
2051
     if (cke)
2052
       qi <= q_next;
2053
   always @ (posedge clk or posedge rst)
2054
     if (rst)
2055
       q <= {length{1'b0}};
2056
     else
2057
       if (cke)
2058
         q <= (q_next>>1) ^ q_next;
2059
   assign q_bin = qi;
2060
endmodule
2061
//////////////////////////////////////////////////////////////////////
2062
////                                                              ////
2063
////  Versatile library, counters                                 ////
2064
////                                                              ////
2065
////  Description                                                 ////
2066
////  counters                                                    ////
2067
////                                                              ////
2068
////                                                              ////
2069
////  To Do:                                                      ////
2070
////   - add more counters                                        ////
2071
////                                                              ////
2072
////  Author(s):                                                  ////
2073
////      - Michael Unneback, unneback@opencores.org              ////
2074
////        ORSoC AB                                              ////
2075
////                                                              ////
2076
//////////////////////////////////////////////////////////////////////
2077
////                                                              ////
2078
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2079
////                                                              ////
2080
//// This source file may be used and distributed without         ////
2081
//// restriction provided that this copyright statement is not    ////
2082
//// removed from the file and that any derivative work contains  ////
2083
//// the original copyright notice and the associated disclaimer. ////
2084
////                                                              ////
2085
//// This source file is free software; you can redistribute it   ////
2086
//// and/or modify it under the terms of the GNU Lesser General   ////
2087
//// Public License as published by the Free Software Foundation; ////
2088
//// either version 2.1 of the License, or (at your option) any   ////
2089
//// later version.                                               ////
2090
////                                                              ////
2091
//// This source is distributed in the hope that it will be       ////
2092
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2093
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2094
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2095
//// details.                                                     ////
2096
////                                                              ////
2097
//// You should have received a copy of the GNU Lesser General    ////
2098
//// Public License along with this source; if not, download it   ////
2099
//// from http://www.opencores.org/lgpl.shtml                     ////
2100
////                                                              ////
2101
//////////////////////////////////////////////////////////////////////
2102 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2103 6 unneback
   parameter length = 4;
2104
   output reg [0:length-1] q;
2105
   input rst;
2106
   input clk;
2107
    always @ (posedge clk or posedge rst)
2108
    if (rst)
2109
        q <= {1'b1,{length-1{1'b0}}};
2110
    else
2111
        q <= {q[length-1],q[0:length-2]};
2112
endmodule
2113 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2114 6 unneback
   parameter length = 4;
2115
   input cke;
2116
   output reg [0:length-1] q;
2117
   input rst;
2118
   input clk;
2119
    always @ (posedge clk or posedge rst)
2120
    if (rst)
2121
        q <= {1'b1,{length-1{1'b0}}};
2122
    else
2123
        if (cke)
2124
            q <= {q[length-1],q[0:length-2]};
2125
endmodule
2126 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2127 6 unneback
   parameter length = 4;
2128
   input cke, clear;
2129
   output reg [0:length-1] q;
2130
   input rst;
2131
   input clk;
2132
    always @ (posedge clk or posedge rst)
2133
    if (rst)
2134
        q <= {1'b1,{length-1{1'b0}}};
2135
    else
2136
        if (cke)
2137
            if (clear)
2138
                q <= {1'b1,{length-1{1'b0}}};
2139
            else
2140
                q <= q >> 1;
2141
endmodule
2142 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2143 6 unneback
   parameter length = 4;
2144
   input cke, clear;
2145
   output reg [0:length-1] q;
2146
   input rst;
2147
   input clk;
2148
    always @ (posedge clk or posedge rst)
2149
    if (rst)
2150
        q <= {1'b1,{length-1{1'b0}}};
2151
    else
2152
        if (cke)
2153
            if (clear)
2154
                q <= {1'b1,{length-1{1'b0}}};
2155
            else
2156
            q <= {q[length-1],q[0:length-2]};
2157
endmodule
2158
//////////////////////////////////////////////////////////////////////
2159
////                                                              ////
2160
////  Versatile library, memories                                 ////
2161
////                                                              ////
2162
////  Description                                                 ////
2163
////  memories                                                    ////
2164
////                                                              ////
2165
////                                                              ////
2166
////  To Do:                                                      ////
2167
////   - add more memory types                                    ////
2168
////                                                              ////
2169
////  Author(s):                                                  ////
2170
////      - Michael Unneback, unneback@opencores.org              ////
2171
////        ORSoC AB                                              ////
2172
////                                                              ////
2173
//////////////////////////////////////////////////////////////////////
2174
////                                                              ////
2175
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2176
////                                                              ////
2177
//// This source file may be used and distributed without         ////
2178
//// restriction provided that this copyright statement is not    ////
2179
//// removed from the file and that any derivative work contains  ////
2180
//// the original copyright notice and the associated disclaimer. ////
2181
////                                                              ////
2182
//// This source file is free software; you can redistribute it   ////
2183
//// and/or modify it under the terms of the GNU Lesser General   ////
2184
//// Public License as published by the Free Software Foundation; ////
2185
//// either version 2.1 of the License, or (at your option) any   ////
2186
//// later version.                                               ////
2187
////                                                              ////
2188
//// This source is distributed in the hope that it will be       ////
2189
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2190
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2191
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2192
//// details.                                                     ////
2193
////                                                              ////
2194
//// You should have received a copy of the GNU Lesser General    ////
2195
//// Public License along with this source; if not, download it   ////
2196
//// from http://www.opencores.org/lgpl.shtml                     ////
2197
////                                                              ////
2198
//////////////////////////////////////////////////////////////////////
2199
/// ROM
2200 7 unneback
module vl_rom_init ( adr, q, clk);
2201
   parameter data_width = 32;
2202
   parameter addr_width = 8;
2203
   input [(addr_width-1):0]       adr;
2204
   output reg [(data_width-1):0] q;
2205
   input                         clk;
2206
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2207
   parameter memory_file = "vl_rom.vmem";
2208
   initial
2209
     begin
2210
        $readmemh(memory_file, rom);
2211
     end
2212
   always @ (posedge clk)
2213
     q <= rom[adr];
2214
endmodule
2215 14 unneback
/*
2216 7 unneback
module vl_rom ( adr, q, clk);
2217 6 unneback
parameter data_width = 32;
2218
parameter addr_width = 4;
2219
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2220
    {32'h18000000},
2221
    {32'hA8200000},
2222
    {32'hA8200000},
2223
    {32'hA8200000},
2224
    {32'h44003000},
2225
    {32'h15000000},
2226
    {32'h15000000},
2227
    {32'h15000000},
2228
    {32'h15000000},
2229
    {32'h15000000},
2230
    {32'h15000000},
2231
    {32'h15000000},
2232
    {32'h15000000},
2233
    {32'h15000000},
2234
    {32'h15000000},
2235
    {32'h15000000}};
2236 7 unneback
input [addr_width-1:0] adr;
2237 6 unneback
output reg [data_width-1:0] q;
2238
input clk;
2239
always @ (posedge clk)
2240 7 unneback
    q <= data[adr];
2241 6 unneback
endmodule
2242 14 unneback
*/
2243 6 unneback
// Single port RAM
2244
module vl_ram ( d, adr, we, q, clk);
2245
   parameter data_width = 32;
2246
   parameter addr_width = 8;
2247
   input [(data_width-1):0]      d;
2248
   input [(addr_width-1):0]       adr;
2249
   input                         we;
2250 7 unneback
   output reg [(data_width-1):0] q;
2251 6 unneback
   input                         clk;
2252
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2253 7 unneback
   parameter init = 0;
2254
   parameter memory_file = "vl_ram.vmem";
2255
   generate if (init) begin : init_mem
2256
   initial
2257
     begin
2258
        $readmemh(memory_file, ram);
2259
     end
2260
   end
2261
   endgenerate
2262 6 unneback
   always @ (posedge clk)
2263
   begin
2264
   if (we)
2265
     ram[adr] <= d;
2266
   q <= ram[adr];
2267
   end
2268
endmodule
2269 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2270
   parameter data_width = 32;
2271
   parameter addr_width = 8;
2272
   input [(data_width-1):0]      d;
2273
   input [(addr_width-1):0]       adr;
2274
   input [(addr_width/4)-1:0]    be;
2275
   input                         we;
2276
   output reg [(data_width-1):0] q;
2277
   input                         clk;
2278
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2279
   parameter init = 0;
2280
   parameter memory_file = "vl_ram.vmem";
2281
   generate if (init) begin : init_mem
2282
   initial
2283
     begin
2284
        $readmemh(memory_file, ram);
2285
     end
2286
   end
2287
   endgenerate
2288
   genvar i;
2289
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2290
      always @ (posedge clk)
2291
      if (we & be[i])
2292
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2293
   end
2294
   endgenerate
2295
   always @ (posedge clk)
2296
      q <= ram[adr];
2297
endmodule
2298 6 unneback
// Dual port RAM
2299
// ACTEL FPGA should not use logic to handle rw collision
2300 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2301 6 unneback
   parameter data_width = 32;
2302
   parameter addr_width = 8;
2303
   input [(data_width-1):0]      d_a;
2304
   input [(addr_width-1):0]       adr_a;
2305
   input [(addr_width-1):0]       adr_b;
2306
   input                         we_a;
2307
   output [(data_width-1):0]      q_b;
2308
   input                         clk_a, clk_b;
2309
   reg [(addr_width-1):0]         adr_b_reg;
2310
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2311 7 unneback
   parameter init = 0;
2312
   parameter memory_file = "vl_ram.vmem";
2313
   generate if (init) begin : init_mem
2314
   initial
2315
     begin
2316
        $readmemh(memory_file, ram);
2317
     end
2318
   end
2319
   endgenerate
2320 6 unneback
   always @ (posedge clk_a)
2321
   if (we_a)
2322
     ram[adr_a] <= d_a;
2323
   always @ (posedge clk_b)
2324
   adr_b_reg <= adr_b;
2325
   assign q_b = ram[adr_b_reg];
2326
endmodule
2327 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2328 6 unneback
   parameter data_width = 32;
2329
   parameter addr_width = 8;
2330
   input [(data_width-1):0]      d_a;
2331
   input [(addr_width-1):0]       adr_a;
2332
   input [(addr_width-1):0]       adr_b;
2333
   input                         we_a;
2334
   output [(data_width-1):0]      q_b;
2335
   output reg [(data_width-1):0] q_a;
2336
   input                         clk_a, clk_b;
2337
   reg [(data_width-1):0]         q_b;
2338
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2339 7 unneback
   parameter init = 0;
2340
   parameter memory_file = "vl_ram.vmem";
2341
   generate if (init) begin : init_mem
2342
   initial
2343
     begin
2344
        $readmemh(memory_file, ram);
2345
     end
2346
   end
2347
   endgenerate
2348 6 unneback
   always @ (posedge clk_a)
2349
     begin
2350
        q_a <= ram[adr_a];
2351
        if (we_a)
2352
             ram[adr_a] <= d_a;
2353
     end
2354
   always @ (posedge clk_b)
2355
          q_b <= ram[adr_b];
2356
endmodule
2357 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2358 6 unneback
   parameter data_width = 32;
2359
   parameter addr_width = 8;
2360
   input [(data_width-1):0]      d_a;
2361
   input [(addr_width-1):0]       adr_a;
2362
   input [(addr_width-1):0]       adr_b;
2363
   input                         we_a;
2364
   output [(data_width-1):0]      q_b;
2365
   input [(data_width-1):0]       d_b;
2366
   output reg [(data_width-1):0] q_a;
2367
   input                         we_b;
2368
   input                         clk_a, clk_b;
2369
   reg [(data_width-1):0]         q_b;
2370
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2371 7 unneback
   parameter init = 0;
2372
   parameter memory_file = "vl_ram.vmem";
2373
   generate if (init) begin : init_mem
2374
   initial
2375
     begin
2376
        $readmemh(memory_file, ram);
2377
     end
2378
   end
2379
   endgenerate
2380 6 unneback
   always @ (posedge clk_a)
2381
     begin
2382
        q_a <= ram[adr_a];
2383
        if (we_a)
2384
             ram[adr_a] <= d_a;
2385
     end
2386
   always @ (posedge clk_b)
2387
     begin
2388
        q_b <= ram[adr_b];
2389
        if (we_b)
2390
          ram[adr_b] <= d_b;
2391
     end
2392
endmodule
2393
// Content addresable memory, CAM
2394
// FIFO
2395 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2396
    d, wr, fifo_full,
2397
    q, rd, fifo_empty,
2398
    fill_level,
2399
    clk, rst
2400
    );
2401
parameter data_width = 18;
2402
parameter addr_width = 4;
2403
// write side
2404
input  [data_width-1:0] d;
2405
input                   wr;
2406
output                  fifo_full;
2407
// read side
2408
output [data_width-1:0] q;
2409
input                   rd;
2410
output                  fifo_empty;
2411
// common
2412
output [addr_width:0]   fill_level;
2413
input rst, clk;
2414
wire [addr_width:1] wadr, radr;
2415
vl_cnt_bin_ce
2416
    # ( .length(addr_width))
2417
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2418
vl_cnt_bin_ce
2419
    # (.length(addr_width))
2420
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2421
vl_dpram_1r1w
2422
    # (.data_width(data_width), .addr_width(addr_width))
2423
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2424
vl_cnt_bin_ce_rew_zq_l1
2425 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2426 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2427
endmodule
2428 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2429
// RAM is supposed to be larger than the two FIFOs
2430
// LFSR counters used adr pointers
2431
module vl_fifo_2r2w_sync_simplex (
2432
    // a side
2433
    a_d, a_wr, a_fifo_full,
2434
    a_q, a_rd, a_fifo_empty,
2435
    a_fill_level,
2436
    // b side
2437
    b_d, b_wr, b_fifo_full,
2438
    b_q, b_rd, b_fifo_empty,
2439
    b_fill_level,
2440
    // common
2441
    clk, rst
2442
    );
2443
parameter data_width = 8;
2444
parameter addr_width = 5;
2445
parameter fifo_full_level = (1<<addr_width)-1;
2446
// a side
2447
input  [data_width-1:0] a_d;
2448
input                   a_wr;
2449
output                  a_fifo_full;
2450
output [data_width-1:0] a_q;
2451
input                   a_rd;
2452
output                  a_fifo_empty;
2453
output [addr_width-1:0] a_fill_level;
2454
// b side
2455
input  [data_width-1:0] b_d;
2456
input                   b_wr;
2457
output                  b_fifo_full;
2458
output [data_width-1:0] b_q;
2459
input                   b_rd;
2460
output                  b_fifo_empty;
2461
output [addr_width-1:0] b_fill_level;
2462
input                   clk;
2463
input                   rst;
2464
// adr_gen
2465
wire [addr_width:1] a_wadr, a_radr;
2466
wire [addr_width:1] b_wadr, b_radr;
2467
// dpram
2468
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2469
vl_cnt_lfsr_ce
2470
    # ( .length(addr_width))
2471
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2472
vl_cnt_lfsr_ce
2473
    # (.length(addr_width))
2474
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2475
vl_cnt_lfsr_ce
2476
    # ( .length(addr_width))
2477
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2478
vl_cnt_lfsr_ce
2479
    # (.length(addr_width))
2480
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2481
// mux read or write adr to DPRAM
2482
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2483
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2484
vl_dpram_2r2w
2485
    # (.data_width(data_width), .addr_width(addr_width+1))
2486
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2487
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2488
vl_cnt_bin_ce_rew_zq_l1
2489 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2490 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2491
vl_cnt_bin_ce_rew_zq_l1
2492 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2493 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2494
endmodule
2495 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2496 11 unneback
   parameter addr_width = 4;
2497
   parameter N = addr_width-1;
2498 6 unneback
   parameter Q1 = 2'b00;
2499
   parameter Q2 = 2'b01;
2500
   parameter Q3 = 2'b11;
2501
   parameter Q4 = 2'b10;
2502
   parameter going_empty = 1'b0;
2503
   parameter going_full  = 1'b1;
2504
   input [N:0]  wptr, rptr;
2505 14 unneback
   output       fifo_empty;
2506 6 unneback
   output       fifo_full;
2507
   input        wclk, rclk, rst;
2508
   wire direction;
2509
   reg  direction_set, direction_clr;
2510
   wire async_empty, async_full;
2511
   wire fifo_full2;
2512 14 unneback
   wire fifo_empty2;
2513 6 unneback
   // direction_set
2514
   always @ (wptr[N:N-1] or rptr[N:N-1])
2515
     case ({wptr[N:N-1],rptr[N:N-1]})
2516
       {Q1,Q2} : direction_set <= 1'b1;
2517
       {Q2,Q3} : direction_set <= 1'b1;
2518
       {Q3,Q4} : direction_set <= 1'b1;
2519
       {Q4,Q1} : direction_set <= 1'b1;
2520
       default : direction_set <= 1'b0;
2521
     endcase
2522
   // direction_clear
2523
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2524
     if (rst)
2525
       direction_clr <= 1'b1;
2526
     else
2527
       case ({wptr[N:N-1],rptr[N:N-1]})
2528
         {Q2,Q1} : direction_clr <= 1'b1;
2529
         {Q3,Q2} : direction_clr <= 1'b1;
2530
         {Q4,Q3} : direction_clr <= 1'b1;
2531
         {Q1,Q4} : direction_clr <= 1'b1;
2532
         default : direction_clr <= 1'b0;
2533
       endcase
2534 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2535 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2536
   assign async_full  = (wptr == rptr) && (direction==going_full);
2537 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2538
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2539 6 unneback
/*
2540
   always @ (posedge wclk or posedge rst or posedge async_full)
2541
     if (rst)
2542
       {fifo_full, fifo_full2} <= 2'b00;
2543
     else if (async_full)
2544
       {fifo_full, fifo_full2} <= 2'b11;
2545
     else
2546
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2547
*/
2548 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2549 6 unneback
     if (async_empty)
2550
       {fifo_empty, fifo_empty2} <= 2'b11;
2551
     else
2552 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2553 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2554
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2555 27 unneback
endmodule // async_compb
2556 6 unneback
module vl_fifo_1r1w_async (
2557
    d, wr, fifo_full, wr_clk, wr_rst,
2558
    q, rd, fifo_empty, rd_clk, rd_rst
2559
    );
2560
parameter data_width = 18;
2561
parameter addr_width = 4;
2562
// write side
2563
input  [data_width-1:0] d;
2564
input                   wr;
2565
output                  fifo_full;
2566
input                   wr_clk;
2567
input                   wr_rst;
2568
// read side
2569
output [data_width-1:0] q;
2570
input                   rd;
2571
output                  fifo_empty;
2572
input                   rd_clk;
2573
input                   rd_rst;
2574
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2575 18 unneback
vl_cnt_gray_ce_bin
2576 6 unneback
    # ( .length(addr_width))
2577
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2578 18 unneback
vl_cnt_gray_ce_bin
2579 6 unneback
    # (.length(addr_width))
2580 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2581 7 unneback
vl_dpram_1r1w
2582 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2583
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2584
vl_fifo_cmp_async
2585
    # (.addr_width(addr_width))
2586
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2587
endmodule
2588 8 unneback
module vl_fifo_2r2w_async (
2589 6 unneback
    // a side
2590
    a_d, a_wr, a_fifo_full,
2591
    a_q, a_rd, a_fifo_empty,
2592
    a_clk, a_rst,
2593
    // b side
2594
    b_d, b_wr, b_fifo_full,
2595
    b_q, b_rd, b_fifo_empty,
2596
    b_clk, b_rst
2597
    );
2598
parameter data_width = 18;
2599
parameter addr_width = 4;
2600
// a side
2601
input  [data_width-1:0] a_d;
2602
input                   a_wr;
2603
output                  a_fifo_full;
2604
output [data_width-1:0] a_q;
2605
input                   a_rd;
2606
output                  a_fifo_empty;
2607
input                   a_clk;
2608
input                   a_rst;
2609
// b side
2610
input  [data_width-1:0] b_d;
2611
input                   b_wr;
2612
output                  b_fifo_full;
2613
output [data_width-1:0] b_q;
2614
input                   b_rd;
2615
output                  b_fifo_empty;
2616
input                   b_clk;
2617
input                   b_rst;
2618
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2619
vl_fifo_1r1w_async_a (
2620
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2621
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2622
    );
2623
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2624
vl_fifo_1r1w_async_b (
2625
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2626
    .q(a_q), .rd(a_rd)