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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 6 unneback
 // ALTERA
47
 //ACTEL
48
// sync reset
49 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
50 6 unneback
// output active high global reset sync with two DFFs 
51
`timescale 1 ns/100 ps
52
module vl_sync_rst ( rst_n_i, rst_o, clk);
53
input rst_n_i, clk;
54
output rst_o;
55 18 unneback
reg [1:0] tmp;
56 6 unneback
always @ (posedge clk or negedge rst_n_i)
57
if (!rst_n_i)
58 17 unneback
        tmp <= 2'b11;
59 6 unneback
else
60 17 unneback
        tmp <= {1'b0,tmp[0]};
61
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
62 6 unneback
endmodule
63
// vl_pll
64 32 unneback
///////////////////////////////////////////////////////////////////////////////
65
`timescale 1 ps/1 ps
66
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
67
parameter index = 0;
68
parameter number_of_clk = 1;
69
parameter period_time_0 = 20000;
70
parameter period_time_1 = 20000;
71
parameter period_time_2 = 20000;
72
parameter period_time_3 = 20000;
73
parameter period_time_4 = 20000;
74
parameter lock_delay = 2000000;
75
input clk_i, rst_n_i;
76
output lock;
77
output reg [0:number_of_clk-1] clk_o;
78
output [0:number_of_clk-1] rst_o;
79
//E2_ifdef SIM_PLL
80
always
81
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
82
generate if (number_of_clk > 1)
83
always
84
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
85
endgenerate
86
generate if (number_of_clk > 2)
87
always
88
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
89
endgenerate
90
always
91
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
92
endgenerate
93
always
94
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
95
endgenerate
96
genvar i;
97
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
98
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
99
end
100
endgenerate
101
assign #lock_delay lock = rst_n_i;
102
endmodule
103
//E2_else
104
generate if (number_of_clk==1 & index==0) begin
105
        pll0 pll_i0 (.areset(1'b1), .inclk(clk_i), .locked(lock), .c0(clk_o[0]));
106
end
107
endgenerate // index==0
108
generate if (number_of_clk==1 & index==1) begin
109
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
110
end
111
endgenerate // index==1
112
generate if (number_of_clk==1 & index==2) begin
113
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
114
end
115
endgenerate // index==2
116
generate if (number_of_clk==1 & index==3) begin
117
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
118
end
119
endgenerate // index==3
120
generate if (number_of_clk==2 & index==0) begin
121
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
122
end
123
endgenerate // index==0
124
generate if (number_of_clk==2 & index==1) begin
125
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
126
end
127
endgenerate // index==1
128
generate if (number_of_clk==2 & index==2) begin
129
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
130
end
131
endgenerate // index==2
132
generate if (number_of_clk==2 & index==3) begin
133
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
134
end
135
endgenerate // index==3
136
generate if (number_of_clk==3 & index==0) begin
137
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
138
end
139
endgenerate // index==0
140
generate if (number_of_clk==3 & index==1) begin
141
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
142
end
143
endgenerate // index==1
144
generate if (number_of_clk==3 & index==2) begin
145
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
146
end
147
endgenerate // index==2
148
generate if (number_of_clk==3 & index==3) begin
149
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
150
end
151
endgenerate // index==3
152
generate if (number_of_clk==4 & index==0) begin
153
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
154
end
155
endgenerate // index==0
156
generate if (number_of_clk==4 & index==1) begin
157
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
158
end
159
endgenerate // index==1
160
generate if (number_of_clk==4 & index==2) begin
161
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
162
end
163
endgenerate // index==2
164
generate if (number_of_clk==4 & index==3) begin
165
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
166
end
167
endgenerate // index==3
168
generate if (number_of_clk==5 & index==0) begin
169
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3], .c4(clk_o[4]));
170
end
171
endgenerate // index==0
172
generate if (number_of_clk==5 & index==1) begin
173
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
174
end
175
endgenerate // index==1
176
generate if (number_of_clk==5 & index==2) begin
177
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
178
end
179
endgenerate // index==2
180
generate if (number_of_clk==5 & index==3) begin
181
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
182
end
183
endgenerate // index==3
184
genvar i;
185
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
186
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
187
end
188
endgenerate
189
endmodule
190
//E2_endif
191
///////////////////////////////////////////////////////////////////////////////
192 6 unneback
 //altera
193
 //actel
194
//////////////////////////////////////////////////////////////////////
195
////                                                              ////
196
////  Versatile library, registers                                ////
197
////                                                              ////
198
////  Description                                                 ////
199
////  Different type of registers                                 ////
200
////                                                              ////
201
////                                                              ////
202
////  To Do:                                                      ////
203
////   - add more different registers                             ////
204
////                                                              ////
205
////  Author(s):                                                  ////
206
////      - Michael Unneback, unneback@opencores.org              ////
207
////        ORSoC AB                                              ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210
////                                                              ////
211
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
212
////                                                              ////
213
//// This source file may be used and distributed without         ////
214
//// restriction provided that this copyright statement is not    ////
215
//// removed from the file and that any derivative work contains  ////
216
//// the original copyright notice and the associated disclaimer. ////
217
////                                                              ////
218
//// This source file is free software; you can redistribute it   ////
219
//// and/or modify it under the terms of the GNU Lesser General   ////
220
//// Public License as published by the Free Software Foundation; ////
221
//// either version 2.1 of the License, or (at your option) any   ////
222
//// later version.                                               ////
223
////                                                              ////
224
//// This source is distributed in the hope that it will be       ////
225
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
226
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
227
//// PURPOSE.  See the GNU Lesser General Public License for more ////
228
//// details.                                                     ////
229
////                                                              ////
230
//// You should have received a copy of the GNU Lesser General    ////
231
//// Public License along with this source; if not, download it   ////
232
//// from http://www.opencores.org/lgpl.shtml                     ////
233
////                                                              ////
234
//////////////////////////////////////////////////////////////////////
235 18 unneback
module vl_dff ( d, q, clk, rst);
236 6 unneback
        parameter width = 1;
237
        parameter reset_value = 0;
238
        input [width-1:0] d;
239
        input clk, rst;
240
        output reg [width-1:0] q;
241
        always @ (posedge clk or posedge rst)
242
        if (rst)
243
                q <= reset_value;
244
        else
245
                q <= d;
246
endmodule
247 18 unneback
module vl_dff_array ( d, q, clk, rst);
248 6 unneback
        parameter width = 1;
249
        parameter depth = 2;
250
        parameter reset_value = 1'b0;
251
        input [width-1:0] d;
252
        input clk, rst;
253
        output [width-1:0] q;
254
        reg  [0:depth-1] q_tmp [width-1:0];
255
        integer i;
256
        always @ (posedge clk or posedge rst)
257
        if (rst) begin
258
            for (i=0;i<depth;i=i+1)
259
                q_tmp[i] <= {width{reset_value}};
260
        end else begin
261
            q_tmp[0] <= d;
262
            for (i=1;i<depth;i=i+1)
263
                q_tmp[i] <= q_tmp[i-1];
264
        end
265
    assign q = q_tmp[depth-1];
266
endmodule
267 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
268 6 unneback
        parameter width = 1;
269
        parameter reset_value = 0;
270
        input [width-1:0] d;
271
        input ce, clk, rst;
272
        output reg [width-1:0] q;
273
        always @ (posedge clk or posedge rst)
274
        if (rst)
275
                q <= reset_value;
276
        else
277
                if (ce)
278
                        q <= d;
279
endmodule
280 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
281 8 unneback
        parameter width = 1;
282
        parameter reset_value = 0;
283
        input [width-1:0] d;
284 10 unneback
        input ce, clear, clk, rst;
285 8 unneback
        output reg [width-1:0] q;
286
        always @ (posedge clk or posedge rst)
287
        if (rst)
288
            q <= reset_value;
289
        else
290
            if (ce)
291
                if (clear)
292
                    q <= {width{1'b0}};
293
                else
294
                    q <= d;
295
endmodule
296 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
297
        parameter width = 1;
298
        parameter reset_value = 0;
299
        input [width-1:0] d;
300
        input ce, set, clk, rst;
301
        output reg [width-1:0] q;
302
        always @ (posedge clk or posedge rst)
303
        if (rst)
304
            q <= reset_value;
305
        else
306
            if (ce)
307
                if (set)
308
                    q <= {width{1'b1}};
309
                else
310
                    q <= d;
311
endmodule
312 29 unneback
module vl_spr ( sp, r, q, clk, rst);
313
        parameter width = 1;
314
        parameter reset_value = 0;
315
        input sp, r;
316
        output reg q;
317
        input clk, rst;
318
        always @ (posedge clk or posedge rst)
319
        if (rst)
320
            q <= reset_value;
321
        else
322
            if (sp)
323
                q <= 1'b1;
324
            else if (r)
325
                q <= 1'b0;
326
endmodule
327
module vl_srp ( s, rp, q, clk, rst);
328
        parameter width = 1;
329
        parameter reset_value = 0;
330
        input s, rp;
331
        output reg q;
332
        input clk, rst;
333
        always @ (posedge clk or posedge rst)
334
        if (rst)
335
            q <= reset_value;
336
        else
337
            if (rp)
338
                q <= 1'b0;
339
            else if (s)
340
                q <= 1'b1;
341
endmodule
342 6 unneback
// megafunction wizard: %LPM_FF%
343
// GENERATION: STANDARD
344
// VERSION: WM1.0
345
// MODULE: lpm_ff 
346
// ============================================================
347
// File Name: dff_sr.v
348
// Megafunction Name(s):
349
//                      lpm_ff
350
//
351
// Simulation Library Files(s):
352
//                      lpm
353
// ============================================================
354
// ************************************************************
355
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
356
//
357
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
358
// ************************************************************
359
//Copyright (C) 1991-2010 Altera Corporation
360
//Your use of Altera Corporation's design tools, logic functions 
361
//and other software and tools, and its AMPP partner logic 
362
//functions, and any output files from any of the foregoing 
363
//(including device programming or simulation files), and any 
364
//associated documentation or information are expressly subject 
365
//to the terms and conditions of the Altera Program License 
366
//Subscription Agreement, Altera MegaCore Function License 
367
//Agreement, or other applicable license agreement, including, 
368
//without limitation, that your use is for the sole purpose of 
369
//programming logic devices manufactured by Altera and sold by 
370
//Altera or its authorized distributors.  Please refer to the 
371
//applicable agreement for further details.
372
// synopsys translate_off
373
`timescale 1 ps / 1 ps
374
// synopsys translate_on
375 18 unneback
module vl_dff_sr (
376 6 unneback
        aclr,
377
        aset,
378
        clock,
379
        data,
380
        q);
381
        input     aclr;
382
        input     aset;
383
        input     clock;
384
        input     data;
385
        output    q;
386
        wire [0:0] sub_wire0;
387
        wire [0:0] sub_wire1 = sub_wire0[0:0];
388
        wire  q = sub_wire1;
389
        wire  sub_wire2 = data;
390
        wire  sub_wire3 = sub_wire2;
391
        lpm_ff  lpm_ff_component (
392
                                .aclr (aclr),
393
                                .clock (clock),
394
                                .data (sub_wire3),
395
                                .aset (aset),
396
                                .q (sub_wire0)
397
                                // synopsys translate_off
398
                                ,
399
                                .aload (),
400
                                .enable (),
401
                                .sclr (),
402
                                .sload (),
403
                                .sset ()
404
                                // synopsys translate_on
405
                                );
406
        defparam
407
                lpm_ff_component.lpm_fftype = "DFF",
408
                lpm_ff_component.lpm_type = "LPM_FF",
409
                lpm_ff_component.lpm_width = 1;
410
endmodule
411
// ============================================================
412
// CNX file retrieval info
413
// ============================================================
414
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
415
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
416
// Retrieval info: PRIVATE: ASET NUMERIC "1"
417
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
418
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
419
// Retrieval info: PRIVATE: DFF NUMERIC "1"
420
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
421
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
422
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
423
// Retrieval info: PRIVATE: SSET NUMERIC "0"
424
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
425
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
426
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
427
// Retrieval info: PRIVATE: nBit NUMERIC "1"
428
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
429
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
430
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
431
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
432
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
433
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
434
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
435
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
436
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
437
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
438
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
439
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
440
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
441
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
444
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
445
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
446
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
447
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
448
// Retrieval info: LIB_FILE: lpm
449
// LATCH
450
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
451 18 unneback
module vl_latch ( d, le, q, clk);
452 6 unneback
input d, le;
453
output q;
454
input clk;
455
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
456
endmodule
457 18 unneback
module vl_shreg ( d, q, clk, rst);
458 17 unneback
parameter depth = 10;
459
input d;
460
output q;
461
input clk, rst;
462
reg [1:depth] dffs;
463
always @ (posedge clk or posedge rst)
464
if (rst)
465
    dffs <= {depth{1'b0}};
466
else
467
    dffs <= {d,dffs[1:depth-1]};
468
assign q = dffs[depth];
469
endmodule
470 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
471 17 unneback
parameter depth = 10;
472
input d, ce;
473
output q;
474
input clk, rst;
475
reg [1:depth] dffs;
476
always @ (posedge clk or posedge rst)
477
if (rst)
478
    dffs <= {depth{1'b0}};
479
else
480
    if (ce)
481
        dffs <= {d,dffs[1:depth-1]};
482
assign q = dffs[depth];
483
endmodule
484 18 unneback
module vl_delay ( d, q, clk, rst);
485 15 unneback
parameter depth = 10;
486
input d;
487
output q;
488
input clk, rst;
489
reg [1:depth] dffs;
490
always @ (posedge clk or posedge rst)
491
if (rst)
492
    dffs <= {depth{1'b0}};
493
else
494
    dffs <= {d,dffs[1:depth-1]};
495
assign q = dffs[depth];
496
endmodule
497 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
498 17 unneback
parameter depth = 10;
499
input d;
500
output q, emptyflag;
501
input clk, rst;
502
reg [1:depth] dffs;
503
always @ (posedge clk or posedge rst)
504
if (rst)
505
    dffs <= {depth{1'b0}};
506
else
507
    dffs <= {d,dffs[1:depth-1]};
508
assign q = dffs[depth];
509
assign emptyflag = !(|dffs);
510
endmodule
511 6 unneback
//////////////////////////////////////////////////////////////////////
512
////                                                              ////
513 18 unneback
////  Logic functions                                             ////
514
////                                                              ////
515
////  Description                                                 ////
516
////  Logic functions such as multiplexers                        ////
517
////                                                              ////
518
////                                                              ////
519
////  To Do:                                                      ////
520
////   -                                                          ////
521
////                                                              ////
522
////  Author(s):                                                  ////
523
////      - Michael Unneback, unneback@opencores.org              ////
524
////        ORSoC AB                                              ////
525
////                                                              ////
526
//////////////////////////////////////////////////////////////////////
527
////                                                              ////
528
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
529
////                                                              ////
530
//// This source file may be used and distributed without         ////
531
//// restriction provided that this copyright statement is not    ////
532
//// removed from the file and that any derivative work contains  ////
533
//// the original copyright notice and the associated disclaimer. ////
534
////                                                              ////
535
//// This source file is free software; you can redistribute it   ////
536
//// and/or modify it under the terms of the GNU Lesser General   ////
537
//// Public License as published by the Free Software Foundation; ////
538
//// either version 2.1 of the License, or (at your option) any   ////
539
//// later version.                                               ////
540
////                                                              ////
541
//// This source is distributed in the hope that it will be       ////
542
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
543
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
544
//// PURPOSE.  See the GNU Lesser General Public License for more ////
545
//// details.                                                     ////
546
////                                                              ////
547
//// You should have received a copy of the GNU Lesser General    ////
548
//// Public License along with this source; if not, download it   ////
549
//// from http://www.opencores.org/lgpl.shtml                     ////
550
////                                                              ////
551
//////////////////////////////////////////////////////////////////////
552
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
553
parameter width = 32;
554
parameter nr_of_ports = 4;
555
input [width-1:0] a3, a2, a1, a0;
556
input [nr_of_ports-1:0] sel;
557 22 unneback
output [width-1:0] dout;
558 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
559 18 unneback
integer i;
560
// and
561
assign tmp[0] = {width{sel[0]}} & a0;
562
assign tmp[1] = {width{sel[1]}} & a1;
563
assign tmp[2] = {width{sel[2]}} & a2;
564
assign tmp[3] = {width{sel[3]}} & a3;
565
// or
566
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
567
endmodule
568
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
569
parameter width = 32;
570
parameter nr_of_ports = 5;
571
input [width-1:0] a4, a3, a2, a1, a0;
572
input [nr_of_ports-1:0] sel;
573 22 unneback
output [width-1:0] dout;
574 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
575 18 unneback
integer i;
576
// and
577
assign tmp[0] = {width{sel[0]}} & a0;
578
assign tmp[1] = {width{sel[1]}} & a1;
579
assign tmp[2] = {width{sel[2]}} & a2;
580
assign tmp[3] = {width{sel[3]}} & a3;
581
assign tmp[4] = {width{sel[4]}} & a4;
582
// or
583
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
584
endmodule
585
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
586
parameter width = 32;
587
parameter nr_of_ports = 6;
588
input [width-1:0] a5, a4, a3, a2, a1, a0;
589
input [nr_of_ports-1:0] sel;
590 22 unneback
output [width-1:0] dout;
591 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
592 18 unneback
integer i;
593
// and
594
assign tmp[0] = {width{sel[0]}} & a0;
595
assign tmp[1] = {width{sel[1]}} & a1;
596
assign tmp[2] = {width{sel[2]}} & a2;
597
assign tmp[3] = {width{sel[3]}} & a3;
598
assign tmp[4] = {width{sel[4]}} & a4;
599
assign tmp[5] = {width{sel[5]}} & a5;
600
// or
601
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
602
endmodule
603
//////////////////////////////////////////////////////////////////////
604
////                                                              ////
605 6 unneback
////  Versatile counter                                           ////
606
////                                                              ////
607
////  Description                                                 ////
608
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
609
////  counter                                                     ////
610
////                                                              ////
611
////  To Do:                                                      ////
612
////   - add LFSR with more taps                                  ////
613
////                                                              ////
614
////  Author(s):                                                  ////
615
////      - Michael Unneback, unneback@opencores.org              ////
616
////        ORSoC AB                                              ////
617
////                                                              ////
618
//////////////////////////////////////////////////////////////////////
619
////                                                              ////
620
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
621
////                                                              ////
622
//// This source file may be used and distributed without         ////
623
//// restriction provided that this copyright statement is not    ////
624
//// removed from the file and that any derivative work contains  ////
625
//// the original copyright notice and the associated disclaimer. ////
626
////                                                              ////
627
//// This source file is free software; you can redistribute it   ////
628
//// and/or modify it under the terms of the GNU Lesser General   ////
629
//// Public License as published by the Free Software Foundation; ////
630
//// either version 2.1 of the License, or (at your option) any   ////
631
//// later version.                                               ////
632
////                                                              ////
633
//// This source is distributed in the hope that it will be       ////
634
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
635
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
636
//// PURPOSE.  See the GNU Lesser General Public License for more ////
637
//// details.                                                     ////
638
////                                                              ////
639
//// You should have received a copy of the GNU Lesser General    ////
640
//// Public License along with this source; if not, download it   ////
641
//// from http://www.opencores.org/lgpl.shtml                     ////
642
////                                                              ////
643
//////////////////////////////////////////////////////////////////////
644
// binary counter
645 22 unneback
module vl_cnt_bin ( q, rst, clk);
646
   parameter length = 4;
647
   output [length:1] q;
648
   input rst;
649
   input clk;
650
   parameter clear_value = 0;
651
   parameter set_value = 1;
652
   parameter wrap_value = 0;
653
   parameter level1_value = 15;
654
   reg  [length:1] qi;
655
   wire [length:1] q_next;
656
   assign q_next = qi + {{length-1{1'b0}},1'b1};
657
   always @ (posedge clk or posedge rst)
658
     if (rst)
659
       qi <= {length{1'b0}};
660
     else
661
       qi <= q_next;
662
   assign q = qi;
663
endmodule
664
//////////////////////////////////////////////////////////////////////
665
////                                                              ////
666
////  Versatile counter                                           ////
667
////                                                              ////
668
////  Description                                                 ////
669
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
670
////  counter                                                     ////
671
////                                                              ////
672
////  To Do:                                                      ////
673
////   - add LFSR with more taps                                  ////
674
////                                                              ////
675
////  Author(s):                                                  ////
676
////      - Michael Unneback, unneback@opencores.org              ////
677
////        ORSoC AB                                              ////
678
////                                                              ////
679
//////////////////////////////////////////////////////////////////////
680
////                                                              ////
681
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
682
////                                                              ////
683
//// This source file may be used and distributed without         ////
684
//// restriction provided that this copyright statement is not    ////
685
//// removed from the file and that any derivative work contains  ////
686
//// the original copyright notice and the associated disclaimer. ////
687
////                                                              ////
688
//// This source file is free software; you can redistribute it   ////
689
//// and/or modify it under the terms of the GNU Lesser General   ////
690
//// Public License as published by the Free Software Foundation; ////
691
//// either version 2.1 of the License, or (at your option) any   ////
692
//// later version.                                               ////
693
////                                                              ////
694
//// This source is distributed in the hope that it will be       ////
695
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
696
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
697
//// PURPOSE.  See the GNU Lesser General Public License for more ////
698
//// details.                                                     ////
699
////                                                              ////
700
//// You should have received a copy of the GNU Lesser General    ////
701
//// Public License along with this source; if not, download it   ////
702
//// from http://www.opencores.org/lgpl.shtml                     ////
703
////                                                              ////
704
//////////////////////////////////////////////////////////////////////
705
// binary counter
706
module vl_cnt_bin_clear ( clear, q, rst, clk);
707
   parameter length = 4;
708
   input clear;
709
   output [length:1] q;
710
   input rst;
711
   input clk;
712
   parameter clear_value = 0;
713
   parameter set_value = 1;
714
   parameter wrap_value = 0;
715
   parameter level1_value = 15;
716
   reg  [length:1] qi;
717
   wire [length:1] q_next;
718
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
719
   always @ (posedge clk or posedge rst)
720
     if (rst)
721
       qi <= {length{1'b0}};
722
     else
723
       qi <= q_next;
724
   assign q = qi;
725
endmodule
726
//////////////////////////////////////////////////////////////////////
727
////                                                              ////
728
////  Versatile counter                                           ////
729
////                                                              ////
730
////  Description                                                 ////
731
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
732
////  counter                                                     ////
733
////                                                              ////
734
////  To Do:                                                      ////
735
////   - add LFSR with more taps                                  ////
736
////                                                              ////
737
////  Author(s):                                                  ////
738
////      - Michael Unneback, unneback@opencores.org              ////
739
////        ORSoC AB                                              ////
740
////                                                              ////
741
//////////////////////////////////////////////////////////////////////
742
////                                                              ////
743
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
744
////                                                              ////
745
//// This source file may be used and distributed without         ////
746
//// restriction provided that this copyright statement is not    ////
747
//// removed from the file and that any derivative work contains  ////
748
//// the original copyright notice and the associated disclaimer. ////
749
////                                                              ////
750
//// This source file is free software; you can redistribute it   ////
751
//// and/or modify it under the terms of the GNU Lesser General   ////
752
//// Public License as published by the Free Software Foundation; ////
753
//// either version 2.1 of the License, or (at your option) any   ////
754
//// later version.                                               ////
755
////                                                              ////
756
//// This source is distributed in the hope that it will be       ////
757
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
758
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
759
//// PURPOSE.  See the GNU Lesser General Public License for more ////
760
//// details.                                                     ////
761
////                                                              ////
762
//// You should have received a copy of the GNU Lesser General    ////
763
//// Public License along with this source; if not, download it   ////
764
//// from http://www.opencores.org/lgpl.shtml                     ////
765
////                                                              ////
766
//////////////////////////////////////////////////////////////////////
767
// binary counter
768 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
769 6 unneback
   parameter length = 4;
770
   input cke;
771
   output [length:1] q;
772
   input rst;
773
   input clk;
774
   parameter clear_value = 0;
775
   parameter set_value = 1;
776
   parameter wrap_value = 0;
777
   parameter level1_value = 15;
778
   reg  [length:1] qi;
779
   wire [length:1] q_next;
780
   assign q_next = qi + {{length-1{1'b0}},1'b1};
781
   always @ (posedge clk or posedge rst)
782
     if (rst)
783
       qi <= {length{1'b0}};
784
     else
785
     if (cke)
786
       qi <= q_next;
787
   assign q = qi;
788
endmodule
789
//////////////////////////////////////////////////////////////////////
790
////                                                              ////
791
////  Versatile counter                                           ////
792
////                                                              ////
793
////  Description                                                 ////
794
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
795
////  counter                                                     ////
796
////                                                              ////
797
////  To Do:                                                      ////
798
////   - add LFSR with more taps                                  ////
799
////                                                              ////
800
////  Author(s):                                                  ////
801
////      - Michael Unneback, unneback@opencores.org              ////
802
////        ORSoC AB                                              ////
803
////                                                              ////
804
//////////////////////////////////////////////////////////////////////
805
////                                                              ////
806
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
807
////                                                              ////
808
//// This source file may be used and distributed without         ////
809
//// restriction provided that this copyright statement is not    ////
810
//// removed from the file and that any derivative work contains  ////
811
//// the original copyright notice and the associated disclaimer. ////
812
////                                                              ////
813
//// This source file is free software; you can redistribute it   ////
814
//// and/or modify it under the terms of the GNU Lesser General   ////
815
//// Public License as published by the Free Software Foundation; ////
816
//// either version 2.1 of the License, or (at your option) any   ////
817
//// later version.                                               ////
818
////                                                              ////
819
//// This source is distributed in the hope that it will be       ////
820
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
821
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
822
//// PURPOSE.  See the GNU Lesser General Public License for more ////
823
//// details.                                                     ////
824
////                                                              ////
825
//// You should have received a copy of the GNU Lesser General    ////
826
//// Public License along with this source; if not, download it   ////
827
//// from http://www.opencores.org/lgpl.shtml                     ////
828
////                                                              ////
829
//////////////////////////////////////////////////////////////////////
830
// binary counter
831 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
832 6 unneback
   parameter length = 4;
833
   input clear;
834
   input cke;
835
   output [length:1] q;
836
   input rst;
837
   input clk;
838
   parameter clear_value = 0;
839
   parameter set_value = 1;
840
   parameter wrap_value = 0;
841
   parameter level1_value = 15;
842
   reg  [length:1] qi;
843
   wire [length:1] q_next;
844
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
845
   always @ (posedge clk or posedge rst)
846
     if (rst)
847
       qi <= {length{1'b0}};
848
     else
849
     if (cke)
850
       qi <= q_next;
851
   assign q = qi;
852
endmodule
853
//////////////////////////////////////////////////////////////////////
854
////                                                              ////
855
////  Versatile counter                                           ////
856
////                                                              ////
857
////  Description                                                 ////
858
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
859
////  counter                                                     ////
860
////                                                              ////
861
////  To Do:                                                      ////
862
////   - add LFSR with more taps                                  ////
863
////                                                              ////
864
////  Author(s):                                                  ////
865
////      - Michael Unneback, unneback@opencores.org              ////
866
////        ORSoC AB                                              ////
867
////                                                              ////
868
//////////////////////////////////////////////////////////////////////
869
////                                                              ////
870
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
871
////                                                              ////
872
//// This source file may be used and distributed without         ////
873
//// restriction provided that this copyright statement is not    ////
874
//// removed from the file and that any derivative work contains  ////
875
//// the original copyright notice and the associated disclaimer. ////
876
////                                                              ////
877
//// This source file is free software; you can redistribute it   ////
878
//// and/or modify it under the terms of the GNU Lesser General   ////
879
//// Public License as published by the Free Software Foundation; ////
880
//// either version 2.1 of the License, or (at your option) any   ////
881
//// later version.                                               ////
882
////                                                              ////
883
//// This source is distributed in the hope that it will be       ////
884
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
885
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
886
//// PURPOSE.  See the GNU Lesser General Public License for more ////
887
//// details.                                                     ////
888
////                                                              ////
889
//// You should have received a copy of the GNU Lesser General    ////
890
//// Public License along with this source; if not, download it   ////
891
//// from http://www.opencores.org/lgpl.shtml                     ////
892
////                                                              ////
893
//////////////////////////////////////////////////////////////////////
894
// binary counter
895 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
896
   parameter length = 4;
897
   input clear;
898
   input cke;
899
   output [length:1] q;
900
   output reg level1;
901
   output reg level2;
902
   input rst;
903
   input clk;
904
   parameter clear_value = 0;
905
   parameter set_value = 1;
906 30 unneback
   parameter wrap_value = 15;
907
   parameter level1_value = 8;
908
   parameter level2_value = 15;
909 29 unneback
   wire rew;
910 30 unneback
   assign rew = 1'b0;
911 29 unneback
   reg  [length:1] qi;
912
   wire [length:1] q_next;
913
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
914
   always @ (posedge clk or posedge rst)
915
     if (rst)
916
       qi <= {length{1'b0}};
917
     else
918
     if (cke)
919
       qi <= q_next;
920
   assign q = qi;
921
    always @ (posedge clk or posedge rst)
922
    if (rst)
923
        level1 <= 1'b0;
924
    else
925
    if (cke)
926
    if (clear)
927
        level1 <= 1'b0;
928
    else if (q_next == level1_value)
929
        level1 <= 1'b1;
930
    else if (qi == level1_value & rew)
931
        level1 <= 1'b0;
932
    always @ (posedge clk or posedge rst)
933
    if (rst)
934
        level2 <= 1'b0;
935
    else
936
    if (cke)
937
    if (clear)
938
        level2 <= 1'b0;
939
    else if (q_next == level2_value)
940
        level2 <= 1'b1;
941
    else if (qi == level2_value & rew)
942
        level2 <= 1'b0;
943
endmodule
944
//////////////////////////////////////////////////////////////////////
945
////                                                              ////
946
////  Versatile counter                                           ////
947
////                                                              ////
948
////  Description                                                 ////
949
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
950
////  counter                                                     ////
951
////                                                              ////
952
////  To Do:                                                      ////
953
////   - add LFSR with more taps                                  ////
954
////                                                              ////
955
////  Author(s):                                                  ////
956
////      - Michael Unneback, unneback@opencores.org              ////
957
////        ORSoC AB                                              ////
958
////                                                              ////
959
//////////////////////////////////////////////////////////////////////
960
////                                                              ////
961
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
962
////                                                              ////
963
//// This source file may be used and distributed without         ////
964
//// restriction provided that this copyright statement is not    ////
965
//// removed from the file and that any derivative work contains  ////
966
//// the original copyright notice and the associated disclaimer. ////
967
////                                                              ////
968
//// This source file is free software; you can redistribute it   ////
969
//// and/or modify it under the terms of the GNU Lesser General   ////
970
//// Public License as published by the Free Software Foundation; ////
971
//// either version 2.1 of the License, or (at your option) any   ////
972
//// later version.                                               ////
973
////                                                              ////
974
//// This source is distributed in the hope that it will be       ////
975
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
976
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
977
//// PURPOSE.  See the GNU Lesser General Public License for more ////
978
//// details.                                                     ////
979
////                                                              ////
980
//// You should have received a copy of the GNU Lesser General    ////
981
//// Public License along with this source; if not, download it   ////
982
//// from http://www.opencores.org/lgpl.shtml                     ////
983
////                                                              ////
984
//////////////////////////////////////////////////////////////////////
985
// binary counter
986 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
987 6 unneback
   parameter length = 4;
988
   input clear;
989
   input set;
990
   input cke;
991
   input rew;
992
   output [length:1] q;
993
   input rst;
994
   input clk;
995
   parameter clear_value = 0;
996
   parameter set_value = 1;
997
   parameter wrap_value = 0;
998
   parameter level1_value = 15;
999
   reg  [length:1] qi;
1000
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1001
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1002
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1003
   assign q_next = rew ? q_next_rew : q_next_fw;
1004
   always @ (posedge clk or posedge rst)
1005
     if (rst)
1006
       qi <= {length{1'b0}};
1007
     else
1008
     if (cke)
1009
       qi <= q_next;
1010
   assign q = qi;
1011
endmodule
1012
//////////////////////////////////////////////////////////////////////
1013
////                                                              ////
1014
////  Versatile counter                                           ////
1015
////                                                              ////
1016
////  Description                                                 ////
1017
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1018
////  counter                                                     ////
1019
////                                                              ////
1020
////  To Do:                                                      ////
1021
////   - add LFSR with more taps                                  ////
1022
////                                                              ////
1023
////  Author(s):                                                  ////
1024
////      - Michael Unneback, unneback@opencores.org              ////
1025
////        ORSoC AB                                              ////
1026
////                                                              ////
1027
//////////////////////////////////////////////////////////////////////
1028
////                                                              ////
1029
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1030
////                                                              ////
1031
//// This source file may be used and distributed without         ////
1032
//// restriction provided that this copyright statement is not    ////
1033
//// removed from the file and that any derivative work contains  ////
1034
//// the original copyright notice and the associated disclaimer. ////
1035
////                                                              ////
1036
//// This source file is free software; you can redistribute it   ////
1037
//// and/or modify it under the terms of the GNU Lesser General   ////
1038
//// Public License as published by the Free Software Foundation; ////
1039
//// either version 2.1 of the License, or (at your option) any   ////
1040
//// later version.                                               ////
1041
////                                                              ////
1042
//// This source is distributed in the hope that it will be       ////
1043
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1044
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1045
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1046
//// details.                                                     ////
1047
////                                                              ////
1048
//// You should have received a copy of the GNU Lesser General    ////
1049
//// Public License along with this source; if not, download it   ////
1050
//// from http://www.opencores.org/lgpl.shtml                     ////
1051
////                                                              ////
1052
//////////////////////////////////////////////////////////////////////
1053
// binary counter
1054 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1055 6 unneback
   parameter length = 4;
1056
   input cke;
1057
   input rew;
1058
   output reg level1;
1059
   input rst;
1060
   input clk;
1061
   parameter clear_value = 0;
1062
   parameter set_value = 1;
1063
   parameter wrap_value = 1;
1064
   parameter level1_value = 15;
1065 29 unneback
   wire clear;
1066 30 unneback
   assign clear = 1'b0;
1067 6 unneback
   reg  [length:1] qi;
1068
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1069
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1070
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1071
   assign q_next = rew ? q_next_rew : q_next_fw;
1072
   always @ (posedge clk or posedge rst)
1073
     if (rst)
1074
       qi <= {length{1'b0}};
1075
     else
1076
     if (cke)
1077
       qi <= q_next;
1078
    always @ (posedge clk or posedge rst)
1079
    if (rst)
1080
        level1 <= 1'b0;
1081
    else
1082
    if (cke)
1083 29 unneback
    if (clear)
1084
        level1 <= 1'b0;
1085
    else if (q_next == level1_value)
1086 6 unneback
        level1 <= 1'b1;
1087
    else if (qi == level1_value & rew)
1088
        level1 <= 1'b0;
1089
endmodule
1090
//////////////////////////////////////////////////////////////////////
1091
////                                                              ////
1092
////  Versatile counter                                           ////
1093
////                                                              ////
1094
////  Description                                                 ////
1095
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1096
////  counter                                                     ////
1097
////                                                              ////
1098
////  To Do:                                                      ////
1099
////   - add LFSR with more taps                                  ////
1100
////                                                              ////
1101
////  Author(s):                                                  ////
1102
////      - Michael Unneback, unneback@opencores.org              ////
1103
////        ORSoC AB                                              ////
1104
////                                                              ////
1105
//////////////////////////////////////////////////////////////////////
1106
////                                                              ////
1107
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1108
////                                                              ////
1109
//// This source file may be used and distributed without         ////
1110
//// restriction provided that this copyright statement is not    ////
1111
//// removed from the file and that any derivative work contains  ////
1112
//// the original copyright notice and the associated disclaimer. ////
1113
////                                                              ////
1114
//// This source file is free software; you can redistribute it   ////
1115
//// and/or modify it under the terms of the GNU Lesser General   ////
1116
//// Public License as published by the Free Software Foundation; ////
1117
//// either version 2.1 of the License, or (at your option) any   ////
1118
//// later version.                                               ////
1119
////                                                              ////
1120
//// This source is distributed in the hope that it will be       ////
1121
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1122
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1123
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1124
//// details.                                                     ////
1125
////                                                              ////
1126
//// You should have received a copy of the GNU Lesser General    ////
1127
//// Public License along with this source; if not, download it   ////
1128
//// from http://www.opencores.org/lgpl.shtml                     ////
1129
////                                                              ////
1130
//////////////////////////////////////////////////////////////////////
1131 25 unneback
// binary counter
1132
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1133
   parameter length = 4;
1134
   input cke;
1135
   input rew;
1136
   output reg zq;
1137
   output reg level1;
1138
   input rst;
1139
   input clk;
1140
   parameter clear_value = 0;
1141
   parameter set_value = 1;
1142
   parameter wrap_value = 1;
1143
   parameter level1_value = 15;
1144 29 unneback
   wire clear;
1145 30 unneback
   assign clear = 1'b0;
1146 25 unneback
   reg  [length:1] qi;
1147
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1148
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1149
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1150
   assign q_next = rew ? q_next_rew : q_next_fw;
1151
   always @ (posedge clk or posedge rst)
1152
     if (rst)
1153
       qi <= {length{1'b0}};
1154
     else
1155
     if (cke)
1156
       qi <= q_next;
1157
   always @ (posedge clk or posedge rst)
1158
     if (rst)
1159
       zq <= 1'b1;
1160
     else
1161
     if (cke)
1162
       zq <= q_next == {length{1'b0}};
1163
    always @ (posedge clk or posedge rst)
1164
    if (rst)
1165
        level1 <= 1'b0;
1166
    else
1167
    if (cke)
1168 29 unneback
    if (clear)
1169
        level1 <= 1'b0;
1170
    else if (q_next == level1_value)
1171 25 unneback
        level1 <= 1'b1;
1172
    else if (qi == level1_value & rew)
1173
        level1 <= 1'b0;
1174
endmodule
1175
//////////////////////////////////////////////////////////////////////
1176
////                                                              ////
1177
////  Versatile counter                                           ////
1178
////                                                              ////
1179
////  Description                                                 ////
1180
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1181
////  counter                                                     ////
1182
////                                                              ////
1183
////  To Do:                                                      ////
1184
////   - add LFSR with more taps                                  ////
1185
////                                                              ////
1186
////  Author(s):                                                  ////
1187
////      - Michael Unneback, unneback@opencores.org              ////
1188
////        ORSoC AB                                              ////
1189
////                                                              ////
1190
//////////////////////////////////////////////////////////////////////
1191
////                                                              ////
1192
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1193
////                                                              ////
1194
//// This source file may be used and distributed without         ////
1195
//// restriction provided that this copyright statement is not    ////
1196
//// removed from the file and that any derivative work contains  ////
1197
//// the original copyright notice and the associated disclaimer. ////
1198
////                                                              ////
1199
//// This source file is free software; you can redistribute it   ////
1200
//// and/or modify it under the terms of the GNU Lesser General   ////
1201
//// Public License as published by the Free Software Foundation; ////
1202
//// either version 2.1 of the License, or (at your option) any   ////
1203
//// later version.                                               ////
1204
////                                                              ////
1205
//// This source is distributed in the hope that it will be       ////
1206
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1207
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1208
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1209
//// details.                                                     ////
1210
////                                                              ////
1211
//// You should have received a copy of the GNU Lesser General    ////
1212
//// Public License along with this source; if not, download it   ////
1213
//// from http://www.opencores.org/lgpl.shtml                     ////
1214
////                                                              ////
1215
//////////////////////////////////////////////////////////////////////
1216
// binary counter
1217
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1218
   parameter length = 4;
1219
   input cke;
1220
   input rew;
1221
   output [length:1] q;
1222
   output reg zq;
1223
   output reg level1;
1224
   input rst;
1225
   input clk;
1226
   parameter clear_value = 0;
1227
   parameter set_value = 1;
1228
   parameter wrap_value = 1;
1229
   parameter level1_value = 15;
1230 29 unneback
   wire clear;
1231 30 unneback
   assign clear = 1'b0;
1232 25 unneback
   reg  [length:1] qi;
1233
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1234
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1235
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1236
   assign q_next = rew ? q_next_rew : q_next_fw;
1237
   always @ (posedge clk or posedge rst)
1238
     if (rst)
1239
       qi <= {length{1'b0}};
1240
     else
1241
     if (cke)
1242
       qi <= q_next;
1243
   assign q = qi;
1244
   always @ (posedge clk or posedge rst)
1245
     if (rst)
1246
       zq <= 1'b1;
1247
     else
1248
     if (cke)
1249
       zq <= q_next == {length{1'b0}};
1250
    always @ (posedge clk or posedge rst)
1251
    if (rst)
1252
        level1 <= 1'b0;
1253
    else
1254
    if (cke)
1255 29 unneback
    if (clear)
1256
        level1 <= 1'b0;
1257
    else if (q_next == level1_value)
1258 25 unneback
        level1 <= 1'b1;
1259
    else if (qi == level1_value & rew)
1260
        level1 <= 1'b0;
1261
endmodule
1262
//////////////////////////////////////////////////////////////////////
1263
////                                                              ////
1264
////  Versatile counter                                           ////
1265
////                                                              ////
1266
////  Description                                                 ////
1267
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1268
////  counter                                                     ////
1269
////                                                              ////
1270
////  To Do:                                                      ////
1271
////   - add LFSR with more taps                                  ////
1272
////                                                              ////
1273
////  Author(s):                                                  ////
1274
////      - Michael Unneback, unneback@opencores.org              ////
1275
////        ORSoC AB                                              ////
1276
////                                                              ////
1277
//////////////////////////////////////////////////////////////////////
1278
////                                                              ////
1279
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1280
////                                                              ////
1281
//// This source file may be used and distributed without         ////
1282
//// restriction provided that this copyright statement is not    ////
1283
//// removed from the file and that any derivative work contains  ////
1284
//// the original copyright notice and the associated disclaimer. ////
1285
////                                                              ////
1286
//// This source file is free software; you can redistribute it   ////
1287
//// and/or modify it under the terms of the GNU Lesser General   ////
1288
//// Public License as published by the Free Software Foundation; ////
1289
//// either version 2.1 of the License, or (at your option) any   ////
1290
//// later version.                                               ////
1291
////                                                              ////
1292
//// This source is distributed in the hope that it will be       ////
1293
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1294
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1295
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1296
//// details.                                                     ////
1297
////                                                              ////
1298
//// You should have received a copy of the GNU Lesser General    ////
1299
//// Public License along with this source; if not, download it   ////
1300
//// from http://www.opencores.org/lgpl.shtml                     ////
1301
////                                                              ////
1302
//////////////////////////////////////////////////////////////////////
1303 6 unneback
// LFSR counter
1304 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1305 6 unneback
   parameter length = 4;
1306
   output reg zq;
1307
   input rst;
1308
   input clk;
1309
   parameter clear_value = 0;
1310
   parameter set_value = 1;
1311
   parameter wrap_value = 8;
1312
   parameter level1_value = 15;
1313
   reg  [length:1] qi;
1314
   reg lfsr_fb;
1315
   wire [length:1] q_next;
1316
   reg [32:1] polynom;
1317
   integer i;
1318
   always @ (qi)
1319
   begin
1320
        case (length)
1321
         2: polynom = 32'b11;                               // 0x3
1322
         3: polynom = 32'b110;                              // 0x6
1323
         4: polynom = 32'b1100;                             // 0xC
1324
         5: polynom = 32'b10100;                            // 0x14
1325
         6: polynom = 32'b110000;                           // 0x30
1326
         7: polynom = 32'b1100000;                          // 0x60
1327
         8: polynom = 32'b10111000;                         // 0xb8
1328
         9: polynom = 32'b100010000;                        // 0x110
1329
        10: polynom = 32'b1001000000;                       // 0x240
1330
        11: polynom = 32'b10100000000;                      // 0x500
1331
        12: polynom = 32'b100000101001;                     // 0x829
1332
        13: polynom = 32'b1000000001100;                    // 0x100C
1333
        14: polynom = 32'b10000000010101;                   // 0x2015
1334
        15: polynom = 32'b110000000000000;                  // 0x6000
1335
        16: polynom = 32'b1101000000001000;                 // 0xD008
1336
        17: polynom = 32'b10010000000000000;                // 0x12000
1337
        18: polynom = 32'b100000010000000000;               // 0x20400
1338
        19: polynom = 32'b1000000000000100011;              // 0x40023
1339
        20: polynom = 32'b10000010000000000000;             // 0x82000
1340
        21: polynom = 32'b101000000000000000000;            // 0x140000
1341
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1342
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1343
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1344
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1345
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1346
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1347
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1348
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1349
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1350
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1351
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1352
        default: polynom = 32'b0;
1353
        endcase
1354
        lfsr_fb = qi[length];
1355
        for (i=length-1; i>=1; i=i-1) begin
1356
            if (polynom[i])
1357
                lfsr_fb = lfsr_fb  ~^ qi[i];
1358
        end
1359
    end
1360
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1361
   always @ (posedge clk or posedge rst)
1362
     if (rst)
1363
       qi <= {length{1'b0}};
1364
     else
1365
       qi <= q_next;
1366
   always @ (posedge clk or posedge rst)
1367
     if (rst)
1368
       zq <= 1'b1;
1369
     else
1370
       zq <= q_next == {length{1'b0}};
1371
endmodule
1372
//////////////////////////////////////////////////////////////////////
1373
////                                                              ////
1374
////  Versatile counter                                           ////
1375
////                                                              ////
1376
////  Description                                                 ////
1377
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1378
////  counter                                                     ////
1379
////                                                              ////
1380
////  To Do:                                                      ////
1381
////   - add LFSR with more taps                                  ////
1382
////                                                              ////
1383
////  Author(s):                                                  ////
1384
////      - Michael Unneback, unneback@opencores.org              ////
1385
////        ORSoC AB                                              ////
1386
////                                                              ////
1387
//////////////////////////////////////////////////////////////////////
1388
////                                                              ////
1389
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1390
////                                                              ////
1391
//// This source file may be used and distributed without         ////
1392
//// restriction provided that this copyright statement is not    ////
1393
//// removed from the file and that any derivative work contains  ////
1394
//// the original copyright notice and the associated disclaimer. ////
1395
////                                                              ////
1396
//// This source file is free software; you can redistribute it   ////
1397
//// and/or modify it under the terms of the GNU Lesser General   ////
1398
//// Public License as published by the Free Software Foundation; ////
1399
//// either version 2.1 of the License, or (at your option) any   ////
1400
//// later version.                                               ////
1401
////                                                              ////
1402
//// This source is distributed in the hope that it will be       ////
1403
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1404
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1405
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1406
//// details.                                                     ////
1407
////                                                              ////
1408
//// You should have received a copy of the GNU Lesser General    ////
1409
//// Public License along with this source; if not, download it   ////
1410
//// from http://www.opencores.org/lgpl.shtml                     ////
1411
////                                                              ////
1412
//////////////////////////////////////////////////////////////////////
1413
// LFSR counter
1414 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1415 6 unneback
   parameter length = 4;
1416
   input cke;
1417
   output reg zq;
1418
   input rst;
1419
   input clk;
1420
   parameter clear_value = 0;
1421
   parameter set_value = 1;
1422
   parameter wrap_value = 8;
1423
   parameter level1_value = 15;
1424
   reg  [length:1] qi;
1425
   reg lfsr_fb;
1426
   wire [length:1] q_next;
1427
   reg [32:1] polynom;
1428
   integer i;
1429
   always @ (qi)
1430
   begin
1431
        case (length)
1432
         2: polynom = 32'b11;                               // 0x3
1433
         3: polynom = 32'b110;                              // 0x6
1434
         4: polynom = 32'b1100;                             // 0xC
1435
         5: polynom = 32'b10100;                            // 0x14
1436
         6: polynom = 32'b110000;                           // 0x30
1437
         7: polynom = 32'b1100000;                          // 0x60
1438
         8: polynom = 32'b10111000;                         // 0xb8
1439
         9: polynom = 32'b100010000;                        // 0x110
1440
        10: polynom = 32'b1001000000;                       // 0x240
1441
        11: polynom = 32'b10100000000;                      // 0x500
1442
        12: polynom = 32'b100000101001;                     // 0x829
1443
        13: polynom = 32'b1000000001100;                    // 0x100C
1444
        14: polynom = 32'b10000000010101;                   // 0x2015
1445
        15: polynom = 32'b110000000000000;                  // 0x6000
1446
        16: polynom = 32'b1101000000001000;                 // 0xD008
1447
        17: polynom = 32'b10010000000000000;                // 0x12000
1448
        18: polynom = 32'b100000010000000000;               // 0x20400
1449
        19: polynom = 32'b1000000000000100011;              // 0x40023
1450
        20: polynom = 32'b10000010000000000000;             // 0x82000
1451
        21: polynom = 32'b101000000000000000000;            // 0x140000
1452
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1453
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1454
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1455
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1456
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1457
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1458
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1459
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1460
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1461
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1462
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1463
        default: polynom = 32'b0;
1464
        endcase
1465
        lfsr_fb = qi[length];
1466
        for (i=length-1; i>=1; i=i-1) begin
1467
            if (polynom[i])
1468
                lfsr_fb = lfsr_fb  ~^ qi[i];
1469
        end
1470
    end
1471
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1472
   always @ (posedge clk or posedge rst)
1473
     if (rst)
1474
       qi <= {length{1'b0}};
1475
     else
1476
     if (cke)
1477
       qi <= q_next;
1478
   always @ (posedge clk or posedge rst)
1479
     if (rst)
1480
       zq <= 1'b1;
1481
     else
1482
     if (cke)
1483
       zq <= q_next == {length{1'b0}};
1484
endmodule
1485
//////////////////////////////////////////////////////////////////////
1486
////                                                              ////
1487
////  Versatile counter                                           ////
1488
////                                                              ////
1489
////  Description                                                 ////
1490
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1491
////  counter                                                     ////
1492
////                                                              ////
1493
////  To Do:                                                      ////
1494
////   - add LFSR with more taps                                  ////
1495
////                                                              ////
1496
////  Author(s):                                                  ////
1497
////      - Michael Unneback, unneback@opencores.org              ////
1498
////        ORSoC AB                                              ////
1499
////                                                              ////
1500
//////////////////////////////////////////////////////////////////////
1501
////                                                              ////
1502
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1503
////                                                              ////
1504
//// This source file may be used and distributed without         ////
1505
//// restriction provided that this copyright statement is not    ////
1506
//// removed from the file and that any derivative work contains  ////
1507
//// the original copyright notice and the associated disclaimer. ////
1508
////                                                              ////
1509
//// This source file is free software; you can redistribute it   ////
1510
//// and/or modify it under the terms of the GNU Lesser General   ////
1511
//// Public License as published by the Free Software Foundation; ////
1512
//// either version 2.1 of the License, or (at your option) any   ////
1513
//// later version.                                               ////
1514
////                                                              ////
1515
//// This source is distributed in the hope that it will be       ////
1516
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1517
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1518
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1519
//// details.                                                     ////
1520
////                                                              ////
1521
//// You should have received a copy of the GNU Lesser General    ////
1522
//// Public License along with this source; if not, download it   ////
1523
//// from http://www.opencores.org/lgpl.shtml                     ////
1524
////                                                              ////
1525
//////////////////////////////////////////////////////////////////////
1526
// LFSR counter
1527 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1528
   parameter length = 4;
1529
   input cke;
1530
   output [length:1] q;
1531
   input rst;
1532
   input clk;
1533
   parameter clear_value = 0;
1534
   parameter set_value = 1;
1535
   parameter wrap_value = 8;
1536
   parameter level1_value = 15;
1537
   reg  [length:1] qi;
1538
   reg lfsr_fb;
1539
   wire [length:1] q_next;
1540
   reg [32:1] polynom;
1541
   integer i;
1542
   always @ (qi)
1543
   begin
1544
        case (length)
1545
         2: polynom = 32'b11;                               // 0x3
1546
         3: polynom = 32'b110;                              // 0x6
1547
         4: polynom = 32'b1100;                             // 0xC
1548
         5: polynom = 32'b10100;                            // 0x14
1549
         6: polynom = 32'b110000;                           // 0x30
1550
         7: polynom = 32'b1100000;                          // 0x60
1551
         8: polynom = 32'b10111000;                         // 0xb8
1552
         9: polynom = 32'b100010000;                        // 0x110
1553
        10: polynom = 32'b1001000000;                       // 0x240
1554
        11: polynom = 32'b10100000000;                      // 0x500
1555
        12: polynom = 32'b100000101001;                     // 0x829
1556
        13: polynom = 32'b1000000001100;                    // 0x100C
1557
        14: polynom = 32'b10000000010101;                   // 0x2015
1558
        15: polynom = 32'b110000000000000;                  // 0x6000
1559
        16: polynom = 32'b1101000000001000;                 // 0xD008
1560
        17: polynom = 32'b10010000000000000;                // 0x12000
1561
        18: polynom = 32'b100000010000000000;               // 0x20400
1562
        19: polynom = 32'b1000000000000100011;              // 0x40023
1563
        20: polynom = 32'b10000010000000000000;             // 0x82000
1564
        21: polynom = 32'b101000000000000000000;            // 0x140000
1565
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1566
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1567
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1568
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1569
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1570
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1571
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1572
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1573
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1574
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1575
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1576
        default: polynom = 32'b0;
1577
        endcase
1578
        lfsr_fb = qi[length];
1579
        for (i=length-1; i>=1; i=i-1) begin
1580
            if (polynom[i])
1581
                lfsr_fb = lfsr_fb  ~^ qi[i];
1582
        end
1583
    end
1584
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1585
   always @ (posedge clk or posedge rst)
1586
     if (rst)
1587
       qi <= {length{1'b0}};
1588
     else
1589
     if (cke)
1590
       qi <= q_next;
1591
   assign q = qi;
1592
endmodule
1593
//////////////////////////////////////////////////////////////////////
1594
////                                                              ////
1595
////  Versatile counter                                           ////
1596
////                                                              ////
1597
////  Description                                                 ////
1598
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1599
////  counter                                                     ////
1600
////                                                              ////
1601
////  To Do:                                                      ////
1602
////   - add LFSR with more taps                                  ////
1603
////                                                              ////
1604
////  Author(s):                                                  ////
1605
////      - Michael Unneback, unneback@opencores.org              ////
1606
////        ORSoC AB                                              ////
1607
////                                                              ////
1608
//////////////////////////////////////////////////////////////////////
1609
////                                                              ////
1610
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1611
////                                                              ////
1612
//// This source file may be used and distributed without         ////
1613
//// restriction provided that this copyright statement is not    ////
1614
//// removed from the file and that any derivative work contains  ////
1615
//// the original copyright notice and the associated disclaimer. ////
1616
////                                                              ////
1617
//// This source file is free software; you can redistribute it   ////
1618
//// and/or modify it under the terms of the GNU Lesser General   ////
1619
//// Public License as published by the Free Software Foundation; ////
1620
//// either version 2.1 of the License, or (at your option) any   ////
1621
//// later version.                                               ////
1622
////                                                              ////
1623
//// This source is distributed in the hope that it will be       ////
1624
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1625
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1626
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1627
//// details.                                                     ////
1628
////                                                              ////
1629
//// You should have received a copy of the GNU Lesser General    ////
1630
//// Public License along with this source; if not, download it   ////
1631
//// from http://www.opencores.org/lgpl.shtml                     ////
1632
////                                                              ////
1633
//////////////////////////////////////////////////////////////////////
1634
// LFSR counter
1635
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1636
   parameter length = 4;
1637
   input clear;
1638
   input cke;
1639
   output [length:1] q;
1640
   input rst;
1641
   input clk;
1642
   parameter clear_value = 0;
1643
   parameter set_value = 1;
1644
   parameter wrap_value = 8;
1645
   parameter level1_value = 15;
1646
   reg  [length:1] qi;
1647
   reg lfsr_fb;
1648
   wire [length:1] q_next;
1649
   reg [32:1] polynom;
1650
   integer i;
1651
   always @ (qi)
1652
   begin
1653
        case (length)
1654
         2: polynom = 32'b11;                               // 0x3
1655
         3: polynom = 32'b110;                              // 0x6
1656
         4: polynom = 32'b1100;                             // 0xC
1657
         5: polynom = 32'b10100;                            // 0x14
1658
         6: polynom = 32'b110000;                           // 0x30
1659
         7: polynom = 32'b1100000;                          // 0x60
1660
         8: polynom = 32'b10111000;                         // 0xb8
1661
         9: polynom = 32'b100010000;                        // 0x110
1662
        10: polynom = 32'b1001000000;                       // 0x240
1663
        11: polynom = 32'b10100000000;                      // 0x500
1664
        12: polynom = 32'b100000101001;                     // 0x829
1665
        13: polynom = 32'b1000000001100;                    // 0x100C
1666
        14: polynom = 32'b10000000010101;                   // 0x2015
1667
        15: polynom = 32'b110000000000000;                  // 0x6000
1668
        16: polynom = 32'b1101000000001000;                 // 0xD008
1669
        17: polynom = 32'b10010000000000000;                // 0x12000
1670
        18: polynom = 32'b100000010000000000;               // 0x20400
1671
        19: polynom = 32'b1000000000000100011;              // 0x40023
1672
        20: polynom = 32'b10000010000000000000;             // 0x82000
1673
        21: polynom = 32'b101000000000000000000;            // 0x140000
1674
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1675
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1676
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1677
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1678
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1679
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1680
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1681
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1682
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1683
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1684
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1685
        default: polynom = 32'b0;
1686
        endcase
1687
        lfsr_fb = qi[length];
1688
        for (i=length-1; i>=1; i=i-1) begin
1689
            if (polynom[i])
1690
                lfsr_fb = lfsr_fb  ~^ qi[i];
1691
        end
1692
    end
1693
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1694
   always @ (posedge clk or posedge rst)
1695
     if (rst)
1696
       qi <= {length{1'b0}};
1697
     else
1698
     if (cke)
1699
       qi <= q_next;
1700
   assign q = qi;
1701
endmodule
1702
//////////////////////////////////////////////////////////////////////
1703
////                                                              ////
1704
////  Versatile counter                                           ////
1705
////                                                              ////
1706
////  Description                                                 ////
1707
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1708
////  counter                                                     ////
1709
////                                                              ////
1710
////  To Do:                                                      ////
1711
////   - add LFSR with more taps                                  ////
1712
////                                                              ////
1713
////  Author(s):                                                  ////
1714
////      - Michael Unneback, unneback@opencores.org              ////
1715
////        ORSoC AB                                              ////
1716
////                                                              ////
1717
//////////////////////////////////////////////////////////////////////
1718
////                                                              ////
1719
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1720
////                                                              ////
1721
//// This source file may be used and distributed without         ////
1722
//// restriction provided that this copyright statement is not    ////
1723
//// removed from the file and that any derivative work contains  ////
1724
//// the original copyright notice and the associated disclaimer. ////
1725
////                                                              ////
1726
//// This source file is free software; you can redistribute it   ////
1727
//// and/or modify it under the terms of the GNU Lesser General   ////
1728
//// Public License as published by the Free Software Foundation; ////
1729
//// either version 2.1 of the License, or (at your option) any   ////
1730
//// later version.                                               ////
1731
////                                                              ////
1732
//// This source is distributed in the hope that it will be       ////
1733
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1734
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1735
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1736
//// details.                                                     ////
1737
////                                                              ////
1738
//// You should have received a copy of the GNU Lesser General    ////
1739
//// Public License along with this source; if not, download it   ////
1740
//// from http://www.opencores.org/lgpl.shtml                     ////
1741
////                                                              ////
1742
//////////////////////////////////////////////////////////////////////
1743
// LFSR counter
1744 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1745
   parameter length = 4;
1746
   input cke;
1747
   output [length:1] q;
1748
   output reg zq;
1749
   input rst;
1750
   input clk;
1751
   parameter clear_value = 0;
1752
   parameter set_value = 1;
1753
   parameter wrap_value = 8;
1754
   parameter level1_value = 15;
1755
   reg  [length:1] qi;
1756
   reg lfsr_fb;
1757
   wire [length:1] q_next;
1758
   reg [32:1] polynom;
1759
   integer i;
1760
   always @ (qi)
1761
   begin
1762
        case (length)
1763
         2: polynom = 32'b11;                               // 0x3
1764
         3: polynom = 32'b110;                              // 0x6
1765
         4: polynom = 32'b1100;                             // 0xC
1766
         5: polynom = 32'b10100;                            // 0x14
1767
         6: polynom = 32'b110000;                           // 0x30
1768
         7: polynom = 32'b1100000;                          // 0x60
1769
         8: polynom = 32'b10111000;                         // 0xb8
1770
         9: polynom = 32'b100010000;                        // 0x110
1771
        10: polynom = 32'b1001000000;                       // 0x240
1772
        11: polynom = 32'b10100000000;                      // 0x500
1773
        12: polynom = 32'b100000101001;                     // 0x829
1774
        13: polynom = 32'b1000000001100;                    // 0x100C
1775
        14: polynom = 32'b10000000010101;                   // 0x2015
1776
        15: polynom = 32'b110000000000000;                  // 0x6000
1777
        16: polynom = 32'b1101000000001000;                 // 0xD008
1778
        17: polynom = 32'b10010000000000000;                // 0x12000
1779
        18: polynom = 32'b100000010000000000;               // 0x20400
1780
        19: polynom = 32'b1000000000000100011;              // 0x40023
1781
        20: polynom = 32'b10000010000000000000;             // 0x82000
1782
        21: polynom = 32'b101000000000000000000;            // 0x140000
1783
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1784
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1785
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1786
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1787
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1788
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1789
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1790
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1791
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1792
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1793
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1794
        default: polynom = 32'b0;
1795
        endcase
1796
        lfsr_fb = qi[length];
1797
        for (i=length-1; i>=1; i=i-1) begin
1798
            if (polynom[i])
1799
                lfsr_fb = lfsr_fb  ~^ qi[i];
1800
        end
1801
    end
1802
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1803
   always @ (posedge clk or posedge rst)
1804
     if (rst)
1805
       qi <= {length{1'b0}};
1806
     else
1807
     if (cke)
1808
       qi <= q_next;
1809
   assign q = qi;
1810
   always @ (posedge clk or posedge rst)
1811
     if (rst)
1812
       zq <= 1'b1;
1813
     else
1814
     if (cke)
1815
       zq <= q_next == {length{1'b0}};
1816
endmodule
1817
//////////////////////////////////////////////////////////////////////
1818
////                                                              ////
1819
////  Versatile counter                                           ////
1820
////                                                              ////
1821
////  Description                                                 ////
1822
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1823
////  counter                                                     ////
1824
////                                                              ////
1825
////  To Do:                                                      ////
1826
////   - add LFSR with more taps                                  ////
1827
////                                                              ////
1828
////  Author(s):                                                  ////
1829
////      - Michael Unneback, unneback@opencores.org              ////
1830
////        ORSoC AB                                              ////
1831
////                                                              ////
1832
//////////////////////////////////////////////////////////////////////
1833
////                                                              ////
1834
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1835
////                                                              ////
1836
//// This source file may be used and distributed without         ////
1837
//// restriction provided that this copyright statement is not    ////
1838
//// removed from the file and that any derivative work contains  ////
1839
//// the original copyright notice and the associated disclaimer. ////
1840
////                                                              ////
1841
//// This source file is free software; you can redistribute it   ////
1842
//// and/or modify it under the terms of the GNU Lesser General   ////
1843
//// Public License as published by the Free Software Foundation; ////
1844
//// either version 2.1 of the License, or (at your option) any   ////
1845
//// later version.                                               ////
1846
////                                                              ////
1847
//// This source is distributed in the hope that it will be       ////
1848
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1849
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1850
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1851
//// details.                                                     ////
1852
////                                                              ////
1853
//// You should have received a copy of the GNU Lesser General    ////
1854
//// Public License along with this source; if not, download it   ////
1855
//// from http://www.opencores.org/lgpl.shtml                     ////
1856
////                                                              ////
1857
//////////////////////////////////////////////////////////////////////
1858
// LFSR counter
1859 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1860 6 unneback
   parameter length = 4;
1861
   input cke;
1862
   input rew;
1863
   output reg level1;
1864
   input rst;
1865
   input clk;
1866
   parameter clear_value = 0;
1867
   parameter set_value = 1;
1868
   parameter wrap_value = 8;
1869
   parameter level1_value = 15;
1870 29 unneback
   wire clear;
1871 30 unneback
   assign clear = 1'b0;
1872 6 unneback
   reg  [length:1] qi;
1873
   reg lfsr_fb, lfsr_fb_rew;
1874
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1875
   reg [32:1] polynom_rew;
1876
   integer j;
1877
   reg [32:1] polynom;
1878
   integer i;
1879
   always @ (qi)
1880
   begin
1881
        case (length)
1882
         2: polynom = 32'b11;                               // 0x3
1883
         3: polynom = 32'b110;                              // 0x6
1884
         4: polynom = 32'b1100;                             // 0xC
1885
         5: polynom = 32'b10100;                            // 0x14
1886
         6: polynom = 32'b110000;                           // 0x30
1887
         7: polynom = 32'b1100000;                          // 0x60
1888
         8: polynom = 32'b10111000;                         // 0xb8
1889
         9: polynom = 32'b100010000;                        // 0x110
1890
        10: polynom = 32'b1001000000;                       // 0x240
1891
        11: polynom = 32'b10100000000;                      // 0x500
1892
        12: polynom = 32'b100000101001;                     // 0x829
1893
        13: polynom = 32'b1000000001100;                    // 0x100C
1894
        14: polynom = 32'b10000000010101;                   // 0x2015
1895
        15: polynom = 32'b110000000000000;                  // 0x6000
1896
        16: polynom = 32'b1101000000001000;                 // 0xD008
1897
        17: polynom = 32'b10010000000000000;                // 0x12000
1898
        18: polynom = 32'b100000010000000000;               // 0x20400
1899
        19: polynom = 32'b1000000000000100011;              // 0x40023
1900
        20: polynom = 32'b10000010000000000000;             // 0x82000
1901
        21: polynom = 32'b101000000000000000000;            // 0x140000
1902
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1903
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1904
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1905
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1906
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1907
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1908
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1909
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1910
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1911
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1912
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1913
        default: polynom = 32'b0;
1914
        endcase
1915
        lfsr_fb = qi[length];
1916
        for (i=length-1; i>=1; i=i-1) begin
1917
            if (polynom[i])
1918
                lfsr_fb = lfsr_fb  ~^ qi[i];
1919
        end
1920
    end
1921
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1922
   always @ (qi)
1923
   begin
1924
        case (length)
1925
         2: polynom_rew = 32'b11;
1926
         3: polynom_rew = 32'b110;
1927
         4: polynom_rew = 32'b1100;
1928
         5: polynom_rew = 32'b10100;
1929
         6: polynom_rew = 32'b110000;
1930
         7: polynom_rew = 32'b1100000;
1931
         8: polynom_rew = 32'b10111000;
1932
         9: polynom_rew = 32'b100010000;
1933
        10: polynom_rew = 32'b1001000000;
1934
        11: polynom_rew = 32'b10100000000;
1935
        12: polynom_rew = 32'b100000101001;
1936
        13: polynom_rew = 32'b1000000001100;
1937
        14: polynom_rew = 32'b10000000010101;
1938
        15: polynom_rew = 32'b110000000000000;
1939
        16: polynom_rew = 32'b1101000000001000;
1940
        17: polynom_rew = 32'b10010000000000000;
1941
        18: polynom_rew = 32'b100000010000000000;
1942
        19: polynom_rew = 32'b1000000000000100011;
1943
        20: polynom_rew = 32'b10000010000000000000;
1944
        21: polynom_rew = 32'b101000000000000000000;
1945
        22: polynom_rew = 32'b1100000000000000000000;
1946
        23: polynom_rew = 32'b10000100000000000000000;
1947
        24: polynom_rew = 32'b111000010000000000000000;
1948
        25: polynom_rew = 32'b1001000000000000000000000;
1949
        26: polynom_rew = 32'b10000000000000000000100011;
1950
        27: polynom_rew = 32'b100000000000000000000010011;
1951
        28: polynom_rew = 32'b1100100000000000000000000000;
1952
        29: polynom_rew = 32'b10100000000000000000000000000;
1953
        30: polynom_rew = 32'b100000000000000000000000101001;
1954
        31: polynom_rew = 32'b1001000000000000000000000000000;
1955
        32: polynom_rew = 32'b10000000001000000000000000000011;
1956
        default: polynom_rew = 32'b0;
1957
        endcase
1958
        // rotate left
1959
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1960
        lfsr_fb_rew = qi[length];
1961
        for (i=length-1; i>=1; i=i-1) begin
1962
            if (polynom_rew[i])
1963
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1964
        end
1965
    end
1966
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1967
   assign q_next = rew ? q_next_rew : q_next_fw;
1968
   always @ (posedge clk or posedge rst)
1969
     if (rst)
1970
       qi <= {length{1'b0}};
1971
     else
1972
     if (cke)
1973
       qi <= q_next;
1974
    always @ (posedge clk or posedge rst)
1975
    if (rst)
1976
        level1 <= 1'b0;
1977
    else
1978
    if (cke)
1979 29 unneback
    if (clear)
1980
        level1 <= 1'b0;
1981
    else if (q_next == level1_value)
1982 6 unneback
        level1 <= 1'b1;
1983
    else if (qi == level1_value & rew)
1984
        level1 <= 1'b0;
1985
endmodule
1986
//////////////////////////////////////////////////////////////////////
1987
////                                                              ////
1988
////  Versatile counter                                           ////
1989
////                                                              ////
1990
////  Description                                                 ////
1991
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1992
////  counter                                                     ////
1993
////                                                              ////
1994
////  To Do:                                                      ////
1995
////   - add LFSR with more taps                                  ////
1996
////                                                              ////
1997
////  Author(s):                                                  ////
1998
////      - Michael Unneback, unneback@opencores.org              ////
1999
////        ORSoC AB                                              ////
2000
////                                                              ////
2001
//////////////////////////////////////////////////////////////////////
2002
////                                                              ////
2003
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2004
////                                                              ////
2005
//// This source file may be used and distributed without         ////
2006
//// restriction provided that this copyright statement is not    ////
2007
//// removed from the file and that any derivative work contains  ////
2008
//// the original copyright notice and the associated disclaimer. ////
2009
////                                                              ////
2010
//// This source file is free software; you can redistribute it   ////
2011
//// and/or modify it under the terms of the GNU Lesser General   ////
2012
//// Public License as published by the Free Software Foundation; ////
2013
//// either version 2.1 of the License, or (at your option) any   ////
2014
//// later version.                                               ////
2015
////                                                              ////
2016
//// This source is distributed in the hope that it will be       ////
2017
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2018
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2019
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2020
//// details.                                                     ////
2021
////                                                              ////
2022
//// You should have received a copy of the GNU Lesser General    ////
2023
//// Public License along with this source; if not, download it   ////
2024
//// from http://www.opencores.org/lgpl.shtml                     ////
2025
////                                                              ////
2026
//////////////////////////////////////////////////////////////////////
2027
// GRAY counter
2028 18 unneback
module vl_cnt_gray ( q, rst, clk);
2029 6 unneback
   parameter length = 4;
2030
   output reg [length:1] q;
2031
   input rst;
2032
   input clk;
2033
   parameter clear_value = 0;
2034
   parameter set_value = 1;
2035
   parameter wrap_value = 8;
2036
   parameter level1_value = 15;
2037
   reg  [length:1] qi;
2038
   wire [length:1] q_next;
2039
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2040
   always @ (posedge clk or posedge rst)
2041
     if (rst)
2042
       qi <= {length{1'b0}};
2043
     else
2044
       qi <= q_next;
2045
   always @ (posedge clk or posedge rst)
2046
     if (rst)
2047
       q <= {length{1'b0}};
2048
     else
2049
         q <= (q_next>>1) ^ q_next;
2050
endmodule
2051
//////////////////////////////////////////////////////////////////////
2052
////                                                              ////
2053
////  Versatile counter                                           ////
2054
////                                                              ////
2055
////  Description                                                 ////
2056
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2057
////  counter                                                     ////
2058
////                                                              ////
2059
////  To Do:                                                      ////
2060
////   - add LFSR with more taps                                  ////
2061
////                                                              ////
2062
////  Author(s):                                                  ////
2063
////      - Michael Unneback, unneback@opencores.org              ////
2064
////        ORSoC AB                                              ////
2065
////                                                              ////
2066
//////////////////////////////////////////////////////////////////////
2067
////                                                              ////
2068
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2069
////                                                              ////
2070
//// This source file may be used and distributed without         ////
2071
//// restriction provided that this copyright statement is not    ////
2072
//// removed from the file and that any derivative work contains  ////
2073
//// the original copyright notice and the associated disclaimer. ////
2074
////                                                              ////
2075
//// This source file is free software; you can redistribute it   ////
2076
//// and/or modify it under the terms of the GNU Lesser General   ////
2077
//// Public License as published by the Free Software Foundation; ////
2078
//// either version 2.1 of the License, or (at your option) any   ////
2079
//// later version.                                               ////
2080
////                                                              ////
2081
//// This source is distributed in the hope that it will be       ////
2082
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2083
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2084
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2085
//// details.                                                     ////
2086
////                                                              ////
2087
//// You should have received a copy of the GNU Lesser General    ////
2088
//// Public License along with this source; if not, download it   ////
2089
//// from http://www.opencores.org/lgpl.shtml                     ////
2090
////                                                              ////
2091
//////////////////////////////////////////////////////////////////////
2092
// GRAY counter
2093 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2094 6 unneback
   parameter length = 4;
2095
   input cke;
2096
   output reg [length:1] q;
2097
   input rst;
2098
   input clk;
2099
   parameter clear_value = 0;
2100
   parameter set_value = 1;
2101
   parameter wrap_value = 8;
2102
   parameter level1_value = 15;
2103
   reg  [length:1] qi;
2104
   wire [length:1] q_next;
2105
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2106
   always @ (posedge clk or posedge rst)
2107
     if (rst)
2108
       qi <= {length{1'b0}};
2109
     else
2110
     if (cke)
2111
       qi <= q_next;
2112
   always @ (posedge clk or posedge rst)
2113
     if (rst)
2114
       q <= {length{1'b0}};
2115
     else
2116
       if (cke)
2117
         q <= (q_next>>1) ^ q_next;
2118
endmodule
2119
//////////////////////////////////////////////////////////////////////
2120
////                                                              ////
2121
////  Versatile counter                                           ////
2122
////                                                              ////
2123
////  Description                                                 ////
2124
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2125
////  counter                                                     ////
2126
////                                                              ////
2127
////  To Do:                                                      ////
2128
////   - add LFSR with more taps                                  ////
2129
////                                                              ////
2130
////  Author(s):                                                  ////
2131
////      - Michael Unneback, unneback@opencores.org              ////
2132
////        ORSoC AB                                              ////
2133
////                                                              ////
2134
//////////////////////////////////////////////////////////////////////
2135
////                                                              ////
2136
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2137
////                                                              ////
2138
//// This source file may be used and distributed without         ////
2139
//// restriction provided that this copyright statement is not    ////
2140
//// removed from the file and that any derivative work contains  ////
2141
//// the original copyright notice and the associated disclaimer. ////
2142
////                                                              ////
2143
//// This source file is free software; you can redistribute it   ////
2144
//// and/or modify it under the terms of the GNU Lesser General   ////
2145
//// Public License as published by the Free Software Foundation; ////
2146
//// either version 2.1 of the License, or (at your option) any   ////
2147
//// later version.                                               ////
2148
////                                                              ////
2149
//// This source is distributed in the hope that it will be       ////
2150
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2151
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2152
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2153
//// details.                                                     ////
2154
////                                                              ////
2155
//// You should have received a copy of the GNU Lesser General    ////
2156
//// Public License along with this source; if not, download it   ////
2157
//// from http://www.opencores.org/lgpl.shtml                     ////
2158
////                                                              ////
2159
//////////////////////////////////////////////////////////////////////
2160
// GRAY counter
2161 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2162 6 unneback
   parameter length = 4;
2163
   input cke;
2164
   output reg [length:1] q;
2165
   output [length:1] q_bin;
2166
   input rst;
2167
   input clk;
2168
   parameter clear_value = 0;
2169
   parameter set_value = 1;
2170
   parameter wrap_value = 8;
2171
   parameter level1_value = 15;
2172
   reg  [length:1] qi;
2173
   wire [length:1] q_next;
2174
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2175
   always @ (posedge clk or posedge rst)
2176
     if (rst)
2177
       qi <= {length{1'b0}};
2178
     else
2179
     if (cke)
2180
       qi <= q_next;
2181
   always @ (posedge clk or posedge rst)
2182
     if (rst)
2183
       q <= {length{1'b0}};
2184
     else
2185
       if (cke)
2186
         q <= (q_next>>1) ^ q_next;
2187
   assign q_bin = qi;
2188
endmodule
2189
//////////////////////////////////////////////////////////////////////
2190
////                                                              ////
2191
////  Versatile library, counters                                 ////
2192
////                                                              ////
2193
////  Description                                                 ////
2194
////  counters                                                    ////
2195
////                                                              ////
2196
////                                                              ////
2197
////  To Do:                                                      ////
2198
////   - add more counters                                        ////
2199
////                                                              ////
2200
////  Author(s):                                                  ////
2201
////      - Michael Unneback, unneback@opencores.org              ////
2202
////        ORSoC AB                                              ////
2203
////                                                              ////
2204
//////////////////////////////////////////////////////////////////////
2205
////                                                              ////
2206
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2207
////                                                              ////
2208
//// This source file may be used and distributed without         ////
2209
//// restriction provided that this copyright statement is not    ////
2210
//// removed from the file and that any derivative work contains  ////
2211
//// the original copyright notice and the associated disclaimer. ////
2212
////                                                              ////
2213
//// This source file is free software; you can redistribute it   ////
2214
//// and/or modify it under the terms of the GNU Lesser General   ////
2215
//// Public License as published by the Free Software Foundation; ////
2216
//// either version 2.1 of the License, or (at your option) any   ////
2217
//// later version.                                               ////
2218
////                                                              ////
2219
//// This source is distributed in the hope that it will be       ////
2220
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2221
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2222
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2223
//// details.                                                     ////
2224
////                                                              ////
2225
//// You should have received a copy of the GNU Lesser General    ////
2226
//// Public License along with this source; if not, download it   ////
2227
//// from http://www.opencores.org/lgpl.shtml                     ////
2228
////                                                              ////
2229
//////////////////////////////////////////////////////////////////////
2230 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2231 6 unneback
   parameter length = 4;
2232
   output reg [0:length-1] q;
2233
   input rst;
2234
   input clk;
2235
    always @ (posedge clk or posedge rst)
2236
    if (rst)
2237
        q <= {1'b1,{length-1{1'b0}}};
2238
    else
2239
        q <= {q[length-1],q[0:length-2]};
2240
endmodule
2241 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2242 6 unneback
   parameter length = 4;
2243
   input cke;
2244
   output reg [0:length-1] q;
2245
   input rst;
2246
   input clk;
2247
    always @ (posedge clk or posedge rst)
2248
    if (rst)
2249
        q <= {1'b1,{length-1{1'b0}}};
2250
    else
2251
        if (cke)
2252
            q <= {q[length-1],q[0:length-2]};
2253
endmodule
2254 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2255 6 unneback
   parameter length = 4;
2256
   input cke, clear;
2257
   output reg [0:length-1] q;
2258
   input rst;
2259
   input clk;
2260
    always @ (posedge clk or posedge rst)
2261
    if (rst)
2262
        q <= {1'b1,{length-1{1'b0}}};
2263
    else
2264
        if (cke)
2265
            if (clear)
2266
                q <= {1'b1,{length-1{1'b0}}};
2267
            else
2268
                q <= q >> 1;
2269
endmodule
2270 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2271 6 unneback
   parameter length = 4;
2272
   input cke, clear;
2273
   output reg [0:length-1] q;
2274
   input rst;
2275
   input clk;
2276
    always @ (posedge clk or posedge rst)
2277
    if (rst)
2278
        q <= {1'b1,{length-1{1'b0}}};
2279
    else
2280
        if (cke)
2281
            if (clear)
2282
                q <= {1'b1,{length-1{1'b0}}};
2283
            else
2284
            q <= {q[length-1],q[0:length-2]};
2285
endmodule
2286
//////////////////////////////////////////////////////////////////////
2287
////                                                              ////
2288
////  Versatile library, memories                                 ////
2289
////                                                              ////
2290
////  Description                                                 ////
2291
////  memories                                                    ////
2292
////                                                              ////
2293
////                                                              ////
2294
////  To Do:                                                      ////
2295
////   - add more memory types                                    ////
2296
////                                                              ////
2297
////  Author(s):                                                  ////
2298
////      - Michael Unneback, unneback@opencores.org              ////
2299
////        ORSoC AB                                              ////
2300
////                                                              ////
2301
//////////////////////////////////////////////////////////////////////
2302
////                                                              ////
2303
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2304
////                                                              ////
2305
//// This source file may be used and distributed without         ////
2306
//// restriction provided that this copyright statement is not    ////
2307
//// removed from the file and that any derivative work contains  ////
2308
//// the original copyright notice and the associated disclaimer. ////
2309
////                                                              ////
2310
//// This source file is free software; you can redistribute it   ////
2311
//// and/or modify it under the terms of the GNU Lesser General   ////
2312
//// Public License as published by the Free Software Foundation; ////
2313
//// either version 2.1 of the License, or (at your option) any   ////
2314
//// later version.                                               ////
2315
////                                                              ////
2316
//// This source is distributed in the hope that it will be       ////
2317
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2318
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2319
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2320
//// details.                                                     ////
2321
////                                                              ////
2322
//// You should have received a copy of the GNU Lesser General    ////
2323
//// Public License along with this source; if not, download it   ////
2324
//// from http://www.opencores.org/lgpl.shtml                     ////
2325
////                                                              ////
2326
//////////////////////////////////////////////////////////////////////
2327
/// ROM
2328 7 unneback
module vl_rom_init ( adr, q, clk);
2329
   parameter data_width = 32;
2330
   parameter addr_width = 8;
2331
   input [(addr_width-1):0]       adr;
2332
   output reg [(data_width-1):0] q;
2333
   input                         clk;
2334
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2335
   parameter memory_file = "vl_rom.vmem";
2336
   initial
2337
     begin
2338
        $readmemh(memory_file, rom);
2339
     end
2340
   always @ (posedge clk)
2341
     q <= rom[adr];
2342
endmodule
2343 14 unneback
/*
2344 7 unneback
module vl_rom ( adr, q, clk);
2345 6 unneback
parameter data_width = 32;
2346
parameter addr_width = 4;
2347
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2348
    {32'h18000000},
2349
    {32'hA8200000},
2350
    {32'hA8200000},
2351
    {32'hA8200000},
2352
    {32'h44003000},
2353
    {32'h15000000},
2354
    {32'h15000000},
2355
    {32'h15000000},
2356
    {32'h15000000},
2357
    {32'h15000000},
2358
    {32'h15000000},
2359
    {32'h15000000},
2360
    {32'h15000000},
2361
    {32'h15000000},
2362
    {32'h15000000},
2363
    {32'h15000000}};
2364 7 unneback
input [addr_width-1:0] adr;
2365 6 unneback
output reg [data_width-1:0] q;
2366
input clk;
2367
always @ (posedge clk)
2368 7 unneback
    q <= data[adr];
2369 6 unneback
endmodule
2370 14 unneback
*/
2371 6 unneback
// Single port RAM
2372
module vl_ram ( d, adr, we, q, clk);
2373
   parameter data_width = 32;
2374
   parameter addr_width = 8;
2375
   input [(data_width-1):0]      d;
2376
   input [(addr_width-1):0]       adr;
2377
   input                         we;
2378 7 unneback
   output reg [(data_width-1):0] q;
2379 6 unneback
   input                         clk;
2380
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2381 7 unneback
   parameter init = 0;
2382
   parameter memory_file = "vl_ram.vmem";
2383
   generate if (init) begin : init_mem
2384
   initial
2385
     begin
2386
        $readmemh(memory_file, ram);
2387
     end
2388
   end
2389
   endgenerate
2390 6 unneback
   always @ (posedge clk)
2391
   begin
2392
   if (we)
2393
     ram[adr] <= d;
2394
   q <= ram[adr];
2395
   end
2396
endmodule
2397 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2398
   parameter data_width = 32;
2399
   parameter addr_width = 8;
2400
   input [(data_width-1):0]      d;
2401
   input [(addr_width-1):0]       adr;
2402
   input [(addr_width/4)-1:0]    be;
2403
   input                         we;
2404
   output reg [(data_width-1):0] q;
2405
   input                         clk;
2406
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2407
   parameter init = 0;
2408
   parameter memory_file = "vl_ram.vmem";
2409
   generate if (init) begin : init_mem
2410
   initial
2411
     begin
2412
        $readmemh(memory_file, ram);
2413
     end
2414
   end
2415
   endgenerate
2416
   genvar i;
2417
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2418
      always @ (posedge clk)
2419
      if (we & be[i])
2420
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2421
   end
2422
   endgenerate
2423
   always @ (posedge clk)
2424
      q <= ram[adr];
2425
endmodule
2426 6 unneback
// Dual port RAM
2427
// ACTEL FPGA should not use logic to handle rw collision
2428 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2429 6 unneback
   parameter data_width = 32;
2430
   parameter addr_width = 8;
2431
   input [(data_width-1):0]      d_a;
2432
   input [(addr_width-1):0]       adr_a;
2433
   input [(addr_width-1):0]       adr_b;
2434
   input                         we_a;
2435
   output [(data_width-1):0]      q_b;
2436
   input                         clk_a, clk_b;
2437
   reg [(addr_width-1):0]         adr_b_reg;
2438
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2439 7 unneback
   parameter init = 0;
2440
   parameter memory_file = "vl_ram.vmem";
2441
   generate if (init) begin : init_mem
2442
   initial
2443
     begin
2444
        $readmemh(memory_file, ram);
2445
     end
2446
   end
2447
   endgenerate
2448 6 unneback
   always @ (posedge clk_a)
2449
   if (we_a)
2450
     ram[adr_a] <= d_a;
2451
   always @ (posedge clk_b)
2452
   adr_b_reg <= adr_b;
2453
   assign q_b = ram[adr_b_reg];
2454
endmodule
2455 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2456 6 unneback
   parameter data_width = 32;
2457
   parameter addr_width = 8;
2458
   input [(data_width-1):0]      d_a;
2459
   input [(addr_width-1):0]       adr_a;
2460
   input [(addr_width-1):0]       adr_b;
2461
   input                         we_a;
2462
   output [(data_width-1):0]      q_b;
2463
   output reg [(data_width-1):0] q_a;
2464
   input                         clk_a, clk_b;
2465
   reg [(data_width-1):0]         q_b;
2466
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2467 7 unneback
   parameter init = 0;
2468
   parameter memory_file = "vl_ram.vmem";
2469
   generate if (init) begin : init_mem
2470
   initial
2471
     begin
2472
        $readmemh(memory_file, ram);
2473
     end
2474
   end
2475
   endgenerate
2476 6 unneback
   always @ (posedge clk_a)
2477
     begin
2478
        q_a <= ram[adr_a];
2479
        if (we_a)
2480
             ram[adr_a] <= d_a;
2481
     end
2482
   always @ (posedge clk_b)
2483
          q_b <= ram[adr_b];
2484
endmodule
2485 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2486 6 unneback
   parameter data_width = 32;
2487
   parameter addr_width = 8;
2488
   input [(data_width-1):0]      d_a;
2489
   input [(addr_width-1):0]       adr_a;
2490
   input [(addr_width-1):0]       adr_b;
2491
   input                         we_a;
2492
   output [(data_width-1):0]      q_b;
2493
   input [(data_width-1):0]       d_b;
2494
   output reg [(data_width-1):0] q_a;
2495
   input                         we_b;
2496
   input                         clk_a, clk_b;
2497
   reg [(data_width-1):0]         q_b;
2498
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2499 7 unneback
   parameter init = 0;
2500
   parameter memory_file = "vl_ram.vmem";
2501
   generate if (init) begin : init_mem
2502
   initial
2503
     begin
2504
        $readmemh(memory_file, ram);
2505
     end
2506
   end
2507
   endgenerate
2508 6 unneback
   always @ (posedge clk_a)
2509
     begin
2510
        q_a <= ram[adr_a];
2511
        if (we_a)
2512
             ram[adr_a] <= d_a;
2513
     end
2514
   always @ (posedge clk_b)
2515
     begin
2516
        q_b <= ram[adr_b];
2517
        if (we_b)
2518
          ram[adr_b] <= d_b;
2519
     end
2520
endmodule
2521
// Content addresable memory, CAM
2522
// FIFO
2523 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2524
    d, wr, fifo_full,
2525
    q, rd, fifo_empty,
2526
    fill_level,
2527
    clk, rst
2528
    );
2529
parameter data_width = 18;
2530
parameter addr_width = 4;
2531
// write side
2532
input  [data_width-1:0] d;
2533
input                   wr;
2534
output                  fifo_full;
2535
// read side
2536
output [data_width-1:0] q;
2537
input                   rd;
2538
output                  fifo_empty;
2539
// common
2540
output [addr_width:0]   fill_level;
2541
input rst, clk;
2542
wire [addr_width:1] wadr, radr;
2543
vl_cnt_bin_ce
2544
    # ( .length(addr_width))
2545
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2546
vl_cnt_bin_ce
2547
    # (.length(addr_width))
2548
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2549
vl_dpram_1r1w
2550
    # (.data_width(data_width), .addr_width(addr_width))
2551
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2552 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
2553 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2554 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2555
endmodule
2556 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2557
// RAM is supposed to be larger than the two FIFOs
2558
// LFSR counters used adr pointers
2559
module vl_fifo_2r2w_sync_simplex (
2560
    // a side
2561
    a_d, a_wr, a_fifo_full,
2562
    a_q, a_rd, a_fifo_empty,
2563
    a_fill_level,
2564
    // b side
2565
    b_d, b_wr, b_fifo_full,
2566
    b_q, b_rd, b_fifo_empty,
2567
    b_fill_level,
2568
    // common
2569
    clk, rst
2570
    );
2571
parameter data_width = 8;
2572
parameter addr_width = 5;
2573
parameter fifo_full_level = (1<<addr_width)-1;
2574
// a side
2575
input  [data_width-1:0] a_d;
2576
input                   a_wr;
2577
output                  a_fifo_full;
2578
output [data_width-1:0] a_q;
2579
input                   a_rd;
2580
output                  a_fifo_empty;
2581
output [addr_width-1:0] a_fill_level;
2582
// b side
2583
input  [data_width-1:0] b_d;
2584
input                   b_wr;
2585
output                  b_fifo_full;
2586
output [data_width-1:0] b_q;
2587
input                   b_rd;
2588
output                  b_fifo_empty;
2589
output [addr_width-1:0] b_fill_level;
2590
input                   clk;
2591
input                   rst;
2592
// adr_gen
2593
wire [addr_width:1] a_wadr, a_radr;
2594
wire [addr_width:1] b_wadr, b_radr;
2595
// dpram
2596
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2597
vl_cnt_lfsr_ce
2598
    # ( .length(addr_width))
2599
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2600
vl_cnt_lfsr_ce
2601
    # (.length