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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 33

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1 6 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 33 unneback
module vl_gbuf ( i, o);
47
input i;
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output o;
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assign o = i;
50
endmodule
51 6 unneback
 // ALTERA
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 //ACTEL
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// sync reset
54 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
55 6 unneback
// output active high global reset sync with two DFFs 
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`timescale 1 ns/100 ps
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module vl_sync_rst ( rst_n_i, rst_o, clk);
58
input rst_n_i, clk;
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output rst_o;
60 18 unneback
reg [1:0] tmp;
61 6 unneback
always @ (posedge clk or negedge rst_n_i)
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if (!rst_n_i)
63 17 unneback
        tmp <= 2'b11;
64 6 unneback
else
65 33 unneback
        tmp <= {1'b0,tmp[1]};
66 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
67 6 unneback
endmodule
68
// vl_pll
69 32 unneback
///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps/1 ps
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
72
parameter index = 0;
73
parameter number_of_clk = 1;
74
parameter period_time_0 = 20000;
75
parameter period_time_1 = 20000;
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parameter period_time_2 = 20000;
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parameter period_time_3 = 20000;
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parameter period_time_4 = 20000;
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parameter lock_delay = 2000000;
80
input clk_i, rst_n_i;
81
output lock;
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output reg [0:number_of_clk-1] clk_o;
83
output [0:number_of_clk-1] rst_o;
84 33 unneback
`ifdef SIM_PLL
85 32 unneback
always
86
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
87
generate if (number_of_clk > 1)
88
always
89
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
90
endgenerate
91
generate if (number_of_clk > 2)
92
always
93
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
94
endgenerate
95 33 unneback
generate if (number_of_clk > 3)
96 32 unneback
always
97
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
98
endgenerate
99 33 unneback
generate if (number_of_clk > 4)
100 32 unneback
always
101
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
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endgenerate
103
genvar i;
104
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
106
end
107
endgenerate
108 33 unneback
//assign #lock_delay lock = rst_n_i;
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assign lock = rst_n_i;
110 32 unneback
endmodule
111 33 unneback
`else
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`ifdef VL_PLL0
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`ifdef VL_PLL0_CLK1
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
115
`endif
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`ifdef VL_PLL0_CLK2
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL0_CLK3
120
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL0_CLK4
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL0_CLK5
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
127
`endif
128
`endif
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`ifdef VL_PLL1
130
`ifdef VL_PLL1_CLK1
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL1_CLK2
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL1_CLK3
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL1_CLK4
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL1_CLK5
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL2
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`ifdef VL_PLL2_CLK1
148
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL2_CLK2
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL2_CLK3
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL2_CLK4
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL2_CLK5
160
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL3
164
`ifdef VL_PLL3_CLK1
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    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
166
`endif
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`ifdef VL_PLL3_CLK2
168
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
169
`endif
170
`ifdef VL_PLL3_CLK3
171
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
172
`endif
173
`ifdef VL_PLL3_CLK4
174
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
175
`endif
176
`ifdef VL_PLL3_CLK5
177
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
178
`endif
179
`endif
180 32 unneback
genvar i;
181
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
182 33 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
183 32 unneback
end
184
endgenerate
185
endmodule
186 33 unneback
`endif
187 32 unneback
///////////////////////////////////////////////////////////////////////////////
188 6 unneback
 //altera
189
 //actel
190
//////////////////////////////////////////////////////////////////////
191
////                                                              ////
192
////  Versatile library, registers                                ////
193
////                                                              ////
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////  Description                                                 ////
195
////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
198
////  To Do:                                                      ////
199
////   - add more different registers                             ////
200
////                                                              ////
201
////  Author(s):                                                  ////
202
////      - Michael Unneback, unneback@opencores.org              ////
203
////        ORSoC AB                                              ////
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////                                                              ////
205
//////////////////////////////////////////////////////////////////////
206
////                                                              ////
207
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
208
////                                                              ////
209
//// This source file may be used and distributed without         ////
210
//// restriction provided that this copyright statement is not    ////
211
//// removed from the file and that any derivative work contains  ////
212
//// the original copyright notice and the associated disclaimer. ////
213
////                                                              ////
214
//// This source file is free software; you can redistribute it   ////
215
//// and/or modify it under the terms of the GNU Lesser General   ////
216
//// Public License as published by the Free Software Foundation; ////
217
//// either version 2.1 of the License, or (at your option) any   ////
218
//// later version.                                               ////
219
////                                                              ////
220
//// This source is distributed in the hope that it will be       ////
221
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
222
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
223
//// PURPOSE.  See the GNU Lesser General Public License for more ////
224
//// details.                                                     ////
225
////                                                              ////
226
//// You should have received a copy of the GNU Lesser General    ////
227
//// Public License along with this source; if not, download it   ////
228
//// from http://www.opencores.org/lgpl.shtml                     ////
229
////                                                              ////
230
//////////////////////////////////////////////////////////////////////
231 18 unneback
module vl_dff ( d, q, clk, rst);
232 6 unneback
        parameter width = 1;
233
        parameter reset_value = 0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output reg [width-1:0] q;
237
        always @ (posedge clk or posedge rst)
238
        if (rst)
239
                q <= reset_value;
240
        else
241
                q <= d;
242
endmodule
243 18 unneback
module vl_dff_array ( d, q, clk, rst);
244 6 unneback
        parameter width = 1;
245
        parameter depth = 2;
246
        parameter reset_value = 1'b0;
247
        input [width-1:0] d;
248
        input clk, rst;
249
        output [width-1:0] q;
250
        reg  [0:depth-1] q_tmp [width-1:0];
251
        integer i;
252
        always @ (posedge clk or posedge rst)
253
        if (rst) begin
254
            for (i=0;i<depth;i=i+1)
255
                q_tmp[i] <= {width{reset_value}};
256
        end else begin
257
            q_tmp[0] <= d;
258
            for (i=1;i<depth;i=i+1)
259
                q_tmp[i] <= q_tmp[i-1];
260
        end
261
    assign q = q_tmp[depth-1];
262
endmodule
263 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
264 6 unneback
        parameter width = 1;
265
        parameter reset_value = 0;
266
        input [width-1:0] d;
267
        input ce, clk, rst;
268
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
                q <= reset_value;
272
        else
273
                if (ce)
274
                        q <= d;
275
endmodule
276 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
277 8 unneback
        parameter width = 1;
278
        parameter reset_value = 0;
279
        input [width-1:0] d;
280 10 unneback
        input ce, clear, clk, rst;
281 8 unneback
        output reg [width-1:0] q;
282
        always @ (posedge clk or posedge rst)
283
        if (rst)
284
            q <= reset_value;
285
        else
286
            if (ce)
287
                if (clear)
288
                    q <= {width{1'b0}};
289
                else
290
                    q <= d;
291
endmodule
292 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
293
        parameter width = 1;
294
        parameter reset_value = 0;
295
        input [width-1:0] d;
296
        input ce, set, clk, rst;
297
        output reg [width-1:0] q;
298
        always @ (posedge clk or posedge rst)
299
        if (rst)
300
            q <= reset_value;
301
        else
302
            if (ce)
303
                if (set)
304
                    q <= {width{1'b1}};
305
                else
306
                    q <= d;
307
endmodule
308 29 unneback
module vl_spr ( sp, r, q, clk, rst);
309
        parameter width = 1;
310
        parameter reset_value = 0;
311
        input sp, r;
312
        output reg q;
313
        input clk, rst;
314
        always @ (posedge clk or posedge rst)
315
        if (rst)
316
            q <= reset_value;
317
        else
318
            if (sp)
319
                q <= 1'b1;
320
            else if (r)
321
                q <= 1'b0;
322
endmodule
323
module vl_srp ( s, rp, q, clk, rst);
324
        parameter width = 1;
325
        parameter reset_value = 0;
326
        input s, rp;
327
        output reg q;
328
        input clk, rst;
329
        always @ (posedge clk or posedge rst)
330
        if (rst)
331
            q <= reset_value;
332
        else
333
            if (rp)
334
                q <= 1'b0;
335
            else if (s)
336
                q <= 1'b1;
337
endmodule
338 6 unneback
// megafunction wizard: %LPM_FF%
339
// GENERATION: STANDARD
340
// VERSION: WM1.0
341
// MODULE: lpm_ff 
342
// ============================================================
343
// File Name: dff_sr.v
344
// Megafunction Name(s):
345
//                      lpm_ff
346
//
347
// Simulation Library Files(s):
348
//                      lpm
349
// ============================================================
350
// ************************************************************
351
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
352
//
353
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
354
// ************************************************************
355
//Copyright (C) 1991-2010 Altera Corporation
356
//Your use of Altera Corporation's design tools, logic functions 
357
//and other software and tools, and its AMPP partner logic 
358
//functions, and any output files from any of the foregoing 
359
//(including device programming or simulation files), and any 
360
//associated documentation or information are expressly subject 
361
//to the terms and conditions of the Altera Program License 
362
//Subscription Agreement, Altera MegaCore Function License 
363
//Agreement, or other applicable license agreement, including, 
364
//without limitation, that your use is for the sole purpose of 
365
//programming logic devices manufactured by Altera and sold by 
366
//Altera or its authorized distributors.  Please refer to the 
367
//applicable agreement for further details.
368
// synopsys translate_off
369
`timescale 1 ps / 1 ps
370
// synopsys translate_on
371 18 unneback
module vl_dff_sr (
372 6 unneback
        aclr,
373
        aset,
374
        clock,
375
        data,
376
        q);
377
        input     aclr;
378
        input     aset;
379
        input     clock;
380
        input     data;
381
        output    q;
382
        wire [0:0] sub_wire0;
383
        wire [0:0] sub_wire1 = sub_wire0[0:0];
384
        wire  q = sub_wire1;
385
        wire  sub_wire2 = data;
386
        wire  sub_wire3 = sub_wire2;
387
        lpm_ff  lpm_ff_component (
388
                                .aclr (aclr),
389
                                .clock (clock),
390
                                .data (sub_wire3),
391
                                .aset (aset),
392
                                .q (sub_wire0)
393
                                // synopsys translate_off
394
                                ,
395
                                .aload (),
396
                                .enable (),
397
                                .sclr (),
398
                                .sload (),
399
                                .sset ()
400
                                // synopsys translate_on
401
                                );
402
        defparam
403
                lpm_ff_component.lpm_fftype = "DFF",
404
                lpm_ff_component.lpm_type = "LPM_FF",
405
                lpm_ff_component.lpm_width = 1;
406
endmodule
407
// ============================================================
408
// CNX file retrieval info
409
// ============================================================
410
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
411
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
412
// Retrieval info: PRIVATE: ASET NUMERIC "1"
413
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
414
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
415
// Retrieval info: PRIVATE: DFF NUMERIC "1"
416
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
417
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
418
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET NUMERIC "0"
420
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
421
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
422
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
423
// Retrieval info: PRIVATE: nBit NUMERIC "1"
424
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
425
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
426
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
427
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
428
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
429
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
430
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
431
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
432
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
433
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
434
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
435
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
436
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
437
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
444
// Retrieval info: LIB_FILE: lpm
445
// LATCH
446
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
447 18 unneback
module vl_latch ( d, le, q, clk);
448 6 unneback
input d, le;
449
output q;
450
input clk;
451
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
452
endmodule
453 18 unneback
module vl_shreg ( d, q, clk, rst);
454 17 unneback
parameter depth = 10;
455
input d;
456
output q;
457
input clk, rst;
458
reg [1:depth] dffs;
459
always @ (posedge clk or posedge rst)
460
if (rst)
461
    dffs <= {depth{1'b0}};
462
else
463
    dffs <= {d,dffs[1:depth-1]};
464
assign q = dffs[depth];
465
endmodule
466 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
467 17 unneback
parameter depth = 10;
468
input d, ce;
469
output q;
470
input clk, rst;
471
reg [1:depth] dffs;
472
always @ (posedge clk or posedge rst)
473
if (rst)
474
    dffs <= {depth{1'b0}};
475
else
476
    if (ce)
477
        dffs <= {d,dffs[1:depth-1]};
478
assign q = dffs[depth];
479
endmodule
480 18 unneback
module vl_delay ( d, q, clk, rst);
481 15 unneback
parameter depth = 10;
482
input d;
483
output q;
484
input clk, rst;
485
reg [1:depth] dffs;
486
always @ (posedge clk or posedge rst)
487
if (rst)
488
    dffs <= {depth{1'b0}};
489
else
490
    dffs <= {d,dffs[1:depth-1]};
491
assign q = dffs[depth];
492
endmodule
493 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
494 17 unneback
parameter depth = 10;
495
input d;
496
output q, emptyflag;
497
input clk, rst;
498
reg [1:depth] dffs;
499
always @ (posedge clk or posedge rst)
500
if (rst)
501
    dffs <= {depth{1'b0}};
502
else
503
    dffs <= {d,dffs[1:depth-1]};
504
assign q = dffs[depth];
505
assign emptyflag = !(|dffs);
506
endmodule
507 6 unneback
//////////////////////////////////////////////////////////////////////
508
////                                                              ////
509 18 unneback
////  Logic functions                                             ////
510
////                                                              ////
511
////  Description                                                 ////
512
////  Logic functions such as multiplexers                        ////
513
////                                                              ////
514
////                                                              ////
515
////  To Do:                                                      ////
516
////   -                                                          ////
517
////                                                              ////
518
////  Author(s):                                                  ////
519
////      - Michael Unneback, unneback@opencores.org              ////
520
////        ORSoC AB                                              ////
521
////                                                              ////
522
//////////////////////////////////////////////////////////////////////
523
////                                                              ////
524
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
525
////                                                              ////
526
//// This source file may be used and distributed without         ////
527
//// restriction provided that this copyright statement is not    ////
528
//// removed from the file and that any derivative work contains  ////
529
//// the original copyright notice and the associated disclaimer. ////
530
////                                                              ////
531
//// This source file is free software; you can redistribute it   ////
532
//// and/or modify it under the terms of the GNU Lesser General   ////
533
//// Public License as published by the Free Software Foundation; ////
534
//// either version 2.1 of the License, or (at your option) any   ////
535
//// later version.                                               ////
536
////                                                              ////
537
//// This source is distributed in the hope that it will be       ////
538
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
539
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
540
//// PURPOSE.  See the GNU Lesser General Public License for more ////
541
//// details.                                                     ////
542
////                                                              ////
543
//// You should have received a copy of the GNU Lesser General    ////
544
//// Public License along with this source; if not, download it   ////
545
//// from http://www.opencores.org/lgpl.shtml                     ////
546
////                                                              ////
547
//////////////////////////////////////////////////////////////////////
548
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
549
parameter width = 32;
550
parameter nr_of_ports = 4;
551
input [width-1:0] a3, a2, a1, a0;
552
input [nr_of_ports-1:0] sel;
553 22 unneback
output [width-1:0] dout;
554 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
555 18 unneback
integer i;
556
// and
557
assign tmp[0] = {width{sel[0]}} & a0;
558
assign tmp[1] = {width{sel[1]}} & a1;
559
assign tmp[2] = {width{sel[2]}} & a2;
560
assign tmp[3] = {width{sel[3]}} & a3;
561
// or
562
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
563
endmodule
564
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
565
parameter width = 32;
566
parameter nr_of_ports = 5;
567
input [width-1:0] a4, a3, a2, a1, a0;
568
input [nr_of_ports-1:0] sel;
569 22 unneback
output [width-1:0] dout;
570 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
571 18 unneback
integer i;
572
// and
573
assign tmp[0] = {width{sel[0]}} & a0;
574
assign tmp[1] = {width{sel[1]}} & a1;
575
assign tmp[2] = {width{sel[2]}} & a2;
576
assign tmp[3] = {width{sel[3]}} & a3;
577
assign tmp[4] = {width{sel[4]}} & a4;
578
// or
579
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
580
endmodule
581
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
582
parameter width = 32;
583
parameter nr_of_ports = 6;
584
input [width-1:0] a5, a4, a3, a2, a1, a0;
585
input [nr_of_ports-1:0] sel;
586 22 unneback
output [width-1:0] dout;
587 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
588 18 unneback
integer i;
589
// and
590
assign tmp[0] = {width{sel[0]}} & a0;
591
assign tmp[1] = {width{sel[1]}} & a1;
592
assign tmp[2] = {width{sel[2]}} & a2;
593
assign tmp[3] = {width{sel[3]}} & a3;
594
assign tmp[4] = {width{sel[4]}} & a4;
595
assign tmp[5] = {width{sel[5]}} & a5;
596
// or
597
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
598
endmodule
599
//////////////////////////////////////////////////////////////////////
600
////                                                              ////
601 6 unneback
////  Versatile counter                                           ////
602
////                                                              ////
603
////  Description                                                 ////
604
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
605
////  counter                                                     ////
606
////                                                              ////
607
////  To Do:                                                      ////
608
////   - add LFSR with more taps                                  ////
609
////                                                              ////
610
////  Author(s):                                                  ////
611
////      - Michael Unneback, unneback@opencores.org              ////
612
////        ORSoC AB                                              ////
613
////                                                              ////
614
//////////////////////////////////////////////////////////////////////
615
////                                                              ////
616
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
617
////                                                              ////
618
//// This source file may be used and distributed without         ////
619
//// restriction provided that this copyright statement is not    ////
620
//// removed from the file and that any derivative work contains  ////
621
//// the original copyright notice and the associated disclaimer. ////
622
////                                                              ////
623
//// This source file is free software; you can redistribute it   ////
624
//// and/or modify it under the terms of the GNU Lesser General   ////
625
//// Public License as published by the Free Software Foundation; ////
626
//// either version 2.1 of the License, or (at your option) any   ////
627
//// later version.                                               ////
628
////                                                              ////
629
//// This source is distributed in the hope that it will be       ////
630
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
631
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
632
//// PURPOSE.  See the GNU Lesser General Public License for more ////
633
//// details.                                                     ////
634
////                                                              ////
635
//// You should have received a copy of the GNU Lesser General    ////
636
//// Public License along with this source; if not, download it   ////
637
//// from http://www.opencores.org/lgpl.shtml                     ////
638
////                                                              ////
639
//////////////////////////////////////////////////////////////////////
640
// binary counter
641 22 unneback
module vl_cnt_bin ( q, rst, clk);
642
   parameter length = 4;
643
   output [length:1] q;
644
   input rst;
645
   input clk;
646
   parameter clear_value = 0;
647
   parameter set_value = 1;
648
   parameter wrap_value = 0;
649
   parameter level1_value = 15;
650
   reg  [length:1] qi;
651
   wire [length:1] q_next;
652
   assign q_next = qi + {{length-1{1'b0}},1'b1};
653
   always @ (posedge clk or posedge rst)
654
     if (rst)
655
       qi <= {length{1'b0}};
656
     else
657
       qi <= q_next;
658
   assign q = qi;
659
endmodule
660
//////////////////////////////////////////////////////////////////////
661
////                                                              ////
662
////  Versatile counter                                           ////
663
////                                                              ////
664
////  Description                                                 ////
665
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
666
////  counter                                                     ////
667
////                                                              ////
668
////  To Do:                                                      ////
669
////   - add LFSR with more taps                                  ////
670
////                                                              ////
671
////  Author(s):                                                  ////
672
////      - Michael Unneback, unneback@opencores.org              ////
673
////        ORSoC AB                                              ////
674
////                                                              ////
675
//////////////////////////////////////////////////////////////////////
676
////                                                              ////
677
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
678
////                                                              ////
679
//// This source file may be used and distributed without         ////
680
//// restriction provided that this copyright statement is not    ////
681
//// removed from the file and that any derivative work contains  ////
682
//// the original copyright notice and the associated disclaimer. ////
683
////                                                              ////
684
//// This source file is free software; you can redistribute it   ////
685
//// and/or modify it under the terms of the GNU Lesser General   ////
686
//// Public License as published by the Free Software Foundation; ////
687
//// either version 2.1 of the License, or (at your option) any   ////
688
//// later version.                                               ////
689
////                                                              ////
690
//// This source is distributed in the hope that it will be       ////
691
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
692
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
693
//// PURPOSE.  See the GNU Lesser General Public License for more ////
694
//// details.                                                     ////
695
////                                                              ////
696
//// You should have received a copy of the GNU Lesser General    ////
697
//// Public License along with this source; if not, download it   ////
698
//// from http://www.opencores.org/lgpl.shtml                     ////
699
////                                                              ////
700
//////////////////////////////////////////////////////////////////////
701
// binary counter
702
module vl_cnt_bin_clear ( clear, q, rst, clk);
703
   parameter length = 4;
704
   input clear;
705
   output [length:1] q;
706
   input rst;
707
   input clk;
708
   parameter clear_value = 0;
709
   parameter set_value = 1;
710
   parameter wrap_value = 0;
711
   parameter level1_value = 15;
712
   reg  [length:1] qi;
713
   wire [length:1] q_next;
714
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
715
   always @ (posedge clk or posedge rst)
716
     if (rst)
717
       qi <= {length{1'b0}};
718
     else
719
       qi <= q_next;
720
   assign q = qi;
721
endmodule
722
//////////////////////////////////////////////////////////////////////
723
////                                                              ////
724
////  Versatile counter                                           ////
725
////                                                              ////
726
////  Description                                                 ////
727
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
728
////  counter                                                     ////
729
////                                                              ////
730
////  To Do:                                                      ////
731
////   - add LFSR with more taps                                  ////
732
////                                                              ////
733
////  Author(s):                                                  ////
734
////      - Michael Unneback, unneback@opencores.org              ////
735
////        ORSoC AB                                              ////
736
////                                                              ////
737
//////////////////////////////////////////////////////////////////////
738
////                                                              ////
739
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
740
////                                                              ////
741
//// This source file may be used and distributed without         ////
742
//// restriction provided that this copyright statement is not    ////
743
//// removed from the file and that any derivative work contains  ////
744
//// the original copyright notice and the associated disclaimer. ////
745
////                                                              ////
746
//// This source file is free software; you can redistribute it   ////
747
//// and/or modify it under the terms of the GNU Lesser General   ////
748
//// Public License as published by the Free Software Foundation; ////
749
//// either version 2.1 of the License, or (at your option) any   ////
750
//// later version.                                               ////
751
////                                                              ////
752
//// This source is distributed in the hope that it will be       ////
753
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
754
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
755
//// PURPOSE.  See the GNU Lesser General Public License for more ////
756
//// details.                                                     ////
757
////                                                              ////
758
//// You should have received a copy of the GNU Lesser General    ////
759
//// Public License along with this source; if not, download it   ////
760
//// from http://www.opencores.org/lgpl.shtml                     ////
761
////                                                              ////
762
//////////////////////////////////////////////////////////////////////
763
// binary counter
764 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
765 6 unneback
   parameter length = 4;
766
   input cke;
767
   output [length:1] q;
768
   input rst;
769
   input clk;
770
   parameter clear_value = 0;
771
   parameter set_value = 1;
772
   parameter wrap_value = 0;
773
   parameter level1_value = 15;
774
   reg  [length:1] qi;
775
   wire [length:1] q_next;
776
   assign q_next = qi + {{length-1{1'b0}},1'b1};
777
   always @ (posedge clk or posedge rst)
778
     if (rst)
779
       qi <= {length{1'b0}};
780
     else
781
     if (cke)
782
       qi <= q_next;
783
   assign q = qi;
784
endmodule
785
//////////////////////////////////////////////////////////////////////
786
////                                                              ////
787
////  Versatile counter                                           ////
788
////                                                              ////
789
////  Description                                                 ////
790
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
791
////  counter                                                     ////
792
////                                                              ////
793
////  To Do:                                                      ////
794
////   - add LFSR with more taps                                  ////
795
////                                                              ////
796
////  Author(s):                                                  ////
797
////      - Michael Unneback, unneback@opencores.org              ////
798
////        ORSoC AB                                              ////
799
////                                                              ////
800
//////////////////////////////////////////////////////////////////////
801
////                                                              ////
802
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
803
////                                                              ////
804
//// This source file may be used and distributed without         ////
805
//// restriction provided that this copyright statement is not    ////
806
//// removed from the file and that any derivative work contains  ////
807
//// the original copyright notice and the associated disclaimer. ////
808
////                                                              ////
809
//// This source file is free software; you can redistribute it   ////
810
//// and/or modify it under the terms of the GNU Lesser General   ////
811
//// Public License as published by the Free Software Foundation; ////
812
//// either version 2.1 of the License, or (at your option) any   ////
813
//// later version.                                               ////
814
////                                                              ////
815
//// This source is distributed in the hope that it will be       ////
816
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
817
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
818
//// PURPOSE.  See the GNU Lesser General Public License for more ////
819
//// details.                                                     ////
820
////                                                              ////
821
//// You should have received a copy of the GNU Lesser General    ////
822
//// Public License along with this source; if not, download it   ////
823
//// from http://www.opencores.org/lgpl.shtml                     ////
824
////                                                              ////
825
//////////////////////////////////////////////////////////////////////
826
// binary counter
827 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
828 6 unneback
   parameter length = 4;
829
   input clear;
830
   input cke;
831
   output [length:1] q;
832
   input rst;
833
   input clk;
834
   parameter clear_value = 0;
835
   parameter set_value = 1;
836
   parameter wrap_value = 0;
837
   parameter level1_value = 15;
838
   reg  [length:1] qi;
839
   wire [length:1] q_next;
840
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
841
   always @ (posedge clk or posedge rst)
842
     if (rst)
843
       qi <= {length{1'b0}};
844
     else
845
     if (cke)
846
       qi <= q_next;
847
   assign q = qi;
848
endmodule
849
//////////////////////////////////////////////////////////////////////
850
////                                                              ////
851
////  Versatile counter                                           ////
852
////                                                              ////
853
////  Description                                                 ////
854
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
855
////  counter                                                     ////
856
////                                                              ////
857
////  To Do:                                                      ////
858
////   - add LFSR with more taps                                  ////
859
////                                                              ////
860
////  Author(s):                                                  ////
861
////      - Michael Unneback, unneback@opencores.org              ////
862
////        ORSoC AB                                              ////
863
////                                                              ////
864
//////////////////////////////////////////////////////////////////////
865
////                                                              ////
866
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
867
////                                                              ////
868
//// This source file may be used and distributed without         ////
869
//// restriction provided that this copyright statement is not    ////
870
//// removed from the file and that any derivative work contains  ////
871
//// the original copyright notice and the associated disclaimer. ////
872
////                                                              ////
873
//// This source file is free software; you can redistribute it   ////
874
//// and/or modify it under the terms of the GNU Lesser General   ////
875
//// Public License as published by the Free Software Foundation; ////
876
//// either version 2.1 of the License, or (at your option) any   ////
877
//// later version.                                               ////
878
////                                                              ////
879
//// This source is distributed in the hope that it will be       ////
880
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
881
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
882
//// PURPOSE.  See the GNU Lesser General Public License for more ////
883
//// details.                                                     ////
884
////                                                              ////
885
//// You should have received a copy of the GNU Lesser General    ////
886
//// Public License along with this source; if not, download it   ////
887
//// from http://www.opencores.org/lgpl.shtml                     ////
888
////                                                              ////
889
//////////////////////////////////////////////////////////////////////
890
// binary counter
891 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
892
   parameter length = 4;
893
   input clear;
894
   input cke;
895
   output [length:1] q;
896
   output reg level1;
897
   output reg level2;
898
   input rst;
899
   input clk;
900
   parameter clear_value = 0;
901
   parameter set_value = 1;
902 30 unneback
   parameter wrap_value = 15;
903
   parameter level1_value = 8;
904
   parameter level2_value = 15;
905 29 unneback
   wire rew;
906 30 unneback
   assign rew = 1'b0;
907 29 unneback
   reg  [length:1] qi;
908
   wire [length:1] q_next;
909
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
910
   always @ (posedge clk or posedge rst)
911
     if (rst)
912
       qi <= {length{1'b0}};
913
     else
914
     if (cke)
915
       qi <= q_next;
916
   assign q = qi;
917
    always @ (posedge clk or posedge rst)
918
    if (rst)
919
        level1 <= 1'b0;
920
    else
921
    if (cke)
922
    if (clear)
923
        level1 <= 1'b0;
924
    else if (q_next == level1_value)
925
        level1 <= 1'b1;
926
    else if (qi == level1_value & rew)
927
        level1 <= 1'b0;
928
    always @ (posedge clk or posedge rst)
929
    if (rst)
930
        level2 <= 1'b0;
931
    else
932
    if (cke)
933
    if (clear)
934
        level2 <= 1'b0;
935
    else if (q_next == level2_value)
936
        level2 <= 1'b1;
937
    else if (qi == level2_value & rew)
938
        level2 <= 1'b0;
939
endmodule
940
//////////////////////////////////////////////////////////////////////
941
////                                                              ////
942
////  Versatile counter                                           ////
943
////                                                              ////
944
////  Description                                                 ////
945
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
946
////  counter                                                     ////
947
////                                                              ////
948
////  To Do:                                                      ////
949
////   - add LFSR with more taps                                  ////
950
////                                                              ////
951
////  Author(s):                                                  ////
952
////      - Michael Unneback, unneback@opencores.org              ////
953
////        ORSoC AB                                              ////
954
////                                                              ////
955
//////////////////////////////////////////////////////////////////////
956
////                                                              ////
957
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
958
////                                                              ////
959
//// This source file may be used and distributed without         ////
960
//// restriction provided that this copyright statement is not    ////
961
//// removed from the file and that any derivative work contains  ////
962
//// the original copyright notice and the associated disclaimer. ////
963
////                                                              ////
964
//// This source file is free software; you can redistribute it   ////
965
//// and/or modify it under the terms of the GNU Lesser General   ////
966
//// Public License as published by the Free Software Foundation; ////
967
//// either version 2.1 of the License, or (at your option) any   ////
968
//// later version.                                               ////
969
////                                                              ////
970
//// This source is distributed in the hope that it will be       ////
971
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
972
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
973
//// PURPOSE.  See the GNU Lesser General Public License for more ////
974
//// details.                                                     ////
975
////                                                              ////
976
//// You should have received a copy of the GNU Lesser General    ////
977
//// Public License along with this source; if not, download it   ////
978
//// from http://www.opencores.org/lgpl.shtml                     ////
979
////                                                              ////
980
//////////////////////////////////////////////////////////////////////
981
// binary counter
982 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
983 6 unneback
   parameter length = 4;
984
   input clear;
985
   input set;
986
   input cke;
987
   input rew;
988
   output [length:1] q;
989
   input rst;
990
   input clk;
991
   parameter clear_value = 0;
992
   parameter set_value = 1;
993
   parameter wrap_value = 0;
994
   parameter level1_value = 15;
995
   reg  [length:1] qi;
996
   wire  [length:1] q_next, q_next_fw, q_next_rew;
997
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
998
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
999
   assign q_next = rew ? q_next_rew : q_next_fw;
1000
   always @ (posedge clk or posedge rst)
1001
     if (rst)
1002
       qi <= {length{1'b0}};
1003
     else
1004
     if (cke)
1005
       qi <= q_next;
1006
   assign q = qi;
1007
endmodule
1008
//////////////////////////////////////////////////////////////////////
1009
////                                                              ////
1010
////  Versatile counter                                           ////
1011
////                                                              ////
1012
////  Description                                                 ////
1013
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1014
////  counter                                                     ////
1015
////                                                              ////
1016
////  To Do:                                                      ////
1017
////   - add LFSR with more taps                                  ////
1018
////                                                              ////
1019
////  Author(s):                                                  ////
1020
////      - Michael Unneback, unneback@opencores.org              ////
1021
////        ORSoC AB                                              ////
1022
////                                                              ////
1023
//////////////////////////////////////////////////////////////////////
1024
////                                                              ////
1025
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1026
////                                                              ////
1027
//// This source file may be used and distributed without         ////
1028
//// restriction provided that this copyright statement is not    ////
1029
//// removed from the file and that any derivative work contains  ////
1030
//// the original copyright notice and the associated disclaimer. ////
1031
////                                                              ////
1032
//// This source file is free software; you can redistribute it   ////
1033
//// and/or modify it under the terms of the GNU Lesser General   ////
1034
//// Public License as published by the Free Software Foundation; ////
1035
//// either version 2.1 of the License, or (at your option) any   ////
1036
//// later version.                                               ////
1037
////                                                              ////
1038
//// This source is distributed in the hope that it will be       ////
1039
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1040
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1041
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1042
//// details.                                                     ////
1043
////                                                              ////
1044
//// You should have received a copy of the GNU Lesser General    ////
1045
//// Public License along with this source; if not, download it   ////
1046
//// from http://www.opencores.org/lgpl.shtml                     ////
1047
////                                                              ////
1048
//////////////////////////////////////////////////////////////////////
1049
// binary counter
1050 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1051 6 unneback
   parameter length = 4;
1052
   input cke;
1053
   input rew;
1054
   output reg level1;
1055
   input rst;
1056
   input clk;
1057
   parameter clear_value = 0;
1058
   parameter set_value = 1;
1059
   parameter wrap_value = 1;
1060
   parameter level1_value = 15;
1061 29 unneback
   wire clear;
1062 30 unneback
   assign clear = 1'b0;
1063 6 unneback
   reg  [length:1] qi;
1064
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1065
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1066
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1067
   assign q_next = rew ? q_next_rew : q_next_fw;
1068
   always @ (posedge clk or posedge rst)
1069
     if (rst)
1070
       qi <= {length{1'b0}};
1071
     else
1072
     if (cke)
1073
       qi <= q_next;
1074
    always @ (posedge clk or posedge rst)
1075
    if (rst)
1076
        level1 <= 1'b0;
1077
    else
1078
    if (cke)
1079 29 unneback
    if (clear)
1080
        level1 <= 1'b0;
1081
    else if (q_next == level1_value)
1082 6 unneback
        level1 <= 1'b1;
1083
    else if (qi == level1_value & rew)
1084
        level1 <= 1'b0;
1085
endmodule
1086
//////////////////////////////////////////////////////////////////////
1087
////                                                              ////
1088
////  Versatile counter                                           ////
1089
////                                                              ////
1090
////  Description                                                 ////
1091
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1092
////  counter                                                     ////
1093
////                                                              ////
1094
////  To Do:                                                      ////
1095
////   - add LFSR with more taps                                  ////
1096
////                                                              ////
1097
////  Author(s):                                                  ////
1098
////      - Michael Unneback, unneback@opencores.org              ////
1099
////        ORSoC AB                                              ////
1100
////                                                              ////
1101
//////////////////////////////////////////////////////////////////////
1102
////                                                              ////
1103
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1104
////                                                              ////
1105
//// This source file may be used and distributed without         ////
1106
//// restriction provided that this copyright statement is not    ////
1107
//// removed from the file and that any derivative work contains  ////
1108
//// the original copyright notice and the associated disclaimer. ////
1109
////                                                              ////
1110
//// This source file is free software; you can redistribute it   ////
1111
//// and/or modify it under the terms of the GNU Lesser General   ////
1112
//// Public License as published by the Free Software Foundation; ////
1113
//// either version 2.1 of the License, or (at your option) any   ////
1114
//// later version.                                               ////
1115
////                                                              ////
1116
//// This source is distributed in the hope that it will be       ////
1117
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1118
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1119
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1120
//// details.                                                     ////
1121
////                                                              ////
1122
//// You should have received a copy of the GNU Lesser General    ////
1123
//// Public License along with this source; if not, download it   ////
1124
//// from http://www.opencores.org/lgpl.shtml                     ////
1125
////                                                              ////
1126
//////////////////////////////////////////////////////////////////////
1127 25 unneback
// binary counter
1128
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1129
   parameter length = 4;
1130
   input cke;
1131
   input rew;
1132
   output reg zq;
1133
   output reg level1;
1134
   input rst;
1135
   input clk;
1136
   parameter clear_value = 0;
1137
   parameter set_value = 1;
1138
   parameter wrap_value = 1;
1139
   parameter level1_value = 15;
1140 29 unneback
   wire clear;
1141 30 unneback
   assign clear = 1'b0;
1142 25 unneback
   reg  [length:1] qi;
1143
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1144
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1145
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1146
   assign q_next = rew ? q_next_rew : q_next_fw;
1147
   always @ (posedge clk or posedge rst)
1148
     if (rst)
1149
       qi <= {length{1'b0}};
1150
     else
1151
     if (cke)
1152
       qi <= q_next;
1153
   always @ (posedge clk or posedge rst)
1154
     if (rst)
1155
       zq <= 1'b1;
1156
     else
1157
     if (cke)
1158
       zq <= q_next == {length{1'b0}};
1159
    always @ (posedge clk or posedge rst)
1160
    if (rst)
1161
        level1 <= 1'b0;
1162
    else
1163
    if (cke)
1164 29 unneback
    if (clear)
1165
        level1 <= 1'b0;
1166
    else if (q_next == level1_value)
1167 25 unneback
        level1 <= 1'b1;
1168
    else if (qi == level1_value & rew)
1169
        level1 <= 1'b0;
1170
endmodule
1171
//////////////////////////////////////////////////////////////////////
1172
////                                                              ////
1173
////  Versatile counter                                           ////
1174
////                                                              ////
1175
////  Description                                                 ////
1176
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1177
////  counter                                                     ////
1178
////                                                              ////
1179
////  To Do:                                                      ////
1180
////   - add LFSR with more taps                                  ////
1181
////                                                              ////
1182
////  Author(s):                                                  ////
1183
////      - Michael Unneback, unneback@opencores.org              ////
1184
////        ORSoC AB                                              ////
1185
////                                                              ////
1186
//////////////////////////////////////////////////////////////////////
1187
////                                                              ////
1188
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1189
////                                                              ////
1190
//// This source file may be used and distributed without         ////
1191
//// restriction provided that this copyright statement is not    ////
1192
//// removed from the file and that any derivative work contains  ////
1193
//// the original copyright notice and the associated disclaimer. ////
1194
////                                                              ////
1195
//// This source file is free software; you can redistribute it   ////
1196
//// and/or modify it under the terms of the GNU Lesser General   ////
1197
//// Public License as published by the Free Software Foundation; ////
1198
//// either version 2.1 of the License, or (at your option) any   ////
1199
//// later version.                                               ////
1200
////                                                              ////
1201
//// This source is distributed in the hope that it will be       ////
1202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1205
//// details.                                                     ////
1206
////                                                              ////
1207
//// You should have received a copy of the GNU Lesser General    ////
1208
//// Public License along with this source; if not, download it   ////
1209
//// from http://www.opencores.org/lgpl.shtml                     ////
1210
////                                                              ////
1211
//////////////////////////////////////////////////////////////////////
1212
// binary counter
1213
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1214
   parameter length = 4;
1215
   input cke;
1216
   input rew;
1217
   output [length:1] q;
1218
   output reg zq;
1219
   output reg level1;
1220
   input rst;
1221
   input clk;
1222
   parameter clear_value = 0;
1223
   parameter set_value = 1;
1224
   parameter wrap_value = 1;
1225
   parameter level1_value = 15;
1226 29 unneback
   wire clear;
1227 30 unneback
   assign clear = 1'b0;
1228 25 unneback
   reg  [length:1] qi;
1229
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1230
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1231
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1232
   assign q_next = rew ? q_next_rew : q_next_fw;
1233
   always @ (posedge clk or posedge rst)
1234
     if (rst)
1235
       qi <= {length{1'b0}};
1236
     else
1237
     if (cke)
1238
       qi <= q_next;
1239
   assign q = qi;
1240
   always @ (posedge clk or posedge rst)
1241
     if (rst)
1242
       zq <= 1'b1;
1243
     else
1244
     if (cke)
1245
       zq <= q_next == {length{1'b0}};
1246
    always @ (posedge clk or posedge rst)
1247
    if (rst)
1248
        level1 <= 1'b0;
1249
    else
1250
    if (cke)
1251 29 unneback
    if (clear)
1252
        level1 <= 1'b0;
1253
    else if (q_next == level1_value)
1254 25 unneback
        level1 <= 1'b1;
1255
    else if (qi == level1_value & rew)
1256
        level1 <= 1'b0;
1257
endmodule
1258
//////////////////////////////////////////////////////////////////////
1259
////                                                              ////
1260
////  Versatile counter                                           ////
1261
////                                                              ////
1262
////  Description                                                 ////
1263
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1264
////  counter                                                     ////
1265
////                                                              ////
1266
////  To Do:                                                      ////
1267
////   - add LFSR with more taps                                  ////
1268
////                                                              ////
1269
////  Author(s):                                                  ////
1270
////      - Michael Unneback, unneback@opencores.org              ////
1271
////        ORSoC AB                                              ////
1272
////                                                              ////
1273
//////////////////////////////////////////////////////////////////////
1274
////                                                              ////
1275
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1276
////                                                              ////
1277
//// This source file may be used and distributed without         ////
1278
//// restriction provided that this copyright statement is not    ////
1279
//// removed from the file and that any derivative work contains  ////
1280
//// the original copyright notice and the associated disclaimer. ////
1281
////                                                              ////
1282
//// This source file is free software; you can redistribute it   ////
1283
//// and/or modify it under the terms of the GNU Lesser General   ////
1284
//// Public License as published by the Free Software Foundation; ////
1285
//// either version 2.1 of the License, or (at your option) any   ////
1286
//// later version.                                               ////
1287
////                                                              ////
1288
//// This source is distributed in the hope that it will be       ////
1289
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1290
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1291
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1292
//// details.                                                     ////
1293
////                                                              ////
1294
//// You should have received a copy of the GNU Lesser General    ////
1295
//// Public License along with this source; if not, download it   ////
1296
//// from http://www.opencores.org/lgpl.shtml                     ////
1297
////                                                              ////
1298
//////////////////////////////////////////////////////////////////////
1299 6 unneback
// LFSR counter
1300 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1301 6 unneback
   parameter length = 4;
1302
   output reg zq;
1303
   input rst;
1304
   input clk;
1305
   parameter clear_value = 0;
1306
   parameter set_value = 1;
1307
   parameter wrap_value = 8;
1308
   parameter level1_value = 15;
1309
   reg  [length:1] qi;
1310
   reg lfsr_fb;
1311
   wire [length:1] q_next;
1312
   reg [32:1] polynom;
1313
   integer i;
1314
   always @ (qi)
1315
   begin
1316
        case (length)
1317
         2: polynom = 32'b11;                               // 0x3
1318
         3: polynom = 32'b110;                              // 0x6
1319
         4: polynom = 32'b1100;                             // 0xC
1320
         5: polynom = 32'b10100;                            // 0x14
1321
         6: polynom = 32'b110000;                           // 0x30
1322
         7: polynom = 32'b1100000;                          // 0x60
1323
         8: polynom = 32'b10111000;                         // 0xb8
1324
         9: polynom = 32'b100010000;                        // 0x110
1325
        10: polynom = 32'b1001000000;                       // 0x240
1326
        11: polynom = 32'b10100000000;                      // 0x500
1327
        12: polynom = 32'b100000101001;                     // 0x829
1328
        13: polynom = 32'b1000000001100;                    // 0x100C
1329
        14: polynom = 32'b10000000010101;                   // 0x2015
1330
        15: polynom = 32'b110000000000000;                  // 0x6000
1331
        16: polynom = 32'b1101000000001000;                 // 0xD008
1332
        17: polynom = 32'b10010000000000000;                // 0x12000
1333
        18: polynom = 32'b100000010000000000;               // 0x20400
1334
        19: polynom = 32'b1000000000000100011;              // 0x40023
1335
        20: polynom = 32'b10000010000000000000;             // 0x82000
1336
        21: polynom = 32'b101000000000000000000;            // 0x140000
1337
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1338
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1339
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1340
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1341
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1342
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1343
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1344
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1345
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1346
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1347
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1348
        default: polynom = 32'b0;
1349
        endcase
1350
        lfsr_fb = qi[length];
1351
        for (i=length-1; i>=1; i=i-1) begin
1352
            if (polynom[i])
1353
                lfsr_fb = lfsr_fb  ~^ qi[i];
1354
        end
1355
    end
1356
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1357
   always @ (posedge clk or posedge rst)
1358
     if (rst)
1359
       qi <= {length{1'b0}};
1360
     else
1361
       qi <= q_next;
1362
   always @ (posedge clk or posedge rst)
1363
     if (rst)
1364
       zq <= 1'b1;
1365
     else
1366
       zq <= q_next == {length{1'b0}};
1367
endmodule
1368
//////////////////////////////////////////////////////////////////////
1369
////                                                              ////
1370
////  Versatile counter                                           ////
1371
////                                                              ////
1372
////  Description                                                 ////
1373
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1374
////  counter                                                     ////
1375
////                                                              ////
1376
////  To Do:                                                      ////
1377
////   - add LFSR with more taps                                  ////
1378
////                                                              ////
1379
////  Author(s):                                                  ////
1380
////      - Michael Unneback, unneback@opencores.org              ////
1381
////        ORSoC AB                                              ////
1382
////                                                              ////
1383
//////////////////////////////////////////////////////////////////////
1384
////                                                              ////
1385
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1386
////                                                              ////
1387
//// This source file may be used and distributed without         ////
1388
//// restriction provided that this copyright statement is not    ////
1389
//// removed from the file and that any derivative work contains  ////
1390
//// the original copyright notice and the associated disclaimer. ////
1391
////                                                              ////
1392
//// This source file is free software; you can redistribute it   ////
1393
//// and/or modify it under the terms of the GNU Lesser General   ////
1394
//// Public License as published by the Free Software Foundation; ////
1395
//// either version 2.1 of the License, or (at your option) any   ////
1396
//// later version.                                               ////
1397
////                                                              ////
1398
//// This source is distributed in the hope that it will be       ////
1399
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1400
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1401
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1402
//// details.                                                     ////
1403
////                                                              ////
1404
//// You should have received a copy of the GNU Lesser General    ////
1405
//// Public License along with this source; if not, download it   ////
1406
//// from http://www.opencores.org/lgpl.shtml                     ////
1407
////                                                              ////
1408
//////////////////////////////////////////////////////////////////////
1409
// LFSR counter
1410 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1411 6 unneback
   parameter length = 4;
1412
   input cke;
1413
   output reg zq;
1414
   input rst;
1415
   input clk;
1416
   parameter clear_value = 0;
1417
   parameter set_value = 1;
1418
   parameter wrap_value = 8;
1419
   parameter level1_value = 15;
1420
   reg  [length:1] qi;
1421
   reg lfsr_fb;
1422
   wire [length:1] q_next;
1423
   reg [32:1] polynom;
1424
   integer i;
1425
   always @ (qi)
1426
   begin
1427
        case (length)
1428
         2: polynom = 32'b11;                               // 0x3
1429
         3: polynom = 32'b110;                              // 0x6
1430
         4: polynom = 32'b1100;                             // 0xC
1431
         5: polynom = 32'b10100;                            // 0x14
1432
         6: polynom = 32'b110000;                           // 0x30
1433
         7: polynom = 32'b1100000;                          // 0x60
1434
         8: polynom = 32'b10111000;                         // 0xb8
1435
         9: polynom = 32'b100010000;                        // 0x110
1436
        10: polynom = 32'b1001000000;                       // 0x240
1437
        11: polynom = 32'b10100000000;                      // 0x500
1438
        12: polynom = 32'b100000101001;                     // 0x829
1439
        13: polynom = 32'b1000000001100;                    // 0x100C
1440
        14: polynom = 32'b10000000010101;                   // 0x2015
1441
        15: polynom = 32'b110000000000000;                  // 0x6000
1442
        16: polynom = 32'b1101000000001000;                 // 0xD008
1443
        17: polynom = 32'b10010000000000000;                // 0x12000
1444
        18: polynom = 32'b100000010000000000;               // 0x20400
1445
        19: polynom = 32'b1000000000000100011;              // 0x40023
1446
        20: polynom = 32'b10000010000000000000;             // 0x82000
1447
        21: polynom = 32'b101000000000000000000;            // 0x140000
1448
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1449
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1450
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1451
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1452
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1453
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1454
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1455
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1456
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1457
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1458
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1459
        default: polynom = 32'b0;
1460
        endcase
1461
        lfsr_fb = qi[length];
1462
        for (i=length-1; i>=1; i=i-1) begin
1463
            if (polynom[i])
1464
                lfsr_fb = lfsr_fb  ~^ qi[i];
1465
        end
1466
    end
1467
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1468
   always @ (posedge clk or posedge rst)
1469
     if (rst)
1470
       qi <= {length{1'b0}};
1471
     else
1472
     if (cke)
1473
       qi <= q_next;
1474
   always @ (posedge clk or posedge rst)
1475
     if (rst)
1476
       zq <= 1'b1;
1477
     else
1478
     if (cke)
1479
       zq <= q_next == {length{1'b0}};
1480
endmodule
1481
//////////////////////////////////////////////////////////////////////
1482
////                                                              ////
1483
////  Versatile counter                                           ////
1484
////                                                              ////
1485
////  Description                                                 ////
1486
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1487
////  counter                                                     ////
1488
////                                                              ////
1489
////  To Do:                                                      ////
1490
////   - add LFSR with more taps                                  ////
1491
////                                                              ////
1492
////  Author(s):                                                  ////
1493
////      - Michael Unneback, unneback@opencores.org              ////
1494
////        ORSoC AB                                              ////
1495
////                                                              ////
1496
//////////////////////////////////////////////////////////////////////
1497
////                                                              ////
1498
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1499
////                                                              ////
1500
//// This source file may be used and distributed without         ////
1501
//// restriction provided that this copyright statement is not    ////
1502
//// removed from the file and that any derivative work contains  ////
1503
//// the original copyright notice and the associated disclaimer. ////
1504
////                                                              ////
1505
//// This source file is free software; you can redistribute it   ////
1506
//// and/or modify it under the terms of the GNU Lesser General   ////
1507
//// Public License as published by the Free Software Foundation; ////
1508
//// either version 2.1 of the License, or (at your option) any   ////
1509
//// later version.                                               ////
1510
////                                                              ////
1511
//// This source is distributed in the hope that it will be       ////
1512
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1513
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1514
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1515
//// details.                                                     ////
1516
////                                                              ////
1517
//// You should have received a copy of the GNU Lesser General    ////
1518
//// Public License along with this source; if not, download it   ////
1519
//// from http://www.opencores.org/lgpl.shtml                     ////
1520
////                                                              ////
1521
//////////////////////////////////////////////////////////////////////
1522
// LFSR counter
1523 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1524
   parameter length = 4;
1525
   input cke;
1526
   output [length:1] q;
1527
   input rst;
1528
   input clk;
1529
   parameter clear_value = 0;
1530
   parameter set_value = 1;
1531
   parameter wrap_value = 8;
1532
   parameter level1_value = 15;
1533
   reg  [length:1] qi;
1534
   reg lfsr_fb;
1535
   wire [length:1] q_next;
1536
   reg [32:1] polynom;
1537
   integer i;
1538
   always @ (qi)
1539
   begin
1540
        case (length)
1541
         2: polynom = 32'b11;                               // 0x3
1542
         3: polynom = 32'b110;                              // 0x6
1543
         4: polynom = 32'b1100;                             // 0xC
1544
         5: polynom = 32'b10100;                            // 0x14
1545
         6: polynom = 32'b110000;                           // 0x30
1546
         7: polynom = 32'b1100000;                          // 0x60
1547
         8: polynom = 32'b10111000;                         // 0xb8
1548
         9: polynom = 32'b100010000;                        // 0x110
1549
        10: polynom = 32'b1001000000;                       // 0x240
1550
        11: polynom = 32'b10100000000;                      // 0x500
1551
        12: polynom = 32'b100000101001;                     // 0x829
1552
        13: polynom = 32'b1000000001100;                    // 0x100C
1553
        14: polynom = 32'b10000000010101;                   // 0x2015
1554
        15: polynom = 32'b110000000000000;                  // 0x6000
1555
        16: polynom = 32'b1101000000001000;                 // 0xD008
1556
        17: polynom = 32'b10010000000000000;                // 0x12000
1557
        18: polynom = 32'b100000010000000000;               // 0x20400
1558
        19: polynom = 32'b1000000000000100011;              // 0x40023
1559
        20: polynom = 32'b10000010000000000000;             // 0x82000
1560
        21: polynom = 32'b101000000000000000000;            // 0x140000
1561
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1562
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1563
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1564
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1565
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1566
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1567
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1568
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1569
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1570
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1571
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1572
        default: polynom = 32'b0;
1573
        endcase
1574
        lfsr_fb = qi[length];
1575
        for (i=length-1; i>=1; i=i-1) begin
1576
            if (polynom[i])
1577
                lfsr_fb = lfsr_fb  ~^ qi[i];
1578
        end
1579
    end
1580
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1581
   always @ (posedge clk or posedge rst)
1582
     if (rst)
1583
       qi <= {length{1'b0}};
1584
     else
1585
     if (cke)
1586
       qi <= q_next;
1587
   assign q = qi;
1588
endmodule
1589
//////////////////////////////////////////////////////////////////////
1590
////                                                              ////
1591
////  Versatile counter                                           ////
1592
////                                                              ////
1593
////  Description                                                 ////
1594
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1595
////  counter                                                     ////
1596
////                                                              ////
1597
////  To Do:                                                      ////
1598
////   - add LFSR with more taps                                  ////
1599
////                                                              ////
1600
////  Author(s):                                                  ////
1601
////      - Michael Unneback, unneback@opencores.org              ////
1602
////        ORSoC AB                                              ////
1603
////                                                              ////
1604
//////////////////////////////////////////////////////////////////////
1605
////                                                              ////
1606
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1607
////                                                              ////
1608
//// This source file may be used and distributed without         ////
1609
//// restriction provided that this copyright statement is not    ////
1610
//// removed from the file and that any derivative work contains  ////
1611
//// the original copyright notice and the associated disclaimer. ////
1612
////                                                              ////
1613
//// This source file is free software; you can redistribute it   ////
1614
//// and/or modify it under the terms of the GNU Lesser General   ////
1615
//// Public License as published by the Free Software Foundation; ////
1616
//// either version 2.1 of the License, or (at your option) any   ////
1617
//// later version.                                               ////
1618
////                                                              ////
1619
//// This source is distributed in the hope that it will be       ////
1620
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1621
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1622
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1623
//// details.                                                     ////
1624
////                                                              ////
1625
//// You should have received a copy of the GNU Lesser General    ////
1626
//// Public License along with this source; if not, download it   ////
1627
//// from http://www.opencores.org/lgpl.shtml                     ////
1628
////                                                              ////
1629
//////////////////////////////////////////////////////////////////////
1630
// LFSR counter
1631
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1632
   parameter length = 4;
1633
   input clear;
1634
   input cke;
1635
   output [length:1] q;
1636
   input rst;
1637
   input clk;
1638
   parameter clear_value = 0;
1639
   parameter set_value = 1;
1640
   parameter wrap_value = 8;
1641
   parameter level1_value = 15;
1642
   reg  [length:1] qi;
1643
   reg lfsr_fb;
1644
   wire [length:1] q_next;
1645
   reg [32:1] polynom;
1646
   integer i;
1647
   always @ (qi)
1648
   begin
1649
        case (length)
1650
         2: polynom = 32'b11;                               // 0x3
1651
         3: polynom = 32'b110;                              // 0x6
1652
         4: polynom = 32'b1100;                             // 0xC
1653
         5: polynom = 32'b10100;                            // 0x14
1654
         6: polynom = 32'b110000;                           // 0x30
1655
         7: polynom = 32'b1100000;                          // 0x60
1656
         8: polynom = 32'b10111000;                         // 0xb8
1657
         9: polynom = 32'b100010000;                        // 0x110
1658
        10: polynom = 32'b1001000000;                       // 0x240
1659
        11: polynom = 32'b10100000000;                      // 0x500
1660
        12: polynom = 32'b100000101001;                     // 0x829
1661
        13: polynom = 32'b1000000001100;                    // 0x100C
1662
        14: polynom = 32'b10000000010101;                   // 0x2015
1663
        15: polynom = 32'b110000000000000;                  // 0x6000
1664
        16: polynom = 32'b1101000000001000;                 // 0xD008
1665
        17: polynom = 32'b10010000000000000;                // 0x12000
1666
        18: polynom = 32'b100000010000000000;               // 0x20400
1667
        19: polynom = 32'b1000000000000100011;              // 0x40023
1668
        20: polynom = 32'b10000010000000000000;             // 0x82000
1669
        21: polynom = 32'b101000000000000000000;            // 0x140000
1670
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1671
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1672
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1673
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1674
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1675
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1676
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1677
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1678
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1679
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1680
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1681
        default: polynom = 32'b0;
1682
        endcase
1683
        lfsr_fb = qi[length];
1684
        for (i=length-1; i>=1; i=i-1) begin
1685
            if (polynom[i])
1686
                lfsr_fb = lfsr_fb  ~^ qi[i];
1687
        end
1688
    end
1689
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1690
   always @ (posedge clk or posedge rst)
1691
     if (rst)
1692
       qi <= {length{1'b0}};
1693
     else
1694
     if (cke)
1695
       qi <= q_next;
1696
   assign q = qi;
1697
endmodule
1698
//////////////////////////////////////////////////////////////////////
1699
////                                                              ////
1700
////  Versatile counter                                           ////
1701
////                                                              ////
1702
////  Description                                                 ////
1703
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1704
////  counter                                                     ////
1705
////                                                              ////
1706
////  To Do:                                                      ////
1707
////   - add LFSR with more taps                                  ////
1708
////                                                              ////
1709
////  Author(s):                                                  ////
1710
////      - Michael Unneback, unneback@opencores.org              ////
1711
////        ORSoC AB                                              ////
1712
////                                                              ////
1713
//////////////////////////////////////////////////////////////////////
1714
////                                                              ////
1715
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1716
////                                                              ////
1717
//// This source file may be used and distributed without         ////
1718
//// restriction provided that this copyright statement is not    ////
1719
//// removed from the file and that any derivative work contains  ////
1720
//// the original copyright notice and the associated disclaimer. ////
1721
////                                                              ////
1722
//// This source file is free software; you can redistribute it   ////
1723
//// and/or modify it under the terms of the GNU Lesser General   ////
1724
//// Public License as published by the Free Software Foundation; ////
1725
//// either version 2.1 of the License, or (at your option) any   ////
1726
//// later version.                                               ////
1727
////                                                              ////
1728
//// This source is distributed in the hope that it will be       ////
1729
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1730
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1731
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1732
//// details.                                                     ////
1733
////                                                              ////
1734
//// You should have received a copy of the GNU Lesser General    ////
1735
//// Public License along with this source; if not, download it   ////
1736
//// from http://www.opencores.org/lgpl.shtml                     ////
1737
////                                                              ////
1738
//////////////////////////////////////////////////////////////////////
1739
// LFSR counter
1740 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1741
   parameter length = 4;
1742
   input cke;
1743
   output [length:1] q;
1744
   output reg zq;
1745
   input rst;
1746
   input clk;
1747
   parameter clear_value = 0;
1748
   parameter set_value = 1;
1749
   parameter wrap_value = 8;
1750
   parameter level1_value = 15;
1751
   reg  [length:1] qi;
1752
   reg lfsr_fb;
1753
   wire [length:1] q_next;
1754
   reg [32:1] polynom;
1755
   integer i;
1756
   always @ (qi)
1757
   begin
1758
        case (length)
1759
         2: polynom = 32'b11;                               // 0x3
1760
         3: polynom = 32'b110;                              // 0x6
1761
         4: polynom = 32'b1100;                             // 0xC
1762
         5: polynom = 32'b10100;                            // 0x14
1763
         6: polynom = 32'b110000;                           // 0x30
1764
         7: polynom = 32'b1100000;                          // 0x60
1765
         8: polynom = 32'b10111000;                         // 0xb8
1766
         9: polynom = 32'b100010000;                        // 0x110
1767
        10: polynom = 32'b1001000000;                       // 0x240
1768
        11: polynom = 32'b10100000000;                      // 0x500
1769
        12: polynom = 32'b100000101001;                     // 0x829
1770
        13: polynom = 32'b1000000001100;                    // 0x100C
1771
        14: polynom = 32'b10000000010101;                   // 0x2015
1772
        15: polynom = 32'b110000000000000;                  // 0x6000
1773
        16: polynom = 32'b1101000000001000;                 // 0xD008
1774
        17: polynom = 32'b10010000000000000;                // 0x12000
1775
        18: polynom = 32'b100000010000000000;               // 0x20400
1776
        19: polynom = 32'b1000000000000100011;              // 0x40023
1777
        20: polynom = 32'b10000010000000000000;             // 0x82000
1778
        21: polynom = 32'b101000000000000000000;            // 0x140000
1779
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1780
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1781
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1782
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1783
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1784
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1785
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1786
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1787
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1788
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1789
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1790
        default: polynom = 32'b0;
1791
        endcase
1792
        lfsr_fb = qi[length];
1793
        for (i=length-1; i>=1; i=i-1) begin
1794
            if (polynom[i])
1795
                lfsr_fb = lfsr_fb  ~^ qi[i];
1796
        end
1797
    end
1798
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1799
   always @ (posedge clk or posedge rst)
1800
     if (rst)
1801
       qi <= {length{1'b0}};
1802
     else
1803
     if (cke)
1804
       qi <= q_next;
1805
   assign q = qi;
1806
   always @ (posedge clk or posedge rst)
1807
     if (rst)
1808
       zq <= 1'b1;
1809
     else
1810
     if (cke)
1811
       zq <= q_next == {length{1'b0}};
1812
endmodule
1813
//////////////////////////////////////////////////////////////////////
1814
////                                                              ////
1815
////  Versatile counter                                           ////
1816
////                                                              ////
1817
////  Description                                                 ////
1818
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1819
////  counter                                                     ////
1820
////                                                              ////
1821
////  To Do:                                                      ////
1822
////   - add LFSR with more taps                                  ////
1823
////                                                              ////
1824
////  Author(s):                                                  ////
1825
////      - Michael Unneback, unneback@opencores.org              ////
1826
////        ORSoC AB                                              ////
1827
////                                                              ////
1828
//////////////////////////////////////////////////////////////////////
1829
////                                                              ////
1830
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1831
////                                                              ////
1832
//// This source file may be used and distributed without         ////
1833
//// restriction provided that this copyright statement is not    ////
1834
//// removed from the file and that any derivative work contains  ////
1835
//// the original copyright notice and the associated disclaimer. ////
1836
////                                                              ////
1837
//// This source file is free software; you can redistribute it   ////
1838
//// and/or modify it under the terms of the GNU Lesser General   ////
1839
//// Public License as published by the Free Software Foundation; ////
1840
//// either version 2.1 of the License, or (at your option) any   ////
1841
//// later version.                                               ////
1842
////                                                              ////
1843
//// This source is distributed in the hope that it will be       ////
1844
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1845
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1846
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1847
//// details.                                                     ////
1848
////                                                              ////
1849
//// You should have received a copy of the GNU Lesser General    ////
1850
//// Public License along with this source; if not, download it   ////
1851
//// from http://www.opencores.org/lgpl.shtml                     ////
1852
////                                                              ////
1853
//////////////////////////////////////////////////////////////////////
1854
// LFSR counter
1855 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1856 6 unneback
   parameter length = 4;
1857
   input cke;
1858
   input rew;
1859
   output reg level1;
1860
   input rst;
1861
   input clk;
1862
   parameter clear_value = 0;
1863
   parameter set_value = 1;
1864
   parameter wrap_value = 8;
1865
   parameter level1_value = 15;
1866 29 unneback
   wire clear;
1867 30 unneback
   assign clear = 1'b0;
1868 6 unneback
   reg  [length:1] qi;
1869
   reg lfsr_fb, lfsr_fb_rew;
1870
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1871
   reg [32:1] polynom_rew;
1872
   integer j;
1873
   reg [32:1] polynom;
1874
   integer i;
1875
   always @ (qi)
1876
   begin
1877
        case (length)
1878
         2: polynom = 32'b11;                               // 0x3
1879
         3: polynom = 32'b110;                              // 0x6
1880
         4: polynom = 32'b1100;                             // 0xC
1881
         5: polynom = 32'b10100;                            // 0x14
1882
         6: polynom = 32'b110000;                           // 0x30
1883
         7: polynom = 32'b1100000;                          // 0x60
1884
         8: polynom = 32'b10111000;                         // 0xb8
1885
         9: polynom = 32'b100010000;                        // 0x110
1886
        10: polynom = 32'b1001000000;                       // 0x240
1887
        11: polynom = 32'b10100000000;                      // 0x500
1888
        12: polynom = 32'b100000101001;                     // 0x829
1889
        13: polynom = 32'b1000000001100;                    // 0x100C
1890
        14: polynom = 32'b10000000010101;                   // 0x2015
1891
        15: polynom = 32'b110000000000000;                  // 0x6000
1892
        16: polynom = 32'b1101000000001000;                 // 0xD008
1893
        17: polynom = 32'b10010000000000000;                // 0x12000
1894
        18: polynom = 32'b100000010000000000;               // 0x20400
1895
        19: polynom = 32'b1000000000000100011;              // 0x40023
1896
        20: polynom = 32'b10000010000000000000;             // 0x82000
1897
        21: polynom = 32'b101000000000000000000;            // 0x140000
1898
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1899
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1900
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1901
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1902
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1903
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1904
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1905
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1906
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1907
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1908
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1909
        default: polynom = 32'b0;
1910
        endcase
1911
        lfsr_fb = qi[length];
1912
        for (i=length-1; i>=1; i=i-1) begin
1913
            if (polynom[i])
1914
                lfsr_fb = lfsr_fb  ~^ qi[i];
1915
        end
1916
    end
1917
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1918
   always @ (qi)
1919
   begin
1920
        case (length)
1921
         2: polynom_rew = 32'b11;
1922
         3: polynom_rew = 32'b110;
1923
         4: polynom_rew = 32'b1100;
1924
         5: polynom_rew = 32'b10100;
1925
         6: polynom_rew = 32'b110000;
1926
         7: polynom_rew = 32'b1100000;
1927
         8: polynom_rew = 32'b10111000;
1928
         9: polynom_rew = 32'b100010000;
1929
        10: polynom_rew = 32'b1001000000;
1930
        11: polynom_rew = 32'b10100000000;
1931
        12: polynom_rew = 32'b100000101001;
1932
        13: polynom_rew = 32'b1000000001100;
1933
        14: polynom_rew = 32'b10000000010101;
1934
        15: polynom_rew = 32'b110000000000000;
1935
        16: polynom_rew = 32'b1101000000001000;
1936
        17: polynom_rew = 32'b10010000000000000;
1937
        18: polynom_rew = 32'b100000010000000000;
1938
        19: polynom_rew = 32'b1000000000000100011;
1939
        20: polynom_rew = 32'b10000010000000000000;
1940
        21: polynom_rew = 32'b101000000000000000000;
1941
        22: polynom_rew = 32'b1100000000000000000000;
1942
        23: polynom_rew = 32'b10000100000000000000000;
1943
        24: polynom_rew = 32'b111000010000000000000000;
1944
        25: polynom_rew = 32'b1001000000000000000000000;
1945
        26: polynom_rew = 32'b10000000000000000000100011;
1946
        27: polynom_rew = 32'b100000000000000000000010011;
1947
        28: polynom_rew = 32'b1100100000000000000000000000;
1948
        29: polynom_rew = 32'b10100000000000000000000000000;
1949
        30: polynom_rew = 32'b100000000000000000000000101001;
1950
        31: polynom_rew = 32'b1001000000000000000000000000000;
1951
        32: polynom_rew = 32'b10000000001000000000000000000011;
1952
        default: polynom_rew = 32'b0;
1953
        endcase
1954
        // rotate left
1955
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1956
        lfsr_fb_rew = qi[length];
1957
        for (i=length-1; i>=1; i=i-1) begin
1958
            if (polynom_rew[i])
1959
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1960
        end
1961
    end
1962
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1963
   assign q_next = rew ? q_next_rew : q_next_fw;
1964
   always @ (posedge clk or posedge rst)
1965
     if (rst)
1966
       qi <= {length{1'b0}};
1967
     else
1968
     if (cke)
1969
       qi <= q_next;
1970
    always @ (posedge clk or posedge rst)
1971
    if (rst)
1972
        level1 <= 1'b0;
1973
    else
1974
    if (cke)
1975 29 unneback
    if (clear)
1976
        level1 <= 1'b0;
1977
    else if (q_next == level1_value)
1978 6 unneback
        level1 <= 1'b1;
1979
    else if (qi == level1_value & rew)
1980
        level1 <= 1'b0;
1981
endmodule
1982
//////////////////////////////////////////////////////////////////////
1983
////                                                              ////
1984
////  Versatile counter                                           ////
1985
////                                                              ////
1986
////  Description                                                 ////
1987
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1988
////  counter                                                     ////
1989
////                                                              ////
1990
////  To Do:                                                      ////
1991
////   - add LFSR with more taps                                  ////
1992
////                                                              ////
1993
////  Author(s):                                                  ////
1994
////      - Michael Unneback, unneback@opencores.org              ////
1995
////        ORSoC AB                                              ////
1996
////                                                              ////
1997
//////////////////////////////////////////////////////////////////////
1998
////                                                              ////
1999
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2000
////                                                              ////
2001
//// This source file may be used and distributed without         ////
2002
//// restriction provided that this copyright statement is not    ////
2003
//// removed from the file and that any derivative work contains  ////
2004
//// the original copyright notice and the associated disclaimer. ////
2005
////                                                              ////
2006
//// This source file is free software; you can redistribute it   ////
2007
//// and/or modify it under the terms of the GNU Lesser General   ////
2008
//// Public License as published by the Free Software Foundation; ////
2009
//// either version 2.1 of the License, or (at your option) any   ////
2010
//// later version.                                               ////
2011
////                                                              ////
2012
//// This source is distributed in the hope that it will be       ////
2013
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2014
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2015
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2016
//// details.                                                     ////
2017
////                                                              ////
2018
//// You should have received a copy of the GNU Lesser General    ////
2019
//// Public License along with this source; if not, download it   ////
2020
//// from http://www.opencores.org/lgpl.shtml                     ////
2021
////                                                              ////
2022
//////////////////////////////////////////////////////////////////////
2023
// GRAY counter
2024 18 unneback
module vl_cnt_gray ( q, rst, clk);
2025 6 unneback
   parameter length = 4;
2026
   output reg [length:1] q;
2027
   input rst;
2028
   input clk;
2029
   parameter clear_value = 0;
2030
   parameter set_value = 1;
2031
   parameter wrap_value = 8;
2032
   parameter level1_value = 15;
2033
   reg  [length:1] qi;
2034
   wire [length:1] q_next;
2035
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2036
   always @ (posedge clk or posedge rst)
2037
     if (rst)
2038
       qi <= {length{1'b0}};
2039
     else
2040
       qi <= q_next;
2041
   always @ (posedge clk or posedge rst)
2042
     if (rst)
2043
       q <= {length{1'b0}};
2044
     else
2045
         q <= (q_next>>1) ^ q_next;
2046
endmodule
2047
//////////////////////////////////////////////////////////////////////
2048
////                                                              ////
2049
////  Versatile counter                                           ////
2050
////                                                              ////
2051
////  Description                                                 ////
2052
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2053
////  counter                                                     ////
2054
////                                                              ////
2055
////  To Do:                                                      ////
2056
////   - add LFSR with more taps                                  ////
2057
////                                                              ////
2058
////  Author(s):                                                  ////
2059
////      - Michael Unneback, unneback@opencores.org              ////
2060
////        ORSoC AB                                              ////
2061
////                                                              ////
2062
//////////////////////////////////////////////////////////////////////
2063
////                                                              ////
2064
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2065
////                                                              ////
2066
//// This source file may be used and distributed without         ////
2067
//// restriction provided that this copyright statement is not    ////
2068
//// removed from the file and that any derivative work contains  ////
2069
//// the original copyright notice and the associated disclaimer. ////
2070
////                                                              ////
2071
//// This source file is free software; you can redistribute it   ////
2072
//// and/or modify it under the terms of the GNU Lesser General   ////
2073
//// Public License as published by the Free Software Foundation; ////
2074
//// either version 2.1 of the License, or (at your option) any   ////
2075
//// later version.                                               ////
2076
////                                                              ////
2077
//// This source is distributed in the hope that it will be       ////
2078
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2079
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2080
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2081
//// details.                                                     ////
2082
////                                                              ////
2083
//// You should have received a copy of the GNU Lesser General    ////
2084
//// Public License along with this source; if not, download it   ////
2085
//// from http://www.opencores.org/lgpl.shtml                     ////
2086
////                                                              ////
2087
//////////////////////////////////////////////////////////////////////
2088
// GRAY counter
2089 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2090 6 unneback
   parameter length = 4;
2091
   input cke;
2092
   output reg [length:1] q;
2093
   input rst;
2094
   input clk;
2095
   parameter clear_value = 0;
2096
   parameter set_value = 1;
2097
   parameter wrap_value = 8;
2098
   parameter level1_value = 15;
2099
   reg  [length:1] qi;
2100
   wire [length:1] q_next;
2101
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2102
   always @ (posedge clk or posedge rst)
2103
     if (rst)
2104
       qi <= {length{1'b0}};
2105
     else
2106
     if (cke)
2107
       qi <= q_next;
2108
   always @ (posedge clk or posedge rst)
2109
     if (rst)
2110
       q <= {length{1'b0}};
2111
     else
2112
       if (cke)
2113
         q <= (q_next>>1) ^ q_next;
2114
endmodule
2115
//////////////////////////////////////////////////////////////////////
2116
////                                                              ////
2117
////  Versatile counter                                           ////
2118
////                                                              ////
2119
////  Description                                                 ////
2120
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2121
////  counter                                                     ////
2122
////                                                              ////
2123
////  To Do:                                                      ////
2124
////   - add LFSR with more taps                                  ////
2125
////                                                              ////
2126
////  Author(s):                                                  ////
2127
////      - Michael Unneback, unneback@opencores.org              ////
2128
////        ORSoC AB                                              ////
2129
////                                                              ////
2130
//////////////////////////////////////////////////////////////////////
2131
////                                                              ////
2132
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2133
////                                                              ////
2134
//// This source file may be used and distributed without         ////
2135
//// restriction provided that this copyright statement is not    ////
2136
//// removed from the file and that any derivative work contains  ////
2137
//// the original copyright notice and the associated disclaimer. ////
2138
////                                                              ////
2139
//// This source file is free software; you can redistribute it   ////
2140
//// and/or modify it under the terms of the GNU Lesser General   ////
2141
//// Public License as published by the Free Software Foundation; ////
2142
//// either version 2.1 of the License, or (at your option) any   ////
2143
//// later version.                                               ////
2144
////                                                              ////
2145
//// This source is distributed in the hope that it will be       ////
2146
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2147
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2148
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2149
//// details.                                                     ////
2150
////                                                              ////
2151
//// You should have received a copy of the GNU Lesser General    ////
2152
//// Public License along with this source; if not, download it   ////
2153
//// from http://www.opencores.org/lgpl.shtml                     ////
2154
////                                                              ////
2155
//////////////////////////////////////////////////////////////////////
2156
// GRAY counter
2157 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2158 6 unneback
   parameter length = 4;
2159
   input cke;
2160
   output reg [length:1] q;
2161
   output [length:1] q_bin;
2162
   input rst;
2163
   input clk;
2164
   parameter clear_value = 0;
2165
   parameter set_value = 1;
2166
   parameter wrap_value = 8;
2167
   parameter level1_value = 15;
2168
   reg  [length:1] qi;
2169
   wire [length:1] q_next;
2170
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2171
   always @ (posedge clk or posedge rst)
2172
     if (rst)
2173
       qi <= {length{1'b0}};
2174
     else
2175
     if (cke)
2176
       qi <= q_next;
2177
   always @ (posedge clk or posedge rst)
2178
     if (rst)
2179
       q <= {length{1'b0}};
2180
     else
2181
       if (cke)
2182
         q <= (q_next>>1) ^ q_next;
2183
   assign q_bin = qi;
2184
endmodule
2185
//////////////////////////////////////////////////////////////////////
2186
////                                                              ////
2187
////  Versatile library, counters                                 ////
2188
////                                                              ////
2189
////  Description                                                 ////
2190
////  counters                                                    ////
2191
////                                                              ////
2192
////                                                              ////
2193
////  To Do:                                                      ////
2194
////   - add more counters                                        ////
2195
////                                                              ////
2196
////  Author(s):                                                  ////
2197
////      - Michael Unneback, unneback@opencores.org              ////
2198
////        ORSoC AB                                              ////
2199
////                                                              ////
2200
//////////////////////////////////////////////////////////////////////
2201
////                                                              ////
2202
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2203
////                                                              ////
2204
//// This source file may be used and distributed without         ////
2205
//// restriction provided that this copyright statement is not    ////
2206
//// removed from the file and that any derivative work contains  ////
2207
//// the original copyright notice and the associated disclaimer. ////
2208
////                                                              ////
2209
//// This source file is free software; you can redistribute it   ////
2210
//// and/or modify it under the terms of the GNU Lesser General   ////
2211
//// Public License as published by the Free Software Foundation; ////
2212
//// either version 2.1 of the License, or (at your option) any   ////
2213
//// later version.                                               ////
2214
////                                                              ////
2215
//// This source is distributed in the hope that it will be       ////
2216
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2217
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2218
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2219
//// details.                                                     ////
2220
////                                                              ////
2221
//// You should have received a copy of the GNU Lesser General    ////
2222
//// Public License along with this source; if not, download it   ////
2223
//// from http://www.opencores.org/lgpl.shtml                     ////
2224
////                                                              ////
2225
//////////////////////////////////////////////////////////////////////
2226 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2227 6 unneback
   parameter length = 4;
2228
   output reg [0:length-1] q;
2229
   input rst;
2230
   input clk;
2231
    always @ (posedge clk or posedge rst)
2232
    if (rst)
2233
        q <= {1'b1,{length-1{1'b0}}};
2234
    else
2235
        q <= {q[length-1],q[0:length-2]};
2236
endmodule
2237 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2238 6 unneback
   parameter length = 4;
2239
   input cke;
2240
   output reg [0:length-1] q;
2241
   input rst;
2242
   input clk;
2243
    always @ (posedge clk or posedge rst)
2244
    if (rst)
2245
        q <= {1'b1,{length-1{1'b0}}};
2246
    else
2247
        if (cke)
2248
            q <= {q[length-1],q[0:length-2]};
2249
endmodule
2250 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2251 6 unneback
   parameter length = 4;
2252
   input cke, clear;
2253
   output reg [0:length-1] q;
2254
   input rst;
2255
   input clk;
2256
    always @ (posedge clk or posedge rst)
2257
    if (rst)
2258
        q <= {1'b1,{length-1{1'b0}}};
2259
    else
2260
        if (cke)
2261
            if (clear)
2262
                q <= {1'b1,{length-1{1'b0}}};
2263
            else
2264
                q <= q >> 1;
2265
endmodule
2266 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2267 6 unneback
   parameter length = 4;
2268
   input cke, clear;
2269
   output reg [0:length-1] q;
2270
   input rst;
2271
   input clk;
2272
    always @ (posedge clk or posedge rst)
2273
    if (rst)
2274
        q <= {1'b1,{length-1{1'b0}}};
2275
    else
2276
        if (cke)
2277
            if (clear)
2278
                q <= {1'b1,{length-1{1'b0}}};
2279
            else
2280
            q <= {q[length-1],q[0:length-2]};
2281
endmodule
2282
//////////////////////////////////////////////////////////////////////
2283
////                                                              ////
2284
////  Versatile library, memories                                 ////
2285
////                                                              ////
2286
////  Description                                                 ////
2287
////  memories                                                    ////
2288
////                                                              ////
2289
////                                                              ////
2290
////  To Do:                                                      ////
2291
////   - add more memory types                                    ////
2292
////                                                              ////
2293
////  Author(s):                                                  ////
2294
////      - Michael Unneback, unneback@opencores.org              ////
2295
////        ORSoC AB                                              ////
2296
////                                                              ////
2297
//////////////////////////////////////////////////////////////////////
2298
////                                                              ////
2299
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2300
////                                                              ////
2301
//// This source file may be used and distributed without         ////
2302
//// restriction provided that this copyright statement is not    ////
2303
//// removed from the file and that any derivative work contains  ////
2304
//// the original copyright notice and the associated disclaimer. ////
2305
////                                                              ////
2306
//// This source file is free software; you can redistribute it   ////
2307
//// and/or modify it under the terms of the GNU Lesser General   ////
2308
//// Public License as published by the Free Software Foundation; ////
2309
//// either version 2.1 of the License, or (at your option) any   ////
2310
//// later version.                                               ////
2311
////                                                              ////
2312
//// This source is distributed in the hope that it will be       ////
2313
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2314
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2315
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2316
//// details.                                                     ////
2317
////                                                              ////
2318
//// You should have received a copy of the GNU Lesser General    ////
2319
//// Public License along with this source; if not, download it   ////
2320
//// from http://www.opencores.org/lgpl.shtml                     ////
2321
////                                                              ////
2322
//////////////////////////////////////////////////////////////////////
2323
/// ROM
2324 7 unneback
module vl_rom_init ( adr, q, clk);
2325
   parameter data_width = 32;
2326
   parameter addr_width = 8;
2327
   input [(addr_width-1):0]       adr;
2328
   output reg [(data_width-1):0] q;
2329
   input                         clk;
2330
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2331
   parameter memory_file = "vl_rom.vmem";
2332
   initial
2333
     begin
2334
        $readmemh(memory_file, rom);
2335
     end
2336
   always @ (posedge clk)
2337
     q <= rom[adr];
2338
endmodule
2339 14 unneback
/*
2340 7 unneback
module vl_rom ( adr, q, clk);
2341 6 unneback
parameter data_width = 32;
2342
parameter addr_width = 4;
2343
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2344
    {32'h18000000},
2345
    {32'hA8200000},
2346
    {32'hA8200000},
2347
    {32'hA8200000},
2348
    {32'h44003000},
2349
    {32'h15000000},
2350
    {32'h15000000},
2351
    {32'h15000000},
2352
    {32'h15000000},
2353
    {32'h15000000},
2354
    {32'h15000000},
2355
    {32'h15000000},
2356
    {32'h15000000},
2357
    {32'h15000000},
2358
    {32'h15000000},
2359
    {32'h15000000}};
2360 7 unneback
input [addr_width-1:0] adr;
2361 6 unneback
output reg [data_width-1:0] q;
2362
input clk;
2363
always @ (posedge clk)
2364 7 unneback
    q <= data[adr];
2365 6 unneback
endmodule
2366 14 unneback
*/
2367 6 unneback
// Single port RAM
2368
module vl_ram ( d, adr, we, q, clk);
2369
   parameter data_width = 32;
2370
   parameter addr_width = 8;
2371
   input [(data_width-1):0]      d;
2372
   input [(addr_width-1):0]       adr;
2373
   input                         we;
2374 7 unneback
   output reg [(data_width-1):0] q;
2375 6 unneback
   input                         clk;
2376
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2377 7 unneback
   parameter init = 0;
2378
   parameter memory_file = "vl_ram.vmem";
2379
   generate if (init) begin : init_mem
2380
   initial
2381
     begin
2382
        $readmemh(memory_file, ram);
2383
     end
2384
   end
2385
   endgenerate
2386 6 unneback
   always @ (posedge clk)
2387
   begin
2388
   if (we)
2389
     ram[adr] <= d;
2390
   q <= ram[adr];
2391
   end
2392
endmodule
2393 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2394
   parameter data_width = 32;
2395
   parameter addr_width = 8;
2396
   input [(data_width-1):0]      d;
2397
   input [(addr_width-1):0]       adr;
2398
   input [(addr_width/4)-1:0]    be;
2399
   input                         we;
2400
   output reg [(data_width-1):0] q;
2401
   input                         clk;
2402
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2403
   parameter init = 0;
2404
   parameter memory_file = "vl_ram.vmem";
2405
   generate if (init) begin : init_mem
2406
   initial
2407
     begin
2408
        $readmemh(memory_file, ram);
2409
     end
2410
   end
2411
   endgenerate
2412
   genvar i;
2413
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2414
      always @ (posedge clk)
2415
      if (we & be[i])
2416
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2417
   end
2418
   endgenerate
2419
   always @ (posedge clk)
2420
      q <= ram[adr];
2421
endmodule
2422 6 unneback
// Dual port RAM
2423
// ACTEL FPGA should not use logic to handle rw collision
2424 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2425 6 unneback
   parameter data_width = 32;
2426
   parameter addr_width = 8;
2427
   input [(data_width-1):0]      d_a;
2428
   input [(addr_width-1):0]       adr_a;
2429
   input [(addr_width-1):0]       adr_b;
2430
   input                         we_a;
2431
   output [(data_width-1):0]      q_b;
2432
   input                         clk_a, clk_b;
2433
   reg [(addr_width-1):0]         adr_b_reg;
2434
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2435 7 unneback
   parameter init = 0;
2436
   parameter memory_file = "vl_ram.vmem";
2437
   generate if (init) begin : init_mem
2438
   initial
2439
     begin
2440
        $readmemh(memory_file, ram);
2441
     end
2442
   end
2443
   endgenerate
2444 6 unneback
   always @ (posedge clk_a)
2445
   if (we_a)
2446
     ram[adr_a] <= d_a;
2447
   always @ (posedge clk_b)
2448
   adr_b_reg <= adr_b;
2449
   assign q_b = ram[adr_b_reg];
2450
endmodule
2451 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2452 6 unneback
   parameter data_width = 32;
2453
   parameter addr_width = 8;
2454
   input [(data_width-1):0]      d_a;
2455
   input [(addr_width-1):0]       adr_a;
2456
   input [(addr_width-1):0]       adr_b;
2457
   input                         we_a;
2458
   output [(data_width-1):0]      q_b;
2459
   output reg [(data_width-1):0] q_a;
2460
   input                         clk_a, clk_b;
2461
   reg [(data_width-1):0]         q_b;
2462
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2463 7 unneback
   parameter init = 0;
2464
   parameter memory_file = "vl_ram.vmem";
2465
   generate if (init) begin : init_mem
2466
   initial
2467
     begin
2468
        $readmemh(memory_file, ram);
2469
     end
2470
   end
2471
   endgenerate
2472 6 unneback
   always @ (posedge clk_a)
2473
     begin
2474
        q_a <= ram[adr_a];
2475
        if (we_a)
2476
             ram[adr_a] <= d_a;
2477
     end
2478
   always @ (posedge clk_b)
2479
          q_b <= ram[adr_b];
2480
endmodule
2481 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2482 6 unneback
   parameter data_width = 32;
2483
   parameter addr_width = 8;
2484
   input [(data_width-1):0]      d_a;
2485
   input [(addr_width-1):0]       adr_a;
2486
   input [(addr_width-1):0]       adr_b;
2487
   input                         we_a;
2488
   output [(data_width-1):0]      q_b;
2489
   input [(data_width-1):0]       d_b;
2490
   output reg [(data_width-1):0] q_a;
2491
   input                         we_b;
2492
   input                         clk_a, clk_b;
2493
   reg [(data_width-1):0]         q_b;
2494
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2495 7 unneback
   parameter init = 0;
2496
   parameter memory_file = "vl_ram.vmem";
2497
   generate if (init) begin : init_mem
2498
   initial
2499
     begin
2500
        $readmemh(memory_file, ram);
2501
     end
2502
   end
2503
   endgenerate
2504 6 unneback
   always @ (posedge clk_a)
2505
     begin
2506
        q_a <= ram[adr_a];
2507
        if (we_a)
2508
             ram[adr_a] <= d_a;
2509
     end
2510
   always @ (posedge clk_b)
2511
     begin
2512
        q_b <= ram[adr_b];
2513
        if (we_b)
2514
          ram[adr_b] <= d_b;
2515
     end
2516
endmodule
2517
// Content addresable memory, CAM
2518
// FIFO
2519 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2520
    d, wr, fifo_full,
2521
    q, rd, fifo_empty,
2522
    fill_level,
2523
    clk, rst
2524
    );
2525
parameter data_width = 18;
2526
parameter addr_width = 4;
2527
// write side
2528
input  [data_width-1:0] d;
2529
input                   wr;
2530
output                  fifo_full;
2531
// read side
2532
output [data_width-1:0] q;
2533
input                   rd;
2534
output                  fifo_empty;
2535
// common
2536
output [addr_width:0]   fill_level;
2537
input rst, clk;
2538
wire [addr_width:1] wadr, radr;
2539
vl_cnt_bin_ce
2540
    # ( .length(addr_width))
2541
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2542
vl_cnt_bin_ce
2543
    # (.length(addr_width))
2544
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2545
vl_dpram_1r1w
2546
    # (.data_width(data_width), .addr_width(addr_width))
2547
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2548 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
2549 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2550 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2551
endmodule
2552 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2553
// RAM is supposed to be larger than the two FIFOs
2554
// LFSR counters used adr pointers
2555
module vl_fifo_2r2w_sync_simplex (
2556
    // a side
2557
    a_d, a_wr, a_fifo_full,
2558
    a_q, a_rd, a_fifo_empty,
2559
    a_fill_level,
2560
    // b side
2561
    b_d, b_wr, b_fifo_full,
2562
    b_q, b_rd, b_fifo_empty,
2563
    b_fill_level,
2564
    // common
2565
    clk, rst
2566
    );
2567
parameter data_width = 8;
2568
parameter addr_width = 5;
2569
parameter fifo_full_level = (1<<addr_width)-1;
2570
// a side
2571
input  [data_width-1:0] a_d;
2572
input                   a_wr;
2573
output                  a_fifo_full;
2574
output [data_width-1:0] a_q;
2575
input                   a_rd;
2576
output                  a_fifo_empty;
2577
output [addr_width-1:0] a_fill_level;
2578
// b side
2579
input  [data_width-1:0] b_d;
2580
input                   b_wr;
2581
output                  b_fifo_full;
2582
output [data_width-1:0] b_q;
2583
input                   b_rd;
2584
output                  b_fifo_empty;
2585
output [addr_width-1:0] b_fill_level;
2586
input                   clk;
2587
input                   rst;
2588
// adr_gen
2589
wire [addr_width:1] a_wadr, a_radr;
2590
wire [addr_width:1] b_wadr, b_radr;
2591
// dpram
2592
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2593
vl_cnt_lfsr_ce
2594
    # ( .length(addr_width))
2595
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2596
vl_cnt_lfsr_ce
2597
    # (.length(addr_width))
2598
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2599
vl_cnt_lfsr_ce
2600
    # ( .length(addr_width))
2601
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2602
vl_cnt_lfsr_ce
2603
    # (.length(addr_width))
2604
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2605
// mux read or write adr to DPRAM
2606
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2607
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2608
vl_dpram_2r2w
2609
    # (.data_width(data_width), .addr_width(addr_width+1))
2610
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr