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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 35

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1 6 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 33 unneback
module vl_gbuf ( i, o);
47
input i;
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output o;
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assign o = i;
50
endmodule
51 6 unneback
 // ALTERA
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 //ACTEL
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// sync reset
54 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
55 6 unneback
// output active high global reset sync with two DFFs 
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`timescale 1 ns/100 ps
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module vl_sync_rst ( rst_n_i, rst_o, clk);
58
input rst_n_i, clk;
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output rst_o;
60 18 unneback
reg [1:0] tmp;
61 6 unneback
always @ (posedge clk or negedge rst_n_i)
62
if (!rst_n_i)
63 17 unneback
        tmp <= 2'b11;
64 6 unneback
else
65 33 unneback
        tmp <= {1'b0,tmp[1]};
66 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
67 6 unneback
endmodule
68
// vl_pll
69 32 unneback
///////////////////////////////////////////////////////////////////////////////
70
`timescale 1 ps/1 ps
71
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
72
parameter index = 0;
73
parameter number_of_clk = 1;
74
parameter period_time_0 = 20000;
75
parameter period_time_1 = 20000;
76
parameter period_time_2 = 20000;
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parameter period_time_3 = 20000;
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parameter period_time_4 = 20000;
79
parameter lock_delay = 2000000;
80
input clk_i, rst_n_i;
81
output lock;
82
output reg [0:number_of_clk-1] clk_o;
83
output [0:number_of_clk-1] rst_o;
84 33 unneback
`ifdef SIM_PLL
85 32 unneback
always
86
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
87
generate if (number_of_clk > 1)
88
always
89
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
90
endgenerate
91
generate if (number_of_clk > 2)
92
always
93
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
94
endgenerate
95 33 unneback
generate if (number_of_clk > 3)
96 32 unneback
always
97
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
98
endgenerate
99 33 unneback
generate if (number_of_clk > 4)
100 32 unneback
always
101
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
102
endgenerate
103
genvar i;
104
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
105
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
106
end
107
endgenerate
108 33 unneback
//assign #lock_delay lock = rst_n_i;
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assign lock = rst_n_i;
110 32 unneback
endmodule
111 33 unneback
`else
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`ifdef VL_PLL0
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`ifdef VL_PLL0_CLK1
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
115
`endif
116
`ifdef VL_PLL0_CLK2
117
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
119
`ifdef VL_PLL0_CLK3
120
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL0_CLK4
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL0_CLK5
126
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
127
`endif
128
`endif
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`ifdef VL_PLL1
130
`ifdef VL_PLL1_CLK1
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL1_CLK2
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL1_CLK3
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL1_CLK4
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL1_CLK5
143
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL2
147
`ifdef VL_PLL2_CLK1
148
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL2_CLK2
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL2_CLK3
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
156
`ifdef VL_PLL2_CLK4
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
159
`ifdef VL_PLL2_CLK5
160
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
162
`endif
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`ifdef VL_PLL3
164
`ifdef VL_PLL3_CLK1
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    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
166
`endif
167
`ifdef VL_PLL3_CLK2
168
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
169
`endif
170
`ifdef VL_PLL3_CLK3
171
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
172
`endif
173
`ifdef VL_PLL3_CLK4
174
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
175
`endif
176
`ifdef VL_PLL3_CLK5
177
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
178
`endif
179
`endif
180 32 unneback
genvar i;
181
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
182 33 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
183 32 unneback
end
184
endgenerate
185
endmodule
186 33 unneback
`endif
187 32 unneback
///////////////////////////////////////////////////////////////////////////////
188 6 unneback
 //altera
189
 //actel
190
//////////////////////////////////////////////////////////////////////
191
////                                                              ////
192
////  Versatile library, registers                                ////
193
////                                                              ////
194
////  Description                                                 ////
195
////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
198
////  To Do:                                                      ////
199
////   - add more different registers                             ////
200
////                                                              ////
201
////  Author(s):                                                  ////
202
////      - Michael Unneback, unneback@opencores.org              ////
203
////        ORSoC AB                                              ////
204
////                                                              ////
205
//////////////////////////////////////////////////////////////////////
206
////                                                              ////
207
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
208
////                                                              ////
209
//// This source file may be used and distributed without         ////
210
//// restriction provided that this copyright statement is not    ////
211
//// removed from the file and that any derivative work contains  ////
212
//// the original copyright notice and the associated disclaimer. ////
213
////                                                              ////
214
//// This source file is free software; you can redistribute it   ////
215
//// and/or modify it under the terms of the GNU Lesser General   ////
216
//// Public License as published by the Free Software Foundation; ////
217
//// either version 2.1 of the License, or (at your option) any   ////
218
//// later version.                                               ////
219
////                                                              ////
220
//// This source is distributed in the hope that it will be       ////
221
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
222
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
223
//// PURPOSE.  See the GNU Lesser General Public License for more ////
224
//// details.                                                     ////
225
////                                                              ////
226
//// You should have received a copy of the GNU Lesser General    ////
227
//// Public License along with this source; if not, download it   ////
228
//// from http://www.opencores.org/lgpl.shtml                     ////
229
////                                                              ////
230
//////////////////////////////////////////////////////////////////////
231 18 unneback
module vl_dff ( d, q, clk, rst);
232 6 unneback
        parameter width = 1;
233
        parameter reset_value = 0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output reg [width-1:0] q;
237
        always @ (posedge clk or posedge rst)
238
        if (rst)
239
                q <= reset_value;
240
        else
241
                q <= d;
242
endmodule
243 18 unneback
module vl_dff_array ( d, q, clk, rst);
244 6 unneback
        parameter width = 1;
245
        parameter depth = 2;
246
        parameter reset_value = 1'b0;
247
        input [width-1:0] d;
248
        input clk, rst;
249
        output [width-1:0] q;
250
        reg  [0:depth-1] q_tmp [width-1:0];
251
        integer i;
252
        always @ (posedge clk or posedge rst)
253
        if (rst) begin
254
            for (i=0;i<depth;i=i+1)
255
                q_tmp[i] <= {width{reset_value}};
256
        end else begin
257
            q_tmp[0] <= d;
258
            for (i=1;i<depth;i=i+1)
259
                q_tmp[i] <= q_tmp[i-1];
260
        end
261
    assign q = q_tmp[depth-1];
262
endmodule
263 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
264 6 unneback
        parameter width = 1;
265
        parameter reset_value = 0;
266
        input [width-1:0] d;
267
        input ce, clk, rst;
268
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
                q <= reset_value;
272
        else
273
                if (ce)
274
                        q <= d;
275
endmodule
276 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
277 8 unneback
        parameter width = 1;
278
        parameter reset_value = 0;
279
        input [width-1:0] d;
280 10 unneback
        input ce, clear, clk, rst;
281 8 unneback
        output reg [width-1:0] q;
282
        always @ (posedge clk or posedge rst)
283
        if (rst)
284
            q <= reset_value;
285
        else
286
            if (ce)
287
                if (clear)
288
                    q <= {width{1'b0}};
289
                else
290
                    q <= d;
291
endmodule
292 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
293
        parameter width = 1;
294
        parameter reset_value = 0;
295
        input [width-1:0] d;
296
        input ce, set, clk, rst;
297
        output reg [width-1:0] q;
298
        always @ (posedge clk or posedge rst)
299
        if (rst)
300
            q <= reset_value;
301
        else
302
            if (ce)
303
                if (set)
304
                    q <= {width{1'b1}};
305
                else
306
                    q <= d;
307
endmodule
308 29 unneback
module vl_spr ( sp, r, q, clk, rst);
309
        parameter width = 1;
310
        parameter reset_value = 0;
311
        input sp, r;
312
        output reg q;
313
        input clk, rst;
314
        always @ (posedge clk or posedge rst)
315
        if (rst)
316
            q <= reset_value;
317
        else
318
            if (sp)
319
                q <= 1'b1;
320
            else if (r)
321
                q <= 1'b0;
322
endmodule
323
module vl_srp ( s, rp, q, clk, rst);
324
        parameter width = 1;
325
        parameter reset_value = 0;
326
        input s, rp;
327
        output reg q;
328
        input clk, rst;
329
        always @ (posedge clk or posedge rst)
330
        if (rst)
331
            q <= reset_value;
332
        else
333
            if (rp)
334
                q <= 1'b0;
335
            else if (s)
336
                q <= 1'b1;
337
endmodule
338 6 unneback
// megafunction wizard: %LPM_FF%
339
// GENERATION: STANDARD
340
// VERSION: WM1.0
341
// MODULE: lpm_ff 
342
// ============================================================
343
// File Name: dff_sr.v
344
// Megafunction Name(s):
345
//                      lpm_ff
346
//
347
// Simulation Library Files(s):
348
//                      lpm
349
// ============================================================
350
// ************************************************************
351
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
352
//
353
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
354
// ************************************************************
355
//Copyright (C) 1991-2010 Altera Corporation
356
//Your use of Altera Corporation's design tools, logic functions 
357
//and other software and tools, and its AMPP partner logic 
358
//functions, and any output files from any of the foregoing 
359
//(including device programming or simulation files), and any 
360
//associated documentation or information are expressly subject 
361
//to the terms and conditions of the Altera Program License 
362
//Subscription Agreement, Altera MegaCore Function License 
363
//Agreement, or other applicable license agreement, including, 
364
//without limitation, that your use is for the sole purpose of 
365
//programming logic devices manufactured by Altera and sold by 
366
//Altera or its authorized distributors.  Please refer to the 
367
//applicable agreement for further details.
368
// synopsys translate_off
369
`timescale 1 ps / 1 ps
370
// synopsys translate_on
371 18 unneback
module vl_dff_sr (
372 6 unneback
        aclr,
373
        aset,
374
        clock,
375
        data,
376
        q);
377
        input     aclr;
378
        input     aset;
379
        input     clock;
380
        input     data;
381
        output    q;
382
        wire [0:0] sub_wire0;
383
        wire [0:0] sub_wire1 = sub_wire0[0:0];
384
        wire  q = sub_wire1;
385
        wire  sub_wire2 = data;
386
        wire  sub_wire3 = sub_wire2;
387
        lpm_ff  lpm_ff_component (
388
                                .aclr (aclr),
389
                                .clock (clock),
390
                                .data (sub_wire3),
391
                                .aset (aset),
392
                                .q (sub_wire0)
393
                                // synopsys translate_off
394
                                ,
395
                                .aload (),
396
                                .enable (),
397
                                .sclr (),
398
                                .sload (),
399
                                .sset ()
400
                                // synopsys translate_on
401
                                );
402
        defparam
403
                lpm_ff_component.lpm_fftype = "DFF",
404
                lpm_ff_component.lpm_type = "LPM_FF",
405
                lpm_ff_component.lpm_width = 1;
406
endmodule
407
// ============================================================
408
// CNX file retrieval info
409
// ============================================================
410
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
411
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
412
// Retrieval info: PRIVATE: ASET NUMERIC "1"
413
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
414
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
415
// Retrieval info: PRIVATE: DFF NUMERIC "1"
416
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
417
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
418
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET NUMERIC "0"
420
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
421
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
422
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
423
// Retrieval info: PRIVATE: nBit NUMERIC "1"
424
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
425
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
426
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
427
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
428
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
429
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
430
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
431
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
432
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
433
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
434
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
435
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
436
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
437
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
444
// Retrieval info: LIB_FILE: lpm
445
// LATCH
446
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
447 18 unneback
module vl_latch ( d, le, q, clk);
448 6 unneback
input d, le;
449
output q;
450
input clk;
451
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
452
endmodule
453 18 unneback
module vl_shreg ( d, q, clk, rst);
454 17 unneback
parameter depth = 10;
455
input d;
456
output q;
457
input clk, rst;
458
reg [1:depth] dffs;
459
always @ (posedge clk or posedge rst)
460
if (rst)
461
    dffs <= {depth{1'b0}};
462
else
463
    dffs <= {d,dffs[1:depth-1]};
464
assign q = dffs[depth];
465
endmodule
466 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
467 17 unneback
parameter depth = 10;
468
input d, ce;
469
output q;
470
input clk, rst;
471
reg [1:depth] dffs;
472
always @ (posedge clk or posedge rst)
473
if (rst)
474
    dffs <= {depth{1'b0}};
475
else
476
    if (ce)
477
        dffs <= {d,dffs[1:depth-1]};
478
assign q = dffs[depth];
479
endmodule
480 18 unneback
module vl_delay ( d, q, clk, rst);
481 15 unneback
parameter depth = 10;
482
input d;
483
output q;
484
input clk, rst;
485
reg [1:depth] dffs;
486
always @ (posedge clk or posedge rst)
487
if (rst)
488
    dffs <= {depth{1'b0}};
489
else
490
    dffs <= {d,dffs[1:depth-1]};
491
assign q = dffs[depth];
492
endmodule
493 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
494 17 unneback
parameter depth = 10;
495
input d;
496
output q, emptyflag;
497
input clk, rst;
498
reg [1:depth] dffs;
499
always @ (posedge clk or posedge rst)
500
if (rst)
501
    dffs <= {depth{1'b0}};
502
else
503
    dffs <= {d,dffs[1:depth-1]};
504
assign q = dffs[depth];
505
assign emptyflag = !(|dffs);
506
endmodule
507 6 unneback
//////////////////////////////////////////////////////////////////////
508
////                                                              ////
509 18 unneback
////  Logic functions                                             ////
510
////                                                              ////
511
////  Description                                                 ////
512
////  Logic functions such as multiplexers                        ////
513
////                                                              ////
514
////                                                              ////
515
////  To Do:                                                      ////
516
////   -                                                          ////
517
////                                                              ////
518
////  Author(s):                                                  ////
519
////      - Michael Unneback, unneback@opencores.org              ////
520
////        ORSoC AB                                              ////
521
////                                                              ////
522
//////////////////////////////////////////////////////////////////////
523
////                                                              ////
524
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
525
////                                                              ////
526
//// This source file may be used and distributed without         ////
527
//// restriction provided that this copyright statement is not    ////
528
//// removed from the file and that any derivative work contains  ////
529
//// the original copyright notice and the associated disclaimer. ////
530
////                                                              ////
531
//// This source file is free software; you can redistribute it   ////
532
//// and/or modify it under the terms of the GNU Lesser General   ////
533
//// Public License as published by the Free Software Foundation; ////
534
//// either version 2.1 of the License, or (at your option) any   ////
535
//// later version.                                               ////
536
////                                                              ////
537
//// This source is distributed in the hope that it will be       ////
538
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
539
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
540
//// PURPOSE.  See the GNU Lesser General Public License for more ////
541
//// details.                                                     ////
542
////                                                              ////
543
//// You should have received a copy of the GNU Lesser General    ////
544
//// Public License along with this source; if not, download it   ////
545
//// from http://www.opencores.org/lgpl.shtml                     ////
546
////                                                              ////
547
//////////////////////////////////////////////////////////////////////
548 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
549
parameter width = 32;
550 35 unneback
localparam nr_of_ports = 2;
551 34 unneback
input [width-1:0] a1, a0;
552
input [nr_of_ports-1:0] sel;
553
output [width-1:0] dout;
554
wire [width-1:0] tmp [nr_of_ports-1:0];
555
integer i;
556
// and
557
assign tmp[0] = {width{sel[0]}} & a0;
558
assign tmp[1] = {width{sel[1]}} & a1;
559
// or
560
assign dout = tmp[1] | tmp[0];
561
endmodule
562
module vl_mux3_andor ( a2, a1, a0, sel, dout);
563
parameter width = 32;
564 35 unneback
localparam nr_of_ports = 3;
565 34 unneback
input [width-1:0] a2, a1, a0;
566
input [nr_of_ports-1:0] sel;
567
output [width-1:0] dout;
568
wire [width-1:0] tmp [nr_of_ports-1:0];
569
integer i;
570
// and
571
assign tmp[0] = {width{sel[0]}} & a0;
572
assign tmp[1] = {width{sel[1]}} & a1;
573
assign tmp[2] = {width{sel[2]}} & a2;
574
// or
575
assign dout = tmp[2] | tmp[1] | tmp[0];
576
endmodule
577 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
578
parameter width = 32;
579 35 unneback
localparam nr_of_ports = 4;
580 18 unneback
input [width-1:0] a3, a2, a1, a0;
581
input [nr_of_ports-1:0] sel;
582 22 unneback
output [width-1:0] dout;
583 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
584 18 unneback
integer i;
585
// and
586
assign tmp[0] = {width{sel[0]}} & a0;
587
assign tmp[1] = {width{sel[1]}} & a1;
588
assign tmp[2] = {width{sel[2]}} & a2;
589
assign tmp[3] = {width{sel[3]}} & a3;
590
// or
591
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
592
endmodule
593
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
594
parameter width = 32;
595 35 unneback
localparam nr_of_ports = 5;
596 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
597
input [nr_of_ports-1:0] sel;
598 22 unneback
output [width-1:0] dout;
599 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
600 18 unneback
integer i;
601
// and
602
assign tmp[0] = {width{sel[0]}} & a0;
603
assign tmp[1] = {width{sel[1]}} & a1;
604
assign tmp[2] = {width{sel[2]}} & a2;
605
assign tmp[3] = {width{sel[3]}} & a3;
606
assign tmp[4] = {width{sel[4]}} & a4;
607
// or
608
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
609
endmodule
610
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
611
parameter width = 32;
612 35 unneback
localparam nr_of_ports = 6;
613 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
614
input [nr_of_ports-1:0] sel;
615 22 unneback
output [width-1:0] dout;
616 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
617 18 unneback
integer i;
618
// and
619
assign tmp[0] = {width{sel[0]}} & a0;
620
assign tmp[1] = {width{sel[1]}} & a1;
621
assign tmp[2] = {width{sel[2]}} & a2;
622
assign tmp[3] = {width{sel[3]}} & a3;
623
assign tmp[4] = {width{sel[4]}} & a4;
624
assign tmp[5] = {width{sel[5]}} & a5;
625
// or
626
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
627
endmodule
628
//////////////////////////////////////////////////////////////////////
629
////                                                              ////
630 6 unneback
////  Versatile counter                                           ////
631
////                                                              ////
632
////  Description                                                 ////
633
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
634
////  counter                                                     ////
635
////                                                              ////
636
////  To Do:                                                      ////
637
////   - add LFSR with more taps                                  ////
638
////                                                              ////
639
////  Author(s):                                                  ////
640
////      - Michael Unneback, unneback@opencores.org              ////
641
////        ORSoC AB                                              ////
642
////                                                              ////
643
//////////////////////////////////////////////////////////////////////
644
////                                                              ////
645
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
646
////                                                              ////
647
//// This source file may be used and distributed without         ////
648
//// restriction provided that this copyright statement is not    ////
649
//// removed from the file and that any derivative work contains  ////
650
//// the original copyright notice and the associated disclaimer. ////
651
////                                                              ////
652
//// This source file is free software; you can redistribute it   ////
653
//// and/or modify it under the terms of the GNU Lesser General   ////
654
//// Public License as published by the Free Software Foundation; ////
655
//// either version 2.1 of the License, or (at your option) any   ////
656
//// later version.                                               ////
657
////                                                              ////
658
//// This source is distributed in the hope that it will be       ////
659
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
660
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
661
//// PURPOSE.  See the GNU Lesser General Public License for more ////
662
//// details.                                                     ////
663
////                                                              ////
664
//// You should have received a copy of the GNU Lesser General    ////
665
//// Public License along with this source; if not, download it   ////
666
//// from http://www.opencores.org/lgpl.shtml                     ////
667
////                                                              ////
668
//////////////////////////////////////////////////////////////////////
669
// binary counter
670 22 unneback
module vl_cnt_bin ( q, rst, clk);
671
   parameter length = 4;
672
   output [length:1] q;
673
   input rst;
674
   input clk;
675
   parameter clear_value = 0;
676
   parameter set_value = 1;
677
   parameter wrap_value = 0;
678
   parameter level1_value = 15;
679
   reg  [length:1] qi;
680
   wire [length:1] q_next;
681
   assign q_next = qi + {{length-1{1'b0}},1'b1};
682
   always @ (posedge clk or posedge rst)
683
     if (rst)
684
       qi <= {length{1'b0}};
685
     else
686
       qi <= q_next;
687
   assign q = qi;
688
endmodule
689
//////////////////////////////////////////////////////////////////////
690
////                                                              ////
691
////  Versatile counter                                           ////
692
////                                                              ////
693
////  Description                                                 ////
694
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
695
////  counter                                                     ////
696
////                                                              ////
697
////  To Do:                                                      ////
698
////   - add LFSR with more taps                                  ////
699
////                                                              ////
700
////  Author(s):                                                  ////
701
////      - Michael Unneback, unneback@opencores.org              ////
702
////        ORSoC AB                                              ////
703
////                                                              ////
704
//////////////////////////////////////////////////////////////////////
705
////                                                              ////
706
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
707
////                                                              ////
708
//// This source file may be used and distributed without         ////
709
//// restriction provided that this copyright statement is not    ////
710
//// removed from the file and that any derivative work contains  ////
711
//// the original copyright notice and the associated disclaimer. ////
712
////                                                              ////
713
//// This source file is free software; you can redistribute it   ////
714
//// and/or modify it under the terms of the GNU Lesser General   ////
715
//// Public License as published by the Free Software Foundation; ////
716
//// either version 2.1 of the License, or (at your option) any   ////
717
//// later version.                                               ////
718
////                                                              ////
719
//// This source is distributed in the hope that it will be       ////
720
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
721
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
722
//// PURPOSE.  See the GNU Lesser General Public License for more ////
723
//// details.                                                     ////
724
////                                                              ////
725
//// You should have received a copy of the GNU Lesser General    ////
726
//// Public License along with this source; if not, download it   ////
727
//// from http://www.opencores.org/lgpl.shtml                     ////
728
////                                                              ////
729
//////////////////////////////////////////////////////////////////////
730
// binary counter
731
module vl_cnt_bin_clear ( clear, q, rst, clk);
732
   parameter length = 4;
733
   input clear;
734
   output [length:1] q;
735
   input rst;
736
   input clk;
737
   parameter clear_value = 0;
738
   parameter set_value = 1;
739
   parameter wrap_value = 0;
740
   parameter level1_value = 15;
741
   reg  [length:1] qi;
742
   wire [length:1] q_next;
743
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
744
   always @ (posedge clk or posedge rst)
745
     if (rst)
746
       qi <= {length{1'b0}};
747
     else
748
       qi <= q_next;
749
   assign q = qi;
750
endmodule
751
//////////////////////////////////////////////////////////////////////
752
////                                                              ////
753
////  Versatile counter                                           ////
754
////                                                              ////
755
////  Description                                                 ////
756
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
757
////  counter                                                     ////
758
////                                                              ////
759
////  To Do:                                                      ////
760
////   - add LFSR with more taps                                  ////
761
////                                                              ////
762
////  Author(s):                                                  ////
763
////      - Michael Unneback, unneback@opencores.org              ////
764
////        ORSoC AB                                              ////
765
////                                                              ////
766
//////////////////////////////////////////////////////////////////////
767
////                                                              ////
768
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
769
////                                                              ////
770
//// This source file may be used and distributed without         ////
771
//// restriction provided that this copyright statement is not    ////
772
//// removed from the file and that any derivative work contains  ////
773
//// the original copyright notice and the associated disclaimer. ////
774
////                                                              ////
775
//// This source file is free software; you can redistribute it   ////
776
//// and/or modify it under the terms of the GNU Lesser General   ////
777
//// Public License as published by the Free Software Foundation; ////
778
//// either version 2.1 of the License, or (at your option) any   ////
779
//// later version.                                               ////
780
////                                                              ////
781
//// This source is distributed in the hope that it will be       ////
782
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
783
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
784
//// PURPOSE.  See the GNU Lesser General Public License for more ////
785
//// details.                                                     ////
786
////                                                              ////
787
//// You should have received a copy of the GNU Lesser General    ////
788
//// Public License along with this source; if not, download it   ////
789
//// from http://www.opencores.org/lgpl.shtml                     ////
790
////                                                              ////
791
//////////////////////////////////////////////////////////////////////
792
// binary counter
793 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
794 6 unneback
   parameter length = 4;
795
   input cke;
796
   output [length:1] q;
797
   input rst;
798
   input clk;
799
   parameter clear_value = 0;
800
   parameter set_value = 1;
801
   parameter wrap_value = 0;
802
   parameter level1_value = 15;
803
   reg  [length:1] qi;
804
   wire [length:1] q_next;
805
   assign q_next = qi + {{length-1{1'b0}},1'b1};
806
   always @ (posedge clk or posedge rst)
807
     if (rst)
808
       qi <= {length{1'b0}};
809
     else
810
     if (cke)
811
       qi <= q_next;
812
   assign q = qi;
813
endmodule
814
//////////////////////////////////////////////////////////////////////
815
////                                                              ////
816
////  Versatile counter                                           ////
817
////                                                              ////
818
////  Description                                                 ////
819
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
820
////  counter                                                     ////
821
////                                                              ////
822
////  To Do:                                                      ////
823
////   - add LFSR with more taps                                  ////
824
////                                                              ////
825
////  Author(s):                                                  ////
826
////      - Michael Unneback, unneback@opencores.org              ////
827
////        ORSoC AB                                              ////
828
////                                                              ////
829
//////////////////////////////////////////////////////////////////////
830
////                                                              ////
831
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
832
////                                                              ////
833
//// This source file may be used and distributed without         ////
834
//// restriction provided that this copyright statement is not    ////
835
//// removed from the file and that any derivative work contains  ////
836
//// the original copyright notice and the associated disclaimer. ////
837
////                                                              ////
838
//// This source file is free software; you can redistribute it   ////
839
//// and/or modify it under the terms of the GNU Lesser General   ////
840
//// Public License as published by the Free Software Foundation; ////
841
//// either version 2.1 of the License, or (at your option) any   ////
842
//// later version.                                               ////
843
////                                                              ////
844
//// This source is distributed in the hope that it will be       ////
845
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
846
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
847
//// PURPOSE.  See the GNU Lesser General Public License for more ////
848
//// details.                                                     ////
849
////                                                              ////
850
//// You should have received a copy of the GNU Lesser General    ////
851
//// Public License along with this source; if not, download it   ////
852
//// from http://www.opencores.org/lgpl.shtml                     ////
853
////                                                              ////
854
//////////////////////////////////////////////////////////////////////
855
// binary counter
856 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
857 6 unneback
   parameter length = 4;
858
   input clear;
859
   input cke;
860
   output [length:1] q;
861
   input rst;
862
   input clk;
863
   parameter clear_value = 0;
864
   parameter set_value = 1;
865
   parameter wrap_value = 0;
866
   parameter level1_value = 15;
867
   reg  [length:1] qi;
868
   wire [length:1] q_next;
869
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
870
   always @ (posedge clk or posedge rst)
871
     if (rst)
872
       qi <= {length{1'b0}};
873
     else
874
     if (cke)
875
       qi <= q_next;
876
   assign q = qi;
877
endmodule
878
//////////////////////////////////////////////////////////////////////
879
////                                                              ////
880
////  Versatile counter                                           ////
881
////                                                              ////
882
////  Description                                                 ////
883
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
884
////  counter                                                     ////
885
////                                                              ////
886
////  To Do:                                                      ////
887
////   - add LFSR with more taps                                  ////
888
////                                                              ////
889
////  Author(s):                                                  ////
890
////      - Michael Unneback, unneback@opencores.org              ////
891
////        ORSoC AB                                              ////
892
////                                                              ////
893
//////////////////////////////////////////////////////////////////////
894
////                                                              ////
895
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
896
////                                                              ////
897
//// This source file may be used and distributed without         ////
898
//// restriction provided that this copyright statement is not    ////
899
//// removed from the file and that any derivative work contains  ////
900
//// the original copyright notice and the associated disclaimer. ////
901
////                                                              ////
902
//// This source file is free software; you can redistribute it   ////
903
//// and/or modify it under the terms of the GNU Lesser General   ////
904
//// Public License as published by the Free Software Foundation; ////
905
//// either version 2.1 of the License, or (at your option) any   ////
906
//// later version.                                               ////
907
////                                                              ////
908
//// This source is distributed in the hope that it will be       ////
909
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
910
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
911
//// PURPOSE.  See the GNU Lesser General Public License for more ////
912
//// details.                                                     ////
913
////                                                              ////
914
//// You should have received a copy of the GNU Lesser General    ////
915
//// Public License along with this source; if not, download it   ////
916
//// from http://www.opencores.org/lgpl.shtml                     ////
917
////                                                              ////
918
//////////////////////////////////////////////////////////////////////
919
// binary counter
920 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
921
   parameter length = 4;
922
   input clear;
923
   input cke;
924
   output [length:1] q;
925
   output reg level1;
926
   output reg level2;
927
   input rst;
928
   input clk;
929
   parameter clear_value = 0;
930
   parameter set_value = 1;
931 30 unneback
   parameter wrap_value = 15;
932
   parameter level1_value = 8;
933
   parameter level2_value = 15;
934 29 unneback
   wire rew;
935 30 unneback
   assign rew = 1'b0;
936 29 unneback
   reg  [length:1] qi;
937
   wire [length:1] q_next;
938
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
939
   always @ (posedge clk or posedge rst)
940
     if (rst)
941
       qi <= {length{1'b0}};
942
     else
943
     if (cke)
944
       qi <= q_next;
945
   assign q = qi;
946
    always @ (posedge clk or posedge rst)
947
    if (rst)
948
        level1 <= 1'b0;
949
    else
950
    if (cke)
951
    if (clear)
952
        level1 <= 1'b0;
953
    else if (q_next == level1_value)
954
        level1 <= 1'b1;
955
    else if (qi == level1_value & rew)
956
        level1 <= 1'b0;
957
    always @ (posedge clk or posedge rst)
958
    if (rst)
959
        level2 <= 1'b0;
960
    else
961
    if (cke)
962
    if (clear)
963
        level2 <= 1'b0;
964
    else if (q_next == level2_value)
965
        level2 <= 1'b1;
966
    else if (qi == level2_value & rew)
967
        level2 <= 1'b0;
968
endmodule
969
//////////////////////////////////////////////////////////////////////
970
////                                                              ////
971
////  Versatile counter                                           ////
972
////                                                              ////
973
////  Description                                                 ////
974
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
975
////  counter                                                     ////
976
////                                                              ////
977
////  To Do:                                                      ////
978
////   - add LFSR with more taps                                  ////
979
////                                                              ////
980
////  Author(s):                                                  ////
981
////      - Michael Unneback, unneback@opencores.org              ////
982
////        ORSoC AB                                              ////
983
////                                                              ////
984
//////////////////////////////////////////////////////////////////////
985
////                                                              ////
986
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
987
////                                                              ////
988
//// This source file may be used and distributed without         ////
989
//// restriction provided that this copyright statement is not    ////
990
//// removed from the file and that any derivative work contains  ////
991
//// the original copyright notice and the associated disclaimer. ////
992
////                                                              ////
993
//// This source file is free software; you can redistribute it   ////
994
//// and/or modify it under the terms of the GNU Lesser General   ////
995
//// Public License as published by the Free Software Foundation; ////
996
//// either version 2.1 of the License, or (at your option) any   ////
997
//// later version.                                               ////
998
////                                                              ////
999
//// This source is distributed in the hope that it will be       ////
1000
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1001
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1002
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1003
//// details.                                                     ////
1004
////                                                              ////
1005
//// You should have received a copy of the GNU Lesser General    ////
1006
//// Public License along with this source; if not, download it   ////
1007
//// from http://www.opencores.org/lgpl.shtml                     ////
1008
////                                                              ////
1009
//////////////////////////////////////////////////////////////////////
1010
// binary counter
1011 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1012 6 unneback
   parameter length = 4;
1013
   input clear;
1014
   input set;
1015
   input cke;
1016
   input rew;
1017
   output [length:1] q;
1018
   input rst;
1019
   input clk;
1020
   parameter clear_value = 0;
1021
   parameter set_value = 1;
1022
   parameter wrap_value = 0;
1023
   parameter level1_value = 15;
1024
   reg  [length:1] qi;
1025
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1026
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1027
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1028
   assign q_next = rew ? q_next_rew : q_next_fw;
1029
   always @ (posedge clk or posedge rst)
1030
     if (rst)
1031
       qi <= {length{1'b0}};
1032
     else
1033
     if (cke)
1034
       qi <= q_next;
1035
   assign q = qi;
1036
endmodule
1037
//////////////////////////////////////////////////////////////////////
1038
////                                                              ////
1039
////  Versatile counter                                           ////
1040
////                                                              ////
1041
////  Description                                                 ////
1042
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1043
////  counter                                                     ////
1044
////                                                              ////
1045
////  To Do:                                                      ////
1046
////   - add LFSR with more taps                                  ////
1047
////                                                              ////
1048
////  Author(s):                                                  ////
1049
////      - Michael Unneback, unneback@opencores.org              ////
1050
////        ORSoC AB                                              ////
1051
////                                                              ////
1052
//////////////////////////////////////////////////////////////////////
1053
////                                                              ////
1054
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1055
////                                                              ////
1056
//// This source file may be used and distributed without         ////
1057
//// restriction provided that this copyright statement is not    ////
1058
//// removed from the file and that any derivative work contains  ////
1059
//// the original copyright notice and the associated disclaimer. ////
1060
////                                                              ////
1061
//// This source file is free software; you can redistribute it   ////
1062
//// and/or modify it under the terms of the GNU Lesser General   ////
1063
//// Public License as published by the Free Software Foundation; ////
1064
//// either version 2.1 of the License, or (at your option) any   ////
1065
//// later version.                                               ////
1066
////                                                              ////
1067
//// This source is distributed in the hope that it will be       ////
1068
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1069
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1070
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1071
//// details.                                                     ////
1072
////                                                              ////
1073
//// You should have received a copy of the GNU Lesser General    ////
1074
//// Public License along with this source; if not, download it   ////
1075
//// from http://www.opencores.org/lgpl.shtml                     ////
1076
////                                                              ////
1077
//////////////////////////////////////////////////////////////////////
1078
// binary counter
1079 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1080 6 unneback
   parameter length = 4;
1081
   input cke;
1082
   input rew;
1083
   output reg level1;
1084
   input rst;
1085
   input clk;
1086
   parameter clear_value = 0;
1087
   parameter set_value = 1;
1088
   parameter wrap_value = 1;
1089
   parameter level1_value = 15;
1090 29 unneback
   wire clear;
1091 30 unneback
   assign clear = 1'b0;
1092 6 unneback
   reg  [length:1] qi;
1093
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1094
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1095
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1096
   assign q_next = rew ? q_next_rew : q_next_fw;
1097
   always @ (posedge clk or posedge rst)
1098
     if (rst)
1099
       qi <= {length{1'b0}};
1100
     else
1101
     if (cke)
1102
       qi <= q_next;
1103
    always @ (posedge clk or posedge rst)
1104
    if (rst)
1105
        level1 <= 1'b0;
1106
    else
1107
    if (cke)
1108 29 unneback
    if (clear)
1109
        level1 <= 1'b0;
1110
    else if (q_next == level1_value)
1111 6 unneback
        level1 <= 1'b1;
1112
    else if (qi == level1_value & rew)
1113
        level1 <= 1'b0;
1114
endmodule
1115
//////////////////////////////////////////////////////////////////////
1116
////                                                              ////
1117
////  Versatile counter                                           ////
1118
////                                                              ////
1119
////  Description                                                 ////
1120
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1121
////  counter                                                     ////
1122
////                                                              ////
1123
////  To Do:                                                      ////
1124
////   - add LFSR with more taps                                  ////
1125
////                                                              ////
1126
////  Author(s):                                                  ////
1127
////      - Michael Unneback, unneback@opencores.org              ////
1128
////        ORSoC AB                                              ////
1129
////                                                              ////
1130
//////////////////////////////////////////////////////////////////////
1131
////                                                              ////
1132
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1133
////                                                              ////
1134
//// This source file may be used and distributed without         ////
1135
//// restriction provided that this copyright statement is not    ////
1136
//// removed from the file and that any derivative work contains  ////
1137
//// the original copyright notice and the associated disclaimer. ////
1138
////                                                              ////
1139
//// This source file is free software; you can redistribute it   ////
1140
//// and/or modify it under the terms of the GNU Lesser General   ////
1141
//// Public License as published by the Free Software Foundation; ////
1142
//// either version 2.1 of the License, or (at your option) any   ////
1143
//// later version.                                               ////
1144
////                                                              ////
1145
//// This source is distributed in the hope that it will be       ////
1146
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1147
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1148
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1149
//// details.                                                     ////
1150
////                                                              ////
1151
//// You should have received a copy of the GNU Lesser General    ////
1152
//// Public License along with this source; if not, download it   ////
1153
//// from http://www.opencores.org/lgpl.shtml                     ////
1154
////                                                              ////
1155
//////////////////////////////////////////////////////////////////////
1156 25 unneback
// binary counter
1157
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1158
   parameter length = 4;
1159
   input cke;
1160
   input rew;
1161
   output reg zq;
1162
   output reg level1;
1163
   input rst;
1164
   input clk;
1165
   parameter clear_value = 0;
1166
   parameter set_value = 1;
1167
   parameter wrap_value = 1;
1168
   parameter level1_value = 15;
1169 29 unneback
   wire clear;
1170 30 unneback
   assign clear = 1'b0;
1171 25 unneback
   reg  [length:1] qi;
1172
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1173
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1174
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1175
   assign q_next = rew ? q_next_rew : q_next_fw;
1176
   always @ (posedge clk or posedge rst)
1177
     if (rst)
1178
       qi <= {length{1'b0}};
1179
     else
1180
     if (cke)
1181
       qi <= q_next;
1182
   always @ (posedge clk or posedge rst)
1183
     if (rst)
1184
       zq <= 1'b1;
1185
     else
1186
     if (cke)
1187
       zq <= q_next == {length{1'b0}};
1188
    always @ (posedge clk or posedge rst)
1189
    if (rst)
1190
        level1 <= 1'b0;
1191
    else
1192
    if (cke)
1193 29 unneback
    if (clear)
1194
        level1 <= 1'b0;
1195
    else if (q_next == level1_value)
1196 25 unneback
        level1 <= 1'b1;
1197
    else if (qi == level1_value & rew)
1198
        level1 <= 1'b0;
1199
endmodule
1200
//////////////////////////////////////////////////////////////////////
1201
////                                                              ////
1202
////  Versatile counter                                           ////
1203
////                                                              ////
1204
////  Description                                                 ////
1205
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1206
////  counter                                                     ////
1207
////                                                              ////
1208
////  To Do:                                                      ////
1209
////   - add LFSR with more taps                                  ////
1210
////                                                              ////
1211
////  Author(s):                                                  ////
1212
////      - Michael Unneback, unneback@opencores.org              ////
1213
////        ORSoC AB                                              ////
1214
////                                                              ////
1215
//////////////////////////////////////////////////////////////////////
1216
////                                                              ////
1217
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1218
////                                                              ////
1219
//// This source file may be used and distributed without         ////
1220
//// restriction provided that this copyright statement is not    ////
1221
//// removed from the file and that any derivative work contains  ////
1222
//// the original copyright notice and the associated disclaimer. ////
1223
////                                                              ////
1224
//// This source file is free software; you can redistribute it   ////
1225
//// and/or modify it under the terms of the GNU Lesser General   ////
1226
//// Public License as published by the Free Software Foundation; ////
1227
//// either version 2.1 of the License, or (at your option) any   ////
1228
//// later version.                                               ////
1229
////                                                              ////
1230
//// This source is distributed in the hope that it will be       ////
1231
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1232
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1233
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1234
//// details.                                                     ////
1235
////                                                              ////
1236
//// You should have received a copy of the GNU Lesser General    ////
1237
//// Public License along with this source; if not, download it   ////
1238
//// from http://www.opencores.org/lgpl.shtml                     ////
1239
////                                                              ////
1240
//////////////////////////////////////////////////////////////////////
1241
// binary counter
1242
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1243
   parameter length = 4;
1244
   input cke;
1245
   input rew;
1246
   output [length:1] q;
1247
   output reg zq;
1248
   output reg level1;
1249
   input rst;
1250
   input clk;
1251
   parameter clear_value = 0;
1252
   parameter set_value = 1;
1253
   parameter wrap_value = 1;
1254
   parameter level1_value = 15;
1255 29 unneback
   wire clear;
1256 30 unneback
   assign clear = 1'b0;
1257 25 unneback
   reg  [length:1] qi;
1258
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1259
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1260
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1261
   assign q_next = rew ? q_next_rew : q_next_fw;
1262
   always @ (posedge clk or posedge rst)
1263
     if (rst)
1264
       qi <= {length{1'b0}};
1265
     else
1266
     if (cke)
1267
       qi <= q_next;
1268
   assign q = qi;
1269
   always @ (posedge clk or posedge rst)
1270
     if (rst)
1271
       zq <= 1'b1;
1272
     else
1273
     if (cke)
1274
       zq <= q_next == {length{1'b0}};
1275
    always @ (posedge clk or posedge rst)
1276
    if (rst)
1277
        level1 <= 1'b0;
1278
    else
1279
    if (cke)
1280 29 unneback
    if (clear)
1281
        level1 <= 1'b0;
1282
    else if (q_next == level1_value)
1283 25 unneback
        level1 <= 1'b1;
1284
    else if (qi == level1_value & rew)
1285
        level1 <= 1'b0;
1286
endmodule
1287
//////////////////////////////////////////////////////////////////////
1288
////                                                              ////
1289
////  Versatile counter                                           ////
1290
////                                                              ////
1291
////  Description                                                 ////
1292
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1293
////  counter                                                     ////
1294
////                                                              ////
1295
////  To Do:                                                      ////
1296
////   - add LFSR with more taps                                  ////
1297
////                                                              ////
1298
////  Author(s):                                                  ////
1299
////      - Michael Unneback, unneback@opencores.org              ////
1300
////        ORSoC AB                                              ////
1301
////                                                              ////
1302
//////////////////////////////////////////////////////////////////////
1303
////                                                              ////
1304
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1305
////                                                              ////
1306
//// This source file may be used and distributed without         ////
1307
//// restriction provided that this copyright statement is not    ////
1308
//// removed from the file and that any derivative work contains  ////
1309
//// the original copyright notice and the associated disclaimer. ////
1310
////                                                              ////
1311
//// This source file is free software; you can redistribute it   ////
1312
//// and/or modify it under the terms of the GNU Lesser General   ////
1313
//// Public License as published by the Free Software Foundation; ////
1314
//// either version 2.1 of the License, or (at your option) any   ////
1315
//// later version.                                               ////
1316
////                                                              ////
1317
//// This source is distributed in the hope that it will be       ////
1318
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1319
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1320
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1321
//// details.                                                     ////
1322
////                                                              ////
1323
//// You should have received a copy of the GNU Lesser General    ////
1324
//// Public License along with this source; if not, download it   ////
1325
//// from http://www.opencores.org/lgpl.shtml                     ////
1326
////                                                              ////
1327
//////////////////////////////////////////////////////////////////////
1328 6 unneback
// LFSR counter
1329 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1330 6 unneback
   parameter length = 4;
1331
   output reg zq;
1332
   input rst;
1333
   input clk;
1334
   parameter clear_value = 0;
1335
   parameter set_value = 1;
1336
   parameter wrap_value = 8;
1337
   parameter level1_value = 15;
1338
   reg  [length:1] qi;
1339
   reg lfsr_fb;
1340
   wire [length:1] q_next;
1341
   reg [32:1] polynom;
1342
   integer i;
1343
   always @ (qi)
1344
   begin
1345
        case (length)
1346
         2: polynom = 32'b11;                               // 0x3
1347
         3: polynom = 32'b110;                              // 0x6
1348
         4: polynom = 32'b1100;                             // 0xC
1349
         5: polynom = 32'b10100;                            // 0x14
1350
         6: polynom = 32'b110000;                           // 0x30
1351
         7: polynom = 32'b1100000;                          // 0x60
1352
         8: polynom = 32'b10111000;                         // 0xb8
1353
         9: polynom = 32'b100010000;                        // 0x110
1354
        10: polynom = 32'b1001000000;                       // 0x240
1355
        11: polynom = 32'b10100000000;                      // 0x500
1356
        12: polynom = 32'b100000101001;                     // 0x829
1357
        13: polynom = 32'b1000000001100;                    // 0x100C
1358
        14: polynom = 32'b10000000010101;                   // 0x2015
1359
        15: polynom = 32'b110000000000000;                  // 0x6000
1360
        16: polynom = 32'b1101000000001000;                 // 0xD008
1361
        17: polynom = 32'b10010000000000000;                // 0x12000
1362
        18: polynom = 32'b100000010000000000;               // 0x20400
1363
        19: polynom = 32'b1000000000000100011;              // 0x40023
1364
        20: polynom = 32'b10000010000000000000;             // 0x82000
1365
        21: polynom = 32'b101000000000000000000;            // 0x140000
1366
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1367
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1368
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1369
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1370
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1371
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1372
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1373
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1374
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1375
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1376
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1377
        default: polynom = 32'b0;
1378
        endcase
1379
        lfsr_fb = qi[length];
1380
        for (i=length-1; i>=1; i=i-1) begin
1381
            if (polynom[i])
1382
                lfsr_fb = lfsr_fb  ~^ qi[i];
1383
        end
1384
    end
1385
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1386
   always @ (posedge clk or posedge rst)
1387
     if (rst)
1388
       qi <= {length{1'b0}};
1389
     else
1390
       qi <= q_next;
1391
   always @ (posedge clk or posedge rst)
1392
     if (rst)
1393
       zq <= 1'b1;
1394
     else
1395
       zq <= q_next == {length{1'b0}};
1396
endmodule
1397
//////////////////////////////////////////////////////////////////////
1398
////                                                              ////
1399
////  Versatile counter                                           ////
1400
////                                                              ////
1401
////  Description                                                 ////
1402
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1403
////  counter                                                     ////
1404
////                                                              ////
1405
////  To Do:                                                      ////
1406
////   - add LFSR with more taps                                  ////
1407
////                                                              ////
1408
////  Author(s):                                                  ////
1409
////      - Michael Unneback, unneback@opencores.org              ////
1410
////        ORSoC AB                                              ////
1411
////                                                              ////
1412
//////////////////////////////////////////////////////////////////////
1413
////                                                              ////
1414
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1415
////                                                              ////
1416
//// This source file may be used and distributed without         ////
1417
//// restriction provided that this copyright statement is not    ////
1418
//// removed from the file and that any derivative work contains  ////
1419
//// the original copyright notice and the associated disclaimer. ////
1420
////                                                              ////
1421
//// This source file is free software; you can redistribute it   ////
1422
//// and/or modify it under the terms of the GNU Lesser General   ////
1423
//// Public License as published by the Free Software Foundation; ////
1424
//// either version 2.1 of the License, or (at your option) any   ////
1425
//// later version.                                               ////
1426
////                                                              ////
1427
//// This source is distributed in the hope that it will be       ////
1428
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1429
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1430
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1431
//// details.                                                     ////
1432
////                                                              ////
1433
//// You should have received a copy of the GNU Lesser General    ////
1434
//// Public License along with this source; if not, download it   ////
1435
//// from http://www.opencores.org/lgpl.shtml                     ////
1436
////                                                              ////
1437
//////////////////////////////////////////////////////////////////////
1438
// LFSR counter
1439 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1440 6 unneback
   parameter length = 4;
1441
   input cke;
1442
   output reg zq;
1443
   input rst;
1444
   input clk;
1445
   parameter clear_value = 0;
1446
   parameter set_value = 1;
1447
   parameter wrap_value = 8;
1448
   parameter level1_value = 15;
1449
   reg  [length:1] qi;
1450
   reg lfsr_fb;
1451
   wire [length:1] q_next;
1452
   reg [32:1] polynom;
1453
   integer i;
1454
   always @ (qi)
1455
   begin
1456
        case (length)
1457
         2: polynom = 32'b11;                               // 0x3
1458
         3: polynom = 32'b110;                              // 0x6
1459
         4: polynom = 32'b1100;                             // 0xC
1460
         5: polynom = 32'b10100;                            // 0x14
1461
         6: polynom = 32'b110000;                           // 0x30
1462
         7: polynom = 32'b1100000;                          // 0x60
1463
         8: polynom = 32'b10111000;                         // 0xb8
1464
         9: polynom = 32'b100010000;                        // 0x110
1465
        10: polynom = 32'b1001000000;                       // 0x240
1466
        11: polynom = 32'b10100000000;                      // 0x500
1467
        12: polynom = 32'b100000101001;                     // 0x829
1468
        13: polynom = 32'b1000000001100;                    // 0x100C
1469
        14: polynom = 32'b10000000010101;                   // 0x2015
1470
        15: polynom = 32'b110000000000000;                  // 0x6000
1471
        16: polynom = 32'b1101000000001000;                 // 0xD008
1472
        17: polynom = 32'b10010000000000000;                // 0x12000
1473
        18: polynom = 32'b100000010000000000;               // 0x20400
1474
        19: polynom = 32'b1000000000000100011;              // 0x40023
1475
        20: polynom = 32'b10000010000000000000;             // 0x82000
1476
        21: polynom = 32'b101000000000000000000;            // 0x140000
1477
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1478
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1479
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1480
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1481
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1482
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1483
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1484
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1485
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1486
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1487
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1488
        default: polynom = 32'b0;
1489
        endcase
1490
        lfsr_fb = qi[length];
1491
        for (i=length-1; i>=1; i=i-1) begin
1492
            if (polynom[i])
1493
                lfsr_fb = lfsr_fb  ~^ qi[i];
1494
        end
1495
    end
1496
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1497
   always @ (posedge clk or posedge rst)
1498
     if (rst)
1499
       qi <= {length{1'b0}};
1500
     else
1501
     if (cke)
1502
       qi <= q_next;
1503
   always @ (posedge clk or posedge rst)
1504
     if (rst)
1505
       zq <= 1'b1;
1506
     else
1507
     if (cke)
1508
       zq <= q_next == {length{1'b0}};
1509
endmodule
1510
//////////////////////////////////////////////////////////////////////
1511
////                                                              ////
1512
////  Versatile counter                                           ////
1513
////                                                              ////
1514
////  Description                                                 ////
1515
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1516
////  counter                                                     ////
1517
////                                                              ////
1518
////  To Do:                                                      ////
1519
////   - add LFSR with more taps                                  ////
1520
////                                                              ////
1521
////  Author(s):                                                  ////
1522
////      - Michael Unneback, unneback@opencores.org              ////
1523
////        ORSoC AB                                              ////
1524
////                                                              ////
1525
//////////////////////////////////////////////////////////////////////
1526
////                                                              ////
1527
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1528
////                                                              ////
1529
//// This source file may be used and distributed without         ////
1530
//// restriction provided that this copyright statement is not    ////
1531
//// removed from the file and that any derivative work contains  ////
1532
//// the original copyright notice and the associated disclaimer. ////
1533
////                                                              ////
1534
//// This source file is free software; you can redistribute it   ////
1535
//// and/or modify it under the terms of the GNU Lesser General   ////
1536
//// Public License as published by the Free Software Foundation; ////
1537
//// either version 2.1 of the License, or (at your option) any   ////
1538
//// later version.                                               ////
1539
////                                                              ////
1540
//// This source is distributed in the hope that it will be       ////
1541
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1542
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1543
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1544
//// details.                                                     ////
1545
////                                                              ////
1546
//// You should have received a copy of the GNU Lesser General    ////
1547
//// Public License along with this source; if not, download it   ////
1548
//// from http://www.opencores.org/lgpl.shtml                     ////
1549
////                                                              ////
1550
//////////////////////////////////////////////////////////////////////
1551
// LFSR counter
1552 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1553
   parameter length = 4;
1554
   input cke;
1555
   output [length:1] q;
1556
   input rst;
1557
   input clk;
1558
   parameter clear_value = 0;
1559
   parameter set_value = 1;
1560
   parameter wrap_value = 8;
1561
   parameter level1_value = 15;
1562
   reg  [length:1] qi;
1563
   reg lfsr_fb;
1564
   wire [length:1] q_next;
1565
   reg [32:1] polynom;
1566
   integer i;
1567
   always @ (qi)
1568
   begin
1569
        case (length)
1570
         2: polynom = 32'b11;                               // 0x3
1571
         3: polynom = 32'b110;                              // 0x6
1572
         4: polynom = 32'b1100;                             // 0xC
1573
         5: polynom = 32'b10100;                            // 0x14
1574
         6: polynom = 32'b110000;                           // 0x30
1575
         7: polynom = 32'b1100000;                          // 0x60
1576
         8: polynom = 32'b10111000;                         // 0xb8
1577
         9: polynom = 32'b100010000;                        // 0x110
1578
        10: polynom = 32'b1001000000;                       // 0x240
1579
        11: polynom = 32'b10100000000;                      // 0x500
1580
        12: polynom = 32'b100000101001;                     // 0x829
1581
        13: polynom = 32'b1000000001100;                    // 0x100C
1582
        14: polynom = 32'b10000000010101;                   // 0x2015
1583
        15: polynom = 32'b110000000000000;                  // 0x6000
1584
        16: polynom = 32'b1101000000001000;                 // 0xD008
1585
        17: polynom = 32'b10010000000000000;                // 0x12000
1586
        18: polynom = 32'b100000010000000000;               // 0x20400
1587
        19: polynom = 32'b1000000000000100011;              // 0x40023
1588
        20: polynom = 32'b10000010000000000000;             // 0x82000
1589
        21: polynom = 32'b101000000000000000000;            // 0x140000
1590
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1591
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1592
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1593
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1594
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1595
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1596
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1597
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1598
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1599
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1600
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1601
        default: polynom = 32'b0;
1602
        endcase
1603
        lfsr_fb = qi[length];
1604
        for (i=length-1; i>=1; i=i-1) begin
1605
            if (polynom[i])
1606
                lfsr_fb = lfsr_fb  ~^ qi[i];
1607
        end
1608
    end
1609
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1610
   always @ (posedge clk or posedge rst)
1611
     if (rst)
1612
       qi <= {length{1'b0}};
1613
     else
1614
     if (cke)
1615
       qi <= q_next;
1616
   assign q = qi;
1617
endmodule
1618
//////////////////////////////////////////////////////////////////////
1619
////                                                              ////
1620
////  Versatile counter                                           ////
1621
////                                                              ////
1622
////  Description                                                 ////
1623
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1624
////  counter                                                     ////
1625
////                                                              ////
1626
////  To Do:                                                      ////
1627
////   - add LFSR with more taps                                  ////
1628
////                                                              ////
1629
////  Author(s):                                                  ////
1630
////      - Michael Unneback, unneback@opencores.org              ////
1631
////        ORSoC AB                                              ////
1632
////                                                              ////
1633
//////////////////////////////////////////////////////////////////////
1634
////                                                              ////
1635
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1636
////                                                              ////
1637
//// This source file may be used and distributed without         ////
1638
//// restriction provided that this copyright statement is not    ////
1639
//// removed from the file and that any derivative work contains  ////
1640
//// the original copyright notice and the associated disclaimer. ////
1641
////                                                              ////
1642
//// This source file is free software; you can redistribute it   ////
1643
//// and/or modify it under the terms of the GNU Lesser General   ////
1644
//// Public License as published by the Free Software Foundation; ////
1645
//// either version 2.1 of the License, or (at your option) any   ////
1646
//// later version.                                               ////
1647
////                                                              ////
1648
//// This source is distributed in the hope that it will be       ////
1649
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1650
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1651
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1652
//// details.                                                     ////
1653
////                                                              ////
1654
//// You should have received a copy of the GNU Lesser General    ////
1655
//// Public License along with this source; if not, download it   ////
1656
//// from http://www.opencores.org/lgpl.shtml                     ////
1657
////                                                              ////
1658
//////////////////////////////////////////////////////////////////////
1659
// LFSR counter
1660
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1661
   parameter length = 4;
1662
   input clear;
1663
   input cke;
1664
   output [length:1] q;
1665
   input rst;
1666
   input clk;
1667
   parameter clear_value = 0;
1668
   parameter set_value = 1;
1669
   parameter wrap_value = 8;
1670
   parameter level1_value = 15;
1671
   reg  [length:1] qi;
1672
   reg lfsr_fb;
1673
   wire [length:1] q_next;
1674
   reg [32:1] polynom;
1675
   integer i;
1676
   always @ (qi)
1677
   begin
1678
        case (length)
1679
         2: polynom = 32'b11;                               // 0x3
1680
         3: polynom = 32'b110;                              // 0x6
1681
         4: polynom = 32'b1100;                             // 0xC
1682
         5: polynom = 32'b10100;                            // 0x14
1683
         6: polynom = 32'b110000;                           // 0x30
1684
         7: polynom = 32'b1100000;                          // 0x60
1685
         8: polynom = 32'b10111000;                         // 0xb8
1686
         9: polynom = 32'b100010000;                        // 0x110
1687
        10: polynom = 32'b1001000000;                       // 0x240
1688
        11: polynom = 32'b10100000000;                      // 0x500
1689
        12: polynom = 32'b100000101001;                     // 0x829
1690
        13: polynom = 32'b1000000001100;                    // 0x100C
1691
        14: polynom = 32'b10000000010101;                   // 0x2015
1692
        15: polynom = 32'b110000000000000;                  // 0x6000
1693
        16: polynom = 32'b1101000000001000;                 // 0xD008
1694
        17: polynom = 32'b10010000000000000;                // 0x12000
1695
        18: polynom = 32'b100000010000000000;               // 0x20400
1696
        19: polynom = 32'b1000000000000100011;              // 0x40023
1697
        20: polynom = 32'b10000010000000000000;             // 0x82000
1698
        21: polynom = 32'b101000000000000000000;            // 0x140000
1699
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1700
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1701
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1702
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1703
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1704
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1705
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1706
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1707
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1708
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1709
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1710
        default: polynom = 32'b0;
1711
        endcase
1712
        lfsr_fb = qi[length];
1713
        for (i=length-1; i>=1; i=i-1) begin
1714
            if (polynom[i])
1715
                lfsr_fb = lfsr_fb  ~^ qi[i];
1716
        end
1717
    end
1718
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1719
   always @ (posedge clk or posedge rst)
1720
     if (rst)
1721
       qi <= {length{1'b0}};
1722
     else
1723
     if (cke)
1724
       qi <= q_next;
1725
   assign q = qi;
1726
endmodule
1727
//////////////////////////////////////////////////////////////////////
1728
////                                                              ////
1729
////  Versatile counter                                           ////
1730
////                                                              ////
1731
////  Description                                                 ////
1732
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1733
////  counter                                                     ////
1734
////                                                              ////
1735
////  To Do:                                                      ////
1736
////   - add LFSR with more taps                                  ////
1737
////                                                              ////
1738
////  Author(s):                                                  ////
1739
////      - Michael Unneback, unneback@opencores.org              ////
1740
////        ORSoC AB                                              ////
1741
////                                                              ////
1742
//////////////////////////////////////////////////////////////////////
1743
////                                                              ////
1744
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1745
////                                                              ////
1746
//// This source file may be used and distributed without         ////
1747
//// restriction provided that this copyright statement is not    ////
1748
//// removed from the file and that any derivative work contains  ////
1749
//// the original copyright notice and the associated disclaimer. ////
1750
////                                                              ////
1751
//// This source file is free software; you can redistribute it   ////
1752
//// and/or modify it under the terms of the GNU Lesser General   ////
1753
//// Public License as published by the Free Software Foundation; ////
1754
//// either version 2.1 of the License, or (at your option) any   ////
1755
//// later version.                                               ////
1756
////                                                              ////
1757
//// This source is distributed in the hope that it will be       ////
1758
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1759
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1760
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1761
//// details.                                                     ////
1762
////                                                              ////
1763
//// You should have received a copy of the GNU Lesser General    ////
1764
//// Public License along with this source; if not, download it   ////
1765
//// from http://www.opencores.org/lgpl.shtml                     ////
1766
////                                                              ////
1767
//////////////////////////////////////////////////////////////////////
1768
// LFSR counter
1769 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1770
   parameter length = 4;
1771
   input cke;
1772
   output [length:1] q;
1773
   output reg zq;
1774
   input rst;
1775
   input clk;
1776
   parameter clear_value = 0;
1777
   parameter set_value = 1;
1778
   parameter wrap_value = 8;
1779
   parameter level1_value = 15;
1780
   reg  [length:1] qi;
1781
   reg lfsr_fb;
1782
   wire [length:1] q_next;
1783
   reg [32:1] polynom;
1784
   integer i;
1785
   always @ (qi)
1786
   begin
1787
        case (length)
1788
         2: polynom = 32'b11;                               // 0x3
1789
         3: polynom = 32'b110;                              // 0x6
1790
         4: polynom = 32'b1100;                             // 0xC
1791
         5: polynom = 32'b10100;                            // 0x14
1792
         6: polynom = 32'b110000;                           // 0x30
1793
         7: polynom = 32'b1100000;                          // 0x60
1794
         8: polynom = 32'b10111000;                         // 0xb8
1795
         9: polynom = 32'b100010000;                        // 0x110
1796
        10: polynom = 32'b1001000000;                       // 0x240
1797
        11: polynom = 32'b10100000000;                      // 0x500
1798
        12: polynom = 32'b100000101001;                     // 0x829
1799
        13: polynom = 32'b1000000001100;                    // 0x100C
1800
        14: polynom = 32'b10000000010101;                   // 0x2015
1801
        15: polynom = 32'b110000000000000;                  // 0x6000
1802
        16: polynom = 32'b1101000000001000;                 // 0xD008
1803
        17: polynom = 32'b10010000000000000;                // 0x12000
1804
        18: polynom = 32'b100000010000000000;               // 0x20400
1805
        19: polynom = 32'b1000000000000100011;              // 0x40023
1806
        20: polynom = 32'b10000010000000000000;             // 0x82000
1807
        21: polynom = 32'b101000000000000000000;            // 0x140000
1808
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1809
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1810
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1811
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1812
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1813
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1814
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1815
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1816
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1817
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1818
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1819
        default: polynom = 32'b0;
1820
        endcase
1821
        lfsr_fb = qi[length];
1822
        for (i=length-1; i>=1; i=i-1) begin
1823
            if (polynom[i])
1824
                lfsr_fb = lfsr_fb  ~^ qi[i];
1825
        end
1826
    end
1827
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1828
   always @ (posedge clk or posedge rst)
1829
     if (rst)
1830
       qi <= {length{1'b0}};
1831
     else
1832
     if (cke)
1833
       qi <= q_next;
1834
   assign q = qi;
1835
   always @ (posedge clk or posedge rst)
1836
     if (rst)
1837
       zq <= 1'b1;
1838
     else
1839
     if (cke)
1840
       zq <= q_next == {length{1'b0}};
1841
endmodule
1842
//////////////////////////////////////////////////////////////////////
1843
////                                                              ////
1844
////  Versatile counter                                           ////
1845
////                                                              ////
1846
////  Description                                                 ////
1847
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1848
////  counter                                                     ////
1849
////                                                              ////
1850
////  To Do:                                                      ////
1851
////   - add LFSR with more taps                                  ////
1852
////                                                              ////
1853
////  Author(s):                                                  ////
1854
////      - Michael Unneback, unneback@opencores.org              ////
1855
////        ORSoC AB                                              ////
1856
////                                                              ////
1857
//////////////////////////////////////////////////////////////////////
1858
////                                                              ////
1859
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1860
////                                                              ////
1861
//// This source file may be used and distributed without         ////
1862
//// restriction provided that this copyright statement is not    ////
1863
//// removed from the file and that any derivative work contains  ////
1864
//// the original copyright notice and the associated disclaimer. ////
1865
////                                                              ////
1866
//// This source file is free software; you can redistribute it   ////
1867
//// and/or modify it under the terms of the GNU Lesser General   ////
1868
//// Public License as published by the Free Software Foundation; ////
1869
//// either version 2.1 of the License, or (at your option) any   ////
1870
//// later version.                                               ////
1871
////                                                              ////
1872
//// This source is distributed in the hope that it will be       ////
1873
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1874
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1875
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1876
//// details.                                                     ////
1877
////                                                              ////
1878
//// You should have received a copy of the GNU Lesser General    ////
1879
//// Public License along with this source; if not, download it   ////
1880
//// from http://www.opencores.org/lgpl.shtml                     ////
1881
////                                                              ////
1882
//////////////////////////////////////////////////////////////////////
1883
// LFSR counter
1884 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1885 6 unneback
   parameter length = 4;
1886
   input cke;
1887
   input rew;
1888
   output reg level1;
1889
   input rst;
1890
   input clk;
1891
   parameter clear_value = 0;
1892
   parameter set_value = 1;
1893
   parameter wrap_value = 8;
1894
   parameter level1_value = 15;
1895 29 unneback
   wire clear;
1896 30 unneback
   assign clear = 1'b0;
1897 6 unneback
   reg  [length:1] qi;
1898
   reg lfsr_fb, lfsr_fb_rew;
1899
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1900
   reg [32:1] polynom_rew;
1901
   integer j;
1902
   reg [32:1] polynom;
1903
   integer i;
1904
   always @ (qi)
1905
   begin
1906
        case (length)
1907
         2: polynom = 32'b11;                               // 0x3
1908
         3: polynom = 32'b110;                              // 0x6
1909
         4: polynom = 32'b1100;                             // 0xC
1910
         5: polynom = 32'b10100;                            // 0x14
1911
         6: polynom = 32'b110000;                           // 0x30
1912
         7: polynom = 32'b1100000;                          // 0x60
1913
         8: polynom = 32'b10111000;                         // 0xb8
1914
         9: polynom = 32'b100010000;                        // 0x110
1915
        10: polynom = 32'b1001000000;                       // 0x240
1916
        11: polynom = 32'b10100000000;                      // 0x500
1917
        12: polynom = 32'b100000101001;                     // 0x829
1918
        13: polynom = 32'b1000000001100;                    // 0x100C
1919
        14: polynom = 32'b10000000010101;                   // 0x2015
1920
        15: polynom = 32'b110000000000000;                  // 0x6000
1921
        16: polynom = 32'b1101000000001000;                 // 0xD008
1922
        17: polynom = 32'b10010000000000000;                // 0x12000
1923
        18: polynom = 32'b100000010000000000;               // 0x20400
1924
        19: polynom = 32'b1000000000000100011;              // 0x40023
1925
        20: polynom = 32'b10000010000000000000;             // 0x82000
1926
        21: polynom = 32'b101000000000000000000;            // 0x140000
1927
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1928
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1929
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1930
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1931
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1932
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1933
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1934
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1935
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1936
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1937
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1938
        default: polynom = 32'b0;
1939
        endcase
1940
        lfsr_fb = qi[length];
1941
        for (i=length-1; i>=1; i=i-1) begin
1942
            if (polynom[i])
1943
                lfsr_fb = lfsr_fb  ~^ qi[i];
1944
        end
1945
    end
1946
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1947
   always @ (qi)
1948
   begin
1949
        case (length)
1950
         2: polynom_rew = 32'b11;
1951
         3: polynom_rew = 32'b110;
1952
         4: polynom_rew = 32'b1100;
1953
         5: polynom_rew = 32'b10100;
1954
         6: polynom_rew = 32'b110000;
1955
         7: polynom_rew = 32'b1100000;
1956
         8: polynom_rew = 32'b10111000;
1957
         9: polynom_rew = 32'b100010000;
1958
        10: polynom_rew = 32'b1001000000;
1959
        11: polynom_rew = 32'b10100000000;
1960
        12: polynom_rew = 32'b100000101001;
1961
        13: polynom_rew = 32'b1000000001100;
1962
        14: polynom_rew = 32'b10000000010101;
1963
        15: polynom_rew = 32'b110000000000000;
1964
        16: polynom_rew = 32'b1101000000001000;
1965
        17: polynom_rew = 32'b10010000000000000;
1966
        18: polynom_rew = 32'b100000010000000000;
1967
        19: polynom_rew = 32'b1000000000000100011;
1968
        20: polynom_rew = 32'b10000010000000000000;
1969
        21: polynom_rew = 32'b101000000000000000000;
1970
        22: polynom_rew = 32'b1100000000000000000000;
1971
        23: polynom_rew = 32'b10000100000000000000000;
1972
        24: polynom_rew = 32'b111000010000000000000000;
1973
        25: polynom_rew = 32'b1001000000000000000000000;
1974
        26: polynom_rew = 32'b10000000000000000000100011;
1975
        27: polynom_rew = 32'b100000000000000000000010011;
1976
        28: polynom_rew = 32'b1100100000000000000000000000;
1977
        29: polynom_rew = 32'b10100000000000000000000000000;
1978
        30: polynom_rew = 32'b100000000000000000000000101001;
1979
        31: polynom_rew = 32'b1001000000000000000000000000000;
1980
        32: polynom_rew = 32'b10000000001000000000000000000011;
1981
        default: polynom_rew = 32'b0;
1982
        endcase
1983
        // rotate left
1984
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1985
        lfsr_fb_rew = qi[length];
1986
        for (i=length-1; i>=1; i=i-1) begin
1987
            if (polynom_rew[i])
1988
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1989
        end
1990
    end
1991
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1992
   assign q_next = rew ? q_next_rew : q_next_fw;
1993
   always @ (posedge clk or posedge rst)
1994
     if (rst)
1995
       qi <= {length{1'b0}};
1996
     else
1997
     if (cke)
1998
       qi <= q_next;
1999
    always @ (posedge clk or posedge rst)
2000
    if (rst)
2001
        level1 <= 1'b0;
2002
    else
2003
    if (cke)
2004 29 unneback
    if (clear)
2005
        level1 <= 1'b0;
2006
    else if (q_next == level1_value)
2007 6 unneback
        level1 <= 1'b1;
2008
    else if (qi == level1_value & rew)
2009
        level1 <= 1'b0;
2010
endmodule
2011
//////////////////////////////////////////////////////////////////////
2012
////                                                              ////
2013
////  Versatile counter                                           ////
2014
////                                                              ////
2015
////  Description                                                 ////
2016
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2017
////  counter                                                     ////
2018
////                                                              ////
2019
////  To Do:                                                      ////
2020
////   - add LFSR with more taps                                  ////
2021
////                                                              ////
2022
////  Author(s):                                                  ////
2023
////      - Michael Unneback, unneback@opencores.org              ////
2024
////        ORSoC AB                                              ////
2025
////                                                              ////
2026
//////////////////////////////////////////////////////////////////////
2027
////                                                              ////
2028
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2029
////                                                              ////
2030
//// This source file may be used and distributed without         ////
2031
//// restriction provided that this copyright statement is not    ////
2032
//// removed from the file and that any derivative work contains  ////
2033
//// the original copyright notice and the associated disclaimer. ////
2034
////                                                              ////
2035
//// This source file is free software; you can redistribute it   ////
2036
//// and/or modify it under the terms of the GNU Lesser General   ////
2037
//// Public License as published by the Free Software Foundation; ////
2038
//// either version 2.1 of the License, or (at your option) any   ////
2039
//// later version.                                               ////
2040
////                                                              ////
2041
//// This source is distributed in the hope that it will be       ////
2042
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2043
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2044
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2045
//// details.                                                     ////
2046
////                                                              ////
2047
//// You should have received a copy of the GNU Lesser General    ////
2048
//// Public License along with this source; if not, download it   ////
2049
//// from http://www.opencores.org/lgpl.shtml                     ////
2050
////                                                              ////
2051
//////////////////////////////////////////////////////////////////////
2052
// GRAY counter
2053 18 unneback
module vl_cnt_gray ( q, rst, clk);
2054 6 unneback
   parameter length = 4;
2055
   output reg [length:1] q;
2056
   input rst;
2057
   input clk;
2058
   parameter clear_value = 0;
2059
   parameter set_value = 1;
2060
   parameter wrap_value = 8;
2061
   parameter level1_value = 15;
2062
   reg  [length:1] qi;
2063
   wire [length:1] q_next;
2064
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2065
   always @ (posedge clk or posedge rst)
2066
     if (rst)
2067
       qi <= {length{1'b0}};
2068
     else
2069
       qi <= q_next;
2070
   always @ (posedge clk or posedge rst)
2071
     if (rst)
2072
       q <= {length{1'b0}};
2073
     else
2074
         q <= (q_next>>1) ^ q_next;
2075
endmodule
2076
//////////////////////////////////////////////////////////////////////
2077
////                                                              ////
2078
////  Versatile counter                                           ////
2079
////                                                              ////
2080
////  Description                                                 ////
2081
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2082
////  counter                                                     ////
2083
////                                                              ////
2084
////  To Do:                                                      ////
2085
////   - add LFSR with more taps                                  ////
2086
////                                                              ////
2087
////  Author(s):                                                  ////
2088
////      - Michael Unneback, unneback@opencores.org              ////
2089
////        ORSoC AB                                              ////
2090
////                                                              ////
2091
//////////////////////////////////////////////////////////////////////
2092
////                                                              ////
2093
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2094
////                                                              ////
2095
//// This source file may be used and distributed without         ////
2096
//// restriction provided that this copyright statement is not    ////
2097
//// removed from the file and that any derivative work contains  ////
2098
//// the original copyright notice and the associated disclaimer. ////
2099
////                                                              ////
2100
//// This source file is free software; you can redistribute it   ////
2101
//// and/or modify it under the terms of the GNU Lesser General   ////
2102
//// Public License as published by the Free Software Foundation; ////
2103
//// either version 2.1 of the License, or (at your option) any   ////
2104
//// later version.                                               ////
2105
////                                                              ////
2106
//// This source is distributed in the hope that it will be       ////
2107
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2108
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2109
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2110
//// details.                                                     ////
2111
////                                                              ////
2112
//// You should have received a copy of the GNU Lesser General    ////
2113
//// Public License along with this source; if not, download it   ////
2114
//// from http://www.opencores.org/lgpl.shtml                     ////
2115
////                                                              ////
2116
//////////////////////////////////////////////////////////////////////
2117
// GRAY counter
2118 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2119 6 unneback
   parameter length = 4;
2120
   input cke;
2121
   output reg [length:1] q;
2122
   input rst;
2123
   input clk;
2124
   parameter clear_value = 0;
2125
   parameter set_value = 1;
2126
   parameter wrap_value = 8;
2127
   parameter level1_value = 15;
2128
   reg  [length:1] qi;
2129
   wire [length:1] q_next;
2130
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2131
   always @ (posedge clk or posedge rst)
2132
     if (rst)
2133
       qi <= {length{1'b0}};
2134
     else
2135
     if (cke)
2136
       qi <= q_next;
2137
   always @ (posedge clk or posedge rst)
2138
     if (rst)
2139
       q <= {length{1'b0}};
2140
     else
2141
       if (cke)
2142
         q <= (q_next>>1) ^ q_next;
2143
endmodule
2144
//////////////////////////////////////////////////////////////////////
2145
////                                                              ////
2146
////  Versatile counter                                           ////
2147
////                                                              ////
2148
////  Description                                                 ////
2149
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2150
////  counter                                                     ////
2151
////                                                              ////
2152
////  To Do:                                                      ////
2153
////   - add LFSR with more taps                                  ////
2154
////                                                              ////
2155
////  Author(s):                                                  ////
2156
////      - Michael Unneback, unneback@opencores.org              ////
2157
////        ORSoC AB                                              ////
2158
////                                                              ////
2159
//////////////////////////////////////////////////////////////////////
2160
////                                                              ////
2161
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2162
////                                                              ////
2163
//// This source file may be used and distributed without         ////
2164
//// restriction provided that this copyright statement is not    ////
2165
//// removed from the file and that any derivative work contains  ////
2166
//// the original copyright notice and the associated disclaimer. ////
2167
////                                                              ////
2168
//// This source file is free software; you can redistribute it   ////
2169
//// and/or modify it under the terms of the GNU Lesser General   ////
2170
//// Public License as published by the Free Software Foundation; ////
2171
//// either version 2.1 of the License, or (at your option) any   ////
2172
//// later version.                                               ////
2173
////                                                              ////
2174
//// This source is distributed in the hope that it will be       ////
2175
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2176
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2177
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2178
//// details.                                                     ////
2179
////                                                              ////
2180
//// You should have received a copy of the GNU Lesser General    ////
2181
//// Public License along with this source; if not, download it   ////
2182
//// from http://www.opencores.org/lgpl.shtml                     ////
2183
////                                                              ////
2184
//////////////////////////////////////////////////////////////////////
2185
// GRAY counter
2186 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2187 6 unneback
   parameter length = 4;
2188
   input cke;
2189
   output reg [length:1] q;
2190
   output [length:1] q_bin;
2191
   input rst;
2192
   input clk;
2193
   parameter clear_value = 0;
2194
   parameter set_value = 1;
2195
   parameter wrap_value = 8;
2196
   parameter level1_value = 15;
2197
   reg  [length:1] qi;
2198
   wire [length:1] q_next;
2199
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2200
   always @ (posedge clk or posedge rst)
2201
     if (rst)
2202
       qi <= {length{1'b0}};
2203
     else
2204
     if (cke)
2205
       qi <= q_next;
2206
   always @ (posedge clk or posedge rst)
2207
     if (rst)
2208
       q <= {length{1'b0}};
2209
     else
2210
       if (cke)
2211
         q <= (q_next>>1) ^ q_next;
2212
   assign q_bin = qi;
2213
endmodule
2214
//////////////////////////////////////////////////////////////////////
2215
////                                                              ////
2216
////  Versatile library, counters                                 ////
2217
////                                                              ////
2218
////  Description                                                 ////
2219
////  counters                                                    ////
2220
////                                                              ////
2221
////                                                              ////
2222
////  To Do:                                                      ////
2223
////   - add more counters                                        ////
2224
////                                                              ////
2225
////  Author(s):                                                  ////
2226
////      - Michael Unneback, unneback@opencores.org              ////
2227
////        ORSoC AB                                              ////
2228
////                                                              ////
2229
//////////////////////////////////////////////////////////////////////
2230
////                                                              ////
2231
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2232
////                                                              ////
2233
//// This source file may be used and distributed without         ////
2234
//// restriction provided that this copyright statement is not    ////
2235
//// removed from the file and that any derivative work contains  ////
2236
//// the original copyright notice and the associated disclaimer. ////
2237
////                                                              ////
2238
//// This source file is free software; you can redistribute it   ////
2239
//// and/or modify it under the terms of the GNU Lesser General   ////
2240
//// Public License as published by the Free Software Foundation; ////
2241
//// either version 2.1 of the License, or (at your option) any   ////
2242
//// later version.                                               ////
2243
////                                                              ////
2244
//// This source is distributed in the hope that it will be       ////
2245
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2246
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2247
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2248
//// details.                                                     ////
2249
////                                                              ////
2250
//// You should have received a copy of the GNU Lesser General    ////
2251
//// Public License along with this source; if not, download it   ////
2252
//// from http://www.opencores.org/lgpl.shtml                     ////
2253
////                                                              ////
2254
//////////////////////////////////////////////////////////////////////
2255 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2256 6 unneback
   parameter length = 4;
2257
   output reg [0:length-1] q;
2258
   input rst;
2259
   input clk;
2260
    always @ (posedge clk or posedge rst)
2261
    if (rst)
2262
        q <= {1'b1,{length-1{1'b0}}};
2263
    else
2264
        q <= {q[length-1],q[0:length-2]};
2265
endmodule
2266 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2267 6 unneback
   parameter length = 4;
2268
   input cke;
2269
   output reg [0:length-1] q;
2270
   input rst;
2271
   input clk;
2272
    always @ (posedge clk or posedge rst)
2273
    if (rst)
2274
        q <= {1'b1,{length-1{1'b0}}};
2275
    else
2276
        if (cke)
2277
            q <= {q[length-1],q[0:length-2]};
2278
endmodule
2279 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2280 6 unneback
   parameter length = 4;
2281
   input cke, clear;
2282
   output reg [0:length-1] q;
2283
   input rst;
2284
   input clk;
2285
    always @ (posedge clk or posedge rst)
2286
    if (rst)
2287
        q <= {1'b1,{length-1{1'b0}}};
2288
    else
2289
        if (cke)
2290
            if (clear)
2291
                q <= {1'b1,{length-1{1'b0}}};
2292
            else
2293
                q <= q >> 1;
2294
endmodule
2295 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2296 6 unneback
   parameter length = 4;
2297
   input cke, clear;
2298
   output reg [0:length-1] q;
2299
   input rst;
2300
   input clk;
2301
    always @ (posedge clk or posedge rst)
2302
    if (rst)
2303
        q <= {1'b1,{length-1{1'b0}}};
2304
    else
2305
        if (cke)
2306
            if (clear)
2307
                q <= {1'b1,{length-1{1'b0}}};
2308
            else
2309
            q <= {q[length-1],q[0:length-2]};
2310
endmodule
2311
//////////////////////////////////////////////////////////////////////
2312
////                                                              ////
2313
////  Versatile library, memories                                 ////
2314
////                                                              ////
2315
////  Description                                                 ////
2316
////  memories                                                    ////
2317
////                                                              ////
2318
////                                                              ////
2319
////  To Do:                                                      ////
2320
////   - add more memory types                                    ////
2321
////                                                              ////
2322
////  Author(s):                                                  ////
2323
////      - Michael Unneback, unneback@opencores.org              ////
2324
////        ORSoC AB                                              ////
2325
////                                                              ////
2326
//////////////////////////////////////////////////////////////////////
2327
////                                                              ////
2328
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2329
////                                                              ////
2330
//// This source file may be used and distributed without         ////
2331
//// restriction provided that this copyright statement is not    ////
2332
//// removed from the file and that any derivative work contains  ////
2333
//// the original copyright notice and the associated disclaimer. ////
2334
////                                                              ////
2335
//// This source file is free software; you can redistribute it   ////
2336
//// and/or modify it under the terms of the GNU Lesser General   ////
2337
//// Public License as published by the Free Software Foundation; ////
2338
//// either version 2.1 of the License, or (at your option) any   ////
2339
//// later version.                                               ////
2340
////                                                              ////
2341
//// This source is distributed in the hope that it will be       ////
2342
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2343
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2344
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2345
//// details.                                                     ////
2346
////                                                              ////
2347
//// You should have received a copy of the GNU Lesser General    ////
2348
//// Public License along with this source; if not, download it   ////
2349
//// from http://www.opencores.org/lgpl.shtml                     ////
2350
////                                                              ////
2351
//////////////////////////////////////////////////////////////////////
2352
/// ROM
2353 7 unneback
module vl_rom_init ( adr, q, clk);
2354
   parameter data_width = 32;
2355
   parameter addr_width = 8;
2356
   input [(addr_width-1):0]       adr;
2357
   output reg [(data_width-1):0] q;
2358
   input                         clk;
2359
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2360
   parameter memory_file = "vl_rom.vmem";
2361
   initial
2362
     begin
2363
        $readmemh(memory_file, rom);
2364
     end
2365
   always @ (posedge clk)
2366
     q <= rom[adr];
2367
endmodule
2368 14 unneback
/*
2369 7 unneback
module vl_rom ( adr, q, clk);
2370 6 unneback
parameter data_width = 32;
2371
parameter addr_width = 4;
2372
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2373
    {32'h18000000},
2374
    {32'hA8200000},
2375
    {32'hA8200000},
2376
    {32'hA8200000},
2377
    {32'h44003000},
2378
    {32'h15000000},
2379
    {32'h15000000},
2380
    {32'h15000000},
2381
    {32'h15000000},
2382
    {32'h15000000},
2383
    {32'h15000000},
2384
    {32'h15000000},
2385
    {32'h15000000},
2386
    {32'h15000000},
2387
    {32'h15000000},
2388
    {32'h15000000}};
2389 7 unneback
input [addr_width-1:0] adr;
2390 6 unneback
output reg [data_width-1:0] q;
2391
input clk;
2392
always @ (posedge clk)
2393 7 unneback
    q <= data[adr];
2394 6 unneback
endmodule
2395 14 unneback
*/
2396 6 unneback
// Single port RAM
2397
module vl_ram ( d, adr, we, q, clk);
2398
   parameter data_width = 32;
2399
   parameter addr_width = 8;
2400
   input [(data_width-1):0]      d;
2401
   input [(addr_width-1):0]       adr;
2402
   input                         we;
2403 7 unneback
   output reg [(data_width-1):0] q;
2404 6 unneback
   input                         clk;
2405
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2406 7 unneback
   parameter init = 0;
2407
   parameter memory_file = "vl_ram.vmem";
2408
   generate if (init) begin : init_mem
2409
   initial
2410
     begin
2411
        $readmemh(memory_file, ram);
2412
     end
2413
   end
2414
   endgenerate
2415 6 unneback
   always @ (posedge clk)
2416
   begin
2417
   if (we)
2418
     ram[adr] <= d;
2419
   q <= ram[adr];
2420
   end
2421
endmodule
2422 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2423
   parameter data_width = 32;
2424
   parameter addr_width = 8;
2425
   input [(data_width-1):0]      d;
2426
   input [(addr_width-1):0]       adr;
2427
   input [(addr_width/4)-1:0]    be;
2428
   input                         we;
2429
   output reg [(data_width-1):0] q;
2430
   input                         clk;
2431
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2432
   parameter init = 0;
2433
   parameter memory_file = "vl_ram.vmem";
2434
   generate if (init) begin : init_mem
2435
   initial
2436
     begin
2437
        $readmemh(memory_file, ram);
2438
     end
2439
   end
2440
   endgenerate
2441
   genvar i;
2442
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2443
      always @ (posedge clk)
2444
      if (we & be[i])
2445
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2446
   end
2447
   endgenerate
2448
   always @ (posedge clk)
2449
      q <= ram[adr];
2450
endmodule
2451 6 unneback
// Dual port RAM
2452
// ACTEL FPGA should not use logic to handle rw collision
2453 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2454 6 unneback
   parameter data_width = 32;
2455
   parameter addr_width = 8;
2456
   input [(data_width-1):0]      d_a;
2457
   input [(addr_width-1):0]       adr_a;
2458
   input [(addr_width-1):0]       adr_b;
2459
   input                         we_a;
2460
   output [(data_width-1):0]      q_b;
2461
   input                         clk_a, clk_b;
2462
   reg [(addr_width-1):0]         adr_b_reg;
2463
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2464 7 unneback
   parameter init = 0;
2465
   parameter memory_file = "vl_ram.vmem";
2466
   generate if (init) begin : init_mem
2467
   initial
2468
     begin
2469
        $readmemh(memory_file, ram);
2470
     end
2471
   end
2472
   endgenerate
2473 6 unneback
   always @ (posedge clk_a)
2474
   if (we_a)
2475
     ram[adr_a] <= d_a;
2476
   always @ (posedge clk_b)
2477
   adr_b_reg <= adr_b;
2478
   assign q_b = ram[adr_b_reg];
2479
endmodule
2480 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2481 6 unneback
   parameter data_width = 32;
2482
   parameter addr_width = 8;
2483
   input [(data_width-1):0]      d_a;
2484
   input [(addr_width-1):0]       adr_a;
2485
   input [(addr_width-1):0]       adr_b;
2486
   input                         we_a;
2487
   output [(data_width-1):0]      q_b;
2488
   output reg [(data_width-1):0] q_a;
2489
   input                         clk_a, clk_b;
2490
   reg [(data_width-1):0]         q_b;
2491
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2492 7 unneback
   parameter init = 0;
2493
   parameter memory_file = "vl_ram.vmem";
2494
   generate if (init) begin : init_mem
2495
   initial
2496
     begin
2497
        $readmemh(memory_file, ram);
2498
     end
2499
   end
2500
   endgenerate
2501 6 unneback
   always @ (posedge clk_a)
2502
     begin
2503
        q_a <= ram[adr_a];
2504
        if (we_a)
2505
             ram[adr_a] <= d_a;
2506
     end
2507
   always @ (posedge clk_b)
2508
          q_b <= ram[adr_b];
2509
endmodule
2510 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2511 6 unneback
   parameter data_width = 32;
2512
   parameter addr_width = 8;
2513
   input [(data_width-1):0]      d_a;
2514
   input [(addr_width-1):0]       adr_a;
2515
   input [(addr_width-1):0]       adr_b;
2516
   input                         we_a;
2517
   output [(data_width-1):0]      q_b;
2518
   input [(data_width-1):0]       d_b;
2519
   output reg [(data_width-1):0] q_a;
2520
   input                         we_b;
2521
   input                         clk_a, clk_b;
2522
   reg [(data_width-1):0]         q_b;
2523
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2524 7 unneback
   parameter init = 0;
2525
   parameter memory_file = "vl_ram.vmem";
2526
   generate if (init) begin : init_mem
2527
   initial
2528
     begin
2529
        $readmemh(memory_file, ram);
2530
     end
2531
   end
2532
   endgenerate
2533 6 unneback
   always @ (posedge clk_a)
2534
     begin
2535
        q_a <= ram[adr_a];
2536
        if (we_a)
2537
             ram[adr_a] <= d_a;
2538
     end
2539
   always @ (posedge clk_b)
2540
     begin
2541
        q_b <= ram[adr_b];
2542
        if (we_b)
2543
          ram[adr_b] <= d_b;
2544
     end
2545
endmodule
2546
// Content addresable memory, CAM
2547
// FIFO
2548 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2549
    d, wr, fifo_full,
2550
    q, rd, fifo_empty,
2551
    fill_level,
2552
    clk, rst
2553
    );
2554
parameter data_width = 18;
2555
parameter addr_width = 4;
2556
// write side
2557
input  [data_width-1:0] d;
2558
input                   wr;
2559
output                  fifo_full;
2560
// read side
2561
output [data_width-1:0] q;
2562
input                   rd;
2563
output                  fifo_empty;
2564
// common
2565
output [addr_width:0]   fill_level;
2566
input rst, clk;
2567
wire [addr_width:1] wadr, radr;
2568
vl_cnt_bin_ce
2569
    # ( .length(addr_width))
2570
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2571
vl_cnt_bin_ce
2572
    # (.length(addr_width))
2573
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2574
vl_dpram_1r1w
2575
    # (.data_width(data_width), .addr_width(addr_width))
2576
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2577 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
2578 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2579 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2580
endmodule
2581 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2582
// RAM is supposed to be larger than the two FIFOs
2583
// LFSR counters used adr pointers
2584
module vl_fifo_2r2w_sync_simplex (
2585
    // a side
2586
    a_d, a_wr, a_fifo_full,
2587
    a_q, a_rd, a_fifo_empty,
2588
    a_fill_level,
2589
    // b side
2590
    b_d, b_wr, b_fifo_full,
2591
    b_q, b_rd, b_fifo_empty,
2592
    b_fill_level,
2593
    // common
2594
    clk, rst
2595
    );
2596
parameter data_width = 8;
2597
parameter addr_width = 5;
2598
parameter fifo_full_level = (1<<addr_width)-1;
2599
// a side
2600
input  [data_width-1:0] a_d;
2601
input                   a_wr;
2602
output                  a_fifo_full;
2603
output [data_width-1:0] a_q;
2604
input                   a_rd;
2605
output                  a_fi