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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 39

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1 6 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 33 unneback
module vl_gbuf ( i, o);
47
input i;
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output o;
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assign o = i;
50
endmodule
51 6 unneback
 // ALTERA
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 //ACTEL
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// sync reset
54 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
55 6 unneback
// output active high global reset sync with two DFFs 
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`timescale 1 ns/100 ps
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module vl_sync_rst ( rst_n_i, rst_o, clk);
58
input rst_n_i, clk;
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output rst_o;
60 18 unneback
reg [1:0] tmp;
61 6 unneback
always @ (posedge clk or negedge rst_n_i)
62
if (!rst_n_i)
63 17 unneback
        tmp <= 2'b11;
64 6 unneback
else
65 33 unneback
        tmp <= {1'b0,tmp[1]};
66 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
67 6 unneback
endmodule
68
// vl_pll
69 32 unneback
///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps/1 ps
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
72
parameter index = 0;
73
parameter number_of_clk = 1;
74
parameter period_time_0 = 20000;
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parameter period_time_1 = 20000;
76
parameter period_time_2 = 20000;
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parameter period_time_3 = 20000;
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parameter period_time_4 = 20000;
79
parameter lock_delay = 2000000;
80
input clk_i, rst_n_i;
81
output lock;
82
output reg [0:number_of_clk-1] clk_o;
83
output [0:number_of_clk-1] rst_o;
84 33 unneback
`ifdef SIM_PLL
85 32 unneback
always
86
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
87
generate if (number_of_clk > 1)
88
always
89
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
90
endgenerate
91
generate if (number_of_clk > 2)
92
always
93
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
94
endgenerate
95 33 unneback
generate if (number_of_clk > 3)
96 32 unneback
always
97
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
98
endgenerate
99 33 unneback
generate if (number_of_clk > 4)
100 32 unneback
always
101
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
102
endgenerate
103
genvar i;
104
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
106
end
107
endgenerate
108 33 unneback
//assign #lock_delay lock = rst_n_i;
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assign lock = rst_n_i;
110 32 unneback
endmodule
111 33 unneback
`else
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`ifdef VL_PLL0
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`ifdef VL_PLL0_CLK1
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
115
`endif
116
`ifdef VL_PLL0_CLK2
117
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL0_CLK3
120
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL0_CLK4
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL0_CLK5
126
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
127
`endif
128
`endif
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`ifdef VL_PLL1
130
`ifdef VL_PLL1_CLK1
131
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL1_CLK2
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL1_CLK3
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL1_CLK4
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL1_CLK5
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL2
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`ifdef VL_PLL2_CLK1
148
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL2_CLK2
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL2_CLK3
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL2_CLK4
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
159
`ifdef VL_PLL2_CLK5
160
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL3
164
`ifdef VL_PLL3_CLK1
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    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
166
`endif
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`ifdef VL_PLL3_CLK2
168
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
169
`endif
170
`ifdef VL_PLL3_CLK3
171
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
172
`endif
173
`ifdef VL_PLL3_CLK4
174
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
175
`endif
176
`ifdef VL_PLL3_CLK5
177
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
178
`endif
179
`endif
180 32 unneback
genvar i;
181
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
182 33 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
183 32 unneback
end
184
endgenerate
185
endmodule
186 33 unneback
`endif
187 32 unneback
///////////////////////////////////////////////////////////////////////////////
188 6 unneback
 //altera
189
 //actel
190
//////////////////////////////////////////////////////////////////////
191
////                                                              ////
192
////  Versatile library, registers                                ////
193
////                                                              ////
194
////  Description                                                 ////
195
////  Different type of registers                                 ////
196
////                                                              ////
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////                                                              ////
198
////  To Do:                                                      ////
199
////   - add more different registers                             ////
200
////                                                              ////
201
////  Author(s):                                                  ////
202
////      - Michael Unneback, unneback@opencores.org              ////
203
////        ORSoC AB                                              ////
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////                                                              ////
205
//////////////////////////////////////////////////////////////////////
206
////                                                              ////
207
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
208
////                                                              ////
209
//// This source file may be used and distributed without         ////
210
//// restriction provided that this copyright statement is not    ////
211
//// removed from the file and that any derivative work contains  ////
212
//// the original copyright notice and the associated disclaimer. ////
213
////                                                              ////
214
//// This source file is free software; you can redistribute it   ////
215
//// and/or modify it under the terms of the GNU Lesser General   ////
216
//// Public License as published by the Free Software Foundation; ////
217
//// either version 2.1 of the License, or (at your option) any   ////
218
//// later version.                                               ////
219
////                                                              ////
220
//// This source is distributed in the hope that it will be       ////
221
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
222
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
223
//// PURPOSE.  See the GNU Lesser General Public License for more ////
224
//// details.                                                     ////
225
////                                                              ////
226
//// You should have received a copy of the GNU Lesser General    ////
227
//// Public License along with this source; if not, download it   ////
228
//// from http://www.opencores.org/lgpl.shtml                     ////
229
////                                                              ////
230
//////////////////////////////////////////////////////////////////////
231 18 unneback
module vl_dff ( d, q, clk, rst);
232 6 unneback
        parameter width = 1;
233
        parameter reset_value = 0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output reg [width-1:0] q;
237
        always @ (posedge clk or posedge rst)
238
        if (rst)
239
                q <= reset_value;
240
        else
241
                q <= d;
242
endmodule
243 18 unneback
module vl_dff_array ( d, q, clk, rst);
244 6 unneback
        parameter width = 1;
245
        parameter depth = 2;
246
        parameter reset_value = 1'b0;
247
        input [width-1:0] d;
248
        input clk, rst;
249
        output [width-1:0] q;
250
        reg  [0:depth-1] q_tmp [width-1:0];
251
        integer i;
252
        always @ (posedge clk or posedge rst)
253
        if (rst) begin
254
            for (i=0;i<depth;i=i+1)
255
                q_tmp[i] <= {width{reset_value}};
256
        end else begin
257
            q_tmp[0] <= d;
258
            for (i=1;i<depth;i=i+1)
259
                q_tmp[i] <= q_tmp[i-1];
260
        end
261
    assign q = q_tmp[depth-1];
262
endmodule
263 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
264 6 unneback
        parameter width = 1;
265
        parameter reset_value = 0;
266
        input [width-1:0] d;
267
        input ce, clk, rst;
268
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
                q <= reset_value;
272
        else
273
                if (ce)
274
                        q <= d;
275
endmodule
276 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
277 8 unneback
        parameter width = 1;
278
        parameter reset_value = 0;
279
        input [width-1:0] d;
280 10 unneback
        input ce, clear, clk, rst;
281 8 unneback
        output reg [width-1:0] q;
282
        always @ (posedge clk or posedge rst)
283
        if (rst)
284
            q <= reset_value;
285
        else
286
            if (ce)
287
                if (clear)
288
                    q <= {width{1'b0}};
289
                else
290
                    q <= d;
291
endmodule
292 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
293
        parameter width = 1;
294
        parameter reset_value = 0;
295
        input [width-1:0] d;
296
        input ce, set, clk, rst;
297
        output reg [width-1:0] q;
298
        always @ (posedge clk or posedge rst)
299
        if (rst)
300
            q <= reset_value;
301
        else
302
            if (ce)
303
                if (set)
304
                    q <= {width{1'b1}};
305
                else
306
                    q <= d;
307
endmodule
308 29 unneback
module vl_spr ( sp, r, q, clk, rst);
309
        parameter width = 1;
310
        parameter reset_value = 0;
311
        input sp, r;
312
        output reg q;
313
        input clk, rst;
314
        always @ (posedge clk or posedge rst)
315
        if (rst)
316
            q <= reset_value;
317
        else
318
            if (sp)
319
                q <= 1'b1;
320
            else if (r)
321
                q <= 1'b0;
322
endmodule
323
module vl_srp ( s, rp, q, clk, rst);
324
        parameter width = 1;
325
        parameter reset_value = 0;
326
        input s, rp;
327
        output reg q;
328
        input clk, rst;
329
        always @ (posedge clk or posedge rst)
330
        if (rst)
331
            q <= reset_value;
332
        else
333
            if (rp)
334
                q <= 1'b0;
335
            else if (s)
336
                q <= 1'b1;
337
endmodule
338 6 unneback
// megafunction wizard: %LPM_FF%
339
// GENERATION: STANDARD
340
// VERSION: WM1.0
341
// MODULE: lpm_ff 
342
// ============================================================
343
// File Name: dff_sr.v
344
// Megafunction Name(s):
345
//                      lpm_ff
346
//
347
// Simulation Library Files(s):
348
//                      lpm
349
// ============================================================
350
// ************************************************************
351
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
352
//
353
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
354
// ************************************************************
355
//Copyright (C) 1991-2010 Altera Corporation
356
//Your use of Altera Corporation's design tools, logic functions 
357
//and other software and tools, and its AMPP partner logic 
358
//functions, and any output files from any of the foregoing 
359
//(including device programming or simulation files), and any 
360
//associated documentation or information are expressly subject 
361
//to the terms and conditions of the Altera Program License 
362
//Subscription Agreement, Altera MegaCore Function License 
363
//Agreement, or other applicable license agreement, including, 
364
//without limitation, that your use is for the sole purpose of 
365
//programming logic devices manufactured by Altera and sold by 
366
//Altera or its authorized distributors.  Please refer to the 
367
//applicable agreement for further details.
368
// synopsys translate_off
369
`timescale 1 ps / 1 ps
370
// synopsys translate_on
371 18 unneback
module vl_dff_sr (
372 6 unneback
        aclr,
373
        aset,
374
        clock,
375
        data,
376
        q);
377
        input     aclr;
378
        input     aset;
379
        input     clock;
380
        input     data;
381
        output    q;
382
        wire [0:0] sub_wire0;
383
        wire [0:0] sub_wire1 = sub_wire0[0:0];
384
        wire  q = sub_wire1;
385
        wire  sub_wire2 = data;
386
        wire  sub_wire3 = sub_wire2;
387
        lpm_ff  lpm_ff_component (
388
                                .aclr (aclr),
389
                                .clock (clock),
390
                                .data (sub_wire3),
391
                                .aset (aset),
392
                                .q (sub_wire0)
393
                                // synopsys translate_off
394
                                ,
395
                                .aload (),
396
                                .enable (),
397
                                .sclr (),
398
                                .sload (),
399
                                .sset ()
400
                                // synopsys translate_on
401
                                );
402
        defparam
403
                lpm_ff_component.lpm_fftype = "DFF",
404
                lpm_ff_component.lpm_type = "LPM_FF",
405
                lpm_ff_component.lpm_width = 1;
406
endmodule
407
// ============================================================
408
// CNX file retrieval info
409
// ============================================================
410
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
411
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
412
// Retrieval info: PRIVATE: ASET NUMERIC "1"
413
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
414
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
415
// Retrieval info: PRIVATE: DFF NUMERIC "1"
416
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
417
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
418
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET NUMERIC "0"
420
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
421
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
422
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
423
// Retrieval info: PRIVATE: nBit NUMERIC "1"
424
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
425
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
426
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
427
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
428
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
429
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
430
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
431
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
432
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
433
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
434
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
435
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
436
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
437
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
444
// Retrieval info: LIB_FILE: lpm
445
// LATCH
446
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
447 18 unneback
module vl_latch ( d, le, q, clk);
448 6 unneback
input d, le;
449
output q;
450
input clk;
451
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
452
endmodule
453 18 unneback
module vl_shreg ( d, q, clk, rst);
454 17 unneback
parameter depth = 10;
455
input d;
456
output q;
457
input clk, rst;
458
reg [1:depth] dffs;
459
always @ (posedge clk or posedge rst)
460
if (rst)
461
    dffs <= {depth{1'b0}};
462
else
463
    dffs <= {d,dffs[1:depth-1]};
464
assign q = dffs[depth];
465
endmodule
466 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
467 17 unneback
parameter depth = 10;
468
input d, ce;
469
output q;
470
input clk, rst;
471
reg [1:depth] dffs;
472
always @ (posedge clk or posedge rst)
473
if (rst)
474
    dffs <= {depth{1'b0}};
475
else
476
    if (ce)
477
        dffs <= {d,dffs[1:depth-1]};
478
assign q = dffs[depth];
479
endmodule
480 18 unneback
module vl_delay ( d, q, clk, rst);
481 15 unneback
parameter depth = 10;
482
input d;
483
output q;
484
input clk, rst;
485
reg [1:depth] dffs;
486
always @ (posedge clk or posedge rst)
487
if (rst)
488
    dffs <= {depth{1'b0}};
489
else
490
    dffs <= {d,dffs[1:depth-1]};
491
assign q = dffs[depth];
492
endmodule
493 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
494 17 unneback
parameter depth = 10;
495
input d;
496
output q, emptyflag;
497
input clk, rst;
498
reg [1:depth] dffs;
499
always @ (posedge clk or posedge rst)
500
if (rst)
501
    dffs <= {depth{1'b0}};
502
else
503
    dffs <= {d,dffs[1:depth-1]};
504
assign q = dffs[depth];
505
assign emptyflag = !(|dffs);
506
endmodule
507 6 unneback
//////////////////////////////////////////////////////////////////////
508
////                                                              ////
509 18 unneback
////  Logic functions                                             ////
510
////                                                              ////
511
////  Description                                                 ////
512
////  Logic functions such as multiplexers                        ////
513
////                                                              ////
514
////                                                              ////
515
////  To Do:                                                      ////
516
////   -                                                          ////
517
////                                                              ////
518
////  Author(s):                                                  ////
519
////      - Michael Unneback, unneback@opencores.org              ////
520
////        ORSoC AB                                              ////
521
////                                                              ////
522
//////////////////////////////////////////////////////////////////////
523
////                                                              ////
524
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
525
////                                                              ////
526
//// This source file may be used and distributed without         ////
527
//// restriction provided that this copyright statement is not    ////
528
//// removed from the file and that any derivative work contains  ////
529
//// the original copyright notice and the associated disclaimer. ////
530
////                                                              ////
531
//// This source file is free software; you can redistribute it   ////
532
//// and/or modify it under the terms of the GNU Lesser General   ////
533
//// Public License as published by the Free Software Foundation; ////
534
//// either version 2.1 of the License, or (at your option) any   ////
535
//// later version.                                               ////
536
////                                                              ////
537
//// This source is distributed in the hope that it will be       ////
538
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
539
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
540
//// PURPOSE.  See the GNU Lesser General Public License for more ////
541
//// details.                                                     ////
542
////                                                              ////
543
//// You should have received a copy of the GNU Lesser General    ////
544
//// Public License along with this source; if not, download it   ////
545
//// from http://www.opencores.org/lgpl.shtml                     ////
546
////                                                              ////
547
//////////////////////////////////////////////////////////////////////
548 36 unneback
module vl_mux_andor ( a, sel, dout);
549
parameter width = 32;
550
parameter nr_of_ports = 4;
551
input [nr_of_ports*width-1:0] a;
552
input [nr_of_ports-1:0] sel;
553
output reg [width-1:0] dout;
554 38 unneback
integer i,j;
555 36 unneback
always @ (a, sel)
556
begin
557
    dout = a[width-1:0] & {width{sel[0]}};
558
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
559 38 unneback
        for (j=0;j<32;j=j+1)
560
            dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
561 36 unneback
end
562
endmodule
563 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
564
parameter width = 32;
565 35 unneback
localparam nr_of_ports = 2;
566 34 unneback
input [width-1:0] a1, a0;
567
input [nr_of_ports-1:0] sel;
568
output [width-1:0] dout;
569 36 unneback
vl_mux_andor
570 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
571 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
572 34 unneback
endmodule
573
module vl_mux3_andor ( a2, a1, a0, sel, dout);
574
parameter width = 32;
575 35 unneback
localparam nr_of_ports = 3;
576 34 unneback
input [width-1:0] a2, a1, a0;
577
input [nr_of_ports-1:0] sel;
578
output [width-1:0] dout;
579 36 unneback
vl_mux_andor
580 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
581 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
582 34 unneback
endmodule
583 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
584
parameter width = 32;
585 35 unneback
localparam nr_of_ports = 4;
586 18 unneback
input [width-1:0] a3, a2, a1, a0;
587
input [nr_of_ports-1:0] sel;
588 22 unneback
output [width-1:0] dout;
589 36 unneback
vl_mux_andor
590 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
591 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
592 18 unneback
endmodule
593
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
594
parameter width = 32;
595 35 unneback
localparam nr_of_ports = 5;
596 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
597
input [nr_of_ports-1:0] sel;
598 22 unneback
output [width-1:0] dout;
599 36 unneback
vl_mux_andor
600 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
601 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
602 18 unneback
endmodule
603
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
604
parameter width = 32;
605 35 unneback
localparam nr_of_ports = 6;
606 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
607
input [nr_of_ports-1:0] sel;
608 22 unneback
output [width-1:0] dout;
609 36 unneback
vl_mux_andor
610 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
611 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
612 18 unneback
endmodule
613
//////////////////////////////////////////////////////////////////////
614
////                                                              ////
615 6 unneback
////  Versatile counter                                           ////
616
////                                                              ////
617
////  Description                                                 ////
618
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
619
////  counter                                                     ////
620
////                                                              ////
621
////  To Do:                                                      ////
622
////   - add LFSR with more taps                                  ////
623
////                                                              ////
624
////  Author(s):                                                  ////
625
////      - Michael Unneback, unneback@opencores.org              ////
626
////        ORSoC AB                                              ////
627
////                                                              ////
628
//////////////////////////////////////////////////////////////////////
629
////                                                              ////
630
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
631
////                                                              ////
632
//// This source file may be used and distributed without         ////
633
//// restriction provided that this copyright statement is not    ////
634
//// removed from the file and that any derivative work contains  ////
635
//// the original copyright notice and the associated disclaimer. ////
636
////                                                              ////
637
//// This source file is free software; you can redistribute it   ////
638
//// and/or modify it under the terms of the GNU Lesser General   ////
639
//// Public License as published by the Free Software Foundation; ////
640
//// either version 2.1 of the License, or (at your option) any   ////
641
//// later version.                                               ////
642
////                                                              ////
643
//// This source is distributed in the hope that it will be       ////
644
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
645
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
646
//// PURPOSE.  See the GNU Lesser General Public License for more ////
647
//// details.                                                     ////
648
////                                                              ////
649
//// You should have received a copy of the GNU Lesser General    ////
650
//// Public License along with this source; if not, download it   ////
651
//// from http://www.opencores.org/lgpl.shtml                     ////
652
////                                                              ////
653
//////////////////////////////////////////////////////////////////////
654
// binary counter
655 22 unneback
module vl_cnt_bin ( q, rst, clk);
656
   parameter length = 4;
657
   output [length:1] q;
658
   input rst;
659
   input clk;
660
   parameter clear_value = 0;
661
   parameter set_value = 1;
662
   parameter wrap_value = 0;
663
   parameter level1_value = 15;
664
   reg  [length:1] qi;
665
   wire [length:1] q_next;
666
   assign q_next = qi + {{length-1{1'b0}},1'b1};
667
   always @ (posedge clk or posedge rst)
668
     if (rst)
669
       qi <= {length{1'b0}};
670
     else
671
       qi <= q_next;
672
   assign q = qi;
673
endmodule
674
//////////////////////////////////////////////////////////////////////
675
////                                                              ////
676
////  Versatile counter                                           ////
677
////                                                              ////
678
////  Description                                                 ////
679
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
680
////  counter                                                     ////
681
////                                                              ////
682
////  To Do:                                                      ////
683
////   - add LFSR with more taps                                  ////
684
////                                                              ////
685
////  Author(s):                                                  ////
686
////      - Michael Unneback, unneback@opencores.org              ////
687
////        ORSoC AB                                              ////
688
////                                                              ////
689
//////////////////////////////////////////////////////////////////////
690
////                                                              ////
691
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
692
////                                                              ////
693
//// This source file may be used and distributed without         ////
694
//// restriction provided that this copyright statement is not    ////
695
//// removed from the file and that any derivative work contains  ////
696
//// the original copyright notice and the associated disclaimer. ////
697
////                                                              ////
698
//// This source file is free software; you can redistribute it   ////
699
//// and/or modify it under the terms of the GNU Lesser General   ////
700
//// Public License as published by the Free Software Foundation; ////
701
//// either version 2.1 of the License, or (at your option) any   ////
702
//// later version.                                               ////
703
////                                                              ////
704
//// This source is distributed in the hope that it will be       ////
705
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
706
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
707
//// PURPOSE.  See the GNU Lesser General Public License for more ////
708
//// details.                                                     ////
709
////                                                              ////
710
//// You should have received a copy of the GNU Lesser General    ////
711
//// Public License along with this source; if not, download it   ////
712
//// from http://www.opencores.org/lgpl.shtml                     ////
713
////                                                              ////
714
//////////////////////////////////////////////////////////////////////
715
// binary counter
716
module vl_cnt_bin_clear ( clear, q, rst, clk);
717
   parameter length = 4;
718
   input clear;
719
   output [length:1] q;
720
   input rst;
721
   input clk;
722
   parameter clear_value = 0;
723
   parameter set_value = 1;
724
   parameter wrap_value = 0;
725
   parameter level1_value = 15;
726
   reg  [length:1] qi;
727
   wire [length:1] q_next;
728
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
729
   always @ (posedge clk or posedge rst)
730
     if (rst)
731
       qi <= {length{1'b0}};
732
     else
733
       qi <= q_next;
734
   assign q = qi;
735
endmodule
736
//////////////////////////////////////////////////////////////////////
737
////                                                              ////
738
////  Versatile counter                                           ////
739
////                                                              ////
740
////  Description                                                 ////
741
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
742
////  counter                                                     ////
743
////                                                              ////
744
////  To Do:                                                      ////
745
////   - add LFSR with more taps                                  ////
746
////                                                              ////
747
////  Author(s):                                                  ////
748
////      - Michael Unneback, unneback@opencores.org              ////
749
////        ORSoC AB                                              ////
750
////                                                              ////
751
//////////////////////////////////////////////////////////////////////
752
////                                                              ////
753
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
754
////                                                              ////
755
//// This source file may be used and distributed without         ////
756
//// restriction provided that this copyright statement is not    ////
757
//// removed from the file and that any derivative work contains  ////
758
//// the original copyright notice and the associated disclaimer. ////
759
////                                                              ////
760
//// This source file is free software; you can redistribute it   ////
761
//// and/or modify it under the terms of the GNU Lesser General   ////
762
//// Public License as published by the Free Software Foundation; ////
763
//// either version 2.1 of the License, or (at your option) any   ////
764
//// later version.                                               ////
765
////                                                              ////
766
//// This source is distributed in the hope that it will be       ////
767
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
768
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
769
//// PURPOSE.  See the GNU Lesser General Public License for more ////
770
//// details.                                                     ////
771
////                                                              ////
772
//// You should have received a copy of the GNU Lesser General    ////
773
//// Public License along with this source; if not, download it   ////
774
//// from http://www.opencores.org/lgpl.shtml                     ////
775
////                                                              ////
776
//////////////////////////////////////////////////////////////////////
777
// binary counter
778 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
779 6 unneback
   parameter length = 4;
780
   input cke;
781
   output [length:1] q;
782
   input rst;
783
   input clk;
784
   parameter clear_value = 0;
785
   parameter set_value = 1;
786
   parameter wrap_value = 0;
787
   parameter level1_value = 15;
788
   reg  [length:1] qi;
789
   wire [length:1] q_next;
790
   assign q_next = qi + {{length-1{1'b0}},1'b1};
791
   always @ (posedge clk or posedge rst)
792
     if (rst)
793
       qi <= {length{1'b0}};
794
     else
795
     if (cke)
796
       qi <= q_next;
797
   assign q = qi;
798
endmodule
799
//////////////////////////////////////////////////////////////////////
800
////                                                              ////
801
////  Versatile counter                                           ////
802
////                                                              ////
803
////  Description                                                 ////
804
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
805
////  counter                                                     ////
806
////                                                              ////
807
////  To Do:                                                      ////
808
////   - add LFSR with more taps                                  ////
809
////                                                              ////
810
////  Author(s):                                                  ////
811
////      - Michael Unneback, unneback@opencores.org              ////
812
////        ORSoC AB                                              ////
813
////                                                              ////
814
//////////////////////////////////////////////////////////////////////
815
////                                                              ////
816
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
817
////                                                              ////
818
//// This source file may be used and distributed without         ////
819
//// restriction provided that this copyright statement is not    ////
820
//// removed from the file and that any derivative work contains  ////
821
//// the original copyright notice and the associated disclaimer. ////
822
////                                                              ////
823
//// This source file is free software; you can redistribute it   ////
824
//// and/or modify it under the terms of the GNU Lesser General   ////
825
//// Public License as published by the Free Software Foundation; ////
826
//// either version 2.1 of the License, or (at your option) any   ////
827
//// later version.                                               ////
828
////                                                              ////
829
//// This source is distributed in the hope that it will be       ////
830
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
831
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
832
//// PURPOSE.  See the GNU Lesser General Public License for more ////
833
//// details.                                                     ////
834
////                                                              ////
835
//// You should have received a copy of the GNU Lesser General    ////
836
//// Public License along with this source; if not, download it   ////
837
//// from http://www.opencores.org/lgpl.shtml                     ////
838
////                                                              ////
839
//////////////////////////////////////////////////////////////////////
840
// binary counter
841 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
842 6 unneback
   parameter length = 4;
843
   input clear;
844
   input cke;
845
   output [length:1] q;
846
   input rst;
847
   input clk;
848
   parameter clear_value = 0;
849
   parameter set_value = 1;
850
   parameter wrap_value = 0;
851
   parameter level1_value = 15;
852
   reg  [length:1] qi;
853
   wire [length:1] q_next;
854
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
855
   always @ (posedge clk or posedge rst)
856
     if (rst)
857
       qi <= {length{1'b0}};
858
     else
859
     if (cke)
860
       qi <= q_next;
861
   assign q = qi;
862
endmodule
863
//////////////////////////////////////////////////////////////////////
864
////                                                              ////
865
////  Versatile counter                                           ////
866
////                                                              ////
867
////  Description                                                 ////
868
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
869
////  counter                                                     ////
870
////                                                              ////
871
////  To Do:                                                      ////
872
////   - add LFSR with more taps                                  ////
873
////                                                              ////
874
////  Author(s):                                                  ////
875
////      - Michael Unneback, unneback@opencores.org              ////
876
////        ORSoC AB                                              ////
877
////                                                              ////
878
//////////////////////////////////////////////////////////////////////
879
////                                                              ////
880
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
881
////                                                              ////
882
//// This source file may be used and distributed without         ////
883
//// restriction provided that this copyright statement is not    ////
884
//// removed from the file and that any derivative work contains  ////
885
//// the original copyright notice and the associated disclaimer. ////
886
////                                                              ////
887
//// This source file is free software; you can redistribute it   ////
888
//// and/or modify it under the terms of the GNU Lesser General   ////
889
//// Public License as published by the Free Software Foundation; ////
890
//// either version 2.1 of the License, or (at your option) any   ////
891
//// later version.                                               ////
892
////                                                              ////
893
//// This source is distributed in the hope that it will be       ////
894
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
895
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
896
//// PURPOSE.  See the GNU Lesser General Public License for more ////
897
//// details.                                                     ////
898
////                                                              ////
899
//// You should have received a copy of the GNU Lesser General    ////
900
//// Public License along with this source; if not, download it   ////
901
//// from http://www.opencores.org/lgpl.shtml                     ////
902
////                                                              ////
903
//////////////////////////////////////////////////////////////////////
904
// binary counter
905 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
906
   parameter length = 4;
907
   input clear;
908
   input cke;
909
   output [length:1] q;
910
   output reg level1;
911
   output reg level2;
912
   input rst;
913
   input clk;
914
   parameter clear_value = 0;
915
   parameter set_value = 1;
916 30 unneback
   parameter wrap_value = 15;
917
   parameter level1_value = 8;
918
   parameter level2_value = 15;
919 29 unneback
   wire rew;
920 30 unneback
   assign rew = 1'b0;
921 29 unneback
   reg  [length:1] qi;
922
   wire [length:1] q_next;
923
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
924
   always @ (posedge clk or posedge rst)
925
     if (rst)
926
       qi <= {length{1'b0}};
927
     else
928
     if (cke)
929
       qi <= q_next;
930
   assign q = qi;
931
    always @ (posedge clk or posedge rst)
932
    if (rst)
933
        level1 <= 1'b0;
934
    else
935
    if (cke)
936
    if (clear)
937
        level1 <= 1'b0;
938
    else if (q_next == level1_value)
939
        level1 <= 1'b1;
940
    else if (qi == level1_value & rew)
941
        level1 <= 1'b0;
942
    always @ (posedge clk or posedge rst)
943
    if (rst)
944
        level2 <= 1'b0;
945
    else
946
    if (cke)
947
    if (clear)
948
        level2 <= 1'b0;
949
    else if (q_next == level2_value)
950
        level2 <= 1'b1;
951
    else if (qi == level2_value & rew)
952
        level2 <= 1'b0;
953
endmodule
954
//////////////////////////////////////////////////////////////////////
955
////                                                              ////
956
////  Versatile counter                                           ////
957
////                                                              ////
958
////  Description                                                 ////
959
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
960
////  counter                                                     ////
961
////                                                              ////
962
////  To Do:                                                      ////
963
////   - add LFSR with more taps                                  ////
964
////                                                              ////
965
////  Author(s):                                                  ////
966
////      - Michael Unneback, unneback@opencores.org              ////
967
////        ORSoC AB                                              ////
968
////                                                              ////
969
//////////////////////////////////////////////////////////////////////
970
////                                                              ////
971
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
972
////                                                              ////
973
//// This source file may be used and distributed without         ////
974
//// restriction provided that this copyright statement is not    ////
975
//// removed from the file and that any derivative work contains  ////
976
//// the original copyright notice and the associated disclaimer. ////
977
////                                                              ////
978
//// This source file is free software; you can redistribute it   ////
979
//// and/or modify it under the terms of the GNU Lesser General   ////
980
//// Public License as published by the Free Software Foundation; ////
981
//// either version 2.1 of the License, or (at your option) any   ////
982
//// later version.                                               ////
983
////                                                              ////
984
//// This source is distributed in the hope that it will be       ////
985
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
986
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
987
//// PURPOSE.  See the GNU Lesser General Public License for more ////
988
//// details.                                                     ////
989
////                                                              ////
990
//// You should have received a copy of the GNU Lesser General    ////
991
//// Public License along with this source; if not, download it   ////
992
//// from http://www.opencores.org/lgpl.shtml                     ////
993
////                                                              ////
994
//////////////////////////////////////////////////////////////////////
995
// binary counter
996 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
997 6 unneback
   parameter length = 4;
998
   input clear;
999
   input set;
1000
   input cke;
1001
   input rew;
1002
   output [length:1] q;
1003
   input rst;
1004
   input clk;
1005
   parameter clear_value = 0;
1006
   parameter set_value = 1;
1007
   parameter wrap_value = 0;
1008
   parameter level1_value = 15;
1009
   reg  [length:1] qi;
1010
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1011
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1012
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1013
   assign q_next = rew ? q_next_rew : q_next_fw;
1014
   always @ (posedge clk or posedge rst)
1015
     if (rst)
1016
       qi <= {length{1'b0}};
1017
     else
1018
     if (cke)
1019
       qi <= q_next;
1020
   assign q = qi;
1021
endmodule
1022
//////////////////////////////////////////////////////////////////////
1023
////                                                              ////
1024
////  Versatile counter                                           ////
1025
////                                                              ////
1026
////  Description                                                 ////
1027
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1028
////  counter                                                     ////
1029
////                                                              ////
1030
////  To Do:                                                      ////
1031
////   - add LFSR with more taps                                  ////
1032
////                                                              ////
1033
////  Author(s):                                                  ////
1034
////      - Michael Unneback, unneback@opencores.org              ////
1035
////        ORSoC AB                                              ////
1036
////                                                              ////
1037
//////////////////////////////////////////////////////////////////////
1038
////                                                              ////
1039
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1040
////                                                              ////
1041
//// This source file may be used and distributed without         ////
1042
//// restriction provided that this copyright statement is not    ////
1043
//// removed from the file and that any derivative work contains  ////
1044
//// the original copyright notice and the associated disclaimer. ////
1045
////                                                              ////
1046
//// This source file is free software; you can redistribute it   ////
1047
//// and/or modify it under the terms of the GNU Lesser General   ////
1048
//// Public License as published by the Free Software Foundation; ////
1049
//// either version 2.1 of the License, or (at your option) any   ////
1050
//// later version.                                               ////
1051
////                                                              ////
1052
//// This source is distributed in the hope that it will be       ////
1053
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1054
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1055
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1056
//// details.                                                     ////
1057
////                                                              ////
1058
//// You should have received a copy of the GNU Lesser General    ////
1059
//// Public License along with this source; if not, download it   ////
1060
//// from http://www.opencores.org/lgpl.shtml                     ////
1061
////                                                              ////
1062
//////////////////////////////////////////////////////////////////////
1063
// binary counter
1064 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1065 6 unneback
   parameter length = 4;
1066
   input cke;
1067
   input rew;
1068
   output reg level1;
1069
   input rst;
1070
   input clk;
1071
   parameter clear_value = 0;
1072
   parameter set_value = 1;
1073
   parameter wrap_value = 1;
1074
   parameter level1_value = 15;
1075 29 unneback
   wire clear;
1076 30 unneback
   assign clear = 1'b0;
1077 6 unneback
   reg  [length:1] qi;
1078
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1079
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1080
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1081
   assign q_next = rew ? q_next_rew : q_next_fw;
1082
   always @ (posedge clk or posedge rst)
1083
     if (rst)
1084
       qi <= {length{1'b0}};
1085
     else
1086
     if (cke)
1087
       qi <= q_next;
1088
    always @ (posedge clk or posedge rst)
1089
    if (rst)
1090
        level1 <= 1'b0;
1091
    else
1092
    if (cke)
1093 29 unneback
    if (clear)
1094
        level1 <= 1'b0;
1095
    else if (q_next == level1_value)
1096 6 unneback
        level1 <= 1'b1;
1097
    else if (qi == level1_value & rew)
1098
        level1 <= 1'b0;
1099
endmodule
1100
//////////////////////////////////////////////////////////////////////
1101
////                                                              ////
1102
////  Versatile counter                                           ////
1103
////                                                              ////
1104
////  Description                                                 ////
1105
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1106
////  counter                                                     ////
1107
////                                                              ////
1108
////  To Do:                                                      ////
1109
////   - add LFSR with more taps                                  ////
1110
////                                                              ////
1111
////  Author(s):                                                  ////
1112
////      - Michael Unneback, unneback@opencores.org              ////
1113
////        ORSoC AB                                              ////
1114
////                                                              ////
1115
//////////////////////////////////////////////////////////////////////
1116
////                                                              ////
1117
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1118
////                                                              ////
1119
//// This source file may be used and distributed without         ////
1120
//// restriction provided that this copyright statement is not    ////
1121
//// removed from the file and that any derivative work contains  ////
1122
//// the original copyright notice and the associated disclaimer. ////
1123
////                                                              ////
1124
//// This source file is free software; you can redistribute it   ////
1125
//// and/or modify it under the terms of the GNU Lesser General   ////
1126
//// Public License as published by the Free Software Foundation; ////
1127
//// either version 2.1 of the License, or (at your option) any   ////
1128
//// later version.                                               ////
1129
////                                                              ////
1130
//// This source is distributed in the hope that it will be       ////
1131
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1132
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1133
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1134
//// details.                                                     ////
1135
////                                                              ////
1136
//// You should have received a copy of the GNU Lesser General    ////
1137
//// Public License along with this source; if not, download it   ////
1138
//// from http://www.opencores.org/lgpl.shtml                     ////
1139
////                                                              ////
1140
//////////////////////////////////////////////////////////////////////
1141 25 unneback
// binary counter
1142
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1143
   parameter length = 4;
1144
   input cke;
1145
   input rew;
1146
   output reg zq;
1147
   output reg level1;
1148
   input rst;
1149
   input clk;
1150
   parameter clear_value = 0;
1151
   parameter set_value = 1;
1152
   parameter wrap_value = 1;
1153
   parameter level1_value = 15;
1154 29 unneback
   wire clear;
1155 30 unneback
   assign clear = 1'b0;
1156 25 unneback
   reg  [length:1] qi;
1157
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1158
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1159
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1160
   assign q_next = rew ? q_next_rew : q_next_fw;
1161
   always @ (posedge clk or posedge rst)
1162
     if (rst)
1163
       qi <= {length{1'b0}};
1164
     else
1165
     if (cke)
1166
       qi <= q_next;
1167
   always @ (posedge clk or posedge rst)
1168
     if (rst)
1169
       zq <= 1'b1;
1170
     else
1171
     if (cke)
1172
       zq <= q_next == {length{1'b0}};
1173
    always @ (posedge clk or posedge rst)
1174
    if (rst)
1175
        level1 <= 1'b0;
1176
    else
1177
    if (cke)
1178 29 unneback
    if (clear)
1179
        level1 <= 1'b0;
1180
    else if (q_next == level1_value)
1181 25 unneback
        level1 <= 1'b1;
1182
    else if (qi == level1_value & rew)
1183
        level1 <= 1'b0;
1184
endmodule
1185
//////////////////////////////////////////////////////////////////////
1186
////                                                              ////
1187
////  Versatile counter                                           ////
1188
////                                                              ////
1189
////  Description                                                 ////
1190
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1191
////  counter                                                     ////
1192
////                                                              ////
1193
////  To Do:                                                      ////
1194
////   - add LFSR with more taps                                  ////
1195
////                                                              ////
1196
////  Author(s):                                                  ////
1197
////      - Michael Unneback, unneback@opencores.org              ////
1198
////        ORSoC AB                                              ////
1199
////                                                              ////
1200
//////////////////////////////////////////////////////////////////////
1201
////                                                              ////
1202
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1203
////                                                              ////
1204
//// This source file may be used and distributed without         ////
1205
//// restriction provided that this copyright statement is not    ////
1206
//// removed from the file and that any derivative work contains  ////
1207
//// the original copyright notice and the associated disclaimer. ////
1208
////                                                              ////
1209
//// This source file is free software; you can redistribute it   ////
1210
//// and/or modify it under the terms of the GNU Lesser General   ////
1211
//// Public License as published by the Free Software Foundation; ////
1212
//// either version 2.1 of the License, or (at your option) any   ////
1213
//// later version.                                               ////
1214
////                                                              ////
1215
//// This source is distributed in the hope that it will be       ////
1216
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1217
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1218
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1219
//// details.                                                     ////
1220
////                                                              ////
1221
//// You should have received a copy of the GNU Lesser General    ////
1222
//// Public License along with this source; if not, download it   ////
1223
//// from http://www.opencores.org/lgpl.shtml                     ////
1224
////                                                              ////
1225
//////////////////////////////////////////////////////////////////////
1226
// binary counter
1227
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1228
   parameter length = 4;
1229
   input cke;
1230
   input rew;
1231
   output [length:1] q;
1232
   output reg zq;
1233
   output reg level1;
1234
   input rst;
1235
   input clk;
1236
   parameter clear_value = 0;
1237
   parameter set_value = 1;
1238
   parameter wrap_value = 1;
1239
   parameter level1_value = 15;
1240 29 unneback
   wire clear;
1241 30 unneback
   assign clear = 1'b0;
1242 25 unneback
   reg  [length:1] qi;
1243
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1244
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1245
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1246
   assign q_next = rew ? q_next_rew : q_next_fw;
1247
   always @ (posedge clk or posedge rst)
1248
     if (rst)
1249
       qi <= {length{1'b0}};
1250
     else
1251
     if (cke)
1252
       qi <= q_next;
1253
   assign q = qi;
1254
   always @ (posedge clk or posedge rst)
1255
     if (rst)
1256
       zq <= 1'b1;
1257
     else
1258
     if (cke)
1259
       zq <= q_next == {length{1'b0}};
1260
    always @ (posedge clk or posedge rst)
1261
    if (rst)
1262
        level1 <= 1'b0;
1263
    else
1264
    if (cke)
1265 29 unneback
    if (clear)
1266
        level1 <= 1'b0;
1267
    else if (q_next == level1_value)
1268 25 unneback
        level1 <= 1'b1;
1269
    else if (qi == level1_value & rew)
1270
        level1 <= 1'b0;
1271
endmodule
1272
//////////////////////////////////////////////////////////////////////
1273
////                                                              ////
1274
////  Versatile counter                                           ////
1275
////                                                              ////
1276
////  Description                                                 ////
1277
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1278
////  counter                                                     ////
1279
////                                                              ////
1280
////  To Do:                                                      ////
1281
////   - add LFSR with more taps                                  ////
1282
////                                                              ////
1283
////  Author(s):                                                  ////
1284
////      - Michael Unneback, unneback@opencores.org              ////
1285
////        ORSoC AB                                              ////
1286
////                                                              ////
1287
//////////////////////////////////////////////////////////////////////
1288
////                                                              ////
1289
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1290
////                                                              ////
1291
//// This source file may be used and distributed without         ////
1292
//// restriction provided that this copyright statement is not    ////
1293
//// removed from the file and that any derivative work contains  ////
1294
//// the original copyright notice and the associated disclaimer. ////
1295
////                                                              ////
1296
//// This source file is free software; you can redistribute it   ////
1297
//// and/or modify it under the terms of the GNU Lesser General   ////
1298
//// Public License as published by the Free Software Foundation; ////
1299
//// either version 2.1 of the License, or (at your option) any   ////
1300
//// later version.                                               ////
1301
////                                                              ////
1302
//// This source is distributed in the hope that it will be       ////
1303
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1304
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1305
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1306
//// details.                                                     ////
1307
////                                                              ////
1308
//// You should have received a copy of the GNU Lesser General    ////
1309
//// Public License along with this source; if not, download it   ////
1310
//// from http://www.opencores.org/lgpl.shtml                     ////
1311
////                                                              ////
1312
//////////////////////////////////////////////////////////////////////
1313 6 unneback
// LFSR counter
1314 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1315 6 unneback
   parameter length = 4;
1316
   output reg zq;
1317
   input rst;
1318
   input clk;
1319
   parameter clear_value = 0;
1320
   parameter set_value = 1;
1321
   parameter wrap_value = 8;
1322
   parameter level1_value = 15;
1323
   reg  [length:1] qi;
1324
   reg lfsr_fb;
1325
   wire [length:1] q_next;
1326
   reg [32:1] polynom;
1327
   integer i;
1328
   always @ (qi)
1329
   begin
1330
        case (length)
1331
         2: polynom = 32'b11;                               // 0x3
1332
         3: polynom = 32'b110;                              // 0x6
1333
         4: polynom = 32'b1100;                             // 0xC
1334
         5: polynom = 32'b10100;                            // 0x14
1335
         6: polynom = 32'b110000;                           // 0x30
1336
         7: polynom = 32'b1100000;                          // 0x60
1337
         8: polynom = 32'b10111000;                         // 0xb8
1338
         9: polynom = 32'b100010000;                        // 0x110
1339
        10: polynom = 32'b1001000000;                       // 0x240
1340
        11: polynom = 32'b10100000000;                      // 0x500
1341
        12: polynom = 32'b100000101001;                     // 0x829
1342
        13: polynom = 32'b1000000001100;                    // 0x100C
1343
        14: polynom = 32'b10000000010101;                   // 0x2015
1344
        15: polynom = 32'b110000000000000;                  // 0x6000
1345
        16: polynom = 32'b1101000000001000;                 // 0xD008
1346
        17: polynom = 32'b10010000000000000;                // 0x12000
1347
        18: polynom = 32'b100000010000000000;               // 0x20400
1348
        19: polynom = 32'b1000000000000100011;              // 0x40023
1349 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1350 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1351
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1352
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1353
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1354
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1355
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1356
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1357
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1358
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1359
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1360
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1361
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1362
        default: polynom = 32'b0;
1363
        endcase
1364
        lfsr_fb = qi[length];
1365
        for (i=length-1; i>=1; i=i-1) begin
1366
            if (polynom[i])
1367
                lfsr_fb = lfsr_fb  ~^ qi[i];
1368
        end
1369
    end
1370
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1371
   always @ (posedge clk or posedge rst)
1372
     if (rst)
1373
       qi <= {length{1'b0}};
1374
     else
1375
       qi <= q_next;
1376
   always @ (posedge clk or posedge rst)
1377
     if (rst)
1378
       zq <= 1'b1;
1379
     else
1380
       zq <= q_next == {length{1'b0}};
1381
endmodule
1382
//////////////////////////////////////////////////////////////////////
1383
////                                                              ////
1384
////  Versatile counter                                           ////
1385
////                                                              ////
1386
////  Description                                                 ////
1387
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1388
////  counter                                                     ////
1389
////                                                              ////
1390
////  To Do:                                                      ////
1391
////   - add LFSR with more taps                                  ////
1392
////                                                              ////
1393
////  Author(s):                                                  ////
1394
////      - Michael Unneback, unneback@opencores.org              ////
1395
////        ORSoC AB                                              ////
1396
////                                                              ////
1397
//////////////////////////////////////////////////////////////////////
1398
////                                                              ////
1399
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1400
////                                                              ////
1401
//// This source file may be used and distributed without         ////
1402
//// restriction provided that this copyright statement is not    ////
1403
//// removed from the file and that any derivative work contains  ////
1404
//// the original copyright notice and the associated disclaimer. ////
1405
////                                                              ////
1406
//// This source file is free software; you can redistribute it   ////
1407
//// and/or modify it under the terms of the GNU Lesser General   ////
1408
//// Public License as published by the Free Software Foundation; ////
1409
//// either version 2.1 of the License, or (at your option) any   ////
1410
//// later version.                                               ////
1411
////                                                              ////
1412
//// This source is distributed in the hope that it will be       ////
1413
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1414
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1415
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1416
//// details.                                                     ////
1417
////                                                              ////
1418
//// You should have received a copy of the GNU Lesser General    ////
1419
//// Public License along with this source; if not, download it   ////
1420
//// from http://www.opencores.org/lgpl.shtml                     ////
1421
////                                                              ////
1422
//////////////////////////////////////////////////////////////////////
1423
// LFSR counter
1424 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1425 6 unneback
   parameter length = 4;
1426
   input cke;
1427
   output reg zq;
1428
   input rst;
1429
   input clk;
1430
   parameter clear_value = 0;
1431
   parameter set_value = 1;
1432
   parameter wrap_value = 8;
1433
   parameter level1_value = 15;
1434
   reg  [length:1] qi;
1435
   reg lfsr_fb;
1436
   wire [length:1] q_next;
1437
   reg [32:1] polynom;
1438
   integer i;
1439
   always @ (qi)
1440
   begin
1441
        case (length)
1442
         2: polynom = 32'b11;                               // 0x3
1443
         3: polynom = 32'b110;                              // 0x6
1444
         4: polynom = 32'b1100;                             // 0xC
1445
         5: polynom = 32'b10100;                            // 0x14
1446
         6: polynom = 32'b110000;                           // 0x30
1447
         7: polynom = 32'b1100000;                          // 0x60
1448
         8: polynom = 32'b10111000;                         // 0xb8
1449
         9: polynom = 32'b100010000;                        // 0x110
1450
        10: polynom = 32'b1001000000;                       // 0x240
1451
        11: polynom = 32'b10100000000;                      // 0x500
1452
        12: polynom = 32'b100000101001;                     // 0x829
1453
        13: polynom = 32'b1000000001100;                    // 0x100C
1454
        14: polynom = 32'b10000000010101;                   // 0x2015
1455
        15: polynom = 32'b110000000000000;                  // 0x6000
1456
        16: polynom = 32'b1101000000001000;                 // 0xD008
1457
        17: polynom = 32'b10010000000000000;                // 0x12000
1458
        18: polynom = 32'b100000010000000000;               // 0x20400
1459
        19: polynom = 32'b1000000000000100011;              // 0x40023
1460 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1461 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1462
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1463
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1464
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1465
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1466
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1467
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1468
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1469
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1470
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1471
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1472
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1473
        default: polynom = 32'b0;
1474
        endcase
1475
        lfsr_fb = qi[length];
1476
        for (i=length-1; i>=1; i=i-1) begin
1477
            if (polynom[i])
1478
                lfsr_fb = lfsr_fb  ~^ qi[i];
1479
        end
1480
    end
1481
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1482
   always @ (posedge clk or posedge rst)
1483
     if (rst)
1484
       qi <= {length{1'b0}};
1485
     else
1486
     if (cke)
1487
       qi <= q_next;
1488
   always @ (posedge clk or posedge rst)
1489
     if (rst)
1490
       zq <= 1'b1;
1491
     else
1492
     if (cke)
1493
       zq <= q_next == {length{1'b0}};
1494
endmodule
1495
//////////////////////////////////////////////////////////////////////
1496
////                                                              ////
1497
////  Versatile counter                                           ////
1498
////                                                              ////
1499
////  Description                                                 ////
1500
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1501
////  counter                                                     ////
1502
////                                                              ////
1503
////  To Do:                                                      ////
1504
////   - add LFSR with more taps                                  ////
1505
////                                                              ////
1506
////  Author(s):                                                  ////
1507
////      - Michael Unneback, unneback@opencores.org              ////
1508
////        ORSoC AB                                              ////
1509
////                                                              ////
1510
//////////////////////////////////////////////////////////////////////
1511
////                                                              ////
1512
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1513
////                                                              ////
1514
//// This source file may be used and distributed without         ////
1515
//// restriction provided that this copyright statement is not    ////
1516
//// removed from the file and that any derivative work contains  ////
1517
//// the original copyright notice and the associated disclaimer. ////
1518
////                                                              ////
1519
//// This source file is free software; you can redistribute it   ////
1520
//// and/or modify it under the terms of the GNU Lesser General   ////
1521
//// Public License as published by the Free Software Foundation; ////
1522
//// either version 2.1 of the License, or (at your option) any   ////
1523
//// later version.                                               ////
1524
////                                                              ////
1525
//// This source is distributed in the hope that it will be       ////
1526
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1527
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1528
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1529
//// details.                                                     ////
1530
////                                                              ////
1531
//// You should have received a copy of the GNU Lesser General    ////
1532
//// Public License along with this source; if not, download it   ////
1533
//// from http://www.opencores.org/lgpl.shtml                     ////
1534
////                                                              ////
1535
//////////////////////////////////////////////////////////////////////
1536
// LFSR counter
1537 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1538
   parameter length = 4;
1539
   input cke;
1540
   output [length:1] q;
1541
   input rst;
1542
   input clk;
1543
   parameter clear_value = 0;
1544
   parameter set_value = 1;
1545
   parameter wrap_value = 8;
1546
   parameter level1_value = 15;
1547
   reg  [length:1] qi;
1548
   reg lfsr_fb;
1549
   wire [length:1] q_next;
1550
   reg [32:1] polynom;
1551
   integer i;
1552
   always @ (qi)
1553
   begin
1554
        case (length)
1555
         2: polynom = 32'b11;                               // 0x3
1556
         3: polynom = 32'b110;                              // 0x6
1557
         4: polynom = 32'b1100;                             // 0xC
1558
         5: polynom = 32'b10100;                            // 0x14
1559
         6: polynom = 32'b110000;                           // 0x30
1560
         7: polynom = 32'b1100000;                          // 0x60
1561
         8: polynom = 32'b10111000;                         // 0xb8
1562
         9: polynom = 32'b100010000;                        // 0x110
1563
        10: polynom = 32'b1001000000;                       // 0x240
1564
        11: polynom = 32'b10100000000;                      // 0x500
1565
        12: polynom = 32'b100000101001;                     // 0x829
1566
        13: polynom = 32'b1000000001100;                    // 0x100C
1567
        14: polynom = 32'b10000000010101;                   // 0x2015
1568
        15: polynom = 32'b110000000000000;                  // 0x6000
1569
        16: polynom = 32'b1101000000001000;                 // 0xD008
1570
        17: polynom = 32'b10010000000000000;                // 0x12000
1571
        18: polynom = 32'b100000010000000000;               // 0x20400
1572
        19: polynom = 32'b1000000000000100011;              // 0x40023
1573 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1574 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1575
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1576
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1577
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1578
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1579
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1580
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1581
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1582
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1583
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1584
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1585
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1586
        default: polynom = 32'b0;
1587
        endcase
1588
        lfsr_fb = qi[length];
1589
        for (i=length-1; i>=1; i=i-1) begin
1590
            if (polynom[i])
1591
                lfsr_fb = lfsr_fb  ~^ qi[i];
1592
        end
1593
    end
1594
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1595
   always @ (posedge clk or posedge rst)
1596
     if (rst)
1597
       qi <= {length{1'b0}};
1598
     else
1599
     if (cke)
1600
       qi <= q_next;
1601
   assign q = qi;
1602
endmodule
1603
//////////////////////////////////////////////////////////////////////
1604
////                                                              ////
1605
////  Versatile counter                                           ////
1606
////                                                              ////
1607
////  Description                                                 ////
1608
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1609
////  counter                                                     ////
1610
////                                                              ////
1611
////  To Do:                                                      ////
1612
////   - add LFSR with more taps                                  ////
1613
////                                                              ////
1614
////  Author(s):                                                  ////
1615
////      - Michael Unneback, unneback@opencores.org              ////
1616
////        ORSoC AB                                              ////
1617
////                                                              ////
1618
//////////////////////////////////////////////////////////////////////
1619
////                                                              ////
1620
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1621
////                                                              ////
1622
//// This source file may be used and distributed without         ////
1623
//// restriction provided that this copyright statement is not    ////
1624
//// removed from the file and that any derivative work contains  ////
1625
//// the original copyright notice and the associated disclaimer. ////
1626
////                                                              ////
1627
//// This source file is free software; you can redistribute it   ////
1628
//// and/or modify it under the terms of the GNU Lesser General   ////
1629
//// Public License as published by the Free Software Foundation; ////
1630
//// either version 2.1 of the License, or (at your option) any   ////
1631
//// later version.                                               ////
1632
////                                                              ////
1633
//// This source is distributed in the hope that it will be       ////
1634
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1635
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1636
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1637
//// details.                                                     ////
1638
////                                                              ////
1639
//// You should have received a copy of the GNU Lesser General    ////
1640
//// Public License along with this source; if not, download it   ////
1641
//// from http://www.opencores.org/lgpl.shtml                     ////
1642
////                                                              ////
1643
//////////////////////////////////////////////////////////////////////
1644
// LFSR counter
1645
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1646
   parameter length = 4;
1647
   input clear;
1648
   input cke;
1649
   output [length:1] q;
1650
   input rst;
1651
   input clk;
1652
   parameter clear_value = 0;
1653
   parameter set_value = 1;
1654
   parameter wrap_value = 8;
1655
   parameter level1_value = 15;
1656
   reg  [length:1] qi;
1657
   reg lfsr_fb;
1658
   wire [length:1] q_next;
1659
   reg [32:1] polynom;
1660
   integer i;
1661
   always @ (qi)
1662
   begin
1663
        case (length)
1664
         2: polynom = 32'b11;                               // 0x3
1665
         3: polynom = 32'b110;                              // 0x6
1666
         4: polynom = 32'b1100;                             // 0xC
1667
         5: polynom = 32'b10100;                            // 0x14
1668
         6: polynom = 32'b110000;                           // 0x30
1669
         7: polynom = 32'b1100000;                          // 0x60
1670
         8: polynom = 32'b10111000;                         // 0xb8
1671
         9: polynom = 32'b100010000;                        // 0x110
1672
        10: polynom = 32'b1001000000;                       // 0x240
1673
        11: polynom = 32'b10100000000;                      // 0x500
1674
        12: polynom = 32'b100000101001;                     // 0x829
1675
        13: polynom = 32'b1000000001100;                    // 0x100C
1676
        14: polynom = 32'b10000000010101;                   // 0x2015
1677
        15: polynom = 32'b110000000000000;                  // 0x6000
1678
        16: polynom = 32'b1101000000001000;                 // 0xD008
1679
        17: polynom = 32'b10010000000000000;                // 0x12000
1680
        18: polynom = 32'b100000010000000000;               // 0x20400
1681
        19: polynom = 32'b1000000000000100011;              // 0x40023
1682 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1683 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1684
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1685
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1686
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1687
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1688
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1689
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1690
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1691
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1692
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1693
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1694
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1695
        default: polynom = 32'b0;
1696
        endcase
1697
        lfsr_fb = qi[length];
1698
        for (i=length-1; i>=1; i=i-1) begin
1699
            if (polynom[i])
1700
                lfsr_fb = lfsr_fb  ~^ qi[i];
1701
        end
1702
    end
1703
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1704
   always @ (posedge clk or posedge rst)
1705
     if (rst)
1706
       qi <= {length{1'b0}};
1707
     else
1708
     if (cke)
1709
       qi <= q_next;
1710
   assign q = qi;
1711
endmodule
1712
//////////////////////////////////////////////////////////////////////
1713
////                                                              ////
1714
////  Versatile counter                                           ////
1715
////                                                              ////
1716
////  Description                                                 ////
1717
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1718
////  counter                                                     ////
1719
////                                                              ////
1720
////  To Do:                                                      ////
1721
////   - add LFSR with more taps                                  ////
1722
////                                                              ////
1723
////  Author(s):                                                  ////
1724
////      - Michael Unneback, unneback@opencores.org              ////
1725
////        ORSoC AB                                              ////
1726
////                                                              ////
1727
//////////////////////////////////////////////////////////////////////
1728
////                                                              ////
1729
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1730
////                                                              ////
1731
//// This source file may be used and distributed without         ////
1732
//// restriction provided that this copyright statement is not    ////
1733
//// removed from the file and that any derivative work contains  ////
1734
//// the original copyright notice and the associated disclaimer. ////
1735
////                                                              ////
1736
//// This source file is free software; you can redistribute it   ////
1737
//// and/or modify it under the terms of the GNU Lesser General   ////
1738
//// Public License as published by the Free Software Foundation; ////
1739
//// either version 2.1 of the License, or (at your option) any   ////
1740
//// later version.                                               ////
1741
////                                                              ////
1742
//// This source is distributed in the hope that it will be       ////
1743
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1744
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1745
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1746
//// details.                                                     ////
1747
////                                                              ////
1748
//// You should have received a copy of the GNU Lesser General    ////
1749
//// Public License along with this source; if not, download it   ////
1750
//// from http://www.opencores.org/lgpl.shtml                     ////
1751
////                                                              ////
1752
//////////////////////////////////////////////////////////////////////
1753
// LFSR counter
1754 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1755
   parameter length = 4;
1756
   input cke;
1757
   output [length:1] q;
1758
   output reg zq;
1759
   input rst;
1760
   input clk;
1761
   parameter clear_value = 0;
1762
   parameter set_value = 1;
1763
   parameter wrap_value = 8;
1764
   parameter level1_value = 15;
1765
   reg  [length:1] qi;
1766
   reg lfsr_fb;
1767
   wire [length:1] q_next;
1768
   reg [32:1] polynom;
1769
   integer i;
1770
   always @ (qi)
1771
   begin
1772
        case (length)
1773
         2: polynom = 32'b11;                               // 0x3
1774
         3: polynom = 32'b110;                              // 0x6
1775
         4: polynom = 32'b1100;                             // 0xC
1776
         5: polynom = 32'b10100;                            // 0x14
1777
         6: polynom = 32'b110000;                           // 0x30
1778
         7: polynom = 32'b1100000;                          // 0x60
1779
         8: polynom = 32'b10111000;                         // 0xb8
1780
         9: polynom = 32'b100010000;                        // 0x110
1781
        10: polynom = 32'b1001000000;                       // 0x240
1782
        11: polynom = 32'b10100000000;                      // 0x500
1783
        12: polynom = 32'b100000101001;                     // 0x829
1784
        13: polynom = 32'b1000000001100;                    // 0x100C
1785
        14: polynom = 32'b10000000010101;                   // 0x2015
1786
        15: polynom = 32'b110000000000000;                  // 0x6000
1787
        16: polynom = 32'b1101000000001000;                 // 0xD008
1788
        17: polynom = 32'b10010000000000000;                // 0x12000
1789
        18: polynom = 32'b100000010000000000;               // 0x20400
1790
        19: polynom = 32'b1000000000000100011;              // 0x40023
1791 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1792 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1793
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1794
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1795
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1796
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1797
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1798
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1799
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1800
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1801
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1802
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1803
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1804
        default: polynom = 32'b0;
1805
        endcase
1806
        lfsr_fb = qi[length];
1807
        for (i=length-1; i>=1; i=i-1) begin
1808
            if (polynom[i])
1809
                lfsr_fb = lfsr_fb  ~^ qi[i];
1810
        end
1811
    end
1812
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1813
   always @ (posedge clk or posedge rst)
1814
     if (rst)
1815
       qi <= {length{1'b0}};
1816
     else
1817
     if (cke)
1818
       qi <= q_next;
1819
   assign q = qi;
1820
   always @ (posedge clk or posedge rst)
1821
     if (rst)
1822
       zq <= 1'b1;
1823
     else
1824
     if (cke)
1825
       zq <= q_next == {length{1'b0}};
1826
endmodule
1827
//////////////////////////////////////////////////////////////////////
1828
////                                                              ////
1829
////  Versatile counter                                           ////
1830
////                                                              ////
1831
////  Description                                                 ////
1832
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1833
////  counter                                                     ////
1834
////                                                              ////
1835
////  To Do:                                                      ////
1836
////   - add LFSR with more taps                                  ////
1837
////                                                              ////
1838
////  Author(s):                                                  ////
1839
////      - Michael Unneback, unneback@opencores.org              ////
1840
////        ORSoC AB                                              ////
1841
////                                                              ////
1842
//////////////////////////////////////////////////////////////////////
1843
////                                                              ////
1844
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1845
////                                                              ////
1846
//// This source file may be used and distributed without         ////
1847
//// restriction provided that this copyright statement is not    ////
1848
//// removed from the file and that any derivative work contains  ////
1849
//// the original copyright notice and the associated disclaimer. ////
1850
////                                                              ////
1851
//// This source file is free software; you can redistribute it   ////
1852
//// and/or modify it under the terms of the GNU Lesser General   ////
1853
//// Public License as published by the Free Software Foundation; ////
1854
//// either version 2.1 of the License, or (at your option) any   ////
1855
//// later version.                                               ////
1856
////                                                              ////
1857
//// This source is distributed in the hope that it will be       ////
1858
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1859
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1860
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1861
//// details.                                                     ////
1862
////                                                              ////
1863
//// You should have received a copy of the GNU Lesser General    ////
1864
//// Public License along with this source; if not, download it   ////
1865
//// from http://www.opencores.org/lgpl.shtml                     ////
1866
////                                                              ////
1867
//////////////////////////////////////////////////////////////////////
1868
// LFSR counter
1869 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1870 6 unneback
   parameter length = 4;
1871
   input cke;
1872
   input rew;
1873
   output reg level1;
1874
   input rst;
1875
   input clk;
1876
   parameter clear_value = 0;
1877
   parameter set_value = 1;
1878
   parameter wrap_value = 8;
1879
   parameter level1_value = 15;
1880 29 unneback
   wire clear;
1881 30 unneback
   assign clear = 1'b0;
1882 6 unneback
   reg  [length:1] qi;
1883
   reg lfsr_fb, lfsr_fb_rew;
1884
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1885
   reg [32:1] polynom_rew;
1886
   integer j;
1887
   reg [32:1] polynom;
1888
   integer i;
1889
   always @ (qi)
1890
   begin
1891
        case (length)
1892
         2: polynom = 32'b11;                               // 0x3
1893
         3: polynom = 32'b110;                              // 0x6
1894
         4: polynom = 32'b1100;                             // 0xC
1895
         5: polynom = 32'b10100;                            // 0x14
1896
         6: polynom = 32'b110000;                           // 0x30
1897
         7: polynom = 32'b1100000;                          // 0x60
1898
         8: polynom = 32'b10111000;                         // 0xb8
1899
         9: polynom = 32'b100010000;                        // 0x110
1900
        10: polynom = 32'b1001000000;                       // 0x240
1901
        11: polynom = 32'b10100000000;                      // 0x500
1902
        12: polynom = 32'b100000101001;                     // 0x829
1903
        13: polynom = 32'b1000000001100;                    // 0x100C
1904
        14: polynom = 32'b10000000010101;                   // 0x2015
1905
        15: polynom = 32'b110000000000000;                  // 0x6000
1906
        16: polynom = 32'b1101000000001000;                 // 0xD008
1907
        17: polynom = 32'b10010000000000000;                // 0x12000
1908
        18: polynom = 32'b100000010000000000;               // 0x20400
1909
        19: polynom = 32'b1000000000000100011;              // 0x40023
1910 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1911 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1912
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1913
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1914
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1915
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1916
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1917
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1918
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1919
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1920
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1921
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1922
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1923
        default: polynom = 32'b0;
1924
        endcase
1925
        lfsr_fb = qi[length];
1926
        for (i=length-1; i>=1; i=i-1) begin
1927
            if (polynom[i])
1928
                lfsr_fb = lfsr_fb  ~^ qi[i];
1929
        end
1930
    end
1931
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1932
   always @ (qi)
1933
   begin
1934
        case (length)
1935
         2: polynom_rew = 32'b11;
1936
         3: polynom_rew = 32'b110;
1937
         4: polynom_rew = 32'b1100;
1938
         5: polynom_rew = 32'b10100;
1939
         6: polynom_rew = 32'b110000;
1940
         7: polynom_rew = 32'b1100000;
1941
         8: polynom_rew = 32'b10111000;
1942
         9: polynom_rew = 32'b100010000;
1943
        10: polynom_rew = 32'b1001000000;
1944
        11: polynom_rew = 32'b10100000000;
1945
        12: polynom_rew = 32'b100000101001;
1946
        13: polynom_rew = 32'b1000000001100;
1947
        14: polynom_rew = 32'b10000000010101;
1948
        15: polynom_rew = 32'b110000000000000;
1949
        16: polynom_rew = 32'b1101000000001000;
1950
        17: polynom_rew = 32'b10010000000000000;
1951
        18: polynom_rew = 32'b100000010000000000;
1952
        19: polynom_rew = 32'b1000000000000100011;
1953
        20: polynom_rew = 32'b10000010000000000000;
1954
        21: polynom_rew = 32'b101000000000000000000;
1955
        22: polynom_rew = 32'b1100000000000000000000;
1956
        23: polynom_rew = 32'b10000100000000000000000;
1957
        24: polynom_rew = 32'b111000010000000000000000;
1958
        25: polynom_rew = 32'b1001000000000000000000000;
1959
        26: polynom_rew = 32'b10000000000000000000100011;
1960
        27: polynom_rew = 32'b100000000000000000000010011;
1961
        28: polynom_rew = 32'b1100100000000000000000000000;
1962
        29: polynom_rew = 32'b10100000000000000000000000000;
1963
        30: polynom_rew = 32'b100000000000000000000000101001;
1964
        31: polynom_rew = 32'b1001000000000000000000000000000;
1965
        32: polynom_rew = 32'b10000000001000000000000000000011;
1966
        default: polynom_rew = 32'b0;
1967
        endcase
1968
        // rotate left
1969
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1970
        lfsr_fb_rew = qi[length];
1971
        for (i=length-1; i>=1; i=i-1) begin
1972
            if (polynom_rew[i])
1973
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1974
        end
1975
    end
1976
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1977
   assign q_next = rew ? q_next_rew : q_next_fw;
1978
   always @ (posedge clk or posedge rst)
1979
     if (rst)
1980
       qi <= {length{1'b0}};
1981
     else
1982
     if (cke)
1983
       qi <= q_next;
1984
    always @ (posedge clk or posedge rst)
1985
    if (rst)
1986
        level1 <= 1'b0;
1987
    else
1988
    if (cke)
1989 29 unneback
    if (clear)
1990
        level1 <= 1'b0;
1991
    else if (q_next == level1_value)
1992 6 unneback
        level1 <= 1'b1;
1993
    else if (qi == level1_value & rew)
1994
        level1 <= 1'b0;
1995
endmodule
1996
//////////////////////////////////////////////////////////////////////
1997
////                                                              ////
1998
////  Versatile counter                                           ////
1999
////                                                              ////
2000
////  Description                                                 ////
2001
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2002
////  counter                                                     ////
2003
////                                                              ////
2004
////  To Do:                                                      ////
2005
////   - add LFSR with more taps                                  ////
2006
////                                                              ////
2007
////  Author(s):                                                  ////
2008
////      - Michael Unneback, unneback@opencores.org              ////
2009
////        ORSoC AB                                              ////
2010
////                                                              ////
2011
//////////////////////////////////////////////////////////////////////
2012
////                                                              ////
2013
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2014
////                                                              ////
2015
//// This source file may be used and distributed without         ////
2016
//// restriction provided that this copyright statement is not    ////
2017
//// removed from the file and that any derivative work contains  ////
2018
//// the original copyright notice and the associated disclaimer. ////
2019
////                                                              ////
2020
//// This source file is free software; you can redistribute it   ////
2021
//// and/or modify it under the terms of the GNU Lesser General   ////
2022
//// Public License as published by the Free Software Foundation; ////
2023
//// either version 2.1 of the License, or (at your option) any   ////
2024
//// later version.                                               ////
2025
////                                                              ////
2026
//// This source is distributed in the hope that it will be       ////
2027
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2028
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2029
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2030
//// details.                                                     ////
2031
////                                                              ////
2032
//// You should have received a copy of the GNU Lesser General    ////
2033
//// Public License along with this source; if not, download it   ////
2034
//// from http://www.opencores.org/lgpl.shtml                     ////
2035
////                                                              ////
2036
//////////////////////////////////////////////////////////////////////
2037
// GRAY counter
2038 18 unneback
module vl_cnt_gray ( q, rst, clk);
2039 6 unneback
   parameter length = 4;
2040
   output reg [length:1] q;
2041
   input rst;
2042
   input clk;
2043
   parameter clear_value = 0;
2044
   parameter set_value = 1;
2045
   parameter wrap_value = 8;
2046
   parameter level1_value = 15;
2047
   reg  [length:1] qi;
2048
   wire [length:1] q_next;
2049
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2050
   always @ (posedge clk or posedge rst)
2051
     if (rst)
2052
       qi <= {length{1'b0}};
2053
     else
2054
       qi <= q_next;
2055
   always @ (posedge clk or posedge rst)
2056
     if (rst)
2057
       q <= {length{1'b0}};
2058
     else
2059
         q <= (q_next>>1) ^ q_next;
2060
endmodule
2061
//////////////////////////////////////////////////////////////////////
2062
////                                                              ////
2063
////  Versatile counter                                           ////
2064
////                                                              ////
2065
////  Description                                                 ////
2066
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2067
////  counter                                                     ////
2068
////                                                              ////
2069
////  To Do:                                                      ////
2070
////   - add LFSR with more taps                                  ////
2071
////                                                              ////
2072
////  Author(s):                                                  ////
2073
////      - Michael Unneback, unneback@opencores.org              ////
2074
////        ORSoC AB                                              ////
2075
////                                                              ////
2076
//////////////////////////////////////////////////////////////////////
2077
////                                                              ////
2078
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2079
////                                                              ////
2080
//// This source file may be used and distributed without         ////
2081
//// restriction provided that this copyright statement is not    ////
2082
//// removed from the file and that any derivative work contains  ////
2083
//// the original copyright notice and the associated disclaimer. ////
2084
////                                                              ////
2085
//// This source file is free software; you can redistribute it   ////
2086
//// and/or modify it under the terms of the GNU Lesser General   ////
2087
//// Public License as published by the Free Software Foundation; ////
2088
//// either version 2.1 of the License, or (at your option) any   ////
2089
//// later version.                                               ////
2090
////                                                              ////
2091
//// This source is distributed in the hope that it will be       ////
2092
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2093
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2094
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2095
//// details.                                                     ////
2096
////                                                              ////
2097
//// You should have received a copy of the GNU Lesser General    ////
2098
//// Public License along with this source; if not, download it   ////
2099
//// from http://www.opencores.org/lgpl.shtml                     ////
2100
////                                                              ////
2101
//////////////////////////////////////////////////////////////////////
2102
// GRAY counter
2103 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2104 6 unneback
   parameter length = 4;
2105
   input cke;
2106
   output reg [length:1] q;
2107
   input rst;
2108
   input clk;
2109
   parameter clear_value = 0;
2110
   parameter set_value = 1;
2111
   parameter wrap_value = 8;
2112
   parameter level1_value = 15;
2113
   reg  [length:1] qi;
2114
   wire [length:1] q_next;
2115
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2116
   always @ (posedge clk or posedge rst)
2117
     if (rst)
2118
       qi <= {length{1'b0}};
2119
     else
2120
     if (cke)
2121
       qi <= q_next;
2122
   always @ (posedge clk or posedge rst)
2123
     if (rst)
2124
       q <= {length{1'b0}};
2125
     else
2126
       if (cke)
2127
         q <= (q_next>>1) ^ q_next;
2128
endmodule
2129
//////////////////////////////////////////////////////////////////////
2130
////                                                              ////
2131
////  Versatile counter                                           ////
2132
////                                                              ////
2133
////  Description                                                 ////
2134
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2135
////  counter                                                     ////
2136
////                                                              ////
2137
////  To Do:                                                      ////
2138
////   - add LFSR with more taps                                  ////
2139
////                                                              ////
2140
////  Author(s):                                                  ////
2141
////      - Michael Unneback, unneback@opencores.org              ////
2142
////        ORSoC AB                                              ////
2143
////                                                              ////
2144
//////////////////////////////////////////////////////////////////////
2145
////                                                              ////
2146
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2147
////                                                              ////
2148
//// This source file may be used and distributed without         ////
2149
//// restriction provided that this copyright statement is not    ////
2150
//// removed from the file and that any derivative work contains  ////
2151
//// the original copyright notice and the associated disclaimer. ////
2152
////                                                              ////
2153
//// This source file is free software; you can redistribute it   ////
2154
//// and/or modify it under the terms of the GNU Lesser General   ////
2155
//// Public License as published by the Free Software Foundation; ////
2156
//// either version 2.1 of the License, or (at your option) any   ////
2157
//// later version.                                               ////
2158
////                                                              ////
2159
//// This source is distributed in the hope that it will be       ////
2160
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2161
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2162
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2163
//// details.                                                     ////
2164
////                                                              ////
2165
//// You should have received a copy of the GNU Lesser General    ////
2166
//// Public License along with this source; if not, download it   ////
2167
//// from http://www.opencores.org/lgpl.shtml                     ////
2168
////                                                              ////
2169
//////////////////////////////////////////////////////////////////////
2170
// GRAY counter
2171 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2172 6 unneback
   parameter length = 4;
2173
   input cke;
2174
   output reg [length:1] q;
2175
   output [length:1] q_bin;
2176
   input rst;
2177
   input clk;
2178
   parameter clear_value = 0;
2179
   parameter set_value = 1;
2180
   parameter wrap_value = 8;
2181
   parameter level1_value = 15;
2182
   reg  [length:1] qi;
2183
   wire [length:1] q_next;
2184
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2185
   always @ (posedge clk or posedge rst)
2186
     if (rst)
2187
       qi <= {length{1'b0}};
2188
     else
2189
     if (cke)
2190
       qi <= q_next;
2191
   always @ (posedge clk or posedge rst)
2192
     if (rst)
2193
       q <= {length{1'b0}};
2194
     else
2195
       if (cke)
2196
         q <= (q_next>>1) ^ q_next;
2197
   assign q_bin = qi;
2198
endmodule
2199
//////////////////////////////////////////////////////////////////////
2200
////                                                              ////
2201
////  Versatile library, counters                                 ////
2202
////                                                              ////
2203
////  Description                                                 ////
2204
////  counters                                                    ////
2205
////                                                              ////
2206
////                                                              ////
2207
////  To Do:                                                      ////
2208
////   - add more counters                                        ////
2209
////                                                              ////
2210
////  Author(s):                                                  ////
2211
////      - Michael Unneback, unneback@opencores.org              ////
2212
////        ORSoC AB                                              ////
2213
////                                                              ////
2214
//////////////////////////////////////////////////////////////////////
2215
////                                                              ////
2216
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2217
////                                                              ////
2218
//// This source file may be used and distributed without         ////
2219
//// restriction provided that this copyright statement is not    ////
2220
//// removed from the file and that any derivative work contains  ////
2221
//// the original copyright notice and the associated disclaimer. ////
2222
////                                                              ////
2223
//// This source file is free software; you can redistribute it   ////
2224
//// and/or modify it under the terms of the GNU Lesser General   ////
2225
//// Public License as published by the Free Software Foundation; ////
2226
//// either version 2.1 of the License, or (at your option) any   ////
2227
//// later version.                                               ////
2228
////                                                              ////
2229
//// This source is distributed in the hope that it will be       ////
2230
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2231
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2232
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2233
//// details.                                                     ////
2234
////                                                              ////
2235
//// You should have received a copy of the GNU Lesser General    ////
2236
//// Public License along with this source; if not, download it   ////
2237
//// from http://www.opencores.org/lgpl.shtml                     ////
2238
////                                                              ////
2239
//////////////////////////////////////////////////////////////////////
2240 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2241 6 unneback
   parameter length = 4;
2242
   output reg [0:length-1] q;
2243
   input rst;
2244
   input clk;
2245
    always @ (posedge clk or posedge rst)
2246
    if (rst)
2247
        q <= {1'b1,{length-1{1'b0}}};
2248
    else
2249
        q <= {q[length-1],q[0:length-2]};
2250
endmodule
2251 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2252 6 unneback
   parameter length = 4;
2253
   input cke;
2254
   output reg [0:length-1] q;
2255
   input rst;
2256
   input clk;
2257
    always @ (posedge clk or posedge rst)
2258
    if (rst)
2259
        q <= {1'b1,{length-1{1'b0}}};
2260
    else
2261
        if (cke)
2262
            q <= {q[length-1],q[0:length-2]};
2263
endmodule
2264 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2265 6 unneback
   parameter length = 4;
2266
   input cke, clear;
2267
   output reg [0:length-1] q;
2268
   input rst;
2269
   input clk;
2270
    always @ (posedge clk or posedge rst)
2271
    if (rst)
2272
        q <= {1'b1,{length-1{1'b0}}};
2273
    else
2274
        if (cke)
2275
            if (clear)
2276
                q <= {1'b1,{length-1{1'b0}}};
2277
            else
2278
                q <= q >> 1;
2279
endmodule
2280 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2281 6 unneback
   parameter length = 4;
2282
   input cke, clear;
2283
   output reg [0:length-1] q;
2284
   input rst;
2285
   input clk;
2286
    always @ (posedge clk or posedge rst)
2287
    if (rst)
2288
        q <= {1'b1,{length-1{1'b0}}};
2289
    else
2290
        if (cke)
2291
            if (clear)
2292
                q <= {1'b1,{length-1{1'b0}}};
2293
            else
2294
            q <= {q[length-1],q[0:length-2]};
2295
endmodule
2296
//////////////////////////////////////////////////////////////////////
2297
////                                                              ////
2298
////  Versatile library, memories                                 ////
2299
////                                                              ////
2300
////  Description                                                 ////
2301
////  memories                                                    ////
2302
////                                                              ////
2303
////                                                              ////
2304
////  To Do:                                                      ////
2305
////   - add more memory types                                    ////
2306
////                                                              ////
2307
////  Author(s):                                                  ////
2308
////      - Michael Unneback, unneback@opencores.org              ////
2309
////        ORSoC AB                                              ////
2310
////                                                              ////
2311
//////////////////////////////////////////////////////////////////////
2312
////                                                              ////
2313
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2314
////                                                              ////
2315
//// This source file may be used and distributed without         ////
2316
//// restriction provided that this copyright statement is not    ////
2317
//// removed from the file and that any derivative work contains  ////
2318
//// the original copyright notice and the associated disclaimer. ////
2319
////                                                              ////
2320
//// This source file is free software; you can redistribute it   ////
2321
//// and/or modify it under the terms of the GNU Lesser General   ////
2322
//// Public License as published by the Free Software Foundation; ////
2323
//// either version 2.1 of the License, or (at your option) any   ////
2324
//// later version.                                               ////
2325
////                                                              ////
2326
//// This source is distributed in the hope that it will be       ////
2327
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2328
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2329
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2330
//// details.                                                     ////
2331
////                                                              ////
2332
//// You should have received a copy of the GNU Lesser General    ////
2333
//// Public License along with this source; if not, download it   ////
2334
//// from http://www.opencores.org/lgpl.shtml                     ////
2335
////                                                              ////
2336
//////////////////////////////////////////////////////////////////////
2337
/// ROM
2338 7 unneback
module vl_rom_init ( adr, q, clk);
2339
   parameter data_width = 32;
2340
   parameter addr_width = 8;
2341
   input [(addr_width-1):0]       adr;
2342
   output reg [(data_width-1):0] q;
2343
   input                         clk;
2344
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2345
   parameter memory_file = "vl_rom.vmem";
2346
   initial
2347
     begin
2348
        $readmemh(memory_file, rom);
2349
     end
2350
   always @ (posedge clk)
2351
     q <= rom[adr];
2352
endmodule
2353 14 unneback
/*
2354 7 unneback
module vl_rom ( adr, q, clk);
2355 6 unneback
parameter data_width = 32;
2356
parameter addr_width = 4;
2357
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2358
    {32'h18000000},
2359
    {32'hA8200000},
2360
    {32'hA8200000},
2361
    {32'hA8200000},
2362
    {32'h44003000},
2363
    {32'h15000000},
2364
    {32'h15000000},
2365
    {32'h15000000},
2366
    {32'h15000000},
2367
    {32'h15000000},
2368
    {32'h15000000},
2369
    {32'h15000000},
2370
    {32'h15000000},
2371
    {32'h15000000},
2372
    {32'h15000000},
2373
    {32'h15000000}};
2374 7 unneback
input [addr_width-1:0] adr;
2375 6 unneback
output reg [data_width-1:0] q;
2376
input clk;
2377
always @ (posedge clk)
2378 7 unneback
    q <= data[adr];
2379 6 unneback
endmodule
2380 14 unneback
*/
2381 6 unneback
// Single port RAM
2382
module vl_ram ( d, adr, we, q, clk);
2383
   parameter data_width = 32;
2384
   parameter addr_width = 8;
2385
   input [(data_width-1):0]      d;
2386
   input [(addr_width-1):0]       adr;
2387
   input                         we;
2388 7 unneback
   output reg [(data_width-1):0] q;
2389 6 unneback
   input                         clk;
2390
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2391 7 unneback
   parameter init = 0;
2392
   parameter memory_file = "vl_ram.vmem";
2393
   generate if (init) begin : init_mem
2394
   initial
2395
     begin
2396
        $readmemh(memory_file, ram);
2397
     end
2398
   end
2399
   endgenerate
2400 6 unneback
   always @ (posedge clk)
2401
   begin
2402
   if (we)
2403
     ram[adr] <= d;
2404
   q <= ram[adr];
2405
   end
2406
endmodule
2407 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2408
   parameter data_width = 32;
2409
   parameter addr_width = 8;
2410
   input [(data_width-1):0]      d;
2411
   input [(addr_width-1):0]       adr;
2412
   input [(addr_width/4)-1:0]    be;
2413
   input                         we;
2414
   output reg [(data_width-1):0] q;
2415
   input                         clk;
2416
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2417
   parameter init = 0;
2418
   parameter memory_file = "vl_ram.vmem";
2419
   generate if (init) begin : init_mem
2420
   initial
2421
     begin
2422
        $readmemh(memory_file, ram);
2423
     end
2424
   end
2425
   endgenerate
2426
   genvar i;
2427
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2428
      always @ (posedge clk)
2429
      if (we & be[i])
2430
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2431
   end
2432
   endgenerate
2433
   always @ (posedge clk)
2434
      q <= ram[adr];
2435
endmodule
2436 6 unneback
// Dual port RAM
2437
// ACTEL FPGA should not use logic to handle rw collision
2438 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2439 6 unneback
   parameter data_width = 32;
2440
   parameter addr_width = 8;
2441
   input [(data_width-1):0]      d_a;
2442
   input [(addr_width-1):0]       adr_a;
2443
   input [(addr_width-1):0]       adr_b;
2444
   input                         we_a;
2445
   output [(data_width-1):0]      q_b;
2446
   input                         clk_a, clk_b;
2447
   reg [(addr_width-1):0]         adr_b_reg;
2448
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2449 7 unneback
   parameter init = 0;
2450
   parameter memory_file = "vl_ram.vmem";
2451
   generate if (init) begin : init_mem
2452
   initial
2453
     begin
2454
        $readmemh(memory_file, ram);
2455
     end
2456
   end
2457
   endgenerate
2458 6 unneback
   always @ (posedge clk_a)
2459
   if (we_a)
2460
     ram[adr_a] <= d_a;
2461
   always @ (posedge clk_b)
2462
   adr_b_reg <= adr_b;
2463
   assign q_b = ram[adr_b_reg];
2464
endmodule
2465 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2466 6 unneback
   parameter data_width = 32;
2467
   parameter addr_width = 8;
2468
   input [(data_width-1):0]      d_a;
2469
   input [(addr_width-1):0]       adr_a;
2470
   input [(addr_width-1):0]       adr_b;
2471
   input                         we_a;
2472
   output [(data_width-1):0]      q_b;
2473
   output reg [(data_width-1):0] q_a;
2474
   input                         clk_a, clk_b;
2475
   reg [(data_width-1):0]         q_b;
2476
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2477 7 unneback
   parameter init = 0;
2478
   parameter memory_file = "vl_ram.vmem";
2479
   generate if (init) begin : init_mem
2480
   initial
2481
     begin
2482
        $readmemh(memory_file, ram);
2483
     end
2484
   end
2485
   endgenerate
2486 6 unneback
   always @ (posedge clk_a)
2487
     begin
2488
        q_a <= ram[adr_a];
2489
        if (we_a)
2490
             ram[adr_a] <= d_a;
2491
     end
2492
   always @ (posedge clk_b)
2493
          q_b <= ram[adr_b];
2494
endmodule
2495 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2496 6 unneback
   parameter data_width = 32;
2497
   parameter addr_width = 8;
2498
   input [(data_width-1):0]      d_a;
2499
   input [(addr_width-1):0]       adr_a;
2500
   input [(addr_width-1):0]       adr_b;
2501
   input                         we_a;
2502
   output [(data_width-1):0]      q_b;
2503
   input [(data_width-1):0]       d_b;
2504
   output reg [(data_width-1):0] q_a;
2505
   input                         we_b;
2506
   input                         clk_a, clk_b;
2507
   reg [(data_width-1):0]         q_b;
2508
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2509 7 unneback
   parameter init = 0;
2510
   parameter memory_file = "vl_ram.vmem";
2511
   generate if (init) begin : init_mem
2512
   initial
2513
     begin
2514
        $readmemh(memory_file, ram);
2515
     end
2516
   end
2517
   endgenerate
2518 6 unneback
   always @ (posedge clk_a)
2519
     begin
2520
        q_a <= ram[adr_a];
2521
        if (we_a)
2522
             ram[adr_a] <= d_a;
2523
     end
2524
   always @ (posedge clk_b)
2525
     begin
2526
        q_b <= ram[adr_b];
2527
        if (we_b)
2528
          ram[adr_b] <= d_b;
2529
     end
2530
endmodule
2531
// Content addresable memory, CAM
2532
// FIFO
2533 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2534
    d, wr, fifo_full,
2535
    q, rd, fifo_empty,
2536
    fill_level,
2537
    clk, rst
2538
    );
2539
parameter data_width = 18;
2540
parameter addr_width = 4;
2541
// write side
2542
input  [data_width-1:0] d;
2543
input                   wr;
2544
output                  fifo_full;
2545
// read side
2546
output [data_width-1:0] q;
2547
input                   rd;
2548
output                  fifo_empty;
2549
// common
2550
output [addr_width:0]   fill_level;
2551
input rst, clk;
2552
wire [addr_width:1] wadr, radr;
2553
vl_cnt_bin_ce
2554
    # ( .length(addr_width))
2555
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2556
vl_cnt_bin_ce
2557
    # (.length(addr_width))
2558
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2559
vl_dpram_1r1w
2560
    # (.data_width(data_width), .addr_width(addr_width))
2561
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2562 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
2563 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2564 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2565
endmodule
2566 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2567
// RAM is supposed to be larger than the two FIFOs
2568
// LFSR counters used adr pointers
2569
module vl_fifo_2r2w_sync_simplex (
2570
    // a side
2571
    a_d, a_wr, a_fifo_full,
2572
    a_q, a_rd, a_fifo_empty,
2573
    a_fill_level,
2574
    // b side
2575
    b_d, b_wr, b_fifo_full,
2576
    b_q, b_rd, b_fifo_empty,
2577
    b_fill_level,
2578
    // common
2579
    clk, rst
2580
    );
2581
parameter data_width = 8;
2582
parameter addr_width = 5;
2583
parameter fifo_full_level = (1<<addr_width)-1;
2584
// a side
2585
input  [data_width-1:0] a_d;
2586
input                   a_wr;
2587
output                  a_fifo_full;
2588
output [data_width-1:0] a_q;
2589
input                   a_rd;
2590
output                  a_fifo_empty;
2591
output [addr_width-1:0] a_fill_level;
2592
// b side
2593
input  [data_width-1:0] b_d;
2594
input                   b_wr;
2595
output                  b_fifo_full;
2596
output [data_width-1:0] b_q;
2597
input                   b_rd;
2598
output                  b_fifo_empty;
2599
output [addr_width-1:0] b_fill_level;
2600
input                   clk;
2601
input                   rst;
2602
// adr_gen
2603
wire [