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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 42

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1 6 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 33 unneback
module vl_gbuf ( i, o);
47
input i;
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output o;
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assign o = i;
50
endmodule
51 6 unneback
 // ALTERA
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 //ACTEL
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// sync reset
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// input active lo async reset, normally from external reset generator and/or switch
55 6 unneback
// output active high global reset sync with two DFFs 
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`timescale 1 ns/100 ps
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module vl_sync_rst ( rst_n_i, rst_o, clk);
58
input rst_n_i, clk;
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output rst_o;
60 18 unneback
reg [1:0] tmp;
61 6 unneback
always @ (posedge clk or negedge rst_n_i)
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if (!rst_n_i)
63 17 unneback
        tmp <= 2'b11;
64 6 unneback
else
65 33 unneback
        tmp <= {1'b0,tmp[1]};
66 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
67 6 unneback
endmodule
68
// vl_pll
69 32 unneback
///////////////////////////////////////////////////////////////////////////////
70
`timescale 1 ps/1 ps
71
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
72
parameter index = 0;
73
parameter number_of_clk = 1;
74
parameter period_time_0 = 20000;
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parameter period_time_1 = 20000;
76
parameter period_time_2 = 20000;
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parameter period_time_3 = 20000;
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parameter period_time_4 = 20000;
79
parameter lock_delay = 2000000;
80
input clk_i, rst_n_i;
81
output lock;
82
output reg [0:number_of_clk-1] clk_o;
83
output [0:number_of_clk-1] rst_o;
84 33 unneback
`ifdef SIM_PLL
85 32 unneback
always
86
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
87
generate if (number_of_clk > 1)
88
always
89
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
90
endgenerate
91
generate if (number_of_clk > 2)
92
always
93
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
94
endgenerate
95 33 unneback
generate if (number_of_clk > 3)
96 32 unneback
always
97
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
98
endgenerate
99 33 unneback
generate if (number_of_clk > 4)
100 32 unneback
always
101
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
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endgenerate
103
genvar i;
104
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
106
end
107
endgenerate
108 33 unneback
//assign #lock_delay lock = rst_n_i;
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assign lock = rst_n_i;
110 32 unneback
endmodule
111 33 unneback
`else
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`ifdef VL_PLL0
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`ifdef VL_PLL0_CLK1
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
115
`endif
116
`ifdef VL_PLL0_CLK2
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL0_CLK3
120
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL0_CLK4
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL0_CLK5
126
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
127
`endif
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`endif
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`ifdef VL_PLL1
130
`ifdef VL_PLL1_CLK1
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL1_CLK2
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL1_CLK3
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL1_CLK4
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL1_CLK5
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL2
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`ifdef VL_PLL2_CLK1
148
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL2_CLK2
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL2_CLK3
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL2_CLK4
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL2_CLK5
160
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL3
164
`ifdef VL_PLL3_CLK1
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    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
166
`endif
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`ifdef VL_PLL3_CLK2
168
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
169
`endif
170
`ifdef VL_PLL3_CLK3
171
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
172
`endif
173
`ifdef VL_PLL3_CLK4
174
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
175
`endif
176
`ifdef VL_PLL3_CLK5
177
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
178
`endif
179
`endif
180 32 unneback
genvar i;
181
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
182 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
183 32 unneback
end
184
endgenerate
185
endmodule
186 33 unneback
`endif
187 32 unneback
///////////////////////////////////////////////////////////////////////////////
188 6 unneback
 //altera
189
 //actel
190
//////////////////////////////////////////////////////////////////////
191
////                                                              ////
192
////  Versatile library, registers                                ////
193
////                                                              ////
194
////  Description                                                 ////
195
////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
198
////  To Do:                                                      ////
199
////   - add more different registers                             ////
200
////                                                              ////
201
////  Author(s):                                                  ////
202
////      - Michael Unneback, unneback@opencores.org              ////
203
////        ORSoC AB                                              ////
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////                                                              ////
205
//////////////////////////////////////////////////////////////////////
206
////                                                              ////
207
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
208
////                                                              ////
209
//// This source file may be used and distributed without         ////
210
//// restriction provided that this copyright statement is not    ////
211
//// removed from the file and that any derivative work contains  ////
212
//// the original copyright notice and the associated disclaimer. ////
213
////                                                              ////
214
//// This source file is free software; you can redistribute it   ////
215
//// and/or modify it under the terms of the GNU Lesser General   ////
216
//// Public License as published by the Free Software Foundation; ////
217
//// either version 2.1 of the License, or (at your option) any   ////
218
//// later version.                                               ////
219
////                                                              ////
220
//// This source is distributed in the hope that it will be       ////
221
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
222
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
223
//// PURPOSE.  See the GNU Lesser General Public License for more ////
224
//// details.                                                     ////
225
////                                                              ////
226
//// You should have received a copy of the GNU Lesser General    ////
227
//// Public License along with this source; if not, download it   ////
228
//// from http://www.opencores.org/lgpl.shtml                     ////
229
////                                                              ////
230
//////////////////////////////////////////////////////////////////////
231 18 unneback
module vl_dff ( d, q, clk, rst);
232 6 unneback
        parameter width = 1;
233
        parameter reset_value = 0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output reg [width-1:0] q;
237
        always @ (posedge clk or posedge rst)
238
        if (rst)
239
                q <= reset_value;
240
        else
241
                q <= d;
242
endmodule
243 18 unneback
module vl_dff_array ( d, q, clk, rst);
244 6 unneback
        parameter width = 1;
245
        parameter depth = 2;
246
        parameter reset_value = 1'b0;
247
        input [width-1:0] d;
248
        input clk, rst;
249
        output [width-1:0] q;
250
        reg  [0:depth-1] q_tmp [width-1:0];
251
        integer i;
252
        always @ (posedge clk or posedge rst)
253
        if (rst) begin
254
            for (i=0;i<depth;i=i+1)
255
                q_tmp[i] <= {width{reset_value}};
256
        end else begin
257
            q_tmp[0] <= d;
258
            for (i=1;i<depth;i=i+1)
259
                q_tmp[i] <= q_tmp[i-1];
260
        end
261
    assign q = q_tmp[depth-1];
262
endmodule
263 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
264 6 unneback
        parameter width = 1;
265
        parameter reset_value = 0;
266
        input [width-1:0] d;
267
        input ce, clk, rst;
268
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
                q <= reset_value;
272
        else
273
                if (ce)
274
                        q <= d;
275
endmodule
276 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
277 8 unneback
        parameter width = 1;
278
        parameter reset_value = 0;
279
        input [width-1:0] d;
280 10 unneback
        input ce, clear, clk, rst;
281 8 unneback
        output reg [width-1:0] q;
282
        always @ (posedge clk or posedge rst)
283
        if (rst)
284
            q <= reset_value;
285
        else
286
            if (ce)
287
                if (clear)
288
                    q <= {width{1'b0}};
289
                else
290
                    q <= d;
291
endmodule
292 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
293
        parameter width = 1;
294
        parameter reset_value = 0;
295
        input [width-1:0] d;
296
        input ce, set, clk, rst;
297
        output reg [width-1:0] q;
298
        always @ (posedge clk or posedge rst)
299
        if (rst)
300
            q <= reset_value;
301
        else
302
            if (ce)
303
                if (set)
304
                    q <= {width{1'b1}};
305
                else
306
                    q <= d;
307
endmodule
308 29 unneback
module vl_spr ( sp, r, q, clk, rst);
309
        parameter width = 1;
310
        parameter reset_value = 0;
311
        input sp, r;
312
        output reg q;
313
        input clk, rst;
314
        always @ (posedge clk or posedge rst)
315
        if (rst)
316
            q <= reset_value;
317
        else
318
            if (sp)
319
                q <= 1'b1;
320
            else if (r)
321
                q <= 1'b0;
322
endmodule
323
module vl_srp ( s, rp, q, clk, rst);
324
        parameter width = 1;
325
        parameter reset_value = 0;
326
        input s, rp;
327
        output reg q;
328
        input clk, rst;
329
        always @ (posedge clk or posedge rst)
330
        if (rst)
331
            q <= reset_value;
332
        else
333
            if (rp)
334
                q <= 1'b0;
335
            else if (s)
336
                q <= 1'b1;
337
endmodule
338 6 unneback
// megafunction wizard: %LPM_FF%
339
// GENERATION: STANDARD
340
// VERSION: WM1.0
341
// MODULE: lpm_ff 
342
// ============================================================
343
// File Name: dff_sr.v
344
// Megafunction Name(s):
345
//                      lpm_ff
346
//
347
// Simulation Library Files(s):
348
//                      lpm
349
// ============================================================
350
// ************************************************************
351
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
352
//
353
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
354
// ************************************************************
355
//Copyright (C) 1991-2010 Altera Corporation
356
//Your use of Altera Corporation's design tools, logic functions 
357
//and other software and tools, and its AMPP partner logic 
358
//functions, and any output files from any of the foregoing 
359
//(including device programming or simulation files), and any 
360
//associated documentation or information are expressly subject 
361
//to the terms and conditions of the Altera Program License 
362
//Subscription Agreement, Altera MegaCore Function License 
363
//Agreement, or other applicable license agreement, including, 
364
//without limitation, that your use is for the sole purpose of 
365
//programming logic devices manufactured by Altera and sold by 
366
//Altera or its authorized distributors.  Please refer to the 
367
//applicable agreement for further details.
368
// synopsys translate_off
369
`timescale 1 ps / 1 ps
370
// synopsys translate_on
371 18 unneback
module vl_dff_sr (
372 6 unneback
        aclr,
373
        aset,
374
        clock,
375
        data,
376
        q);
377
        input     aclr;
378
        input     aset;
379
        input     clock;
380
        input     data;
381
        output    q;
382
        wire [0:0] sub_wire0;
383
        wire [0:0] sub_wire1 = sub_wire0[0:0];
384
        wire  q = sub_wire1;
385
        wire  sub_wire2 = data;
386
        wire  sub_wire3 = sub_wire2;
387
        lpm_ff  lpm_ff_component (
388
                                .aclr (aclr),
389
                                .clock (clock),
390
                                .data (sub_wire3),
391
                                .aset (aset),
392
                                .q (sub_wire0)
393
                                // synopsys translate_off
394
                                ,
395
                                .aload (),
396
                                .enable (),
397
                                .sclr (),
398
                                .sload (),
399
                                .sset ()
400
                                // synopsys translate_on
401
                                );
402
        defparam
403
                lpm_ff_component.lpm_fftype = "DFF",
404
                lpm_ff_component.lpm_type = "LPM_FF",
405
                lpm_ff_component.lpm_width = 1;
406
endmodule
407
// ============================================================
408
// CNX file retrieval info
409
// ============================================================
410
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
411
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
412
// Retrieval info: PRIVATE: ASET NUMERIC "1"
413
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
414
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
415
// Retrieval info: PRIVATE: DFF NUMERIC "1"
416
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
417
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
418
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET NUMERIC "0"
420
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
421
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
422
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
423
// Retrieval info: PRIVATE: nBit NUMERIC "1"
424
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
425
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
426
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
427
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
428
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
429
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
430
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
431
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
432
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
433
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
434
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
435
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
436
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
437
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
444
// Retrieval info: LIB_FILE: lpm
445
// LATCH
446
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
447 18 unneback
module vl_latch ( d, le, q, clk);
448 6 unneback
input d, le;
449
output q;
450
input clk;
451
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
452
endmodule
453 18 unneback
module vl_shreg ( d, q, clk, rst);
454 17 unneback
parameter depth = 10;
455
input d;
456
output q;
457
input clk, rst;
458
reg [1:depth] dffs;
459
always @ (posedge clk or posedge rst)
460
if (rst)
461
    dffs <= {depth{1'b0}};
462
else
463
    dffs <= {d,dffs[1:depth-1]};
464
assign q = dffs[depth];
465
endmodule
466 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
467 17 unneback
parameter depth = 10;
468
input d, ce;
469
output q;
470
input clk, rst;
471
reg [1:depth] dffs;
472
always @ (posedge clk or posedge rst)
473
if (rst)
474
    dffs <= {depth{1'b0}};
475
else
476
    if (ce)
477
        dffs <= {d,dffs[1:depth-1]};
478
assign q = dffs[depth];
479
endmodule
480 18 unneback
module vl_delay ( d, q, clk, rst);
481 15 unneback
parameter depth = 10;
482
input d;
483
output q;
484
input clk, rst;
485
reg [1:depth] dffs;
486
always @ (posedge clk or posedge rst)
487
if (rst)
488
    dffs <= {depth{1'b0}};
489
else
490
    dffs <= {d,dffs[1:depth-1]};
491
assign q = dffs[depth];
492
endmodule
493 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
494 17 unneback
parameter depth = 10;
495
input d;
496
output q, emptyflag;
497
input clk, rst;
498
reg [1:depth] dffs;
499
always @ (posedge clk or posedge rst)
500
if (rst)
501
    dffs <= {depth{1'b0}};
502
else
503
    dffs <= {d,dffs[1:depth-1]};
504
assign q = dffs[depth];
505
assign emptyflag = !(|dffs);
506
endmodule
507 6 unneback
//////////////////////////////////////////////////////////////////////
508
////                                                              ////
509 18 unneback
////  Logic functions                                             ////
510
////                                                              ////
511
////  Description                                                 ////
512
////  Logic functions such as multiplexers                        ////
513
////                                                              ////
514
////                                                              ////
515
////  To Do:                                                      ////
516
////   -                                                          ////
517
////                                                              ////
518
////  Author(s):                                                  ////
519
////      - Michael Unneback, unneback@opencores.org              ////
520
////        ORSoC AB                                              ////
521
////                                                              ////
522
//////////////////////////////////////////////////////////////////////
523
////                                                              ////
524
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
525
////                                                              ////
526
//// This source file may be used and distributed without         ////
527
//// restriction provided that this copyright statement is not    ////
528
//// removed from the file and that any derivative work contains  ////
529
//// the original copyright notice and the associated disclaimer. ////
530
////                                                              ////
531
//// This source file is free software; you can redistribute it   ////
532
//// and/or modify it under the terms of the GNU Lesser General   ////
533
//// Public License as published by the Free Software Foundation; ////
534
//// either version 2.1 of the License, or (at your option) any   ////
535
//// later version.                                               ////
536
////                                                              ////
537
//// This source is distributed in the hope that it will be       ////
538
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
539
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
540
//// PURPOSE.  See the GNU Lesser General Public License for more ////
541
//// details.                                                     ////
542
////                                                              ////
543
//// You should have received a copy of the GNU Lesser General    ////
544
//// Public License along with this source; if not, download it   ////
545
//// from http://www.opencores.org/lgpl.shtml                     ////
546
////                                                              ////
547
//////////////////////////////////////////////////////////////////////
548 36 unneback
module vl_mux_andor ( a, sel, dout);
549
parameter width = 32;
550
parameter nr_of_ports = 4;
551
input [nr_of_ports*width-1:0] a;
552
input [nr_of_ports-1:0] sel;
553
output reg [width-1:0] dout;
554 38 unneback
integer i,j;
555 36 unneback
always @ (a, sel)
556
begin
557
    dout = a[width-1:0] & {width{sel[0]}};
558 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
559
        for (j=0;j<width;j=j+1)
560
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
561 36 unneback
end
562
endmodule
563 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
564
parameter width = 32;
565 35 unneback
localparam nr_of_ports = 2;
566 34 unneback
input [width-1:0] a1, a0;
567
input [nr_of_ports-1:0] sel;
568
output [width-1:0] dout;
569 36 unneback
vl_mux_andor
570 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
571 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
572 34 unneback
endmodule
573
module vl_mux3_andor ( a2, a1, a0, sel, dout);
574
parameter width = 32;
575 35 unneback
localparam nr_of_ports = 3;
576 34 unneback
input [width-1:0] a2, a1, a0;
577
input [nr_of_ports-1:0] sel;
578
output [width-1:0] dout;
579 36 unneback
vl_mux_andor
580 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
581 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
582 34 unneback
endmodule
583 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
584
parameter width = 32;
585 35 unneback
localparam nr_of_ports = 4;
586 18 unneback
input [width-1:0] a3, a2, a1, a0;
587
input [nr_of_ports-1:0] sel;
588 22 unneback
output [width-1:0] dout;
589 36 unneback
vl_mux_andor
590 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
591 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
592 18 unneback
endmodule
593
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
594
parameter width = 32;
595 35 unneback
localparam nr_of_ports = 5;
596 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
597
input [nr_of_ports-1:0] sel;
598 22 unneback
output [width-1:0] dout;
599 36 unneback
vl_mux_andor
600 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
601 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
602 18 unneback
endmodule
603
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
604
parameter width = 32;
605 35 unneback
localparam nr_of_ports = 6;
606 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
607
input [nr_of_ports-1:0] sel;
608 22 unneback
output [width-1:0] dout;
609 36 unneback
vl_mux_andor
610 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
611 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
612 18 unneback
endmodule
613
//////////////////////////////////////////////////////////////////////
614
////                                                              ////
615 6 unneback
////  Versatile counter                                           ////
616
////                                                              ////
617
////  Description                                                 ////
618
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
619
////  counter                                                     ////
620
////                                                              ////
621
////  To Do:                                                      ////
622
////   - add LFSR with more taps                                  ////
623
////                                                              ////
624
////  Author(s):                                                  ////
625
////      - Michael Unneback, unneback@opencores.org              ////
626
////        ORSoC AB                                              ////
627
////                                                              ////
628
//////////////////////////////////////////////////////////////////////
629
////                                                              ////
630
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
631
////                                                              ////
632
//// This source file may be used and distributed without         ////
633
//// restriction provided that this copyright statement is not    ////
634
//// removed from the file and that any derivative work contains  ////
635
//// the original copyright notice and the associated disclaimer. ////
636
////                                                              ////
637
//// This source file is free software; you can redistribute it   ////
638
//// and/or modify it under the terms of the GNU Lesser General   ////
639
//// Public License as published by the Free Software Foundation; ////
640
//// either version 2.1 of the License, or (at your option) any   ////
641
//// later version.                                               ////
642
////                                                              ////
643
//// This source is distributed in the hope that it will be       ////
644
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
645
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
646
//// PURPOSE.  See the GNU Lesser General Public License for more ////
647
//// details.                                                     ////
648
////                                                              ////
649
//// You should have received a copy of the GNU Lesser General    ////
650
//// Public License along with this source; if not, download it   ////
651
//// from http://www.opencores.org/lgpl.shtml                     ////
652
////                                                              ////
653
//////////////////////////////////////////////////////////////////////
654
// binary counter
655 40 unneback
module vl_cnt_bin_ce (
656
 cke, q, rst, clk);
657 22 unneback
   parameter length = 4;
658 6 unneback
   input cke;
659
   output [length:1] q;
660
   input rst;
661
   input clk;
662
   parameter clear_value = 0;
663
   parameter set_value = 1;
664
   parameter wrap_value = 0;
665
   parameter level1_value = 15;
666
   reg  [length:1] qi;
667
   wire [length:1] q_next;
668
   assign q_next = qi + {{length-1{1'b0}},1'b1};
669
   always @ (posedge clk or posedge rst)
670
     if (rst)
671
       qi <= {length{1'b0}};
672
     else
673
     if (cke)
674
       qi <= q_next;
675
   assign q = qi;
676
endmodule
677
//////////////////////////////////////////////////////////////////////
678
////                                                              ////
679
////  Versatile counter                                           ////
680
////                                                              ////
681
////  Description                                                 ////
682
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
683
////  counter                                                     ////
684
////                                                              ////
685
////  To Do:                                                      ////
686
////   - add LFSR with more taps                                  ////
687
////                                                              ////
688
////  Author(s):                                                  ////
689
////      - Michael Unneback, unneback@opencores.org              ////
690
////        ORSoC AB                                              ////
691
////                                                              ////
692
//////////////////////////////////////////////////////////////////////
693
////                                                              ////
694
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
695
////                                                              ////
696
//// This source file may be used and distributed without         ////
697
//// restriction provided that this copyright statement is not    ////
698
//// removed from the file and that any derivative work contains  ////
699
//// the original copyright notice and the associated disclaimer. ////
700
////                                                              ////
701
//// This source file is free software; you can redistribute it   ////
702
//// and/or modify it under the terms of the GNU Lesser General   ////
703
//// Public License as published by the Free Software Foundation; ////
704
//// either version 2.1 of the License, or (at your option) any   ////
705
//// later version.                                               ////
706
////                                                              ////
707
//// This source is distributed in the hope that it will be       ////
708
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
709
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
710
//// PURPOSE.  See the GNU Lesser General Public License for more ////
711
//// details.                                                     ////
712
////                                                              ////
713
//// You should have received a copy of the GNU Lesser General    ////
714
//// Public License along with this source; if not, download it   ////
715
//// from http://www.opencores.org/lgpl.shtml                     ////
716
////                                                              ////
717
//////////////////////////////////////////////////////////////////////
718
// binary counter
719 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
720
 cke, rew, zq, level1, rst, clk);
721 6 unneback
   parameter length = 4;
722
   input cke;
723
   input rew;
724 25 unneback
   output reg zq;
725
   output reg level1;
726
   input rst;
727
   input clk;
728
   parameter clear_value = 0;
729
   parameter set_value = 1;
730
   parameter wrap_value = 1;
731
   parameter level1_value = 15;
732 29 unneback
   wire clear;
733 30 unneback
   assign clear = 1'b0;
734 25 unneback
   reg  [length:1] qi;
735
   wire  [length:1] q_next, q_next_fw, q_next_rew;
736
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
737
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
738
   assign q_next = rew ? q_next_rew : q_next_fw;
739
   always @ (posedge clk or posedge rst)
740
     if (rst)
741
       qi <= {length{1'b0}};
742
     else
743
     if (cke)
744
       qi <= q_next;
745
   always @ (posedge clk or posedge rst)
746
     if (rst)
747
       zq <= 1'b1;
748
     else
749
     if (cke)
750
       zq <= q_next == {length{1'b0}};
751
    always @ (posedge clk or posedge rst)
752
    if (rst)
753
        level1 <= 1'b0;
754
    else
755
    if (cke)
756 29 unneback
    if (clear)
757
        level1 <= 1'b0;
758
    else if (q_next == level1_value)
759 25 unneback
        level1 <= 1'b1;
760
    else if (qi == level1_value & rew)
761
        level1 <= 1'b0;
762
endmodule
763
//////////////////////////////////////////////////////////////////////
764
////                                                              ////
765
////  Versatile counter                                           ////
766
////                                                              ////
767
////  Description                                                 ////
768
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
769
////  counter                                                     ////
770
////                                                              ////
771
////  To Do:                                                      ////
772
////   - add LFSR with more taps                                  ////
773
////                                                              ////
774
////  Author(s):                                                  ////
775
////      - Michael Unneback, unneback@opencores.org              ////
776
////        ORSoC AB                                              ////
777
////                                                              ////
778
//////////////////////////////////////////////////////////////////////
779
////                                                              ////
780
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
781
////                                                              ////
782
//// This source file may be used and distributed without         ////
783
//// restriction provided that this copyright statement is not    ////
784
//// removed from the file and that any derivative work contains  ////
785
//// the original copyright notice and the associated disclaimer. ////
786
////                                                              ////
787
//// This source file is free software; you can redistribute it   ////
788
//// and/or modify it under the terms of the GNU Lesser General   ////
789
//// Public License as published by the Free Software Foundation; ////
790
//// either version 2.1 of the License, or (at your option) any   ////
791
//// later version.                                               ////
792
////                                                              ////
793
//// This source is distributed in the hope that it will be       ////
794
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
795
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
796
//// PURPOSE.  See the GNU Lesser General Public License for more ////
797
//// details.                                                     ////
798
////                                                              ////
799
//// You should have received a copy of the GNU Lesser General    ////
800
//// Public License along with this source; if not, download it   ////
801
//// from http://www.opencores.org/lgpl.shtml                     ////
802
////                                                              ////
803
//////////////////////////////////////////////////////////////////////
804
// binary counter
805 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
806
 cke, rew, q, zq, level1, rst, clk);
807 25 unneback
   parameter length = 4;
808
   input cke;
809
   input rew;
810
   output [length:1] q;
811
   output reg zq;
812
   output reg level1;
813
   input rst;
814
   input clk;
815
   parameter clear_value = 0;
816
   parameter set_value = 1;
817
   parameter wrap_value = 1;
818
   parameter level1_value = 15;
819 29 unneback
   wire clear;
820 30 unneback
   assign clear = 1'b0;
821 25 unneback
   reg  [length:1] qi;
822
   wire  [length:1] q_next, q_next_fw, q_next_rew;
823
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
824
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
825
   assign q_next = rew ? q_next_rew : q_next_fw;
826
   always @ (posedge clk or posedge rst)
827
     if (rst)
828
       qi <= {length{1'b0}};
829
     else
830
     if (cke)
831
       qi <= q_next;
832
   assign q = qi;
833
   always @ (posedge clk or posedge rst)
834
     if (rst)
835
       zq <= 1'b1;
836
     else
837
     if (cke)
838
       zq <= q_next == {length{1'b0}};
839
    always @ (posedge clk or posedge rst)
840
    if (rst)
841
        level1 <= 1'b0;
842
    else
843
    if (cke)
844 29 unneback
    if (clear)
845
        level1 <= 1'b0;
846
    else if (q_next == level1_value)
847 25 unneback
        level1 <= 1'b1;
848
    else if (qi == level1_value & rew)
849
        level1 <= 1'b0;
850
endmodule
851
//////////////////////////////////////////////////////////////////////
852
////                                                              ////
853
////  Versatile counter                                           ////
854
////                                                              ////
855
////  Description                                                 ////
856
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
857
////  counter                                                     ////
858
////                                                              ////
859
////  To Do:                                                      ////
860
////   - add LFSR with more taps                                  ////
861
////                                                              ////
862
////  Author(s):                                                  ////
863
////      - Michael Unneback, unneback@opencores.org              ////
864
////        ORSoC AB                                              ////
865
////                                                              ////
866
//////////////////////////////////////////////////////////////////////
867
////                                                              ////
868
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
869
////                                                              ////
870
//// This source file may be used and distributed without         ////
871
//// restriction provided that this copyright statement is not    ////
872
//// removed from the file and that any derivative work contains  ////
873
//// the original copyright notice and the associated disclaimer. ////
874
////                                                              ////
875
//// This source file is free software; you can redistribute it   ////
876
//// and/or modify it under the terms of the GNU Lesser General   ////
877
//// Public License as published by the Free Software Foundation; ////
878
//// either version 2.1 of the License, or (at your option) any   ////
879
//// later version.                                               ////
880
////                                                              ////
881
//// This source is distributed in the hope that it will be       ////
882
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
883
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
884
//// PURPOSE.  See the GNU Lesser General Public License for more ////
885
//// details.                                                     ////
886
////                                                              ////
887
//// You should have received a copy of the GNU Lesser General    ////
888
//// Public License along with this source; if not, download it   ////
889
//// from http://www.opencores.org/lgpl.shtml                     ////
890
////                                                              ////
891
//////////////////////////////////////////////////////////////////////
892 6 unneback
// GRAY counter
893 40 unneback
module vl_cnt_gray_ce_bin (
894
 cke, q, q_bin, rst, clk);
895 6 unneback
   parameter length = 4;
896
   input cke;
897
   output reg [length:1] q;
898
   output [length:1] q_bin;
899
   input rst;
900
   input clk;
901
   parameter clear_value = 0;
902
   parameter set_value = 1;
903
   parameter wrap_value = 8;
904
   parameter level1_value = 15;
905
   reg  [length:1] qi;
906
   wire [length:1] q_next;
907
   assign q_next = qi + {{length-1{1'b0}},1'b1};
908
   always @ (posedge clk or posedge rst)
909
     if (rst)
910
       qi <= {length{1'b0}};
911
     else
912
     if (cke)
913
       qi <= q_next;
914
   always @ (posedge clk or posedge rst)
915
     if (rst)
916
       q <= {length{1'b0}};
917
     else
918
       if (cke)
919
         q <= (q_next>>1) ^ q_next;
920
   assign q_bin = qi;
921
endmodule
922
//////////////////////////////////////////////////////////////////////
923
////                                                              ////
924
////  Versatile library, counters                                 ////
925
////                                                              ////
926
////  Description                                                 ////
927
////  counters                                                    ////
928
////                                                              ////
929
////                                                              ////
930
////  To Do:                                                      ////
931
////   - add more counters                                        ////
932
////                                                              ////
933
////  Author(s):                                                  ////
934
////      - Michael Unneback, unneback@opencores.org              ////
935
////        ORSoC AB                                              ////
936
////                                                              ////
937
//////////////////////////////////////////////////////////////////////
938
////                                                              ////
939
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
940
////                                                              ////
941
//// This source file may be used and distributed without         ////
942
//// restriction provided that this copyright statement is not    ////
943
//// removed from the file and that any derivative work contains  ////
944
//// the original copyright notice and the associated disclaimer. ////
945
////                                                              ////
946
//// This source file is free software; you can redistribute it   ////
947
//// and/or modify it under the terms of the GNU Lesser General   ////
948
//// Public License as published by the Free Software Foundation; ////
949
//// either version 2.1 of the License, or (at your option) any   ////
950
//// later version.                                               ////
951
////                                                              ////
952
//// This source is distributed in the hope that it will be       ////
953
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
954
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
955
//// PURPOSE.  See the GNU Lesser General Public License for more ////
956
//// details.                                                     ////
957
////                                                              ////
958
//// You should have received a copy of the GNU Lesser General    ////
959
//// Public License along with this source; if not, download it   ////
960
//// from http://www.opencores.org/lgpl.shtml                     ////
961
////                                                              ////
962
//////////////////////////////////////////////////////////////////////
963 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
964 6 unneback
   parameter length = 4;
965
   output reg [0:length-1] q;
966
   input rst;
967
   input clk;
968
    always @ (posedge clk or posedge rst)
969
    if (rst)
970
        q <= {1'b1,{length-1{1'b0}}};
971
    else
972
        q <= {q[length-1],q[0:length-2]};
973
endmodule
974 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
975 6 unneback
   parameter length = 4;
976
   input cke;
977
   output reg [0:length-1] q;
978
   input rst;
979
   input clk;
980
    always @ (posedge clk or posedge rst)
981
    if (rst)
982
        q <= {1'b1,{length-1{1'b0}}};
983
    else
984
        if (cke)
985
            q <= {q[length-1],q[0:length-2]};
986
endmodule
987 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
988 6 unneback
   parameter length = 4;
989
   input cke, clear;
990
   output reg [0:length-1] q;
991
   input rst;
992
   input clk;
993
    always @ (posedge clk or posedge rst)
994
    if (rst)
995
        q <= {1'b1,{length-1{1'b0}}};
996
    else
997
        if (cke)
998
            if (clear)
999
                q <= {1'b1,{length-1{1'b0}}};
1000
            else
1001
                q <= q >> 1;
1002
endmodule
1003 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1004 6 unneback
   parameter length = 4;
1005
   input cke, clear;
1006
   output reg [0:length-1] q;
1007
   input rst;
1008
   input clk;
1009
    always @ (posedge clk or posedge rst)
1010
    if (rst)
1011
        q <= {1'b1,{length-1{1'b0}}};
1012
    else
1013
        if (cke)
1014
            if (clear)
1015
                q <= {1'b1,{length-1{1'b0}}};
1016
            else
1017
            q <= {q[length-1],q[0:length-2]};
1018
endmodule
1019
//////////////////////////////////////////////////////////////////////
1020
////                                                              ////
1021
////  Versatile library, memories                                 ////
1022
////                                                              ////
1023
////  Description                                                 ////
1024
////  memories                                                    ////
1025
////                                                              ////
1026
////                                                              ////
1027
////  To Do:                                                      ////
1028
////   - add more memory types                                    ////
1029
////                                                              ////
1030
////  Author(s):                                                  ////
1031
////      - Michael Unneback, unneback@opencores.org              ////
1032
////        ORSoC AB                                              ////
1033
////                                                              ////
1034
//////////////////////////////////////////////////////////////////////
1035
////                                                              ////
1036
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1037
////                                                              ////
1038
//// This source file may be used and distributed without         ////
1039
//// restriction provided that this copyright statement is not    ////
1040
//// removed from the file and that any derivative work contains  ////
1041
//// the original copyright notice and the associated disclaimer. ////
1042
////                                                              ////
1043
//// This source file is free software; you can redistribute it   ////
1044
//// and/or modify it under the terms of the GNU Lesser General   ////
1045
//// Public License as published by the Free Software Foundation; ////
1046
//// either version 2.1 of the License, or (at your option) any   ////
1047
//// later version.                                               ////
1048
////                                                              ////
1049
//// This source is distributed in the hope that it will be       ////
1050
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1051
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1052
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1053
//// details.                                                     ////
1054
////                                                              ////
1055
//// You should have received a copy of the GNU Lesser General    ////
1056
//// Public License along with this source; if not, download it   ////
1057
//// from http://www.opencores.org/lgpl.shtml                     ////
1058
////                                                              ////
1059
//////////////////////////////////////////////////////////////////////
1060
/// ROM
1061 7 unneback
module vl_rom_init ( adr, q, clk);
1062
   parameter data_width = 32;
1063
   parameter addr_width = 8;
1064
   input [(addr_width-1):0]       adr;
1065
   output reg [(data_width-1):0] q;
1066
   input                         clk;
1067
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1068
   parameter memory_file = "vl_rom.vmem";
1069
   initial
1070
     begin
1071
        $readmemh(memory_file, rom);
1072
     end
1073
   always @ (posedge clk)
1074
     q <= rom[adr];
1075
endmodule
1076 14 unneback
/*
1077 7 unneback
module vl_rom ( adr, q, clk);
1078 6 unneback
parameter data_width = 32;
1079
parameter addr_width = 4;
1080
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1081
    {32'h18000000},
1082
    {32'hA8200000},
1083
    {32'hA8200000},
1084
    {32'hA8200000},
1085
    {32'h44003000},
1086
    {32'h15000000},
1087
    {32'h15000000},
1088
    {32'h15000000},
1089
    {32'h15000000},
1090
    {32'h15000000},
1091
    {32'h15000000},
1092
    {32'h15000000},
1093
    {32'h15000000},
1094
    {32'h15000000},
1095
    {32'h15000000},
1096
    {32'h15000000}};
1097 7 unneback
input [addr_width-1:0] adr;
1098 6 unneback
output reg [data_width-1:0] q;
1099
input clk;
1100
always @ (posedge clk)
1101 7 unneback
    q <= data[adr];
1102 6 unneback
endmodule
1103 14 unneback
*/
1104 6 unneback
// Single port RAM
1105
module vl_ram ( d, adr, we, q, clk);
1106
   parameter data_width = 32;
1107
   parameter addr_width = 8;
1108
   input [(data_width-1):0]      d;
1109
   input [(addr_width-1):0]       adr;
1110
   input                         we;
1111 7 unneback
   output reg [(data_width-1):0] q;
1112 6 unneback
   input                         clk;
1113
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1114 7 unneback
   parameter init = 0;
1115
   parameter memory_file = "vl_ram.vmem";
1116
   generate if (init) begin : init_mem
1117
   initial
1118
     begin
1119
        $readmemh(memory_file, ram);
1120
     end
1121
   end
1122
   endgenerate
1123 6 unneback
   always @ (posedge clk)
1124
   begin
1125
   if (we)
1126
     ram[adr] <= d;
1127
   q <= ram[adr];
1128
   end
1129
endmodule
1130 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1131
   parameter data_width = 32;
1132
   parameter addr_width = 8;
1133
   input [(data_width-1):0]      d;
1134
   input [(addr_width-1):0]       adr;
1135
   input [(addr_width/4)-1:0]    be;
1136
   input                         we;
1137
   output reg [(data_width-1):0] q;
1138
   input                         clk;
1139
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1140
   parameter init = 0;
1141
   parameter memory_file = "vl_ram.vmem";
1142
   generate if (init) begin : init_mem
1143
   initial
1144
     begin
1145
        $readmemh(memory_file, ram);
1146
     end
1147
   end
1148
   endgenerate
1149
   genvar i;
1150
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1151
      always @ (posedge clk)
1152
      if (we & be[i])
1153
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1154
   end
1155
   endgenerate
1156
   always @ (posedge clk)
1157
      q <= ram[adr];
1158
endmodule
1159 6 unneback
// Dual port RAM
1160
// ACTEL FPGA should not use logic to handle rw collision
1161 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1162 6 unneback
   parameter data_width = 32;
1163
   parameter addr_width = 8;
1164
   input [(data_width-1):0]      d_a;
1165
   input [(addr_width-1):0]       adr_a;
1166
   input [(addr_width-1):0]       adr_b;
1167
   input                         we_a;
1168
   output [(data_width-1):0]      q_b;
1169
   input                         clk_a, clk_b;
1170
   reg [(addr_width-1):0]         adr_b_reg;
1171
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1172 7 unneback
   parameter init = 0;
1173
   parameter memory_file = "vl_ram.vmem";
1174
   generate if (init) begin : init_mem
1175
   initial
1176
     begin
1177
        $readmemh(memory_file, ram);
1178
     end
1179
   end
1180
   endgenerate
1181 6 unneback
   always @ (posedge clk_a)
1182
   if (we_a)
1183
     ram[adr_a] <= d_a;
1184
   always @ (posedge clk_b)
1185
   adr_b_reg <= adr_b;
1186
   assign q_b = ram[adr_b_reg];
1187
endmodule
1188 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1189 6 unneback
   parameter data_width = 32;
1190
   parameter addr_width = 8;
1191
   input [(data_width-1):0]      d_a;
1192
   input [(addr_width-1):0]       adr_a;
1193
   input [(addr_width-1):0]       adr_b;
1194
   input                         we_a;
1195
   output [(data_width-1):0]      q_b;
1196
   output reg [(data_width-1):0] q_a;
1197
   input                         clk_a, clk_b;
1198
   reg [(data_width-1):0]         q_b;
1199
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1200 7 unneback
   parameter init = 0;
1201
   parameter memory_file = "vl_ram.vmem";
1202
   generate if (init) begin : init_mem
1203
   initial
1204
     begin
1205
        $readmemh(memory_file, ram);
1206
     end
1207
   end
1208
   endgenerate
1209 6 unneback
   always @ (posedge clk_a)
1210
     begin
1211
        q_a <= ram[adr_a];
1212
        if (we_a)
1213
             ram[adr_a] <= d_a;
1214
     end
1215
   always @ (posedge clk_b)
1216
          q_b <= ram[adr_b];
1217
endmodule
1218 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1219 6 unneback
   parameter data_width = 32;
1220
   parameter addr_width = 8;
1221
   input [(data_width-1):0]      d_a;
1222
   input [(addr_width-1):0]       adr_a;
1223
   input [(addr_width-1):0]       adr_b;
1224
   input                         we_a;
1225
   output [(data_width-1):0]      q_b;
1226
   input [(data_width-1):0]       d_b;
1227
   output reg [(data_width-1):0] q_a;
1228
   input                         we_b;
1229
   input                         clk_a, clk_b;
1230
   reg [(data_width-1):0]         q_b;
1231
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1232 7 unneback
   parameter init = 0;
1233
   parameter memory_file = "vl_ram.vmem";
1234
   generate if (init) begin : init_mem
1235
   initial
1236
     begin
1237
        $readmemh(memory_file, ram);
1238
     end
1239
   end
1240
   endgenerate
1241 6 unneback
   always @ (posedge clk_a)
1242
     begin
1243
        q_a <= ram[adr_a];
1244
        if (we_a)
1245
             ram[adr_a] <= d_a;
1246
     end
1247
   always @ (posedge clk_b)
1248
     begin
1249
        q_b <= ram[adr_b];
1250
        if (we_b)
1251
          ram[adr_b] <= d_b;
1252
     end
1253
endmodule
1254
// Content addresable memory, CAM
1255
// FIFO
1256 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1257
    d, wr, fifo_full,
1258
    q, rd, fifo_empty,
1259
    fill_level,
1260
    clk, rst
1261
    );
1262
parameter data_width = 18;
1263
parameter addr_width = 4;
1264
// write side
1265
input  [data_width-1:0] d;
1266
input                   wr;
1267
output                  fifo_full;
1268
// read side
1269
output [data_width-1:0] q;
1270
input                   rd;
1271
output                  fifo_empty;
1272
// common
1273
output [addr_width:0]   fill_level;
1274
input rst, clk;
1275
wire [addr_width:1] wadr, radr;
1276
vl_cnt_bin_ce
1277
    # ( .length(addr_width))
1278
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1279
vl_cnt_bin_ce
1280
    # (.length(addr_width))
1281
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1282
vl_dpram_1r1w
1283
    # (.data_width(data_width), .addr_width(addr_width))
1284
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1285 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1286 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1287 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1288
endmodule
1289 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1290
// RAM is supposed to be larger than the two FIFOs
1291
// LFSR counters used adr pointers
1292
module vl_fifo_2r2w_sync_simplex (
1293
    // a side
1294
    a_d, a_wr, a_fifo_full,
1295
    a_q, a_rd, a_fifo_empty,
1296
    a_fill_level,
1297
    // b side
1298
    b_d, b_wr, b_fifo_full,
1299
    b_q, b_rd, b_fifo_empty,
1300
    b_fill_level,
1301
    // common
1302
    clk, rst
1303
    );
1304
parameter data_width = 8;
1305
parameter addr_width = 5;
1306
parameter fifo_full_level = (1<<addr_width)-1;
1307
// a side
1308
input  [data_width-1:0] a_d;
1309
input                   a_wr;
1310
output                  a_fifo_full;
1311
output [data_width-1:0] a_q;
1312
input                   a_rd;
1313
output                  a_fifo_empty;
1314
output [addr_width-1:0] a_fill_level;
1315
// b side
1316
input  [data_width-1:0] b_d;
1317
input                   b_wr;
1318
output                  b_fifo_full;
1319
output [data_width-1:0] b_q;
1320
input                   b_rd;
1321
output                  b_fifo_empty;
1322
output [addr_width-1:0] b_fill_level;
1323
input                   clk;
1324
input                   rst;
1325
// adr_gen
1326
wire [addr_width:1] a_wadr, a_radr;
1327
wire [addr_width:1] b_wadr, b_radr;
1328
// dpram
1329
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1330
vl_cnt_lfsr_ce
1331
    # ( .length(addr_width))
1332
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1333
vl_cnt_lfsr_ce
1334
    # (.length(addr_width))
1335
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1336
vl_cnt_lfsr_ce
1337
    # ( .length(addr_width))
1338
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1339
vl_cnt_lfsr_ce
1340
    # (.length(addr_width))
1341
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1342
// mux read or write adr to DPRAM
1343
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1344
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1345
vl_dpram_2r2w
1346
    # (.data_width(data_width), .addr_width(addr_width+1))
1347
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1348
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1349
vl_cnt_bin_ce_rew_zq_l1
1350 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1351 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1352
vl_cnt_bin_ce_rew_zq_l1
1353 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1354 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1355
endmodule
1356 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1357 11 unneback
   parameter addr_width = 4;
1358
   parameter N = addr_width-1;
1359 6 unneback
   parameter Q1 = 2'b00;
1360
   parameter Q2 = 2'b01;
1361
   parameter Q3 = 2'b11;
1362
   parameter Q4 = 2'b10;
1363
   parameter going_empty = 1'b0;
1364
   parameter going_full  = 1'b1;
1365
   input [N:0]  wptr, rptr;
1366 14 unneback
   output       fifo_empty;
1367 6 unneback
   output       fifo_full;
1368
   input        wclk, rclk, rst;
1369
   wire direction;
1370
   reg  direction_set, direction_clr;
1371
   wire async_empty, async_full;
1372
   wire fifo_full2;
1373 14 unneback
   wire fifo_empty2;
1374 6 unneback
   // direction_set
1375
   always @ (wptr[N:N-1] or rptr[N:N-1])
1376
     case ({wptr[N:N-1],rptr[N:N-1]})
1377
       {Q1,Q2} : direction_set <= 1'b1;
1378
       {Q2,Q3} : direction_set <= 1'b1;
1379
       {Q3,Q4} : direction_set <= 1'b1;
1380
       {Q4,Q1} : direction_set <= 1'b1;
1381
       default : direction_set <= 1'b0;
1382
     endcase
1383
   // direction_clear
1384
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1385
     if (rst)
1386
       direction_clr <= 1'b1;
1387
     else
1388
       case ({wptr[N:N-1],rptr[N:N-1]})
1389
         {Q2,Q1} : direction_clr <= 1'b1;
1390
         {Q3,Q2} : direction_clr <= 1'b1;
1391
         {Q4,Q3} : direction_clr <= 1'b1;
1392
         {Q1,Q4} : direction_clr <= 1'b1;
1393
         default : direction_clr <= 1'b0;
1394
       endcase
1395 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1396 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1397
   assign async_full  = (wptr == rptr) && (direction==going_full);
1398 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1399
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1400 6 unneback
/*
1401
   always @ (posedge wclk or posedge rst or posedge async_full)
1402
     if (rst)
1403
       {fifo_full, fifo_full2} <= 2'b00;
1404
     else if (async_full)
1405
       {fifo_full, fifo_full2} <= 2'b11;
1406
     else
1407
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1408
*/
1409 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1410 6 unneback
     if (async_empty)
1411
       {fifo_empty, fifo_empty2} <= 2'b11;
1412
     else
1413 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1414 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1415
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1416 27 unneback
endmodule // async_compb
1417 6 unneback
module vl_fifo_1r1w_async (
1418
    d, wr, fifo_full, wr_clk, wr_rst,
1419
    q, rd, fifo_empty, rd_clk, rd_rst
1420
    );
1421
parameter data_width = 18;
1422
parameter addr_width = 4;
1423
// write side
1424
input  [data_width-1:0] d;
1425
input                   wr;
1426
output                  fifo_full;
1427
input                   wr_clk;
1428
input                   wr_rst;
1429
// read side
1430
output [data_width-1:0] q;
1431
input                   rd;
1432
output                  fifo_empty;
1433
input                   rd_clk;
1434
input                   rd_rst;
1435
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1436 18 unneback
vl_cnt_gray_ce_bin
1437 6 unneback
    # ( .length(addr_width))
1438
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1439 18 unneback
vl_cnt_gray_ce_bin
1440 6 unneback
    # (.length(addr_width))
1441 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1442 7 unneback
vl_dpram_1r1w
1443 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1444
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1445
vl_fifo_cmp_async
1446
    # (.addr_width(addr_width))
1447
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1448
endmodule
1449 8 unneback
module vl_fifo_2r2w_async (
1450 6 unneback
    // a side
1451
    a_d, a_wr, a_fifo_full,
1452
    a_q, a_rd, a_fifo_empty,
1453
    a_clk, a_rst,
1454
    // b side
1455
    b_d, b_wr, b_fifo_full,
1456
    b_q, b_rd, b_fifo_empty,
1457
    b_clk, b_rst
1458
    );
1459
parameter data_width = 18;
1460
parameter addr_width = 4;
1461
// a side
1462
input  [data_width-1:0] a_d;
1463
input                   a_wr;
1464
output                  a_fifo_full;
1465
output [data_width-1:0] a_q;
1466
input                   a_rd;
1467
output                  a_fifo_empty;
1468
input                   a_clk;
1469
input                   a_rst;
1470
// b side
1471
input  [data_width-1:0] b_d;
1472
input                   b_wr;
1473
output                  b_fifo_full;
1474
output [data_width-1:0] b_q;
1475
input                   b_rd;
1476
output                  b_fifo_empty;
1477
input                   b_clk;
1478
input                   b_rst;
1479
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1480
vl_fifo_1r1w_async_a (
1481
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1482
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1483
    );
1484
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1485
vl_fifo_1r1w_async_b (
1486
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1487
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1488
    );
1489
endmodule
1490 8 unneback
module vl_fifo_2r2w_async_simplex (
1491 6 unneback
    // a side
1492
    a_d, a_wr, a_fifo_full,
1493
    a_q, a_rd, a_fifo_empty,
1494
    a_clk, a_rst,
1495
    // b side
1496
    b_d, b_wr, b_fifo_full,
1497
    b_q, b_rd, b_fifo_empty,
1498
    b_clk, b_rst
1499
    );
1500
parameter data_width = 18;
1501
parameter addr_width = 4;
1502
// a side
1503
input  [data_width-1:0] a_d;
1504
input                   a_wr;
1505
output                  a_fifo_full;
1506
output [data_width-1:0] a_q;
1507
input                   a_rd;
1508
output                  a_fifo_empty;
1509
input                   a_clk;
1510
input                   a_rst;
1511
// b side
1512
input  [data_width-1:0] b_d;
1513
input                   b_wr;
1514
output                  b_fifo_full;
1515
output [data_width-1:0] b_q;
1516
input                   b_rd;
1517
output                  b_fifo_empty;
1518
input                   b_clk;
1519
input                   b_rst;
1520
// adr_gen
1521
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1522
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1523
// dpram
1524
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1525 18 unneback
vl_cnt_gray_ce_bin
1526 6 unneback
    # ( .length(addr_width))
1527
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1528 18 unneback
vl_cnt_gray_ce_bin
1529 6 unneback
    # (.length(addr_width))
1530
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1531 18 unneback
vl_cnt_gray_ce_bin
1532 6 unneback
    # ( .length(addr_width))
1533
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1534 18 unneback
vl_cnt_gray_ce_bin
1535 6 unneback
    # (.length(addr_width))
1536
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1537
// mux read or write adr to DPRAM
1538
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1539
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1540 11 unneback
vl_dpram_2r2w
1541 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1542
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1543
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1544 11 unneback
vl_fifo_cmp_async
1545 6 unneback
    # (.addr_width(addr_width))
1546
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1547 11 unneback
vl_fifo_cmp_async
1548 6 unneback
    # (.addr_width(addr_width))
1549
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1550
endmodule
1551 12 unneback
//////////////////////////////////////////////////////////////////////
1552
////                                                              ////
1553
////  Versatile library, wishbone stuff                           ////
1554
////                                                              ////
1555
////  Description                                                 ////
1556
////  Wishbone compliant modules                                  ////
1557
////                                                              ////
1558
////                                                              ////
1559
////  To Do:                                                      ////
1560
////   -                                                          ////
1561
////                                                              ////
1562
////  Author(s):                                                  ////
1563
////      - Michael Unneback, unneback@opencores.org              ////
1564
////        ORSoC AB                                              ////
1565
////                                                              ////
1566
//////////////////////////////////////////////////////////////////////
1567
////                                                              ////
1568
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1569
////                                                              ////
1570
//// This source file may be used and distributed without         ////
1571
//// restriction provided that this copyright statement is not    ////
1572
//// removed from the file and that any derivative work contains  ////
1573
//// the original copyright notice and the associated disclaimer. ////
1574
////                                                              ////
1575
//// This source file is free software; you can redistribute it   ////
1576
//// and/or modify it under the terms of the GNU Lesser General   ////
1577
//// Public License as published by the Free Software Foundation; ////
1578
//// either version 2.1 of the License, or (at your option) any   ////
1579
//// later version.                                               ////
1580
////                                                              ////
1581
//// This source is distributed in the hope that it will be       ////
1582
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1583
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1584
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1585
//// details.                                                     ////
1586
////                                                              ////
1587
//// You should have received a copy of the GNU Lesser General    ////
1588
//// Public License along with this source; if not, download it   ////
1589
//// from http://www.opencores.org/lgpl.shtml                     ////
1590
////                                                              ////
1591
//////////////////////////////////////////////////////////////////////
1592
// async wb3 - wb3 bridge
1593
`timescale 1ns/1ns
1594 18 unneback
module vl_wb3wb3_bridge (
1595 12 unneback
        // wishbone slave side
1596
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1597
        // wishbone master side
1598
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1599
input [31:0] wbs_dat_i;
1600
input [31:2] wbs_adr_i;
1601
input [3:0]  wbs_sel_i;
1602
input [1:0]  wbs_bte_i;
1603
input [2:0]  wbs_cti_i;
1604
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1605
output [31:0] wbs_dat_o;
1606 14 unneback
output wbs_ack_o;
1607 12 unneback
input wbs_clk, wbs_rst;
1608
output [31:0] wbm_dat_o;
1609
output reg [31:2] wbm_adr_o;
1610
output [3:0]  wbm_sel_o;
1611
output reg [1:0]  wbm_bte_o;
1612
output reg [2:0]  wbm_cti_o;
1613 14 unneback
output reg wbm_we_o;
1614
output wbm_cyc_o;
1615 12 unneback
output wbm_stb_o;
1616
input [31:0]  wbm_dat_i;
1617
input wbm_ack_i;
1618
input wbm_clk, wbm_rst;
1619
parameter addr_width = 4;
1620
// bte
1621
parameter linear       = 2'b00;
1622
parameter wrap4        = 2'b01;
1623
parameter wrap8        = 2'b10;
1624
parameter wrap16       = 2'b11;
1625
// cti
1626
parameter classic      = 3'b000;
1627
parameter incburst     = 3'b010;
1628
parameter endofburst   = 3'b111;
1629
parameter wbs_adr  = 1'b0;
1630
parameter wbs_data = 1'b1;
1631 33 unneback
parameter wbm_adr0      = 2'b00;
1632
parameter wbm_adr1      = 2'b01;
1633
parameter wbm_data      = 2'b10;
1634
parameter wbm_data_wait = 2'b11;
1635 12 unneback
reg [1:0] wbs_bte_reg;
1636
reg wbs;
1637
wire wbs_eoc_alert, wbm_eoc_alert;
1638
reg wbs_eoc, wbm_eoc;
1639
reg [1:0] wbm;
1640 14 unneback
wire [1:16] wbs_count, wbm_count;
1641 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1642
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1643
reg a_rd_reg;
1644
wire b_rd_adr, b_rd_data;
1645 14 unneback
wire b_rd_data_reg;
1646
wire [35:0] temp;
1647 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1648
always @ (posedge wbs_clk or posedge wbs_rst)
1649
if (wbs_rst)
1650
        wbs_eoc <= 1'b0;
1651
else
1652
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1653
                wbs_eoc <= wbs_bte_i==linear;
1654
        else if (wbs_eoc_alert & (a_rd | a_wr))
1655
                wbs_eoc <= 1'b1;
1656 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1657 12 unneback
    cnt0 (
1658
        .cke(wbs_ack_o),
1659
        .clear(wbs_eoc),
1660
        .q(wbs_count),
1661
        .rst(wbs_rst),
1662
        .clk(wbs_clk));
1663
always @ (posedge wbs_clk or posedge wbs_rst)
1664
if (wbs_rst)
1665
        wbs <= wbs_adr;
1666
else
1667
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1668
                wbs <= wbs_data;
1669
        else if (wbs_eoc & wbs_ack_o)
1670
                wbs <= wbs_adr;
1671
// wbs FIFO
1672
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1673
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1674
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1675
              1'b0;
1676
assign a_rd = !a_fifo_empty;
1677
always @ (posedge wbs_clk or posedge wbs_rst)
1678
if (wbs_rst)
1679
        a_rd_reg <= 1'b0;
1680
else
1681
        a_rd_reg <= a_rd;
1682
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1683
assign wbs_dat_o = a_q[35:4];
1684
always @ (posedge wbs_clk or posedge wbs_rst)
1685
if (wbs_rst)
1686 13 unneback
        wbs_bte_reg <= 2'b00;
1687 12 unneback
else
1688 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1689 12 unneback
// wbm FIFO
1690
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1691
always @ (posedge wbm_clk or posedge wbm_rst)
1692
if (wbm_rst)
1693
        wbm_eoc <= 1'b0;
1694
else
1695
        if (wbm==wbm_adr0 & !b_fifo_empty)
1696
                wbm_eoc <= b_q[4:3] == linear;
1697
        else if (wbm_eoc_alert & wbm_ack_i)
1698
                wbm_eoc <= 1'b1;
1699
always @ (posedge wbm_clk or posedge wbm_rst)
1700
if (wbm_rst)
1701
        wbm <= wbm_adr0;
1702
else
1703 33 unneback
/*
1704 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1705
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1706
        (wbm==wbm_adr1 & !wbm_we_o) |
1707
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1708
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1709 33 unneback
*/
1710
    case (wbm)
1711
    wbm_adr0:
1712
        if (!b_fifo_empty)
1713
            wbm <= wbm_adr1;
1714
    wbm_adr1:
1715
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1716
            wbm <= wbm_data;
1717
    wbm_data:
1718
        if (wbm_ack_i & wbm_eoc)
1719
            wbm <= wbm_adr0;
1720
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1721
            wbm <= wbm_data_wait;
1722
    wbm_data_wait:
1723
        if (!b_fifo_empty)
1724
            wbm <= wbm_data;
1725
    endcase
1726 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1727
assign b_wr = !wbm_we_o & wbm_ack_i;
1728
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1729
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1730
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1731 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1732 12 unneback
                   1'b0;
1733
assign b_rd = b_rd_adr | b_rd_data;
1734 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1735
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1736 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1737 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1738 12 unneback
    cnt1 (
1739
        .cke(wbm_ack_i),
1740
        .clear(wbm_eoc),
1741
        .q(wbm_count),
1742
        .rst(wbm_rst),
1743
        .clk(wbm_clk));
1744 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1745
assign wbm_stb_o = (wbm==wbm_data);
1746 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1747
if (wbm_rst)
1748
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1749
else begin
1750
        if (wbm==wbm_adr0 & !b_fifo_empty)
1751
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1752
        else if (wbm_eoc_alert & wbm_ack_i)
1753
                wbm_cti_o <= endofburst;
1754
end
1755
//async_fifo_dw_simplex_top
1756
vl_fifo_2r2w_async_simplex
1757
# ( .data_width(36), .addr_width(addr_width))
1758
fifo (
1759
    // a side
1760
    .a_d(a_d),
1761
    .a_wr(a_wr),
1762
    .a_fifo_full(a_fifo_full),
1763
    .a_q(a_q),
1764
    .a_rd(a_rd),
1765
    .a_fifo_empty(a_fifo_empty),
1766
    .a_clk(wbs_clk),
1767
    .a_rst(wbs_rst),
1768
    // b side
1769
    .b_d(b_d),
1770
    .b_wr(b_wr),
1771
    .b_fifo_full(b_fifo_full),
1772
    .b_q(b_q),
1773
    .b_rd(b_rd),
1774
    .b_fifo_empty(b_fifo_empty),
1775
    .b_clk(wbm_clk),
1776
    .b_rst(wbm_rst)
1777
    );
1778
endmodule
1779 39 unneback
module vl_wb3_arbiter_type1 (
1780
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1781
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1782
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1783
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1784
    wb_clk, wb_rst
1785
);
1786
parameter nr_of_ports = 3;
1787
parameter adr_size = 26;
1788
parameter adr_lo   = 2;
1789
parameter dat_size = 32;
1790
parameter sel_size = dat_size/8;
1791
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1792
localparam dw = dat_size * nr_of_ports;
1793
localparam sw = sel_size * nr_of_ports;
1794
localparam cw = 3 * nr_of_ports;
1795
localparam bw = 2 * nr_of_ports;
1796
input  [dw-1:0] wbm_dat_o;
1797
input  [aw-1:0] wbm_adr_o;
1798
input  [sw-1:0] wbm_sel_o;
1799
input  [cw-1:0] wbm_cti_o;
1800
input  [bw-1:0] wbm_bte_o;
1801
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1802
output [dw-1:0] wbm_dat_i;
1803
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1804
output [dat_size-1:0] wbs_dat_i;
1805
output [adr_size-1:adr_lo] wbs_adr_i;
1806
output [sel_size-1:0] wbs_sel_i;
1807
output [2:0] wbs_cti_i;
1808
output [1:0] wbs_bte_i;
1809
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1810
input  [dat_size-1:0] wbs_dat_o;
1811
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1812
input wb_clk, wb_rst;
1813
wire [nr_of_ports-1:0] select;
1814
wire [nr_of_ports-1:0] state;
1815
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1816
wire [nr_of_ports-1:0] sel;
1817
wire idle;
1818
genvar i;
1819
assign idle = !(|state);
1820
generate
1821
if (nr_of_ports == 2) begin
1822
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1823
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1824
    assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : 2'b00;
1825
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1826
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1827
end
1828
endgenerate
1829
generate
1830
if (nr_of_ports == 3) begin
1831
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1832
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1833
    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : 3'b000;
1834
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1835
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1836
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1837
end
1838
endgenerate
1839
generate
1840
for (i=0;i<nr_of_ports;i=i+1) begin
1841
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
1842
end
1843
endgenerate
1844
    assign sel = select | state;
1845
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
1846
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
1847
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
1848
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
1849
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
1850
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
1851
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
1852
    assign wbs_cyc_i = |sel;
1853
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
1854
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
1855
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
1856
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
1857
endmodule
1858 17 unneback
// WB ROM
1859 18 unneback
module vl_wb_boot_rom (
1860 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
1861 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
1862
    parameter adr_hi = 31;
1863
    parameter adr_lo = 28;
1864
    parameter adr_sel = 4'hf;
1865
    parameter addr_width = 5;
1866 33 unneback
/*
1867
`ifndef BOOT_ROM
1868
`define BOOT_ROM "boot_rom.v"
1869
`endif
1870
*/
1871 18 unneback
    input [adr_hi:2]    wb_adr_i;
1872
    input               wb_stb_i;
1873
    input               wb_cyc_i;
1874
    output [31:0]        wb_dat_o;
1875
    output              wb_ack_o;
1876
    output              hit_o;
1877
    input               wb_clk;
1878
    input               wb_rst;
1879
    wire hit;
1880
    reg [31:0] wb_dat;
1881
    reg wb_ack;
1882
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1883 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
1884
    if (wb_rst)
1885 18 unneback
        wb_dat <= 32'h15000000;
1886 17 unneback
    else
1887 18 unneback
         case (wb_adr_i[addr_width-1:2])
1888 33 unneback
`ifdef BOOT_ROM
1889
`include `BOOT_ROM
1890
`endif
1891 17 unneback
           /*
1892
            // Zero r0 and jump to 0x00000100
1893 18 unneback
 
1894
            1 : wb_dat <= 32'hA8200000;
1895
            2 : wb_dat <= 32'hA8C00100;
1896
            3 : wb_dat <= 32'h44003000;
1897
            4 : wb_dat <= 32'h15000000;
1898 17 unneback
            */
1899
           default:
1900 18 unneback
             wb_dat <= 32'h00000000;
1901 17 unneback
         endcase // case (wb_adr_i)
1902
always @ (posedge wb_clk or posedge wb_rst)
1903
    if (wb_rst)
1904 18 unneback
        wb_ack <= 1'b0;
1905 17 unneback
    else
1906 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1907
assign hit_o = hit;
1908
assign wb_dat_o = wb_dat & {32{wb_ack}};
1909
assign wb_ack_o = wb_ack;
1910 17 unneback
endmodule
1911 32 unneback
module vl_wb_dpram (
1912
        // wishbone slave side a
1913
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1914
        wbsa_clk, wbsa_rst,
1915
        // wishbone slave side a
1916
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1917
        wbsb_clk, wbsb_rst);
1918
parameter data_width = 32;
1919
parameter addr_width = 8;
1920
parameter dat_o_mask_a = 1;
1921
parameter dat_o_mask_b = 1;
1922
input [31:0] wbsa_dat_i;
1923
input [addr_width-1:2] wbsa_adr_i;
1924
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1925
output [31:0] wbsa_dat_o;
1926
output wbsa_ack_o;
1927
input wbsa_clk, wbsa_rst;
1928
input [31:0] wbsb_dat_i;
1929
input [addr_width-1:2] wbsb_adr_i;
1930
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1931
output [31:0] wbsb_dat_o;
1932
output wbsb_ack_o;
1933
input wbsb_clk, wbsb_rst;
1934
wire wbsa_dat_tmp, wbsb_dat_tmp;
1935
vl_dpram_2r2w # (
1936 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
1937 32 unneback
dpram0(
1938
    .d_a(wbsa_dat_i),
1939
    .q_a(wbsa_dat_tmp),
1940
    .adr_a(wbsa_adr_i),
1941
    .we_a(wbsa_we_i),
1942
    .clk_a(wbsa_clk),
1943
    .d_b(wbsb_dat_i),
1944
    .q_b(wbsb_dat_tmp),
1945
    .adr_b(wbsb_adr_i),
1946
    .we_b(wbsb_we_i),
1947
    .clk_b(wbsb_clk) );
1948 33 unneback
generate if (dat_o_mask_a==1)
1949 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
1950
endgenerate
1951 33 unneback
generate if (dat_o_mask_a==0)
1952 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
1953
endgenerate
1954 33 unneback
generate if (dat_o_mask_b==1)
1955 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
1956
endgenerate
1957 33 unneback
generate if (dat_o_mask_b==0)
1958 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
1959
endgenerate
1960
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
1961
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
1962
endmodule
1963 18 unneback
//////////////////////////////////////////////////////////////////////
1964
////                                                              ////
1965
////  Arithmetic functions                                        ////
1966
////                                                              ////
1967
////  Description                                                 ////
1968
////  Arithmetic functions for ALU and DSP                        ////
1969
////                                                              ////
1970
////                                                              ////
1971
////  To Do:                                                      ////
1972
////   -                                                          ////
1973
////                                                              ////
1974
////  Author(s):                                                  ////
1975
////      - Michael Unneback, unneback@opencores.org              ////
1976
////        ORSoC AB                                              ////
1977
////                                                              ////
1978
//////////////////////////////////////////////////////////////////////
1979
////                                                              ////
1980
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1981
////                                                              ////
1982
//// This source file may be used and distributed without         ////
1983
//// restriction provided that this copyright statement is not    ////
1984
//// removed from the file and that any derivative work contains  ////
1985
//// the original copyright notice and the associated disclaimer. ////
1986
////                                                              ////
1987
//// This source file is free software; you can redistribute it   ////
1988
//// and/or modify it under the terms of the GNU Lesser General   ////
1989
//// Public License as published by the Free Software Foundation; ////
1990
//// either version 2.1 of the License, or (at your option) any   ////
1991
//// later version.                                               ////
1992
////                                                              ////
1993
//// This source is distributed in the hope that it will be       ////
1994
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1995
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1996
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1997
//// details.                                                     ////
1998
////                                                              ////
1999
//// You should have received a copy of the GNU Lesser General    ////
2000
//// Public License along with this source; if not, download it   ////
2001
//// from http://www.opencores.org/lgpl.shtml                     ////
2002
////                                                              ////
2003
//////////////////////////////////////////////////////////////////////
2004
// signed multiplication
2005
module vl_mults (a,b,p);
2006
parameter operand_a_width = 18;
2007
parameter operand_b_width = 18;
2008
parameter result_hi = 35;
2009
parameter result_lo = 0;
2010
input [operand_a_width-1:0] a;
2011
input [operand_b_width-1:0] b;
2012
output [result_hi:result_lo] p;
2013
wire signed [operand_a_width-1:0] ai;
2014
wire signed [operand_b_width-1:0] bi;
2015
wire signed [operand_a_width+operand_b_width-1:0] result;
2016
    assign ai = a;
2017
    assign bi = b;
2018
    assign result = ai * bi;
2019
    assign p = result[result_hi:result_lo];
2020
endmodule
2021
module vl_mults18x18 (a,b,p);
2022
input [17:0] a,b;
2023
output [35:0] p;
2024
vl_mult
2025
    # (.operand_a_width(18), .operand_b_width(18))
2026
    mult0 (.a(a), .b(b), .p(p));
2027
endmodule
2028
// unsigned multiplication
2029
module vl_mult (a,b,p);
2030
parameter operand_a_width = 18;
2031
parameter operand_b_width = 18;
2032
parameter result_hi = 35;
2033
parameter result_lo = 0;
2034
input [operand_a_width-1:0] a;
2035
input [operand_b_width-1:0] b;
2036
output [result_hi:result_hi] p;
2037
wire [operand_a_width+operand_b_width-1:0] result;
2038
    assign result = a * b;
2039
    assign p = result[result_hi:result_lo];
2040
endmodule
2041
// shift unit
2042
// supporting the following shift functions
2043
//   SLL
2044
//   SRL
2045
//   SRA
2046
module vl_shift_unit_32( din, s, dout, opcode);
2047
input [31:0] din; // data in operand
2048
input [4:0] s; // shift operand
2049
input [1:0] opcode;
2050
output [31:0] dout;
2051
parameter opcode_sll = 2'b00;
2052
//parameter opcode_srl = 2'b01;
2053
parameter opcode_sra = 2'b10;
2054
//parameter opcode_ror = 2'b11;
2055
wire sll, sra;
2056
assign sll = opcode == opcode_sll;
2057
assign sra = opcode == opcode_sra;
2058
wire [15:1] s1;
2059
wire [3:0] sign;
2060
wire [7:0] tmp [0:3];
2061
// first stage is multiplier based
2062
// shift operand as fractional 8.7
2063
assign s1[15] = sll & s[2:0]==3'd7;
2064
assign s1[14] = sll & s[2:0]==3'd6;
2065
assign s1[13] = sll & s[2:0]==3'd5;
2066
assign s1[12] = sll & s[2:0]==3'd4;
2067
assign s1[11] = sll & s[2:0]==3'd3;
2068
assign s1[10] = sll & s[2:0]==3'd2;
2069
assign s1[ 9] = sll & s[2:0]==3'd1;
2070
assign s1[ 8] = s[2:0]==3'd0;
2071
assign s1[ 7] = !sll & s[2:0]==3'd1;
2072
assign s1[ 6] = !sll & s[2:0]==3'd2;
2073
assign s1[ 5] = !sll & s[2:0]==3'd3;
2074
assign s1[ 4] = !sll & s[2:0]==3'd4;
2075
assign s1[ 3] = !sll & s[2:0]==3'd5;
2076
assign s1[ 2] = !sll & s[2:0]==3'd6;
2077
assign s1[ 1] = !sll & s[2:0]==3'd7;
2078
assign sign[3] = din[31] & sra;
2079
assign sign[2] = sign[3] & (&din[31:24]);
2080
assign sign[1] = sign[2] & (&din[23:16]);
2081
assign sign[0] = sign[1] & (&din[15:8]);
2082
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2083
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2084
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2085
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2086
// second stage is multiplexer based
2087
// shift on byte level
2088
// mux byte 3
2089
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2090
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2091
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2092
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2093
                     {8{sign[3]}};
2094
// mux byte 2
2095
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2096
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2097
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2098
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2099
                     (s[4:3]==2'b01) ? tmp[3] :
2100
                     {8{sign[3]}};
2101
// mux byte 1
2102
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2103
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2104
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2105
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2106
                     (s[4:3]==2'b01) ? tmp[2] :
2107
                     (s[4:3]==2'b10) ? tmp[3] :
2108
                     {8{sign[3]}};
2109
// mux byte 0
2110
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2111
                     (sll) ?  {8{1'b0}}:
2112
                     (s[4:3]==2'b01) ? tmp[1] :
2113
                     (s[4:3]==2'b10) ? tmp[2] :
2114
                     tmp[3];
2115
endmodule
2116
// logic unit
2117
// supporting the following logic functions
2118
//    a and b
2119
//    a or  b
2120
//    a xor b
2121
//    not b
2122
module vl_logic_unit( a, b, result, opcode);
2123
parameter width = 32;
2124
parameter opcode_and = 2'b00;
2125
parameter opcode_or  = 2'b01;
2126
parameter opcode_xor = 2'b10;
2127
input [width-1:0] a,b;
2128
output [width-1:0] result;
2129
input [1:0] opcode;
2130
assign result = (opcode==opcode_and) ? a & b :
2131
                (opcode==opcode_or)  ? a | b :
2132
                (opcode==opcode_xor) ? a ^ b :
2133
                b;
2134
endmodule
2135
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2136
parameter width = 32;
2137
parameter opcode_add = 1'b0;
2138
parameter opcode_sub = 1'b1;
2139
input [width-1:0] a,b;
2140
input c_in, add_sub, sign;
2141
output [width-1:0] result;
2142
output c_out, z, ovfl;
2143
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2144
assign z = (result=={width{1'b0}});
2145
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2146
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2147
endmodule

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