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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 44

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1 6 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 33 unneback
module vl_gbuf ( i, o);
47
input i;
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output o;
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assign o = i;
50
endmodule
51 6 unneback
 // ALTERA
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 //ACTEL
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// sync reset
54 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
55 6 unneback
// output active high global reset sync with two DFFs 
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`timescale 1 ns/100 ps
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module vl_sync_rst ( rst_n_i, rst_o, clk);
58
input rst_n_i, clk;
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output rst_o;
60 18 unneback
reg [1:0] tmp;
61 6 unneback
always @ (posedge clk or negedge rst_n_i)
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if (!rst_n_i)
63 17 unneback
        tmp <= 2'b11;
64 6 unneback
else
65 33 unneback
        tmp <= {1'b0,tmp[1]};
66 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
67 6 unneback
endmodule
68
// vl_pll
69 32 unneback
///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps/1 ps
71
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
72
parameter index = 0;
73
parameter number_of_clk = 1;
74
parameter period_time_0 = 20000;
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parameter period_time_1 = 20000;
76
parameter period_time_2 = 20000;
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parameter period_time_3 = 20000;
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parameter period_time_4 = 20000;
79
parameter lock_delay = 2000000;
80
input clk_i, rst_n_i;
81
output lock;
82
output reg [0:number_of_clk-1] clk_o;
83
output [0:number_of_clk-1] rst_o;
84 33 unneback
`ifdef SIM_PLL
85 32 unneback
always
86
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
87
generate if (number_of_clk > 1)
88
always
89
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
90
endgenerate
91
generate if (number_of_clk > 2)
92
always
93
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
94
endgenerate
95 33 unneback
generate if (number_of_clk > 3)
96 32 unneback
always
97
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
98
endgenerate
99 33 unneback
generate if (number_of_clk > 4)
100 32 unneback
always
101
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
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endgenerate
103
genvar i;
104
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
106
end
107
endgenerate
108 33 unneback
//assign #lock_delay lock = rst_n_i;
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assign lock = rst_n_i;
110 32 unneback
endmodule
111 33 unneback
`else
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`ifdef VL_PLL0
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`ifdef VL_PLL0_CLK1
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
115
`endif
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`ifdef VL_PLL0_CLK2
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL0_CLK3
120
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL0_CLK4
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL0_CLK5
126
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
127
`endif
128
`endif
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`ifdef VL_PLL1
130
`ifdef VL_PLL1_CLK1
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL1_CLK2
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL1_CLK3
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL1_CLK4
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL1_CLK5
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL2
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`ifdef VL_PLL2_CLK1
148
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL2_CLK2
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL2_CLK3
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
156
`ifdef VL_PLL2_CLK4
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL2_CLK5
160
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL3
164
`ifdef VL_PLL3_CLK1
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    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
166
`endif
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`ifdef VL_PLL3_CLK2
168
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
169
`endif
170
`ifdef VL_PLL3_CLK3
171
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
172
`endif
173
`ifdef VL_PLL3_CLK4
174
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
175
`endif
176
`ifdef VL_PLL3_CLK5
177
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
178
`endif
179
`endif
180 32 unneback
genvar i;
181
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
182 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
183 32 unneback
end
184
endgenerate
185
endmodule
186 33 unneback
`endif
187 32 unneback
///////////////////////////////////////////////////////////////////////////////
188 6 unneback
 //altera
189
 //actel
190
//////////////////////////////////////////////////////////////////////
191
////                                                              ////
192
////  Versatile library, registers                                ////
193
////                                                              ////
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////  Description                                                 ////
195
////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
198
////  To Do:                                                      ////
199
////   - add more different registers                             ////
200
////                                                              ////
201
////  Author(s):                                                  ////
202
////      - Michael Unneback, unneback@opencores.org              ////
203
////        ORSoC AB                                              ////
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////                                                              ////
205
//////////////////////////////////////////////////////////////////////
206
////                                                              ////
207
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
208
////                                                              ////
209
//// This source file may be used and distributed without         ////
210
//// restriction provided that this copyright statement is not    ////
211
//// removed from the file and that any derivative work contains  ////
212
//// the original copyright notice and the associated disclaimer. ////
213
////                                                              ////
214
//// This source file is free software; you can redistribute it   ////
215
//// and/or modify it under the terms of the GNU Lesser General   ////
216
//// Public License as published by the Free Software Foundation; ////
217
//// either version 2.1 of the License, or (at your option) any   ////
218
//// later version.                                               ////
219
////                                                              ////
220
//// This source is distributed in the hope that it will be       ////
221
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
222
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
223
//// PURPOSE.  See the GNU Lesser General Public License for more ////
224
//// details.                                                     ////
225
////                                                              ////
226
//// You should have received a copy of the GNU Lesser General    ////
227
//// Public License along with this source; if not, download it   ////
228
//// from http://www.opencores.org/lgpl.shtml                     ////
229
////                                                              ////
230
//////////////////////////////////////////////////////////////////////
231 18 unneback
module vl_dff ( d, q, clk, rst);
232 6 unneback
        parameter width = 1;
233
        parameter reset_value = 0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output reg [width-1:0] q;
237
        always @ (posedge clk or posedge rst)
238
        if (rst)
239
                q <= reset_value;
240
        else
241
                q <= d;
242
endmodule
243 18 unneback
module vl_dff_array ( d, q, clk, rst);
244 6 unneback
        parameter width = 1;
245
        parameter depth = 2;
246
        parameter reset_value = 1'b0;
247
        input [width-1:0] d;
248
        input clk, rst;
249
        output [width-1:0] q;
250
        reg  [0:depth-1] q_tmp [width-1:0];
251
        integer i;
252
        always @ (posedge clk or posedge rst)
253
        if (rst) begin
254
            for (i=0;i<depth;i=i+1)
255
                q_tmp[i] <= {width{reset_value}};
256
        end else begin
257
            q_tmp[0] <= d;
258
            for (i=1;i<depth;i=i+1)
259
                q_tmp[i] <= q_tmp[i-1];
260
        end
261
    assign q = q_tmp[depth-1];
262
endmodule
263 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
264 6 unneback
        parameter width = 1;
265
        parameter reset_value = 0;
266
        input [width-1:0] d;
267
        input ce, clk, rst;
268
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
                q <= reset_value;
272
        else
273
                if (ce)
274
                        q <= d;
275
endmodule
276 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
277 8 unneback
        parameter width = 1;
278
        parameter reset_value = 0;
279
        input [width-1:0] d;
280 10 unneback
        input ce, clear, clk, rst;
281 8 unneback
        output reg [width-1:0] q;
282
        always @ (posedge clk or posedge rst)
283
        if (rst)
284
            q <= reset_value;
285
        else
286
            if (ce)
287
                if (clear)
288
                    q <= {width{1'b0}};
289
                else
290
                    q <= d;
291
endmodule
292 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
293
        parameter width = 1;
294
        parameter reset_value = 0;
295
        input [width-1:0] d;
296
        input ce, set, clk, rst;
297
        output reg [width-1:0] q;
298
        always @ (posedge clk or posedge rst)
299
        if (rst)
300
            q <= reset_value;
301
        else
302
            if (ce)
303
                if (set)
304
                    q <= {width{1'b1}};
305
                else
306
                    q <= d;
307
endmodule
308 29 unneback
module vl_spr ( sp, r, q, clk, rst);
309
        parameter width = 1;
310
        parameter reset_value = 0;
311
        input sp, r;
312
        output reg q;
313
        input clk, rst;
314
        always @ (posedge clk or posedge rst)
315
        if (rst)
316
            q <= reset_value;
317
        else
318
            if (sp)
319
                q <= 1'b1;
320
            else if (r)
321
                q <= 1'b0;
322
endmodule
323
module vl_srp ( s, rp, q, clk, rst);
324
        parameter width = 1;
325
        parameter reset_value = 0;
326
        input s, rp;
327
        output reg q;
328
        input clk, rst;
329
        always @ (posedge clk or posedge rst)
330
        if (rst)
331
            q <= reset_value;
332
        else
333
            if (rp)
334
                q <= 1'b0;
335
            else if (s)
336
                q <= 1'b1;
337
endmodule
338 6 unneback
// megafunction wizard: %LPM_FF%
339
// GENERATION: STANDARD
340
// VERSION: WM1.0
341
// MODULE: lpm_ff 
342
// ============================================================
343
// File Name: dff_sr.v
344
// Megafunction Name(s):
345
//                      lpm_ff
346
//
347
// Simulation Library Files(s):
348
//                      lpm
349
// ============================================================
350
// ************************************************************
351
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
352
//
353
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
354
// ************************************************************
355
//Copyright (C) 1991-2010 Altera Corporation
356
//Your use of Altera Corporation's design tools, logic functions 
357
//and other software and tools, and its AMPP partner logic 
358
//functions, and any output files from any of the foregoing 
359
//(including device programming or simulation files), and any 
360
//associated documentation or information are expressly subject 
361
//to the terms and conditions of the Altera Program License 
362
//Subscription Agreement, Altera MegaCore Function License 
363
//Agreement, or other applicable license agreement, including, 
364
//without limitation, that your use is for the sole purpose of 
365
//programming logic devices manufactured by Altera and sold by 
366
//Altera or its authorized distributors.  Please refer to the 
367
//applicable agreement for further details.
368
// synopsys translate_off
369
`timescale 1 ps / 1 ps
370
// synopsys translate_on
371 18 unneback
module vl_dff_sr (
372 6 unneback
        aclr,
373
        aset,
374
        clock,
375
        data,
376
        q);
377
        input     aclr;
378
        input     aset;
379
        input     clock;
380
        input     data;
381
        output    q;
382
        wire [0:0] sub_wire0;
383
        wire [0:0] sub_wire1 = sub_wire0[0:0];
384
        wire  q = sub_wire1;
385
        wire  sub_wire2 = data;
386
        wire  sub_wire3 = sub_wire2;
387
        lpm_ff  lpm_ff_component (
388
                                .aclr (aclr),
389
                                .clock (clock),
390
                                .data (sub_wire3),
391
                                .aset (aset),
392
                                .q (sub_wire0)
393
                                // synopsys translate_off
394
                                ,
395
                                .aload (),
396
                                .enable (),
397
                                .sclr (),
398
                                .sload (),
399
                                .sset ()
400
                                // synopsys translate_on
401
                                );
402
        defparam
403
                lpm_ff_component.lpm_fftype = "DFF",
404
                lpm_ff_component.lpm_type = "LPM_FF",
405
                lpm_ff_component.lpm_width = 1;
406
endmodule
407
// ============================================================
408
// CNX file retrieval info
409
// ============================================================
410
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
411
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
412
// Retrieval info: PRIVATE: ASET NUMERIC "1"
413
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
414
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
415
// Retrieval info: PRIVATE: DFF NUMERIC "1"
416
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
417
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
418
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET NUMERIC "0"
420
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
421
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
422
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
423
// Retrieval info: PRIVATE: nBit NUMERIC "1"
424
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
425
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
426
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
427
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
428
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
429
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
430
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
431
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
432
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
433
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
434
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
435
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
436
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
437
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
444
// Retrieval info: LIB_FILE: lpm
445
// LATCH
446
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
447 18 unneback
module vl_latch ( d, le, q, clk);
448 6 unneback
input d, le;
449
output q;
450
input clk;
451
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
452
endmodule
453 18 unneback
module vl_shreg ( d, q, clk, rst);
454 17 unneback
parameter depth = 10;
455
input d;
456
output q;
457
input clk, rst;
458
reg [1:depth] dffs;
459
always @ (posedge clk or posedge rst)
460
if (rst)
461
    dffs <= {depth{1'b0}};
462
else
463
    dffs <= {d,dffs[1:depth-1]};
464
assign q = dffs[depth];
465
endmodule
466 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
467 17 unneback
parameter depth = 10;
468
input d, ce;
469
output q;
470
input clk, rst;
471
reg [1:depth] dffs;
472
always @ (posedge clk or posedge rst)
473
if (rst)
474
    dffs <= {depth{1'b0}};
475
else
476
    if (ce)
477
        dffs <= {d,dffs[1:depth-1]};
478
assign q = dffs[depth];
479
endmodule
480 18 unneback
module vl_delay ( d, q, clk, rst);
481 15 unneback
parameter depth = 10;
482
input d;
483
output q;
484
input clk, rst;
485
reg [1:depth] dffs;
486
always @ (posedge clk or posedge rst)
487
if (rst)
488
    dffs <= {depth{1'b0}};
489
else
490
    dffs <= {d,dffs[1:depth-1]};
491
assign q = dffs[depth];
492
endmodule
493 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
494 17 unneback
parameter depth = 10;
495
input d;
496
output q, emptyflag;
497
input clk, rst;
498
reg [1:depth] dffs;
499
always @ (posedge clk or posedge rst)
500
if (rst)
501
    dffs <= {depth{1'b0}};
502
else
503
    dffs <= {d,dffs[1:depth-1]};
504
assign q = dffs[depth];
505
assign emptyflag = !(|dffs);
506
endmodule
507 6 unneback
//////////////////////////////////////////////////////////////////////
508
////                                                              ////
509 18 unneback
////  Logic functions                                             ////
510
////                                                              ////
511
////  Description                                                 ////
512
////  Logic functions such as multiplexers                        ////
513
////                                                              ////
514
////                                                              ////
515
////  To Do:                                                      ////
516
////   -                                                          ////
517
////                                                              ////
518
////  Author(s):                                                  ////
519
////      - Michael Unneback, unneback@opencores.org              ////
520
////        ORSoC AB                                              ////
521
////                                                              ////
522
//////////////////////////////////////////////////////////////////////
523
////                                                              ////
524
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
525
////                                                              ////
526
//// This source file may be used and distributed without         ////
527
//// restriction provided that this copyright statement is not    ////
528
//// removed from the file and that any derivative work contains  ////
529
//// the original copyright notice and the associated disclaimer. ////
530
////                                                              ////
531
//// This source file is free software; you can redistribute it   ////
532
//// and/or modify it under the terms of the GNU Lesser General   ////
533
//// Public License as published by the Free Software Foundation; ////
534
//// either version 2.1 of the License, or (at your option) any   ////
535
//// later version.                                               ////
536
////                                                              ////
537
//// This source is distributed in the hope that it will be       ////
538
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
539
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
540
//// PURPOSE.  See the GNU Lesser General Public License for more ////
541
//// details.                                                     ////
542
////                                                              ////
543
//// You should have received a copy of the GNU Lesser General    ////
544
//// Public License along with this source; if not, download it   ////
545
//// from http://www.opencores.org/lgpl.shtml                     ////
546
////                                                              ////
547
//////////////////////////////////////////////////////////////////////
548 36 unneback
module vl_mux_andor ( a, sel, dout);
549
parameter width = 32;
550
parameter nr_of_ports = 4;
551
input [nr_of_ports*width-1:0] a;
552
input [nr_of_ports-1:0] sel;
553
output reg [width-1:0] dout;
554 38 unneback
integer i,j;
555 36 unneback
always @ (a, sel)
556
begin
557
    dout = a[width-1:0] & {width{sel[0]}};
558 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
559
        for (j=0;j<width;j=j+1)
560
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
561 36 unneback
end
562
endmodule
563 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
564
parameter width = 32;
565 35 unneback
localparam nr_of_ports = 2;
566 34 unneback
input [width-1:0] a1, a0;
567
input [nr_of_ports-1:0] sel;
568
output [width-1:0] dout;
569 36 unneback
vl_mux_andor
570 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
571 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
572 34 unneback
endmodule
573
module vl_mux3_andor ( a2, a1, a0, sel, dout);
574
parameter width = 32;
575 35 unneback
localparam nr_of_ports = 3;
576 34 unneback
input [width-1:0] a2, a1, a0;
577
input [nr_of_ports-1:0] sel;
578
output [width-1:0] dout;
579 36 unneback
vl_mux_andor
580 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
581 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
582 34 unneback
endmodule
583 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
584
parameter width = 32;
585 35 unneback
localparam nr_of_ports = 4;
586 18 unneback
input [width-1:0] a3, a2, a1, a0;
587
input [nr_of_ports-1:0] sel;
588 22 unneback
output [width-1:0] dout;
589 36 unneback
vl_mux_andor
590 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
591 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
592 18 unneback
endmodule
593
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
594
parameter width = 32;
595 35 unneback
localparam nr_of_ports = 5;
596 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
597
input [nr_of_ports-1:0] sel;
598 22 unneback
output [width-1:0] dout;
599 36 unneback
vl_mux_andor
600 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
601 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
602 18 unneback
endmodule
603
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
604
parameter width = 32;
605 35 unneback
localparam nr_of_ports = 6;
606 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
607
input [nr_of_ports-1:0] sel;
608 22 unneback
output [width-1:0] dout;
609 36 unneback
vl_mux_andor
610 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
611 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
612 18 unneback
endmodule
613 43 unneback
module vl_parity_generate (data, parity);
614
parameter word_size = 32;
615
parameter chunk_size = 8;
616
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
617
input [word_size-1:0] data;
618
output reg [word_size/chunk_size-1:0] parity;
619
integer i,j;
620
always @ (data)
621
for (i=0;i<word_size/chunk_size;i=i+1) begin
622
    parity[i] = parity_type;
623
    for (j=0;j<chunk_size;j=j+1) begin
624
        parity[i] = data[i+j] ^ parity[i];
625
    end
626
end
627
endmodule
628
module vl_parity_check( data, parity, parity_error);
629
parameter word_size = 32;
630
parameter chunk_size = 8;
631
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
632
input [word_size-1:0] data;
633
input [word_size/chunk_size-1:0] parity;
634
output parity_error;
635 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
636 43 unneback
integer i,j;
637
always @ (data or parity)
638
for (i=0;i<word_size/chunk_size;i=i+1) begin
639
    error_flag[i] = parity[i] ^ parity_type;
640
    for (j=0;j<chunk_size;j=j+1) begin
641
        error_flag[i] = data[i+j] ^ error_flag[i];
642
    end
643
end
644
assign parity_error = |error_flag;
645
endmodule
646 18 unneback
//////////////////////////////////////////////////////////////////////
647
////                                                              ////
648 44 unneback
////  IO functions                                                ////
649
////                                                              ////
650
////  Description                                                 ////
651
////  IO functions such as IOB flip-flops                         ////
652
////                                                              ////
653
////                                                              ////
654
////  To Do:                                                      ////
655
////   -                                                          ////
656
////                                                              ////
657
////  Author(s):                                                  ////
658
////      - Michael Unneback, unneback@opencores.org              ////
659
////        ORSoC AB                                              ////
660
////                                                              ////
661
//////////////////////////////////////////////////////////////////////
662
////                                                              ////
663
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
664
////                                                              ////
665
//// This source file may be used and distributed without         ////
666
//// restriction provided that this copyright statement is not    ////
667
//// removed from the file and that any derivative work contains  ////
668
//// the original copyright notice and the associated disclaimer. ////
669
////                                                              ////
670
//// This source file is free software; you can redistribute it   ////
671
//// and/or modify it under the terms of the GNU Lesser General   ////
672
//// Public License as published by the Free Software Foundation; ////
673
//// either version 2.1 of the License, or (at your option) any   ////
674
//// later version.                                               ////
675
////                                                              ////
676
//// This source is distributed in the hope that it will be       ////
677
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
678
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
679
//// PURPOSE.  See the GNU Lesser General Public License for more ////
680
//// details.                                                     ////
681
////                                                              ////
682
//// You should have received a copy of the GNU Lesser General    ////
683
//// Public License along with this source; if not, download it   ////
684
//// from http://www.opencores.org/lgpl.shtml                     ////
685
////                                                              ////
686
//////////////////////////////////////////////////////////////////////
687
module vl_o_dff (d_i, o_pad, clk, rst);
688
parameter width = 1;
689
input [width-1:0]  d_i;
690
output [width-1:0] o_pad;
691
input clk, rst;
692
wire [width-1:0] d_i_int `SYN_KEEP;
693
assign d_i_int = d_i;
694
genvar i;
695
for (i=0;i<width;i=i+1) begin
696
    always @ (posedge clk or posedge rst)
697
    if (rst)
698
        o_pad[i] <= 1'b0;
699
    else
700
        o_pad[i] <= d_i_int[i];
701
end
702
endgenerate
703
endmodule
704
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
705
parameter width = 1;
706
input  [width-1:0] d_o;
707
output reg [width-1:0] d_i;
708
input oe;
709
inout [width-1:0] io_pad;
710
input clk, rst;
711
wire [width-1:0] oe_d `SYN_KEEP;
712
reg [width-1:0] oe_q;
713
reg [width-1:0] d_o_q;
714
assign oe_d = {width{oe}};
715
genvar i;
716
generate
717
for (i=0;i<width;i=i+1) begin
718
    always @ (posedge clk or posedge rst)
719
    if (rst)
720
        oe_q[i] <= 1'b0;
721
    else
722
        oe_q[i] <= oe_d[i];
723
    always @ (posedge clk or posedge rst)
724
    if (rst)
725
        d_o_q[i] <= 1'b0;
726
    else
727
        d_o_q[i] <= d_o[i];
728
    always @ (posedge clk or posedge rst)
729
    if (rst)
730
        d_i[i] <= 1'b0;
731
    else
732
        d_i[i] <= io_pad[i];
733
    assign io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
734
end
735
endgenerate
736
endmodule
737
//////////////////////////////////////////////////////////////////////
738
////                                                              ////
739 6 unneback
////  Versatile counter                                           ////
740
////                                                              ////
741
////  Description                                                 ////
742
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
743
////  counter                                                     ////
744
////                                                              ////
745
////  To Do:                                                      ////
746
////   - add LFSR with more taps                                  ////
747
////                                                              ////
748
////  Author(s):                                                  ////
749
////      - Michael Unneback, unneback@opencores.org              ////
750
////        ORSoC AB                                              ////
751
////                                                              ////
752
//////////////////////////////////////////////////////////////////////
753
////                                                              ////
754
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
755
////                                                              ////
756
//// This source file may be used and distributed without         ////
757
//// restriction provided that this copyright statement is not    ////
758
//// removed from the file and that any derivative work contains  ////
759
//// the original copyright notice and the associated disclaimer. ////
760
////                                                              ////
761
//// This source file is free software; you can redistribute it   ////
762
//// and/or modify it under the terms of the GNU Lesser General   ////
763
//// Public License as published by the Free Software Foundation; ////
764
//// either version 2.1 of the License, or (at your option) any   ////
765
//// later version.                                               ////
766
////                                                              ////
767
//// This source is distributed in the hope that it will be       ////
768
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
769
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
770
//// PURPOSE.  See the GNU Lesser General Public License for more ////
771
//// details.                                                     ////
772
////                                                              ////
773
//// You should have received a copy of the GNU Lesser General    ////
774
//// Public License along with this source; if not, download it   ////
775
//// from http://www.opencores.org/lgpl.shtml                     ////
776
////                                                              ////
777
//////////////////////////////////////////////////////////////////////
778
// binary counter
779 40 unneback
module vl_cnt_bin_ce (
780
 cke, q, rst, clk);
781 22 unneback
   parameter length = 4;
782 6 unneback
   input cke;
783
   output [length:1] q;
784
   input rst;
785
   input clk;
786
   parameter clear_value = 0;
787
   parameter set_value = 1;
788
   parameter wrap_value = 0;
789
   parameter level1_value = 15;
790
   reg  [length:1] qi;
791
   wire [length:1] q_next;
792
   assign q_next = qi + {{length-1{1'b0}},1'b1};
793
   always @ (posedge clk or posedge rst)
794
     if (rst)
795
       qi <= {length{1'b0}};
796
     else
797
     if (cke)
798
       qi <= q_next;
799
   assign q = qi;
800
endmodule
801
//////////////////////////////////////////////////////////////////////
802
////                                                              ////
803
////  Versatile counter                                           ////
804
////                                                              ////
805
////  Description                                                 ////
806
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
807
////  counter                                                     ////
808
////                                                              ////
809
////  To Do:                                                      ////
810
////   - add LFSR with more taps                                  ////
811
////                                                              ////
812
////  Author(s):                                                  ////
813
////      - Michael Unneback, unneback@opencores.org              ////
814
////        ORSoC AB                                              ////
815
////                                                              ////
816
//////////////////////////////////////////////////////////////////////
817
////                                                              ////
818
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
819
////                                                              ////
820
//// This source file may be used and distributed without         ////
821
//// restriction provided that this copyright statement is not    ////
822
//// removed from the file and that any derivative work contains  ////
823
//// the original copyright notice and the associated disclaimer. ////
824
////                                                              ////
825
//// This source file is free software; you can redistribute it   ////
826
//// and/or modify it under the terms of the GNU Lesser General   ////
827
//// Public License as published by the Free Software Foundation; ////
828
//// either version 2.1 of the License, or (at your option) any   ////
829
//// later version.                                               ////
830
////                                                              ////
831
//// This source is distributed in the hope that it will be       ////
832
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
833
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
834
//// PURPOSE.  See the GNU Lesser General Public License for more ////
835
//// details.                                                     ////
836
////                                                              ////
837
//// You should have received a copy of the GNU Lesser General    ////
838
//// Public License along with this source; if not, download it   ////
839
//// from http://www.opencores.org/lgpl.shtml                     ////
840
////                                                              ////
841
//////////////////////////////////////////////////////////////////////
842
// binary counter
843 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
844
 cke, rew, zq, level1, rst, clk);
845 6 unneback
   parameter length = 4;
846
   input cke;
847
   input rew;
848 25 unneback
   output reg zq;
849
   output reg level1;
850
   input rst;
851
   input clk;
852
   parameter clear_value = 0;
853
   parameter set_value = 1;
854
   parameter wrap_value = 1;
855
   parameter level1_value = 15;
856 29 unneback
   wire clear;
857 30 unneback
   assign clear = 1'b0;
858 25 unneback
   reg  [length:1] qi;
859
   wire  [length:1] q_next, q_next_fw, q_next_rew;
860
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
861
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
862
   assign q_next = rew ? q_next_rew : q_next_fw;
863
   always @ (posedge clk or posedge rst)
864
     if (rst)
865
       qi <= {length{1'b0}};
866
     else
867
     if (cke)
868
       qi <= q_next;
869
   always @ (posedge clk or posedge rst)
870
     if (rst)
871
       zq <= 1'b1;
872
     else
873
     if (cke)
874
       zq <= q_next == {length{1'b0}};
875
    always @ (posedge clk or posedge rst)
876
    if (rst)
877
        level1 <= 1'b0;
878
    else
879
    if (cke)
880 29 unneback
    if (clear)
881
        level1 <= 1'b0;
882
    else if (q_next == level1_value)
883 25 unneback
        level1 <= 1'b1;
884
    else if (qi == level1_value & rew)
885
        level1 <= 1'b0;
886
endmodule
887
//////////////////////////////////////////////////////////////////////
888
////                                                              ////
889
////  Versatile counter                                           ////
890
////                                                              ////
891
////  Description                                                 ////
892
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
893
////  counter                                                     ////
894
////                                                              ////
895
////  To Do:                                                      ////
896
////   - add LFSR with more taps                                  ////
897
////                                                              ////
898
////  Author(s):                                                  ////
899
////      - Michael Unneback, unneback@opencores.org              ////
900
////        ORSoC AB                                              ////
901
////                                                              ////
902
//////////////////////////////////////////////////////////////////////
903
////                                                              ////
904
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
905
////                                                              ////
906
//// This source file may be used and distributed without         ////
907
//// restriction provided that this copyright statement is not    ////
908
//// removed from the file and that any derivative work contains  ////
909
//// the original copyright notice and the associated disclaimer. ////
910
////                                                              ////
911
//// This source file is free software; you can redistribute it   ////
912
//// and/or modify it under the terms of the GNU Lesser General   ////
913
//// Public License as published by the Free Software Foundation; ////
914
//// either version 2.1 of the License, or (at your option) any   ////
915
//// later version.                                               ////
916
////                                                              ////
917
//// This source is distributed in the hope that it will be       ////
918
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
919
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
920
//// PURPOSE.  See the GNU Lesser General Public License for more ////
921
//// details.                                                     ////
922
////                                                              ////
923
//// You should have received a copy of the GNU Lesser General    ////
924
//// Public License along with this source; if not, download it   ////
925
//// from http://www.opencores.org/lgpl.shtml                     ////
926
////                                                              ////
927
//////////////////////////////////////////////////////////////////////
928
// binary counter
929 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
930
 cke, rew, q, zq, level1, rst, clk);
931 25 unneback
   parameter length = 4;
932
   input cke;
933
   input rew;
934
   output [length:1] q;
935
   output reg zq;
936
   output reg level1;
937
   input rst;
938
   input clk;
939
   parameter clear_value = 0;
940
   parameter set_value = 1;
941
   parameter wrap_value = 1;
942
   parameter level1_value = 15;
943 29 unneback
   wire clear;
944 30 unneback
   assign clear = 1'b0;
945 25 unneback
   reg  [length:1] qi;
946
   wire  [length:1] q_next, q_next_fw, q_next_rew;
947
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
948
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
949
   assign q_next = rew ? q_next_rew : q_next_fw;
950
   always @ (posedge clk or posedge rst)
951
     if (rst)
952
       qi <= {length{1'b0}};
953
     else
954
     if (cke)
955
       qi <= q_next;
956
   assign q = qi;
957
   always @ (posedge clk or posedge rst)
958
     if (rst)
959
       zq <= 1'b1;
960
     else
961
     if (cke)
962
       zq <= q_next == {length{1'b0}};
963
    always @ (posedge clk or posedge rst)
964
    if (rst)
965
        level1 <= 1'b0;
966
    else
967
    if (cke)
968 29 unneback
    if (clear)
969
        level1 <= 1'b0;
970
    else if (q_next == level1_value)
971 25 unneback
        level1 <= 1'b1;
972
    else if (qi == level1_value & rew)
973
        level1 <= 1'b0;
974
endmodule
975
//////////////////////////////////////////////////////////////////////
976
////                                                              ////
977
////  Versatile counter                                           ////
978
////                                                              ////
979
////  Description                                                 ////
980
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
981
////  counter                                                     ////
982
////                                                              ////
983
////  To Do:                                                      ////
984
////   - add LFSR with more taps                                  ////
985
////                                                              ////
986
////  Author(s):                                                  ////
987
////      - Michael Unneback, unneback@opencores.org              ////
988
////        ORSoC AB                                              ////
989
////                                                              ////
990
//////////////////////////////////////////////////////////////////////
991
////                                                              ////
992
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
993
////                                                              ////
994
//// This source file may be used and distributed without         ////
995
//// restriction provided that this copyright statement is not    ////
996
//// removed from the file and that any derivative work contains  ////
997
//// the original copyright notice and the associated disclaimer. ////
998
////                                                              ////
999
//// This source file is free software; you can redistribute it   ////
1000
//// and/or modify it under the terms of the GNU Lesser General   ////
1001
//// Public License as published by the Free Software Foundation; ////
1002
//// either version 2.1 of the License, or (at your option) any   ////
1003
//// later version.                                               ////
1004
////                                                              ////
1005
//// This source is distributed in the hope that it will be       ////
1006
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1007
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1008
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1009
//// details.                                                     ////
1010
////                                                              ////
1011
//// You should have received a copy of the GNU Lesser General    ////
1012
//// Public License along with this source; if not, download it   ////
1013
//// from http://www.opencores.org/lgpl.shtml                     ////
1014
////                                                              ////
1015
//////////////////////////////////////////////////////////////////////
1016 6 unneback
// GRAY counter
1017 40 unneback
module vl_cnt_gray_ce_bin (
1018
 cke, q, q_bin, rst, clk);
1019 6 unneback
   parameter length = 4;
1020
   input cke;
1021
   output reg [length:1] q;
1022
   output [length:1] q_bin;
1023
   input rst;
1024
   input clk;
1025
   parameter clear_value = 0;
1026
   parameter set_value = 1;
1027
   parameter wrap_value = 8;
1028
   parameter level1_value = 15;
1029
   reg  [length:1] qi;
1030
   wire [length:1] q_next;
1031
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1032
   always @ (posedge clk or posedge rst)
1033
     if (rst)
1034
       qi <= {length{1'b0}};
1035
     else
1036
     if (cke)
1037
       qi <= q_next;
1038
   always @ (posedge clk or posedge rst)
1039
     if (rst)
1040
       q <= {length{1'b0}};
1041
     else
1042
       if (cke)
1043
         q <= (q_next>>1) ^ q_next;
1044
   assign q_bin = qi;
1045
endmodule
1046
//////////////////////////////////////////////////////////////////////
1047
////                                                              ////
1048
////  Versatile library, counters                                 ////
1049
////                                                              ////
1050
////  Description                                                 ////
1051
////  counters                                                    ////
1052
////                                                              ////
1053
////                                                              ////
1054
////  To Do:                                                      ////
1055
////   - add more counters                                        ////
1056
////                                                              ////
1057
////  Author(s):                                                  ////
1058
////      - Michael Unneback, unneback@opencores.org              ////
1059
////        ORSoC AB                                              ////
1060
////                                                              ////
1061
//////////////////////////////////////////////////////////////////////
1062
////                                                              ////
1063
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1064
////                                                              ////
1065
//// This source file may be used and distributed without         ////
1066
//// restriction provided that this copyright statement is not    ////
1067
//// removed from the file and that any derivative work contains  ////
1068
//// the original copyright notice and the associated disclaimer. ////
1069
////                                                              ////
1070
//// This source file is free software; you can redistribute it   ////
1071
//// and/or modify it under the terms of the GNU Lesser General   ////
1072
//// Public License as published by the Free Software Foundation; ////
1073
//// either version 2.1 of the License, or (at your option) any   ////
1074
//// later version.                                               ////
1075
////                                                              ////
1076
//// This source is distributed in the hope that it will be       ////
1077
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1078
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1079
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1080
//// details.                                                     ////
1081
////                                                              ////
1082
//// You should have received a copy of the GNU Lesser General    ////
1083
//// Public License along with this source; if not, download it   ////
1084
//// from http://www.opencores.org/lgpl.shtml                     ////
1085
////                                                              ////
1086
//////////////////////////////////////////////////////////////////////
1087 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1088 6 unneback
   parameter length = 4;
1089
   output reg [0:length-1] q;
1090
   input rst;
1091
   input clk;
1092
    always @ (posedge clk or posedge rst)
1093
    if (rst)
1094
        q <= {1'b1,{length-1{1'b0}}};
1095
    else
1096
        q <= {q[length-1],q[0:length-2]};
1097
endmodule
1098 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1099 6 unneback
   parameter length = 4;
1100
   input cke;
1101
   output reg [0:length-1] q;
1102
   input rst;
1103
   input clk;
1104
    always @ (posedge clk or posedge rst)
1105
    if (rst)
1106
        q <= {1'b1,{length-1{1'b0}}};
1107
    else
1108
        if (cke)
1109
            q <= {q[length-1],q[0:length-2]};
1110
endmodule
1111 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1112 6 unneback
   parameter length = 4;
1113
   input cke, clear;
1114
   output reg [0:length-1] q;
1115
   input rst;
1116
   input clk;
1117
    always @ (posedge clk or posedge rst)
1118
    if (rst)
1119
        q <= {1'b1,{length-1{1'b0}}};
1120
    else
1121
        if (cke)
1122
            if (clear)
1123
                q <= {1'b1,{length-1{1'b0}}};
1124
            else
1125
                q <= q >> 1;
1126
endmodule
1127 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1128 6 unneback
   parameter length = 4;
1129
   input cke, clear;
1130
   output reg [0:length-1] q;
1131
   input rst;
1132
   input clk;
1133
    always @ (posedge clk or posedge rst)
1134
    if (rst)
1135
        q <= {1'b1,{length-1{1'b0}}};
1136
    else
1137
        if (cke)
1138
            if (clear)
1139
                q <= {1'b1,{length-1{1'b0}}};
1140
            else
1141
            q <= {q[length-1],q[0:length-2]};
1142
endmodule
1143
//////////////////////////////////////////////////////////////////////
1144
////                                                              ////
1145
////  Versatile library, memories                                 ////
1146
////                                                              ////
1147
////  Description                                                 ////
1148
////  memories                                                    ////
1149
////                                                              ////
1150
////                                                              ////
1151
////  To Do:                                                      ////
1152
////   - add more memory types                                    ////
1153
////                                                              ////
1154
////  Author(s):                                                  ////
1155
////      - Michael Unneback, unneback@opencores.org              ////
1156
////        ORSoC AB                                              ////
1157
////                                                              ////
1158
//////////////////////////////////////////////////////////////////////
1159
////                                                              ////
1160
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1161
////                                                              ////
1162
//// This source file may be used and distributed without         ////
1163
//// restriction provided that this copyright statement is not    ////
1164
//// removed from the file and that any derivative work contains  ////
1165
//// the original copyright notice and the associated disclaimer. ////
1166
////                                                              ////
1167
//// This source file is free software; you can redistribute it   ////
1168
//// and/or modify it under the terms of the GNU Lesser General   ////
1169
//// Public License as published by the Free Software Foundation; ////
1170
//// either version 2.1 of the License, or (at your option) any   ////
1171
//// later version.                                               ////
1172
////                                                              ////
1173
//// This source is distributed in the hope that it will be       ////
1174
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1175
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1176
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1177
//// details.                                                     ////
1178
////                                                              ////
1179
//// You should have received a copy of the GNU Lesser General    ////
1180
//// Public License along with this source; if not, download it   ////
1181
//// from http://www.opencores.org/lgpl.shtml                     ////
1182
////                                                              ////
1183
//////////////////////////////////////////////////////////////////////
1184
/// ROM
1185 7 unneback
module vl_rom_init ( adr, q, clk);
1186
   parameter data_width = 32;
1187
   parameter addr_width = 8;
1188
   input [(addr_width-1):0]       adr;
1189
   output reg [(data_width-1):0] q;
1190
   input                         clk;
1191
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1192
   parameter memory_file = "vl_rom.vmem";
1193
   initial
1194
     begin
1195
        $readmemh(memory_file, rom);
1196
     end
1197
   always @ (posedge clk)
1198
     q <= rom[adr];
1199
endmodule
1200 14 unneback
/*
1201 7 unneback
module vl_rom ( adr, q, clk);
1202 6 unneback
parameter data_width = 32;
1203
parameter addr_width = 4;
1204
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1205
    {32'h18000000},
1206
    {32'hA8200000},
1207
    {32'hA8200000},
1208
    {32'hA8200000},
1209
    {32'h44003000},
1210
    {32'h15000000},
1211
    {32'h15000000},
1212
    {32'h15000000},
1213
    {32'h15000000},
1214
    {32'h15000000},
1215
    {32'h15000000},
1216
    {32'h15000000},
1217
    {32'h15000000},
1218
    {32'h15000000},
1219
    {32'h15000000},
1220
    {32'h15000000}};
1221 7 unneback
input [addr_width-1:0] adr;
1222 6 unneback
output reg [data_width-1:0] q;
1223
input clk;
1224
always @ (posedge clk)
1225 7 unneback
    q <= data[adr];
1226 6 unneback
endmodule
1227 14 unneback
*/
1228 6 unneback
// Single port RAM
1229
module vl_ram ( d, adr, we, q, clk);
1230
   parameter data_width = 32;
1231
   parameter addr_width = 8;
1232
   input [(data_width-1):0]      d;
1233
   input [(addr_width-1):0]       adr;
1234
   input                         we;
1235 7 unneback
   output reg [(data_width-1):0] q;
1236 6 unneback
   input                         clk;
1237
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1238 7 unneback
   parameter init = 0;
1239
   parameter memory_file = "vl_ram.vmem";
1240
   generate if (init) begin : init_mem
1241
   initial
1242
     begin
1243
        $readmemh(memory_file, ram);
1244
     end
1245
   end
1246
   endgenerate
1247 6 unneback
   always @ (posedge clk)
1248
   begin
1249
   if (we)
1250
     ram[adr] <= d;
1251
   q <= ram[adr];
1252
   end
1253
endmodule
1254 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1255
   parameter data_width = 32;
1256
   parameter addr_width = 8;
1257
   input [(data_width-1):0]      d;
1258
   input [(addr_width-1):0]       adr;
1259
   input [(addr_width/4)-1:0]    be;
1260
   input                         we;
1261
   output reg [(data_width-1):0] q;
1262
   input                         clk;
1263
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1264
   parameter init = 0;
1265
   parameter memory_file = "vl_ram.vmem";
1266
   generate if (init) begin : init_mem
1267
   initial
1268
     begin
1269
        $readmemh(memory_file, ram);
1270
     end
1271
   end
1272
   endgenerate
1273
   genvar i;
1274
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1275
      always @ (posedge clk)
1276
      if (we & be[i])
1277
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1278
   end
1279
   endgenerate
1280
   always @ (posedge clk)
1281
      q <= ram[adr];
1282
endmodule
1283 6 unneback
// Dual port RAM
1284
// ACTEL FPGA should not use logic to handle rw collision
1285 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1286 6 unneback
   parameter data_width = 32;
1287
   parameter addr_width = 8;
1288
   input [(data_width-1):0]      d_a;
1289
   input [(addr_width-1):0]       adr_a;
1290
   input [(addr_width-1):0]       adr_b;
1291
   input                         we_a;
1292
   output [(data_width-1):0]      q_b;
1293
   input                         clk_a, clk_b;
1294
   reg [(addr_width-1):0]         adr_b_reg;
1295
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1296 7 unneback
   parameter init = 0;
1297
   parameter memory_file = "vl_ram.vmem";
1298
   generate if (init) begin : init_mem
1299
   initial
1300
     begin
1301
        $readmemh(memory_file, ram);
1302
     end
1303
   end
1304
   endgenerate
1305 6 unneback
   always @ (posedge clk_a)
1306
   if (we_a)
1307
     ram[adr_a] <= d_a;
1308
   always @ (posedge clk_b)
1309
   adr_b_reg <= adr_b;
1310
   assign q_b = ram[adr_b_reg];
1311
endmodule
1312 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1313 6 unneback
   parameter data_width = 32;
1314
   parameter addr_width = 8;
1315
   input [(data_width-1):0]      d_a;
1316
   input [(addr_width-1):0]       adr_a;
1317
   input [(addr_width-1):0]       adr_b;
1318
   input                         we_a;
1319
   output [(data_width-1):0]      q_b;
1320
   output reg [(data_width-1):0] q_a;
1321
   input                         clk_a, clk_b;
1322
   reg [(data_width-1):0]         q_b;
1323
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1324 7 unneback
   parameter init = 0;
1325
   parameter memory_file = "vl_ram.vmem";
1326
   generate if (init) begin : init_mem
1327
   initial
1328
     begin
1329
        $readmemh(memory_file, ram);
1330
     end
1331
   end
1332
   endgenerate
1333 6 unneback
   always @ (posedge clk_a)
1334
     begin
1335
        q_a <= ram[adr_a];
1336
        if (we_a)
1337
             ram[adr_a] <= d_a;
1338
     end
1339
   always @ (posedge clk_b)
1340
          q_b <= ram[adr_b];
1341
endmodule
1342 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1343 6 unneback
   parameter data_width = 32;
1344
   parameter addr_width = 8;
1345
   input [(data_width-1):0]      d_a;
1346
   input [(addr_width-1):0]       adr_a;
1347
   input [(addr_width-1):0]       adr_b;
1348
   input                         we_a;
1349
   output [(data_width-1):0]      q_b;
1350
   input [(data_width-1):0]       d_b;
1351
   output reg [(data_width-1):0] q_a;
1352
   input                         we_b;
1353
   input                         clk_a, clk_b;
1354
   reg [(data_width-1):0]         q_b;
1355
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1356 7 unneback
   parameter init = 0;
1357
   parameter memory_file = "vl_ram.vmem";
1358
   generate if (init) begin : init_mem
1359
   initial
1360
     begin
1361
        $readmemh(memory_file, ram);
1362
     end
1363
   end
1364
   endgenerate
1365 6 unneback
   always @ (posedge clk_a)
1366
     begin
1367
        q_a <= ram[adr_a];
1368
        if (we_a)
1369
             ram[adr_a] <= d_a;
1370
     end
1371
   always @ (posedge clk_b)
1372
     begin
1373
        q_b <= ram[adr_b];
1374
        if (we_b)
1375
          ram[adr_b] <= d_b;
1376
     end
1377
endmodule
1378
// Content addresable memory, CAM
1379
// FIFO
1380 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1381
    d, wr, fifo_full,
1382
    q, rd, fifo_empty,
1383
    fill_level,
1384
    clk, rst
1385
    );
1386
parameter data_width = 18;
1387
parameter addr_width = 4;
1388
// write side
1389
input  [data_width-1:0] d;
1390
input                   wr;
1391
output                  fifo_full;
1392
// read side
1393
output [data_width-1:0] q;
1394
input                   rd;
1395
output                  fifo_empty;
1396
// common
1397
output [addr_width:0]   fill_level;
1398
input rst, clk;
1399
wire [addr_width:1] wadr, radr;
1400
vl_cnt_bin_ce
1401
    # ( .length(addr_width))
1402
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1403
vl_cnt_bin_ce
1404
    # (.length(addr_width))
1405
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1406
vl_dpram_1r1w
1407
    # (.data_width(data_width), .addr_width(addr_width))
1408
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1409 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1410 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1411 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1412
endmodule
1413 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1414
// RAM is supposed to be larger than the two FIFOs
1415
// LFSR counters used adr pointers
1416
module vl_fifo_2r2w_sync_simplex (
1417
    // a side
1418
    a_d, a_wr, a_fifo_full,
1419
    a_q, a_rd, a_fifo_empty,
1420
    a_fill_level,
1421
    // b side
1422
    b_d, b_wr, b_fifo_full,
1423
    b_q, b_rd, b_fifo_empty,
1424
    b_fill_level,
1425
    // common
1426
    clk, rst
1427
    );
1428
parameter data_width = 8;
1429
parameter addr_width = 5;
1430
parameter fifo_full_level = (1<<addr_width)-1;
1431
// a side
1432
input  [data_width-1:0] a_d;
1433
input                   a_wr;
1434
output                  a_fifo_full;
1435
output [data_width-1:0] a_q;
1436
input                   a_rd;
1437
output                  a_fifo_empty;
1438
output [addr_width-1:0] a_fill_level;
1439
// b side
1440
input  [data_width-1:0] b_d;
1441
input                   b_wr;
1442
output                  b_fifo_full;
1443
output [data_width-1:0] b_q;
1444
input                   b_rd;
1445
output                  b_fifo_empty;
1446
output [addr_width-1:0] b_fill_level;
1447
input                   clk;
1448
input                   rst;
1449
// adr_gen
1450
wire [addr_width:1] a_wadr, a_radr;
1451
wire [addr_width:1] b_wadr, b_radr;
1452
// dpram
1453
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1454
vl_cnt_lfsr_ce
1455
    # ( .length(addr_width))
1456
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1457
vl_cnt_lfsr_ce
1458
    # (.length(addr_width))
1459
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1460
vl_cnt_lfsr_ce
1461
    # ( .length(addr_width))
1462
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1463
vl_cnt_lfsr_ce
1464
    # (.length(addr_width))
1465
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1466
// mux read or write adr to DPRAM
1467
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1468
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1469
vl_dpram_2r2w
1470
    # (.data_width(data_width), .addr_width(addr_width+1))
1471
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1472
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1473
vl_cnt_bin_ce_rew_zq_l1
1474 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1475 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1476
vl_cnt_bin_ce_rew_zq_l1
1477 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1478 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1479
endmodule
1480 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1481 11 unneback
   parameter addr_width = 4;
1482
   parameter N = addr_width-1;
1483 6 unneback
   parameter Q1 = 2'b00;
1484
   parameter Q2 = 2'b01;
1485
   parameter Q3 = 2'b11;
1486
   parameter Q4 = 2'b10;
1487
   parameter going_empty = 1'b0;
1488
   parameter going_full  = 1'b1;
1489
   input [N:0]  wptr, rptr;
1490 14 unneback
   output       fifo_empty;
1491 6 unneback
   output       fifo_full;
1492
   input        wclk, rclk, rst;
1493
   wire direction;
1494
   reg  direction_set, direction_clr;
1495
   wire async_empty, async_full;
1496
   wire fifo_full2;
1497 14 unneback
   wire fifo_empty2;
1498 6 unneback
   // direction_set
1499
   always @ (wptr[N:N-1] or rptr[N:N-1])
1500
     case ({wptr[N:N-1],rptr[N:N-1]})
1501
       {Q1,Q2} : direction_set <= 1'b1;
1502
       {Q2,Q3} : direction_set <= 1'b1;
1503
       {Q3,Q4} : direction_set <= 1'b1;
1504
       {Q4,Q1} : direction_set <= 1'b1;
1505
       default : direction_set <= 1'b0;
1506
     endcase
1507
   // direction_clear
1508
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1509
     if (rst)
1510
       direction_clr <= 1'b1;
1511
     else
1512
       case ({wptr[N:N-1],rptr[N:N-1]})
1513
         {Q2,Q1} : direction_clr <= 1'b1;
1514
         {Q3,Q2} : direction_clr <= 1'b1;
1515
         {Q4,Q3} : direction_clr <= 1'b1;
1516
         {Q1,Q4} : direction_clr <= 1'b1;
1517
         default : direction_clr <= 1'b0;
1518
       endcase
1519 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1520 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1521
   assign async_full  = (wptr == rptr) && (direction==going_full);
1522 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1523
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1524 6 unneback
/*
1525
   always @ (posedge wclk or posedge rst or posedge async_full)
1526
     if (rst)
1527
       {fifo_full, fifo_full2} <= 2'b00;
1528
     else if (async_full)
1529
       {fifo_full, fifo_full2} <= 2'b11;
1530
     else
1531
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1532
*/
1533 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1534 6 unneback
     if (async_empty)
1535
       {fifo_empty, fifo_empty2} <= 2'b11;
1536
     else
1537 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1538 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1539
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1540 27 unneback
endmodule // async_compb
1541 6 unneback
module vl_fifo_1r1w_async (
1542
    d, wr, fifo_full, wr_clk, wr_rst,
1543
    q, rd, fifo_empty, rd_clk, rd_rst
1544
    );
1545
parameter data_width = 18;
1546
parameter addr_width = 4;
1547
// write side
1548
input  [data_width-1:0] d;
1549
input                   wr;
1550
output                  fifo_full;
1551
input                   wr_clk;
1552
input                   wr_rst;
1553
// read side
1554
output [data_width-1:0] q;
1555
input                   rd;
1556
output                  fifo_empty;
1557
input                   rd_clk;
1558
input                   rd_rst;
1559
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1560 18 unneback
vl_cnt_gray_ce_bin
1561 6 unneback
    # ( .length(addr_width))
1562
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1563 18 unneback
vl_cnt_gray_ce_bin
1564 6 unneback
    # (.length(addr_width))
1565 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1566 7 unneback
vl_dpram_1r1w
1567 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1568
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1569
vl_fifo_cmp_async
1570
    # (.addr_width(addr_width))
1571
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1572
endmodule
1573 8 unneback
module vl_fifo_2r2w_async (
1574 6 unneback
    // a side
1575
    a_d, a_wr, a_fifo_full,
1576
    a_q, a_rd, a_fifo_empty,
1577
    a_clk, a_rst,
1578
    // b side
1579
    b_d, b_wr, b_fifo_full,
1580
    b_q, b_rd, b_fifo_empty,
1581
    b_clk, b_rst
1582
    );
1583
parameter data_width = 18;
1584
parameter addr_width = 4;
1585
// a side
1586
input  [data_width-1:0] a_d;
1587
input                   a_wr;
1588
output                  a_fifo_full;
1589
output [data_width-1:0] a_q;
1590
input                   a_rd;
1591
output                  a_fifo_empty;
1592
input                   a_clk;
1593
input                   a_rst;
1594
// b side
1595
input  [data_width-1:0] b_d;
1596
input                   b_wr;
1597
output                  b_fifo_full;
1598
output [data_width-1:0] b_q;
1599
input                   b_rd;
1600
output                  b_fifo_empty;
1601
input                   b_clk;
1602
input                   b_rst;
1603
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1604
vl_fifo_1r1w_async_a (
1605
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1606
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1607
    );
1608
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1609
vl_fifo_1r1w_async_b (
1610
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1611
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1612
    );
1613
endmodule
1614 8 unneback
module vl_fifo_2r2w_async_simplex (
1615 6 unneback
    // a side
1616
    a_d, a_wr, a_fifo_full,
1617
    a_q, a_rd, a_fifo_empty,
1618
    a_clk, a_rst,
1619
    // b side
1620
    b_d, b_wr, b_fifo_full,
1621
    b_q, b_rd, b_fifo_empty,
1622
    b_clk, b_rst
1623
    );
1624
parameter data_width = 18;
1625
parameter addr_width = 4;
1626
// a side
1627
input  [data_width-1:0] a_d;
1628
input                   a_wr;
1629
output                  a_fifo_full;
1630
output [data_width-1:0] a_q;
1631
input                   a_rd;
1632
output                  a_fifo_empty;
1633
input                   a_clk;
1634
input                   a_rst;
1635
// b side
1636
input  [data_width-1:0] b_d;
1637
input                   b_wr;
1638
output                  b_fifo_full;
1639
output [data_width-1:0] b_q;
1640
input                   b_rd;
1641
output                  b_fifo_empty;
1642
input                   b_clk;
1643
input                   b_rst;
1644
// adr_gen
1645
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1646
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1647
// dpram
1648
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1649 18 unneback
vl_cnt_gray_ce_bin
1650 6 unneback
    # ( .length(addr_width))
1651
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1652 18 unneback
vl_cnt_gray_ce_bin
1653 6 unneback
    # (.length(addr_width))
1654
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1655 18 unneback
vl_cnt_gray_ce_bin
1656 6 unneback
    # ( .length(addr_width))
1657
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1658 18 unneback
vl_cnt_gray_ce_bin
1659 6 unneback
    # (.length(addr_width))
1660
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1661
// mux read or write adr to DPRAM
1662
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1663
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1664 11 unneback
vl_dpram_2r2w
1665 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1666
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1667
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1668 11 unneback
vl_fifo_cmp_async
1669 6 unneback
    # (.addr_width(addr_width))
1670
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1671 11 unneback
vl_fifo_cmp_async
1672 6 unneback
    # (.addr_width(addr_width))
1673
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1674
endmodule
1675 12 unneback
//////////////////////////////////////////////////////////////////////
1676
////                                                              ////
1677
////  Versatile library, wishbone stuff                           ////
1678
////                                                              ////
1679
////  Description                                                 ////
1680
////  Wishbone compliant modules                                  ////
1681
////                                                              ////
1682
////                                                              ////
1683
////  To Do:                                                      ////
1684
////   -                                                          ////
1685
////                                                              ////
1686
////  Author(s):                                                  ////
1687
////      - Michael Unneback, unneback@opencores.org              ////
1688
////        ORSoC AB                                              ////
1689
////                                                              ////
1690
//////////////////////////////////////////////////////////////////////
1691
////                                                              ////
1692
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1693
////                                                              ////
1694
//// This source file may be used and distributed without         ////
1695
//// restriction provided that this copyright statement is not    ////
1696
//// removed from the file and that any derivative work contains  ////
1697
//// the original copyright notice and the associated disclaimer. ////
1698
////                                                              ////
1699
//// This source file is free software; you can redistribute it   ////
1700
//// and/or modify it under the terms of the GNU Lesser General   ////
1701
//// Public License as published by the Free Software Foundation; ////
1702
//// either version 2.1 of the License, or (at your option) any   ////
1703
//// later version.                                               ////
1704
////                                                              ////
1705
//// This source is distributed in the hope that it will be       ////
1706
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1707
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1708
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1709
//// details.                                                     ////
1710
////                                                              ////
1711
//// You should have received a copy of the GNU Lesser General    ////
1712
//// Public License along with this source; if not, download it   ////
1713
//// from http://www.opencores.org/lgpl.shtml                     ////
1714
////                                                              ////
1715
//////////////////////////////////////////////////////////////////////
1716
// async wb3 - wb3 bridge
1717
`timescale 1ns/1ns
1718 18 unneback
module vl_wb3wb3_bridge (
1719 12 unneback
        // wishbone slave side
1720
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1721
        // wishbone master side
1722
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1723
input [31:0] wbs_dat_i;
1724
input [31:2] wbs_adr_i;
1725
input [3:0]  wbs_sel_i;
1726
input [1:0]  wbs_bte_i;
1727
input [2:0]  wbs_cti_i;
1728
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1729
output [31:0] wbs_dat_o;
1730 14 unneback
output wbs_ack_o;
1731 12 unneback
input wbs_clk, wbs_rst;
1732
output [31:0] wbm_dat_o;
1733
output reg [31:2] wbm_adr_o;
1734
output [3:0]  wbm_sel_o;
1735
output reg [1:0]  wbm_bte_o;
1736
output reg [2:0]  wbm_cti_o;
1737 14 unneback
output reg wbm_we_o;
1738
output wbm_cyc_o;
1739 12 unneback
output wbm_stb_o;
1740
input [31:0]  wbm_dat_i;
1741
input wbm_ack_i;
1742
input wbm_clk, wbm_rst;
1743
parameter addr_width = 4;
1744
// bte
1745
parameter linear       = 2'b00;
1746
parameter wrap4        = 2'b01;
1747
parameter wrap8        = 2'b10;
1748
parameter wrap16       = 2'b11;
1749
// cti
1750
parameter classic      = 3'b000;
1751
parameter incburst     = 3'b010;
1752
parameter endofburst   = 3'b111;
1753
parameter wbs_adr  = 1'b0;
1754
parameter wbs_data = 1'b1;
1755 33 unneback
parameter wbm_adr0      = 2'b00;
1756
parameter wbm_adr1      = 2'b01;
1757
parameter wbm_data      = 2'b10;
1758
parameter wbm_data_wait = 2'b11;
1759 12 unneback
reg [1:0] wbs_bte_reg;
1760
reg wbs;
1761
wire wbs_eoc_alert, wbm_eoc_alert;
1762
reg wbs_eoc, wbm_eoc;
1763
reg [1:0] wbm;
1764 14 unneback
wire [1:16] wbs_count, wbm_count;
1765 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1766
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1767
reg a_rd_reg;
1768
wire b_rd_adr, b_rd_data;
1769 14 unneback
wire b_rd_data_reg;
1770
wire [35:0] temp;
1771 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1772
always @ (posedge wbs_clk or posedge wbs_rst)
1773
if (wbs_rst)
1774
        wbs_eoc <= 1'b0;
1775
else
1776
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1777
                wbs_eoc <= wbs_bte_i==linear;
1778
        else if (wbs_eoc_alert & (a_rd | a_wr))
1779
                wbs_eoc <= 1'b1;
1780 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1781 12 unneback
    cnt0 (
1782
        .cke(wbs_ack_o),
1783
        .clear(wbs_eoc),
1784
        .q(wbs_count),
1785
        .rst(wbs_rst),
1786
        .clk(wbs_clk));
1787
always @ (posedge wbs_clk or posedge wbs_rst)
1788
if (wbs_rst)
1789
        wbs <= wbs_adr;
1790
else
1791
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1792
                wbs <= wbs_data;
1793
        else if (wbs_eoc & wbs_ack_o)
1794
                wbs <= wbs_adr;
1795
// wbs FIFO
1796
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1797
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1798
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1799
              1'b0;
1800
assign a_rd = !a_fifo_empty;
1801
always @ (posedge wbs_clk or posedge wbs_rst)
1802
if (wbs_rst)
1803
        a_rd_reg <= 1'b0;
1804
else
1805
        a_rd_reg <= a_rd;
1806
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1807
assign wbs_dat_o = a_q[35:4];
1808
always @ (posedge wbs_clk or posedge wbs_rst)
1809
if (wbs_rst)
1810 13 unneback
        wbs_bte_reg <= 2'b00;
1811 12 unneback
else
1812 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1813 12 unneback
// wbm FIFO
1814
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1815
always @ (posedge wbm_clk or posedge wbm_rst)
1816
if (wbm_rst)
1817
        wbm_eoc <= 1'b0;
1818
else
1819
        if (wbm==wbm_adr0 & !b_fifo_empty)
1820
                wbm_eoc <= b_q[4:3] == linear;
1821
        else if (wbm_eoc_alert & wbm_ack_i)
1822
                wbm_eoc <= 1'b1;
1823
always @ (posedge wbm_clk or posedge wbm_rst)
1824
if (wbm_rst)
1825
        wbm <= wbm_adr0;
1826
else
1827 33 unneback
/*
1828 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1829
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1830
        (wbm==wbm_adr1 & !wbm_we_o) |
1831
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1832
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1833 33 unneback
*/
1834
    case (wbm)
1835
    wbm_adr0:
1836
        if (!b_fifo_empty)
1837
            wbm <= wbm_adr1;
1838
    wbm_adr1:
1839
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1840
            wbm <= wbm_data;
1841
    wbm_data:
1842
        if (wbm_ack_i & wbm_eoc)
1843
            wbm <= wbm_adr0;
1844
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1845
            wbm <= wbm_data_wait;
1846
    wbm_data_wait:
1847
        if (!b_fifo_empty)
1848
            wbm <= wbm_data;
1849
    endcase
1850 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1851
assign b_wr = !wbm_we_o & wbm_ack_i;
1852
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1853
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1854
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1855 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1856 12 unneback
                   1'b0;
1857
assign b_rd = b_rd_adr | b_rd_data;
1858 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1859
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1860 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1861 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1862 12 unneback
    cnt1 (
1863
        .cke(wbm_ack_i),
1864
        .clear(wbm_eoc),
1865
        .q(wbm_count),
1866
        .rst(wbm_rst),
1867
        .clk(wbm_clk));
1868 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1869
assign wbm_stb_o = (wbm==wbm_data);
1870 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1871
if (wbm_rst)
1872
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1873
else begin
1874
        if (wbm==wbm_adr0 & !b_fifo_empty)
1875
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1876
        else if (wbm_eoc_alert & wbm_ack_i)
1877
                wbm_cti_o <= endofburst;
1878
end
1879
//async_fifo_dw_simplex_top
1880
vl_fifo_2r2w_async_simplex
1881
# ( .data_width(36), .addr_width(addr_width))
1882
fifo (
1883
    // a side
1884
    .a_d(a_d),
1885
    .a_wr(a_wr),
1886
    .a_fifo_full(a_fifo_full),
1887
    .a_q(a_q),
1888
    .a_rd(a_rd),
1889
    .a_fifo_empty(a_fifo_empty),
1890
    .a_clk(wbs_clk),
1891
    .a_rst(wbs_rst),
1892
    // b side
1893
    .b_d(b_d),
1894
    .b_wr(b_wr),
1895
    .b_fifo_full(b_fifo_full),
1896
    .b_q(b_q),
1897
    .b_rd(b_rd),
1898
    .b_fifo_empty(b_fifo_empty),
1899
    .b_clk(wbm_clk),
1900
    .b_rst(wbm_rst)
1901
    );
1902
endmodule
1903 39 unneback
module vl_wb3_arbiter_type1 (
1904
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1905
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1906
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1907
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1908
    wb_clk, wb_rst
1909
);
1910
parameter nr_of_ports = 3;
1911
parameter adr_size = 26;
1912
parameter adr_lo   = 2;
1913
parameter dat_size = 32;
1914
parameter sel_size = dat_size/8;
1915
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1916
localparam dw = dat_size * nr_of_ports;
1917
localparam sw = sel_size * nr_of_ports;
1918
localparam cw = 3 * nr_of_ports;
1919
localparam bw = 2 * nr_of_ports;
1920
input  [dw-1:0] wbm_dat_o;
1921
input  [aw-1:0] wbm_adr_o;
1922
input  [sw-1:0] wbm_sel_o;
1923
input  [cw-1:0] wbm_cti_o;
1924
input  [bw-1:0] wbm_bte_o;
1925
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1926
output [dw-1:0] wbm_dat_i;
1927
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1928
output [dat_size-1:0] wbs_dat_i;
1929
output [adr_size-1:adr_lo] wbs_adr_i;
1930
output [sel_size-1:0] wbs_sel_i;
1931
output [2:0] wbs_cti_i;
1932
output [1:0] wbs_bte_i;
1933
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1934
input  [dat_size-1:0] wbs_dat_o;
1935
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1936
input wb_clk, wb_rst;
1937 44 unneback
reg  [nr_of_ports-1:0] select;
1938 39 unneback
wire [nr_of_ports-1:0] state;
1939
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1940
wire [nr_of_ports-1:0] sel;
1941
wire idle;
1942
genvar i;
1943
assign idle = !(|state);
1944
generate
1945
if (nr_of_ports == 2) begin
1946
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1947
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1948 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1949
    always @ (idle or wbm_cyc_o)
1950
    if (idle)
1951
        casex (wbm_cyc_o)
1952
        2'b1x : select = 2'b10;
1953
        2'b01 : select = 2'b01;
1954
        default : select = {nr_of_ports{1'b0}};
1955
        endcase
1956
    else
1957
        select = {nr_of_ports{1'b0}};
1958 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1959
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1960
end
1961
endgenerate
1962
generate
1963
if (nr_of_ports == 3) begin
1964
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1965
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1966 44 unneback
    always @ (idle or wbm_cyc_o)
1967
    if (idle)
1968
        casex (wbm_cyc_o)
1969
        3'b1xx : select = 3'b100;
1970
        3'b01x : select = 3'b010;
1971
        3'b001 : select = 3'b001;
1972
        default : select = {nr_of_ports{1'b0}};
1973
        endcase
1974
    else
1975
        select = {nr_of_ports{1'b0}};
1976
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1977 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1978
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1979
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1980
end
1981
endgenerate
1982
generate
1983 44 unneback
if (nr_of_ports == 4) begin
1984
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1985
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1986
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1987
    always @ (idle or wbm_cyc_o)
1988
    if (idle)
1989
        casex (wbm_cyc_o)
1990
        4'b1xxx : select = 4'b1000;
1991
        4'b01xx : select = 4'b0100;
1992
        4'b001x : select = 4'b0010;
1993
        4'b0001 : select = 4'b0001;
1994
        default : select = {nr_of_ports{1'b0}};
1995
        endcase
1996
    else
1997
        select = {nr_of_ports{1'b0}};
1998
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
1999
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2000
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2001
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2002
end
2003
endgenerate
2004
generate
2005
if (nr_of_ports == 5) begin
2006
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2007
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2008
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2009
    always @ (idle or wbm_cyc_o)
2010
    if (idle)
2011
        casex (wbm_cyc_o)
2012
        5'b1xxxx : select = 5'b10000;
2013
        5'b01xxx : select = 5'b01000;
2014
        5'b001xx : select = 5'b00100;
2015
        5'b0001x : select = 5'b00010;
2016
        5'b00001 : select = 5'b00001;
2017
        default : select = {nr_of_ports{1'b0}};
2018
        endcase
2019
    else
2020
        select = {nr_of_ports{1'b0}};
2021
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
2022
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
2023
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2024
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2025
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2026
end
2027
endgenerate
2028
generate
2029 39 unneback
for (i=0;i<nr_of_ports;i=i+1) begin
2030
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
2031
end
2032
endgenerate
2033
    assign sel = select | state;
2034
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
2035
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
2036
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
2037
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
2038
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
2039
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
2040
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
2041
    assign wbs_cyc_i = |sel;
2042
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
2043
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
2044
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
2045
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
2046
endmodule
2047 17 unneback
// WB ROM
2048 18 unneback
module vl_wb_boot_rom (
2049 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2050 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2051
    parameter adr_hi = 31;
2052
    parameter adr_lo = 28;
2053
    parameter adr_sel = 4'hf;
2054
    parameter addr_width = 5;
2055 33 unneback
/*
2056
`ifndef BOOT_ROM
2057
`define BOOT_ROM "boot_rom.v"
2058
`endif
2059
*/
2060 18 unneback
    input [adr_hi:2]    wb_adr_i;
2061
    input               wb_stb_i;
2062
    input               wb_cyc_i;
2063
    output [31:0]        wb_dat_o;
2064
    output              wb_ack_o;
2065
    output              hit_o;
2066
    input               wb_clk;
2067
    input               wb_rst;
2068
    wire hit;
2069
    reg [31:0] wb_dat;
2070
    reg wb_ack;
2071
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2072 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2073
    if (wb_rst)
2074 18 unneback
        wb_dat <= 32'h15000000;
2075 17 unneback
    else
2076 18 unneback
         case (wb_adr_i[addr_width-1:2])
2077 33 unneback
`ifdef BOOT_ROM
2078
`include `BOOT_ROM
2079
`endif
2080 17 unneback
           /*
2081
            // Zero r0 and jump to 0x00000100
2082 18 unneback
 
2083
            1 : wb_dat <= 32'hA8200000;
2084
            2 : wb_dat <= 32'hA8C00100;
2085
            3 : wb_dat <= 32'h44003000;
2086
            4 : wb_dat <= 32'h15000000;
2087 17 unneback
            */
2088
           default:
2089 18 unneback
             wb_dat <= 32'h00000000;
2090 17 unneback
         endcase // case (wb_adr_i)
2091
always @ (posedge wb_clk or posedge wb_rst)
2092
    if (wb_rst)
2093 18 unneback
        wb_ack <= 1'b0;
2094 17 unneback
    else
2095 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2096
assign hit_o = hit;
2097
assign wb_dat_o = wb_dat & {32{wb_ack}};
2098
assign wb_ack_o = wb_ack;
2099 17 unneback
endmodule
2100 32 unneback
module vl_wb_dpram (
2101
        // wishbone slave side a
2102
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
2103
        wbsa_clk, wbsa_rst,
2104
        // wishbone slave side a
2105
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
2106
        wbsb_clk, wbsb_rst);
2107
parameter data_width = 32;
2108
parameter addr_width = 8;
2109
parameter dat_o_mask_a = 1;
2110
parameter dat_o_mask_b = 1;
2111
input [31:0] wbsa_dat_i;
2112
input [addr_width-1:2] wbsa_adr_i;
2113
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2114
output [31:0] wbsa_dat_o;
2115
output wbsa_ack_o;
2116
input wbsa_clk, wbsa_rst;
2117
input [31:0] wbsb_dat_i;
2118
input [addr_width-1:2] wbsb_adr_i;
2119
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2120
output [31:0] wbsb_dat_o;
2121
output wbsb_ack_o;
2122
input wbsb_clk, wbsb_rst;
2123
wire wbsa_dat_tmp, wbsb_dat_tmp;
2124
vl_dpram_2r2w # (
2125 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
2126 32 unneback
dpram0(
2127
    .d_a(wbsa_dat_i),
2128
    .q_a(wbsa_dat_tmp),
2129
    .adr_a(wbsa_adr_i),
2130
    .we_a(wbsa_we_i),
2131
    .clk_a(wbsa_clk),
2132
    .d_b(wbsb_dat_i),
2133
    .q_b(wbsb_dat_tmp),
2134
    .adr_b(wbsb_adr_i),
2135
    .we_b(wbsb_we_i),
2136
    .clk_b(wbsb_clk) );
2137 33 unneback
generate if (dat_o_mask_a==1)
2138 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
2139
endgenerate
2140 33 unneback
generate if (dat_o_mask_a==0)
2141 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
2142
endgenerate
2143 33 unneback
generate if (dat_o_mask_b==1)
2144 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
2145
endgenerate
2146 33 unneback
generate if (dat_o_mask_b==0)
2147 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
2148
endgenerate
2149
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2150
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2151
endmodule
2152 18 unneback
//////////////////////////////////////////////////////////////////////
2153
////                                                              ////
2154
////  Arithmetic functions                                        ////
2155
////                                                              ////
2156
////  Description                                                 ////
2157
////  Arithmetic functions for ALU and DSP                        ////
2158
////                                                              ////
2159
////                                                              ////
2160
////  To Do:                                                      ////
2161
////   -                                                          ////
2162
////                                                              ////
2163
////  Author(s):                                                  ////
2164
////      - Michael Unneback, unneback@opencores.org              ////
2165
////        ORSoC AB                                              ////
2166
////                                                              ////
2167
//////////////////////////////////////////////////////////////////////
2168
////                                                              ////
2169
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2170
////                                                              ////
2171
//// This source file may be used and distributed without         ////
2172
//// restriction provided that this copyright statement is not    ////
2173
//// removed from the file and that any derivative work contains  ////
2174
//// the original copyright notice and the associated disclaimer. ////
2175
////                                                              ////
2176
//// This source file is free software; you can redistribute it   ////
2177
//// and/or modify it under the terms of the GNU Lesser General   ////
2178
//// Public License as published by the Free Software Foundation; ////
2179
//// either version 2.1 of the License, or (at your option) any   ////
2180
//// later version.                                               ////
2181
////                                                              ////
2182
//// This source is distributed in the hope that it will be       ////
2183
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2184
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2185
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2186
//// details.                                                     ////
2187
////                                                              ////
2188
//// You should have received a copy of the GNU Lesser General    ////
2189
//// Public License along with this source; if not, download it   ////
2190
//// from http://www.opencores.org/lgpl.shtml                     ////
2191
////                                                              ////
2192
//////////////////////////////////////////////////////////////////////
2193
// signed multiplication
2194
module vl_mults (a,b,p);
2195
parameter operand_a_width = 18;
2196
parameter operand_b_width = 18;
2197
parameter result_hi = 35;
2198
parameter result_lo = 0;
2199
input [operand_a_width-1:0] a;
2200
input [operand_b_width-1:0] b;
2201
output [result_hi:result_lo] p;
2202
wire signed [operand_a_width-1:0] ai;
2203
wire signed [operand_b_width-1:0] bi;
2204
wire signed [operand_a_width+operand_b_width-1:0] result;
2205
    assign ai = a;
2206
    assign bi = b;
2207
    assign result = ai * bi;
2208
    assign p = result[result_hi:result_lo];
2209
endmodule
2210
module vl_mults18x18 (a,b,p);
2211
input [17:0] a,b;
2212
output [35:0] p;
2213
vl_mult
2214
    # (.operand_a_width(18), .operand_b_width(18))
2215
    mult0 (.a(a), .b(b), .p(p));
2216
endmodule
2217
// unsigned multiplication
2218
module vl_mult (a,b,p);
2219
parameter operand_a_width = 18;
2220
parameter operand_b_width = 18;
2221
parameter result_hi = 35;
2222
parameter result_lo = 0;
2223
input [operand_a_width-1:0] a;
2224
input [operand_b_width-1:0] b;
2225
output [result_hi:result_hi] p;
2226
wire [operand_a_width+operand_b_width-1:0] result;
2227
    assign result = a * b;
2228
    assign p = result[result_hi:result_lo];
2229
endmodule
2230
// shift unit
2231
// supporting the following shift functions
2232
//   SLL
2233
//   SRL
2234
//   SRA
2235
module vl_shift_unit_32( din, s, dout, opcode);
2236
input [31:0] din; // data in operand
2237
input [4:0] s; // shift operand
2238
input [1:0] opcode;
2239
output [31:0] dout;
2240
parameter opcode_sll = 2'b00;
2241
//parameter opcode_srl = 2'b01;
2242
parameter opcode_sra = 2'b10;
2243
//parameter opcode_ror = 2'b11;
2244
wire sll, sra;
2245
assign sll = opcode == opcode_sll;
2246
assign sra = opcode == opcode_sra;
2247
wire [15:1] s1;
2248
wire [3:0] sign;
2249
wire [7:0] tmp [0:3];
2250
// first stage is multiplier based
2251
// shift operand as fractional 8.7
2252
assign s1[15] = sll & s[2:0]==3'd7;
2253
assign s1[14] = sll & s[2:0]==3'd6;
2254
assign s1[13] = sll & s[2:0]==3'd5;
2255
assign s1[12] = sll & s[2:0]==3'd4;
2256
assign s1[11] = sll & s[2:0]==3'd3;
2257
assign s1[10] = sll & s[2:0]==3'd2;
2258
assign s1[ 9] = sll & s[2:0]==3'd1;
2259
assign s1[ 8] = s[2:0]==3'd0;
2260
assign s1[ 7] = !sll & s[2:0]==3'd1;
2261
assign s1[ 6] = !sll & s[2:0]==3'd2;
2262
assign s1[ 5] = !sll & s[2:0]==3'd3;
2263
assign s1[ 4] = !sll & s[2:0]==3'd4;
2264
assign s1[ 3] = !sll & s[2:0]==3'd5;
2265
assign s1[ 2] = !sll & s[2:0]==3'd6;
2266
assign s1[ 1] = !sll & s[2:0]==3'd7;
2267
assign sign[3] = din[31] & sra;
2268
assign sign[2] = sign[3] & (&din[31:24]);
2269
assign sign[1] = sign[2] & (&din[23:16]);
2270
assign sign[0] = sign[1] & (&din[15:8]);
2271
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2272
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2273
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2274
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2275
// second stage is multiplexer based
2276
// shift on byte level
2277
// mux byte 3
2278
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2279
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2280
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2281
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2282
                     {8{sign[3]}};
2283
// mux byte 2
2284
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2285
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2286
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2287
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2288
                     (s[4:3]==2'b01) ? tmp[3] :
2289
                     {8{sign[3]}};
2290
// mux byte 1
2291
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2292
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2293
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2294
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2295
                     (s[4:3]==2'b01) ? tmp[2] :
2296
                     (s[4:3]==2'b10) ? tmp[3] :
2297
                     {8{sign[3]}};
2298
// mux byte 0
2299
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2300
                     (sll) ?  {8{1'b0}}:
2301
                     (s[4:3]==2'b01) ? tmp[1] :
2302
                     (s[4:3]==2'b10) ? tmp[2] :
2303
                     tmp[3];
2304
endmodule
2305
// logic unit
2306
// supporting the following logic functions
2307
//    a and b
2308
//    a or  b
2309
//    a xor b
2310
//    not b
2311
module vl_logic_unit( a, b, result, opcode);
2312
parameter width = 32;
2313
parameter opcode_and = 2'b00;
2314
parameter opcode_or  = 2'b01;
2315
parameter opcode_xor = 2'b10;
2316
input [width-1:0] a,b;
2317
output [width-1:0] result;
2318
input [1:0] opcode;
2319
assign result = (opcode==opcode_and) ? a & b :
2320
                (opcode==opcode_or)  ? a | b :
2321
                (opcode==opcode_xor) ? a ^ b :
2322
                b;
2323
endmodule
2324
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2325
parameter width = 32;
2326
parameter opcode_add = 1'b0;
2327
parameter opcode_sub = 1'b1;
2328
input [width-1:0] a,b;
2329
input c_in, add_sub, sign;
2330
output [width-1:0] result;
2331
output c_out, z, ovfl;
2332
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2333
assign z = (result=={width{1'b0}});
2334
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2335
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2336
endmodule

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