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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 45

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1 6 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 33 unneback
module vl_gbuf ( i, o);
47
input i;
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output o;
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assign o = i;
50
endmodule
51 6 unneback
 // ALTERA
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 //ACTEL
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// sync reset
54 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
55 6 unneback
// output active high global reset sync with two DFFs 
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`timescale 1 ns/100 ps
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module vl_sync_rst ( rst_n_i, rst_o, clk);
58
input rst_n_i, clk;
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output rst_o;
60 18 unneback
reg [1:0] tmp;
61 6 unneback
always @ (posedge clk or negedge rst_n_i)
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if (!rst_n_i)
63 17 unneback
        tmp <= 2'b11;
64 6 unneback
else
65 33 unneback
        tmp <= {1'b0,tmp[1]};
66 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
67 6 unneback
endmodule
68
// vl_pll
69 32 unneback
///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps/1 ps
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
72
parameter index = 0;
73
parameter number_of_clk = 1;
74
parameter period_time_0 = 20000;
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parameter period_time_1 = 20000;
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parameter period_time_2 = 20000;
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parameter period_time_3 = 20000;
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parameter period_time_4 = 20000;
79
parameter lock_delay = 2000000;
80
input clk_i, rst_n_i;
81
output lock;
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output reg [0:number_of_clk-1] clk_o;
83
output [0:number_of_clk-1] rst_o;
84 33 unneback
`ifdef SIM_PLL
85 32 unneback
always
86
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
87
generate if (number_of_clk > 1)
88
always
89
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
90
endgenerate
91
generate if (number_of_clk > 2)
92
always
93
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
94
endgenerate
95 33 unneback
generate if (number_of_clk > 3)
96 32 unneback
always
97
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
98
endgenerate
99 33 unneback
generate if (number_of_clk > 4)
100 32 unneback
always
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     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
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endgenerate
103
genvar i;
104
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
106
end
107
endgenerate
108 33 unneback
//assign #lock_delay lock = rst_n_i;
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assign lock = rst_n_i;
110 32 unneback
endmodule
111 33 unneback
`else
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`ifdef VL_PLL0
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`ifdef VL_PLL0_CLK1
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
115
`endif
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`ifdef VL_PLL0_CLK2
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL0_CLK3
120
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL0_CLK4
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL0_CLK5
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL1
130
`ifdef VL_PLL1_CLK1
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL1_CLK2
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL1_CLK3
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL1_CLK4
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL1_CLK5
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL2
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`ifdef VL_PLL2_CLK1
148
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL2_CLK2
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL2_CLK3
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL2_CLK4
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL2_CLK5
160
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL3
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`ifdef VL_PLL3_CLK1
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    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
166
`endif
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`ifdef VL_PLL3_CLK2
168
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
169
`endif
170
`ifdef VL_PLL3_CLK3
171
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
172
`endif
173
`ifdef VL_PLL3_CLK4
174
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
175
`endif
176
`ifdef VL_PLL3_CLK5
177
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
178
`endif
179
`endif
180 32 unneback
genvar i;
181
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
182 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
183 32 unneback
end
184
endgenerate
185
endmodule
186 33 unneback
`endif
187 32 unneback
///////////////////////////////////////////////////////////////////////////////
188 6 unneback
 //altera
189
 //actel
190
//////////////////////////////////////////////////////////////////////
191
////                                                              ////
192
////  Versatile library, registers                                ////
193
////                                                              ////
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////  Description                                                 ////
195
////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
198
////  To Do:                                                      ////
199
////   - add more different registers                             ////
200
////                                                              ////
201
////  Author(s):                                                  ////
202
////      - Michael Unneback, unneback@opencores.org              ////
203
////        ORSoC AB                                              ////
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////                                                              ////
205
//////////////////////////////////////////////////////////////////////
206
////                                                              ////
207
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
208
////                                                              ////
209
//// This source file may be used and distributed without         ////
210
//// restriction provided that this copyright statement is not    ////
211
//// removed from the file and that any derivative work contains  ////
212
//// the original copyright notice and the associated disclaimer. ////
213
////                                                              ////
214
//// This source file is free software; you can redistribute it   ////
215
//// and/or modify it under the terms of the GNU Lesser General   ////
216
//// Public License as published by the Free Software Foundation; ////
217
//// either version 2.1 of the License, or (at your option) any   ////
218
//// later version.                                               ////
219
////                                                              ////
220
//// This source is distributed in the hope that it will be       ////
221
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
222
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
223
//// PURPOSE.  See the GNU Lesser General Public License for more ////
224
//// details.                                                     ////
225
////                                                              ////
226
//// You should have received a copy of the GNU Lesser General    ////
227
//// Public License along with this source; if not, download it   ////
228
//// from http://www.opencores.org/lgpl.shtml                     ////
229
////                                                              ////
230
//////////////////////////////////////////////////////////////////////
231 18 unneback
module vl_dff ( d, q, clk, rst);
232 6 unneback
        parameter width = 1;
233
        parameter reset_value = 0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output reg [width-1:0] q;
237
        always @ (posedge clk or posedge rst)
238
        if (rst)
239
                q <= reset_value;
240
        else
241
                q <= d;
242
endmodule
243 18 unneback
module vl_dff_array ( d, q, clk, rst);
244 6 unneback
        parameter width = 1;
245
        parameter depth = 2;
246
        parameter reset_value = 1'b0;
247
        input [width-1:0] d;
248
        input clk, rst;
249
        output [width-1:0] q;
250
        reg  [0:depth-1] q_tmp [width-1:0];
251
        integer i;
252
        always @ (posedge clk or posedge rst)
253
        if (rst) begin
254
            for (i=0;i<depth;i=i+1)
255
                q_tmp[i] <= {width{reset_value}};
256
        end else begin
257
            q_tmp[0] <= d;
258
            for (i=1;i<depth;i=i+1)
259
                q_tmp[i] <= q_tmp[i-1];
260
        end
261
    assign q = q_tmp[depth-1];
262
endmodule
263 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
264 6 unneback
        parameter width = 1;
265
        parameter reset_value = 0;
266
        input [width-1:0] d;
267
        input ce, clk, rst;
268
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
                q <= reset_value;
272
        else
273
                if (ce)
274
                        q <= d;
275
endmodule
276 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
277 8 unneback
        parameter width = 1;
278
        parameter reset_value = 0;
279
        input [width-1:0] d;
280 10 unneback
        input ce, clear, clk, rst;
281 8 unneback
        output reg [width-1:0] q;
282
        always @ (posedge clk or posedge rst)
283
        if (rst)
284
            q <= reset_value;
285
        else
286
            if (ce)
287
                if (clear)
288
                    q <= {width{1'b0}};
289
                else
290
                    q <= d;
291
endmodule
292 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
293
        parameter width = 1;
294
        parameter reset_value = 0;
295
        input [width-1:0] d;
296
        input ce, set, clk, rst;
297
        output reg [width-1:0] q;
298
        always @ (posedge clk or posedge rst)
299
        if (rst)
300
            q <= reset_value;
301
        else
302
            if (ce)
303
                if (set)
304
                    q <= {width{1'b1}};
305
                else
306
                    q <= d;
307
endmodule
308 29 unneback
module vl_spr ( sp, r, q, clk, rst);
309
        parameter width = 1;
310
        parameter reset_value = 0;
311
        input sp, r;
312
        output reg q;
313
        input clk, rst;
314
        always @ (posedge clk or posedge rst)
315
        if (rst)
316
            q <= reset_value;
317
        else
318
            if (sp)
319
                q <= 1'b1;
320
            else if (r)
321
                q <= 1'b0;
322
endmodule
323
module vl_srp ( s, rp, q, clk, rst);
324
        parameter width = 1;
325
        parameter reset_value = 0;
326
        input s, rp;
327
        output reg q;
328
        input clk, rst;
329
        always @ (posedge clk or posedge rst)
330
        if (rst)
331
            q <= reset_value;
332
        else
333
            if (rp)
334
                q <= 1'b0;
335
            else if (s)
336
                q <= 1'b1;
337
endmodule
338 6 unneback
// megafunction wizard: %LPM_FF%
339
// GENERATION: STANDARD
340
// VERSION: WM1.0
341
// MODULE: lpm_ff 
342
// ============================================================
343
// File Name: dff_sr.v
344
// Megafunction Name(s):
345
//                      lpm_ff
346
//
347
// Simulation Library Files(s):
348
//                      lpm
349
// ============================================================
350
// ************************************************************
351
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
352
//
353
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
354
// ************************************************************
355
//Copyright (C) 1991-2010 Altera Corporation
356
//Your use of Altera Corporation's design tools, logic functions 
357
//and other software and tools, and its AMPP partner logic 
358
//functions, and any output files from any of the foregoing 
359
//(including device programming or simulation files), and any 
360
//associated documentation or information are expressly subject 
361
//to the terms and conditions of the Altera Program License 
362
//Subscription Agreement, Altera MegaCore Function License 
363
//Agreement, or other applicable license agreement, including, 
364
//without limitation, that your use is for the sole purpose of 
365
//programming logic devices manufactured by Altera and sold by 
366
//Altera or its authorized distributors.  Please refer to the 
367
//applicable agreement for further details.
368
// synopsys translate_off
369
`timescale 1 ps / 1 ps
370
// synopsys translate_on
371 18 unneback
module vl_dff_sr (
372 6 unneback
        aclr,
373
        aset,
374
        clock,
375
        data,
376
        q);
377
        input     aclr;
378
        input     aset;
379
        input     clock;
380
        input     data;
381
        output    q;
382
        wire [0:0] sub_wire0;
383
        wire [0:0] sub_wire1 = sub_wire0[0:0];
384
        wire  q = sub_wire1;
385
        wire  sub_wire2 = data;
386
        wire  sub_wire3 = sub_wire2;
387
        lpm_ff  lpm_ff_component (
388
                                .aclr (aclr),
389
                                .clock (clock),
390
                                .data (sub_wire3),
391
                                .aset (aset),
392
                                .q (sub_wire0)
393
                                // synopsys translate_off
394
                                ,
395
                                .aload (),
396
                                .enable (),
397
                                .sclr (),
398
                                .sload (),
399
                                .sset ()
400
                                // synopsys translate_on
401
                                );
402
        defparam
403
                lpm_ff_component.lpm_fftype = "DFF",
404
                lpm_ff_component.lpm_type = "LPM_FF",
405
                lpm_ff_component.lpm_width = 1;
406
endmodule
407
// ============================================================
408
// CNX file retrieval info
409
// ============================================================
410
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
411
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
412
// Retrieval info: PRIVATE: ASET NUMERIC "1"
413
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
414
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
415
// Retrieval info: PRIVATE: DFF NUMERIC "1"
416
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
417
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
418
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET NUMERIC "0"
420
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
421
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
422
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
423
// Retrieval info: PRIVATE: nBit NUMERIC "1"
424
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
425
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
426
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
427
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
428
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
429
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
430
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
431
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
432
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
433
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
434
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
435
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
436
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
437
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
444
// Retrieval info: LIB_FILE: lpm
445
// LATCH
446
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
447 18 unneback
module vl_latch ( d, le, q, clk);
448 6 unneback
input d, le;
449
output q;
450
input clk;
451
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
452
endmodule
453 18 unneback
module vl_shreg ( d, q, clk, rst);
454 17 unneback
parameter depth = 10;
455
input d;
456
output q;
457
input clk, rst;
458
reg [1:depth] dffs;
459
always @ (posedge clk or posedge rst)
460
if (rst)
461
    dffs <= {depth{1'b0}};
462
else
463
    dffs <= {d,dffs[1:depth-1]};
464
assign q = dffs[depth];
465
endmodule
466 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
467 17 unneback
parameter depth = 10;
468
input d, ce;
469
output q;
470
input clk, rst;
471
reg [1:depth] dffs;
472
always @ (posedge clk or posedge rst)
473
if (rst)
474
    dffs <= {depth{1'b0}};
475
else
476
    if (ce)
477
        dffs <= {d,dffs[1:depth-1]};
478
assign q = dffs[depth];
479
endmodule
480 18 unneback
module vl_delay ( d, q, clk, rst);
481 15 unneback
parameter depth = 10;
482
input d;
483
output q;
484
input clk, rst;
485
reg [1:depth] dffs;
486
always @ (posedge clk or posedge rst)
487
if (rst)
488
    dffs <= {depth{1'b0}};
489
else
490
    dffs <= {d,dffs[1:depth-1]};
491
assign q = dffs[depth];
492
endmodule
493 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
494 17 unneback
parameter depth = 10;
495
input d;
496
output q, emptyflag;
497
input clk, rst;
498
reg [1:depth] dffs;
499
always @ (posedge clk or posedge rst)
500
if (rst)
501
    dffs <= {depth{1'b0}};
502
else
503
    dffs <= {d,dffs[1:depth-1]};
504
assign q = dffs[depth];
505
assign emptyflag = !(|dffs);
506
endmodule
507 6 unneback
//////////////////////////////////////////////////////////////////////
508
////                                                              ////
509 18 unneback
////  Logic functions                                             ////
510
////                                                              ////
511
////  Description                                                 ////
512
////  Logic functions such as multiplexers                        ////
513
////                                                              ////
514
////                                                              ////
515
////  To Do:                                                      ////
516
////   -                                                          ////
517
////                                                              ////
518
////  Author(s):                                                  ////
519
////      - Michael Unneback, unneback@opencores.org              ////
520
////        ORSoC AB                                              ////
521
////                                                              ////
522
//////////////////////////////////////////////////////////////////////
523
////                                                              ////
524
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
525
////                                                              ////
526
//// This source file may be used and distributed without         ////
527
//// restriction provided that this copyright statement is not    ////
528
//// removed from the file and that any derivative work contains  ////
529
//// the original copyright notice and the associated disclaimer. ////
530
////                                                              ////
531
//// This source file is free software; you can redistribute it   ////
532
//// and/or modify it under the terms of the GNU Lesser General   ////
533
//// Public License as published by the Free Software Foundation; ////
534
//// either version 2.1 of the License, or (at your option) any   ////
535
//// later version.                                               ////
536
////                                                              ////
537
//// This source is distributed in the hope that it will be       ////
538
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
539
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
540
//// PURPOSE.  See the GNU Lesser General Public License for more ////
541
//// details.                                                     ////
542
////                                                              ////
543
//// You should have received a copy of the GNU Lesser General    ////
544
//// Public License along with this source; if not, download it   ////
545
//// from http://www.opencores.org/lgpl.shtml                     ////
546
////                                                              ////
547
//////////////////////////////////////////////////////////////////////
548 36 unneback
module vl_mux_andor ( a, sel, dout);
549
parameter width = 32;
550
parameter nr_of_ports = 4;
551
input [nr_of_ports*width-1:0] a;
552
input [nr_of_ports-1:0] sel;
553
output reg [width-1:0] dout;
554 38 unneback
integer i,j;
555 36 unneback
always @ (a, sel)
556
begin
557
    dout = a[width-1:0] & {width{sel[0]}};
558 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
559
        for (j=0;j<width;j=j+1)
560
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
561 36 unneback
end
562
endmodule
563 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
564
parameter width = 32;
565 35 unneback
localparam nr_of_ports = 2;
566 34 unneback
input [width-1:0] a1, a0;
567
input [nr_of_ports-1:0] sel;
568
output [width-1:0] dout;
569 36 unneback
vl_mux_andor
570 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
571 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
572 34 unneback
endmodule
573
module vl_mux3_andor ( a2, a1, a0, sel, dout);
574
parameter width = 32;
575 35 unneback
localparam nr_of_ports = 3;
576 34 unneback
input [width-1:0] a2, a1, a0;
577
input [nr_of_ports-1:0] sel;
578
output [width-1:0] dout;
579 36 unneback
vl_mux_andor
580 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
581 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
582 34 unneback
endmodule
583 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
584
parameter width = 32;
585 35 unneback
localparam nr_of_ports = 4;
586 18 unneback
input [width-1:0] a3, a2, a1, a0;
587
input [nr_of_ports-1:0] sel;
588 22 unneback
output [width-1:0] dout;
589 36 unneback
vl_mux_andor
590 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
591 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
592 18 unneback
endmodule
593
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
594
parameter width = 32;
595 35 unneback
localparam nr_of_ports = 5;
596 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
597
input [nr_of_ports-1:0] sel;
598 22 unneback
output [width-1:0] dout;
599 36 unneback
vl_mux_andor
600 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
601 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
602 18 unneback
endmodule
603
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
604
parameter width = 32;
605 35 unneback
localparam nr_of_ports = 6;
606 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
607
input [nr_of_ports-1:0] sel;
608 22 unneback
output [width-1:0] dout;
609 36 unneback
vl_mux_andor
610 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
611 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
612 18 unneback
endmodule
613 43 unneback
module vl_parity_generate (data, parity);
614
parameter word_size = 32;
615
parameter chunk_size = 8;
616
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
617
input [word_size-1:0] data;
618
output reg [word_size/chunk_size-1:0] parity;
619
integer i,j;
620
always @ (data)
621
for (i=0;i<word_size/chunk_size;i=i+1) begin
622
    parity[i] = parity_type;
623
    for (j=0;j<chunk_size;j=j+1) begin
624
        parity[i] = data[i+j] ^ parity[i];
625
    end
626
end
627
endmodule
628
module vl_parity_check( data, parity, parity_error);
629
parameter word_size = 32;
630
parameter chunk_size = 8;
631
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
632
input [word_size-1:0] data;
633
input [word_size/chunk_size-1:0] parity;
634
output parity_error;
635 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
636 43 unneback
integer i,j;
637
always @ (data or parity)
638
for (i=0;i<word_size/chunk_size;i=i+1) begin
639
    error_flag[i] = parity[i] ^ parity_type;
640
    for (j=0;j<chunk_size;j=j+1) begin
641
        error_flag[i] = data[i+j] ^ error_flag[i];
642
    end
643
end
644
assign parity_error = |error_flag;
645
endmodule
646 18 unneback
//////////////////////////////////////////////////////////////////////
647
////                                                              ////
648 44 unneback
////  IO functions                                                ////
649
////                                                              ////
650
////  Description                                                 ////
651
////  IO functions such as IOB flip-flops                         ////
652
////                                                              ////
653
////                                                              ////
654
////  To Do:                                                      ////
655
////   -                                                          ////
656
////                                                              ////
657
////  Author(s):                                                  ////
658
////      - Michael Unneback, unneback@opencores.org              ////
659
////        ORSoC AB                                              ////
660
////                                                              ////
661
//////////////////////////////////////////////////////////////////////
662
////                                                              ////
663
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
664
////                                                              ////
665
//// This source file may be used and distributed without         ////
666
//// restriction provided that this copyright statement is not    ////
667
//// removed from the file and that any derivative work contains  ////
668
//// the original copyright notice and the associated disclaimer. ////
669
////                                                              ////
670
//// This source file is free software; you can redistribute it   ////
671
//// and/or modify it under the terms of the GNU Lesser General   ////
672
//// Public License as published by the Free Software Foundation; ////
673
//// either version 2.1 of the License, or (at your option) any   ////
674
//// later version.                                               ////
675
////                                                              ////
676
//// This source is distributed in the hope that it will be       ////
677
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
678
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
679
//// PURPOSE.  See the GNU Lesser General Public License for more ////
680
//// details.                                                     ////
681
////                                                              ////
682
//// You should have received a copy of the GNU Lesser General    ////
683
//// Public License along with this source; if not, download it   ////
684
//// from http://www.opencores.org/lgpl.shtml                     ////
685
////                                                              ////
686
//////////////////////////////////////////////////////////////////////
687 45 unneback
`timescale 1ns/1ns
688 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
689
parameter width = 1;
690 45 unneback
parameter reset_value = {width{1'b0}};
691
input  [width-1:0]  d_i;
692 44 unneback
output [width-1:0] o_pad;
693
input clk, rst;
694
wire [width-1:0] d_i_int `SYN_KEEP;
695 45 unneback
reg  [width-1:0] o_pad_int;
696 44 unneback
assign d_i_int = d_i;
697
genvar i;
698 45 unneback
generate
699 44 unneback
for (i=0;i<width;i=i+1) begin
700
    always @ (posedge clk or posedge rst)
701
    if (rst)
702 45 unneback
        o_pad_int[i] <= reset_value[i];
703 44 unneback
    else
704 45 unneback
        o_pad_int[i] <= d_i_int[i];
705
    assign #1 o_pad[i] = o_pad_int[i];
706 44 unneback
end
707
endgenerate
708
endmodule
709 45 unneback
`timescale 1ns/1ns
710 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
711
parameter width = 1;
712
input  [width-1:0] d_o;
713
output reg [width-1:0] d_i;
714
input oe;
715
inout [width-1:0] io_pad;
716
input clk, rst;
717
wire [width-1:0] oe_d `SYN_KEEP;
718
reg [width-1:0] oe_q;
719
reg [width-1:0] d_o_q;
720
assign oe_d = {width{oe}};
721
genvar i;
722
generate
723
for (i=0;i<width;i=i+1) begin
724
    always @ (posedge clk or posedge rst)
725
    if (rst)
726
        oe_q[i] <= 1'b0;
727
    else
728
        oe_q[i] <= oe_d[i];
729
    always @ (posedge clk or posedge rst)
730
    if (rst)
731
        d_o_q[i] <= 1'b0;
732
    else
733
        d_o_q[i] <= d_o[i];
734
    always @ (posedge clk or posedge rst)
735
    if (rst)
736
        d_i[i] <= 1'b0;
737
    else
738
        d_i[i] <= io_pad[i];
739 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
740 44 unneback
end
741
endgenerate
742
endmodule
743
//////////////////////////////////////////////////////////////////////
744
////                                                              ////
745 6 unneback
////  Versatile counter                                           ////
746
////                                                              ////
747
////  Description                                                 ////
748
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
749
////  counter                                                     ////
750
////                                                              ////
751
////  To Do:                                                      ////
752
////   - add LFSR with more taps                                  ////
753
////                                                              ////
754
////  Author(s):                                                  ////
755
////      - Michael Unneback, unneback@opencores.org              ////
756
////        ORSoC AB                                              ////
757
////                                                              ////
758
//////////////////////////////////////////////////////////////////////
759
////                                                              ////
760
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
761
////                                                              ////
762
//// This source file may be used and distributed without         ////
763
//// restriction provided that this copyright statement is not    ////
764
//// removed from the file and that any derivative work contains  ////
765
//// the original copyright notice and the associated disclaimer. ////
766
////                                                              ////
767
//// This source file is free software; you can redistribute it   ////
768
//// and/or modify it under the terms of the GNU Lesser General   ////
769
//// Public License as published by the Free Software Foundation; ////
770
//// either version 2.1 of the License, or (at your option) any   ////
771
//// later version.                                               ////
772
////                                                              ////
773
//// This source is distributed in the hope that it will be       ////
774
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
775
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
776
//// PURPOSE.  See the GNU Lesser General Public License for more ////
777
//// details.                                                     ////
778
////                                                              ////
779
//// You should have received a copy of the GNU Lesser General    ////
780
//// Public License along with this source; if not, download it   ////
781
//// from http://www.opencores.org/lgpl.shtml                     ////
782
////                                                              ////
783
//////////////////////////////////////////////////////////////////////
784
// binary counter
785 40 unneback
module vl_cnt_bin_ce (
786
 cke, q, rst, clk);
787 22 unneback
   parameter length = 4;
788 6 unneback
   input cke;
789
   output [length:1] q;
790
   input rst;
791
   input clk;
792
   parameter clear_value = 0;
793
   parameter set_value = 1;
794
   parameter wrap_value = 0;
795
   parameter level1_value = 15;
796
   reg  [length:1] qi;
797
   wire [length:1] q_next;
798
   assign q_next = qi + {{length-1{1'b0}},1'b1};
799
   always @ (posedge clk or posedge rst)
800
     if (rst)
801
       qi <= {length{1'b0}};
802
     else
803
     if (cke)
804
       qi <= q_next;
805
   assign q = qi;
806
endmodule
807
//////////////////////////////////////////////////////////////////////
808
////                                                              ////
809
////  Versatile counter                                           ////
810
////                                                              ////
811
////  Description                                                 ////
812
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
813
////  counter                                                     ////
814
////                                                              ////
815
////  To Do:                                                      ////
816
////   - add LFSR with more taps                                  ////
817
////                                                              ////
818
////  Author(s):                                                  ////
819
////      - Michael Unneback, unneback@opencores.org              ////
820
////        ORSoC AB                                              ////
821
////                                                              ////
822
//////////////////////////////////////////////////////////////////////
823
////                                                              ////
824
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
825
////                                                              ////
826
//// This source file may be used and distributed without         ////
827
//// restriction provided that this copyright statement is not    ////
828
//// removed from the file and that any derivative work contains  ////
829
//// the original copyright notice and the associated disclaimer. ////
830
////                                                              ////
831
//// This source file is free software; you can redistribute it   ////
832
//// and/or modify it under the terms of the GNU Lesser General   ////
833
//// Public License as published by the Free Software Foundation; ////
834
//// either version 2.1 of the License, or (at your option) any   ////
835
//// later version.                                               ////
836
////                                                              ////
837
//// This source is distributed in the hope that it will be       ////
838
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
839
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
840
//// PURPOSE.  See the GNU Lesser General Public License for more ////
841
//// details.                                                     ////
842
////                                                              ////
843
//// You should have received a copy of the GNU Lesser General    ////
844
//// Public License along with this source; if not, download it   ////
845
//// from http://www.opencores.org/lgpl.shtml                     ////
846
////                                                              ////
847
//////////////////////////////////////////////////////////////////////
848
// binary counter
849 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
850
 cke, rew, zq, level1, rst, clk);
851 6 unneback
   parameter length = 4;
852
   input cke;
853
   input rew;
854 25 unneback
   output reg zq;
855
   output reg level1;
856
   input rst;
857
   input clk;
858
   parameter clear_value = 0;
859
   parameter set_value = 1;
860
   parameter wrap_value = 1;
861
   parameter level1_value = 15;
862 29 unneback
   wire clear;
863 30 unneback
   assign clear = 1'b0;
864 25 unneback
   reg  [length:1] qi;
865
   wire  [length:1] q_next, q_next_fw, q_next_rew;
866
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
867
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
868
   assign q_next = rew ? q_next_rew : q_next_fw;
869
   always @ (posedge clk or posedge rst)
870
     if (rst)
871
       qi <= {length{1'b0}};
872
     else
873
     if (cke)
874
       qi <= q_next;
875
   always @ (posedge clk or posedge rst)
876
     if (rst)
877
       zq <= 1'b1;
878
     else
879
     if (cke)
880
       zq <= q_next == {length{1'b0}};
881
    always @ (posedge clk or posedge rst)
882
    if (rst)
883
        level1 <= 1'b0;
884
    else
885
    if (cke)
886 29 unneback
    if (clear)
887
        level1 <= 1'b0;
888
    else if (q_next == level1_value)
889 25 unneback
        level1 <= 1'b1;
890
    else if (qi == level1_value & rew)
891
        level1 <= 1'b0;
892
endmodule
893
//////////////////////////////////////////////////////////////////////
894
////                                                              ////
895
////  Versatile counter                                           ////
896
////                                                              ////
897
////  Description                                                 ////
898
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
899
////  counter                                                     ////
900
////                                                              ////
901
////  To Do:                                                      ////
902
////   - add LFSR with more taps                                  ////
903
////                                                              ////
904
////  Author(s):                                                  ////
905
////      - Michael Unneback, unneback@opencores.org              ////
906
////        ORSoC AB                                              ////
907
////                                                              ////
908
//////////////////////////////////////////////////////////////////////
909
////                                                              ////
910
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
911
////                                                              ////
912
//// This source file may be used and distributed without         ////
913
//// restriction provided that this copyright statement is not    ////
914
//// removed from the file and that any derivative work contains  ////
915
//// the original copyright notice and the associated disclaimer. ////
916
////                                                              ////
917
//// This source file is free software; you can redistribute it   ////
918
//// and/or modify it under the terms of the GNU Lesser General   ////
919
//// Public License as published by the Free Software Foundation; ////
920
//// either version 2.1 of the License, or (at your option) any   ////
921
//// later version.                                               ////
922
////                                                              ////
923
//// This source is distributed in the hope that it will be       ////
924
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
925
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
926
//// PURPOSE.  See the GNU Lesser General Public License for more ////
927
//// details.                                                     ////
928
////                                                              ////
929
//// You should have received a copy of the GNU Lesser General    ////
930
//// Public License along with this source; if not, download it   ////
931
//// from http://www.opencores.org/lgpl.shtml                     ////
932
////                                                              ////
933
//////////////////////////////////////////////////////////////////////
934
// binary counter
935 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
936
 cke, rew, q, zq, level1, rst, clk);
937 25 unneback
   parameter length = 4;
938
   input cke;
939
   input rew;
940
   output [length:1] q;
941
   output reg zq;
942
   output reg level1;
943
   input rst;
944
   input clk;
945
   parameter clear_value = 0;
946
   parameter set_value = 1;
947
   parameter wrap_value = 1;
948
   parameter level1_value = 15;
949 29 unneback
   wire clear;
950 30 unneback
   assign clear = 1'b0;
951 25 unneback
   reg  [length:1] qi;
952
   wire  [length:1] q_next, q_next_fw, q_next_rew;
953
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
954
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
955
   assign q_next = rew ? q_next_rew : q_next_fw;
956
   always @ (posedge clk or posedge rst)
957
     if (rst)
958
       qi <= {length{1'b0}};
959
     else
960
     if (cke)
961
       qi <= q_next;
962
   assign q = qi;
963
   always @ (posedge clk or posedge rst)
964
     if (rst)
965
       zq <= 1'b1;
966
     else
967
     if (cke)
968
       zq <= q_next == {length{1'b0}};
969
    always @ (posedge clk or posedge rst)
970
    if (rst)
971
        level1 <= 1'b0;
972
    else
973
    if (cke)
974 29 unneback
    if (clear)
975
        level1 <= 1'b0;
976
    else if (q_next == level1_value)
977 25 unneback
        level1 <= 1'b1;
978
    else if (qi == level1_value & rew)
979
        level1 <= 1'b0;
980
endmodule
981
//////////////////////////////////////////////////////////////////////
982
////                                                              ////
983
////  Versatile counter                                           ////
984
////                                                              ////
985
////  Description                                                 ////
986
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
987
////  counter                                                     ////
988
////                                                              ////
989
////  To Do:                                                      ////
990
////   - add LFSR with more taps                                  ////
991
////                                                              ////
992
////  Author(s):                                                  ////
993
////      - Michael Unneback, unneback@opencores.org              ////
994
////        ORSoC AB                                              ////
995
////                                                              ////
996
//////////////////////////////////////////////////////////////////////
997
////                                                              ////
998
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
999
////                                                              ////
1000
//// This source file may be used and distributed without         ////
1001
//// restriction provided that this copyright statement is not    ////
1002
//// removed from the file and that any derivative work contains  ////
1003
//// the original copyright notice and the associated disclaimer. ////
1004
////                                                              ////
1005
//// This source file is free software; you can redistribute it   ////
1006
//// and/or modify it under the terms of the GNU Lesser General   ////
1007
//// Public License as published by the Free Software Foundation; ////
1008
//// either version 2.1 of the License, or (at your option) any   ////
1009
//// later version.                                               ////
1010
////                                                              ////
1011
//// This source is distributed in the hope that it will be       ////
1012
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1013
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1014
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1015
//// details.                                                     ////
1016
////                                                              ////
1017
//// You should have received a copy of the GNU Lesser General    ////
1018
//// Public License along with this source; if not, download it   ////
1019
//// from http://www.opencores.org/lgpl.shtml                     ////
1020
////                                                              ////
1021
//////////////////////////////////////////////////////////////////////
1022 6 unneback
// GRAY counter
1023 40 unneback
module vl_cnt_gray_ce_bin (
1024
 cke, q, q_bin, rst, clk);
1025 6 unneback
   parameter length = 4;
1026
   input cke;
1027
   output reg [length:1] q;
1028
   output [length:1] q_bin;
1029
   input rst;
1030
   input clk;
1031
   parameter clear_value = 0;
1032
   parameter set_value = 1;
1033
   parameter wrap_value = 8;
1034
   parameter level1_value = 15;
1035
   reg  [length:1] qi;
1036
   wire [length:1] q_next;
1037
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1038
   always @ (posedge clk or posedge rst)
1039
     if (rst)
1040
       qi <= {length{1'b0}};
1041
     else
1042
     if (cke)
1043
       qi <= q_next;
1044
   always @ (posedge clk or posedge rst)
1045
     if (rst)
1046
       q <= {length{1'b0}};
1047
     else
1048
       if (cke)
1049
         q <= (q_next>>1) ^ q_next;
1050
   assign q_bin = qi;
1051
endmodule
1052
//////////////////////////////////////////////////////////////////////
1053
////                                                              ////
1054
////  Versatile library, counters                                 ////
1055
////                                                              ////
1056
////  Description                                                 ////
1057
////  counters                                                    ////
1058
////                                                              ////
1059
////                                                              ////
1060
////  To Do:                                                      ////
1061
////   - add more counters                                        ////
1062
////                                                              ////
1063
////  Author(s):                                                  ////
1064
////      - Michael Unneback, unneback@opencores.org              ////
1065
////        ORSoC AB                                              ////
1066
////                                                              ////
1067
//////////////////////////////////////////////////////////////////////
1068
////                                                              ////
1069
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1070
////                                                              ////
1071
//// This source file may be used and distributed without         ////
1072
//// restriction provided that this copyright statement is not    ////
1073
//// removed from the file and that any derivative work contains  ////
1074
//// the original copyright notice and the associated disclaimer. ////
1075
////                                                              ////
1076
//// This source file is free software; you can redistribute it   ////
1077
//// and/or modify it under the terms of the GNU Lesser General   ////
1078
//// Public License as published by the Free Software Foundation; ////
1079
//// either version 2.1 of the License, or (at your option) any   ////
1080
//// later version.                                               ////
1081
////                                                              ////
1082
//// This source is distributed in the hope that it will be       ////
1083
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1084
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1085
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1086
//// details.                                                     ////
1087
////                                                              ////
1088
//// You should have received a copy of the GNU Lesser General    ////
1089
//// Public License along with this source; if not, download it   ////
1090
//// from http://www.opencores.org/lgpl.shtml                     ////
1091
////                                                              ////
1092
//////////////////////////////////////////////////////////////////////
1093 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1094 6 unneback
   parameter length = 4;
1095
   output reg [0:length-1] q;
1096
   input rst;
1097
   input clk;
1098
    always @ (posedge clk or posedge rst)
1099
    if (rst)
1100
        q <= {1'b1,{length-1{1'b0}}};
1101
    else
1102
        q <= {q[length-1],q[0:length-2]};
1103
endmodule
1104 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1105 6 unneback
   parameter length = 4;
1106
   input cke;
1107
   output reg [0:length-1] q;
1108
   input rst;
1109
   input clk;
1110
    always @ (posedge clk or posedge rst)
1111
    if (rst)
1112
        q <= {1'b1,{length-1{1'b0}}};
1113
    else
1114
        if (cke)
1115
            q <= {q[length-1],q[0:length-2]};
1116
endmodule
1117 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1118 6 unneback
   parameter length = 4;
1119
   input cke, clear;
1120
   output reg [0:length-1] q;
1121
   input rst;
1122
   input clk;
1123
    always @ (posedge clk or posedge rst)
1124
    if (rst)
1125
        q <= {1'b1,{length-1{1'b0}}};
1126
    else
1127
        if (cke)
1128
            if (clear)
1129
                q <= {1'b1,{length-1{1'b0}}};
1130
            else
1131
                q <= q >> 1;
1132
endmodule
1133 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1134 6 unneback
   parameter length = 4;
1135
   input cke, clear;
1136
   output reg [0:length-1] q;
1137
   input rst;
1138
   input clk;
1139
    always @ (posedge clk or posedge rst)
1140
    if (rst)
1141
        q <= {1'b1,{length-1{1'b0}}};
1142
    else
1143
        if (cke)
1144
            if (clear)
1145
                q <= {1'b1,{length-1{1'b0}}};
1146
            else
1147
            q <= {q[length-1],q[0:length-2]};
1148
endmodule
1149
//////////////////////////////////////////////////////////////////////
1150
////                                                              ////
1151
////  Versatile library, memories                                 ////
1152
////                                                              ////
1153
////  Description                                                 ////
1154
////  memories                                                    ////
1155
////                                                              ////
1156
////                                                              ////
1157
////  To Do:                                                      ////
1158
////   - add more memory types                                    ////
1159
////                                                              ////
1160
////  Author(s):                                                  ////
1161
////      - Michael Unneback, unneback@opencores.org              ////
1162
////        ORSoC AB                                              ////
1163
////                                                              ////
1164
//////////////////////////////////////////////////////////////////////
1165
////                                                              ////
1166
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1167
////                                                              ////
1168
//// This source file may be used and distributed without         ////
1169
//// restriction provided that this copyright statement is not    ////
1170
//// removed from the file and that any derivative work contains  ////
1171
//// the original copyright notice and the associated disclaimer. ////
1172
////                                                              ////
1173
//// This source file is free software; you can redistribute it   ////
1174
//// and/or modify it under the terms of the GNU Lesser General   ////
1175
//// Public License as published by the Free Software Foundation; ////
1176
//// either version 2.1 of the License, or (at your option) any   ////
1177
//// later version.                                               ////
1178
////                                                              ////
1179
//// This source is distributed in the hope that it will be       ////
1180
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1181
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1182
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1183
//// details.                                                     ////
1184
////                                                              ////
1185
//// You should have received a copy of the GNU Lesser General    ////
1186
//// Public License along with this source; if not, download it   ////
1187
//// from http://www.opencores.org/lgpl.shtml                     ////
1188
////                                                              ////
1189
//////////////////////////////////////////////////////////////////////
1190
/// ROM
1191 7 unneback
module vl_rom_init ( adr, q, clk);
1192
   parameter data_width = 32;
1193
   parameter addr_width = 8;
1194
   input [(addr_width-1):0]       adr;
1195
   output reg [(data_width-1):0] q;
1196
   input                         clk;
1197
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1198
   parameter memory_file = "vl_rom.vmem";
1199
   initial
1200
     begin
1201
        $readmemh(memory_file, rom);
1202
     end
1203
   always @ (posedge clk)
1204
     q <= rom[adr];
1205
endmodule
1206 14 unneback
/*
1207 7 unneback
module vl_rom ( adr, q, clk);
1208 6 unneback
parameter data_width = 32;
1209
parameter addr_width = 4;
1210
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1211
    {32'h18000000},
1212
    {32'hA8200000},
1213
    {32'hA8200000},
1214
    {32'hA8200000},
1215
    {32'h44003000},
1216
    {32'h15000000},
1217
    {32'h15000000},
1218
    {32'h15000000},
1219
    {32'h15000000},
1220
    {32'h15000000},
1221
    {32'h15000000},
1222
    {32'h15000000},
1223
    {32'h15000000},
1224
    {32'h15000000},
1225
    {32'h15000000},
1226
    {32'h15000000}};
1227 7 unneback
input [addr_width-1:0] adr;
1228 6 unneback
output reg [data_width-1:0] q;
1229
input clk;
1230
always @ (posedge clk)
1231 7 unneback
    q <= data[adr];
1232 6 unneback
endmodule
1233 14 unneback
*/
1234 6 unneback
// Single port RAM
1235
module vl_ram ( d, adr, we, q, clk);
1236
   parameter data_width = 32;
1237
   parameter addr_width = 8;
1238
   input [(data_width-1):0]      d;
1239
   input [(addr_width-1):0]       adr;
1240
   input                         we;
1241 7 unneback
   output reg [(data_width-1):0] q;
1242 6 unneback
   input                         clk;
1243
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1244 7 unneback
   parameter init = 0;
1245
   parameter memory_file = "vl_ram.vmem";
1246
   generate if (init) begin : init_mem
1247
   initial
1248
     begin
1249
        $readmemh(memory_file, ram);
1250
     end
1251
   end
1252
   endgenerate
1253 6 unneback
   always @ (posedge clk)
1254
   begin
1255
   if (we)
1256
     ram[adr] <= d;
1257
   q <= ram[adr];
1258
   end
1259
endmodule
1260 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1261
   parameter data_width = 32;
1262
   parameter addr_width = 8;
1263
   input [(data_width-1):0]      d;
1264
   input [(addr_width-1):0]       adr;
1265
   input [(addr_width/4)-1:0]    be;
1266
   input                         we;
1267
   output reg [(data_width-1):0] q;
1268
   input                         clk;
1269
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1270
   parameter init = 0;
1271
   parameter memory_file = "vl_ram.vmem";
1272
   generate if (init) begin : init_mem
1273
   initial
1274
     begin
1275
        $readmemh(memory_file, ram);
1276
     end
1277
   end
1278
   endgenerate
1279
   genvar i;
1280
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1281
      always @ (posedge clk)
1282
      if (we & be[i])
1283
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1284
   end
1285
   endgenerate
1286
   always @ (posedge clk)
1287
      q <= ram[adr];
1288
endmodule
1289 6 unneback
// Dual port RAM
1290
// ACTEL FPGA should not use logic to handle rw collision
1291 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1292 6 unneback
   parameter data_width = 32;
1293
   parameter addr_width = 8;
1294
   input [(data_width-1):0]      d_a;
1295
   input [(addr_width-1):0]       adr_a;
1296
   input [(addr_width-1):0]       adr_b;
1297
   input                         we_a;
1298
   output [(data_width-1):0]      q_b;
1299
   input                         clk_a, clk_b;
1300
   reg [(addr_width-1):0]         adr_b_reg;
1301
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1302 7 unneback
   parameter init = 0;
1303
   parameter memory_file = "vl_ram.vmem";
1304
   generate if (init) begin : init_mem
1305
   initial
1306
     begin
1307
        $readmemh(memory_file, ram);
1308
     end
1309
   end
1310
   endgenerate
1311 6 unneback
   always @ (posedge clk_a)
1312
   if (we_a)
1313
     ram[adr_a] <= d_a;
1314
   always @ (posedge clk_b)
1315
   adr_b_reg <= adr_b;
1316
   assign q_b = ram[adr_b_reg];
1317
endmodule
1318 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1319 6 unneback
   parameter data_width = 32;
1320
   parameter addr_width = 8;
1321
   input [(data_width-1):0]      d_a;
1322
   input [(addr_width-1):0]       adr_a;
1323
   input [(addr_width-1):0]       adr_b;
1324
   input                         we_a;
1325
   output [(data_width-1):0]      q_b;
1326
   output reg [(data_width-1):0] q_a;
1327
   input                         clk_a, clk_b;
1328
   reg [(data_width-1):0]         q_b;
1329
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1330 7 unneback
   parameter init = 0;
1331
   parameter memory_file = "vl_ram.vmem";
1332
   generate if (init) begin : init_mem
1333
   initial
1334
     begin
1335
        $readmemh(memory_file, ram);
1336
     end
1337
   end
1338
   endgenerate
1339 6 unneback
   always @ (posedge clk_a)
1340
     begin
1341
        q_a <= ram[adr_a];
1342
        if (we_a)
1343
             ram[adr_a] <= d_a;
1344
     end
1345
   always @ (posedge clk_b)
1346
          q_b <= ram[adr_b];
1347
endmodule
1348 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1349 6 unneback
   parameter data_width = 32;
1350
   parameter addr_width = 8;
1351
   input [(data_width-1):0]      d_a;
1352
   input [(addr_width-1):0]       adr_a;
1353
   input [(addr_width-1):0]       adr_b;
1354
   input                         we_a;
1355
   output [(data_width-1):0]      q_b;
1356
   input [(data_width-1):0]       d_b;
1357
   output reg [(data_width-1):0] q_a;
1358
   input                         we_b;
1359
   input                         clk_a, clk_b;
1360
   reg [(data_width-1):0]         q_b;
1361
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1362 7 unneback
   parameter init = 0;
1363
   parameter memory_file = "vl_ram.vmem";
1364
   generate if (init) begin : init_mem
1365
   initial
1366
     begin
1367
        $readmemh(memory_file, ram);
1368
     end
1369
   end
1370
   endgenerate
1371 6 unneback
   always @ (posedge clk_a)
1372
     begin
1373
        q_a <= ram[adr_a];
1374
        if (we_a)
1375
             ram[adr_a] <= d_a;
1376
     end
1377
   always @ (posedge clk_b)
1378
     begin
1379
        q_b <= ram[adr_b];
1380
        if (we_b)
1381
          ram[adr_b] <= d_b;
1382
     end
1383
endmodule
1384
// Content addresable memory, CAM
1385
// FIFO
1386 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1387
    d, wr, fifo_full,
1388
    q, rd, fifo_empty,
1389
    fill_level,
1390
    clk, rst
1391
    );
1392
parameter data_width = 18;
1393
parameter addr_width = 4;
1394
// write side
1395
input  [data_width-1:0] d;
1396
input                   wr;
1397
output                  fifo_full;
1398
// read side
1399
output [data_width-1:0] q;
1400
input                   rd;
1401
output                  fifo_empty;
1402
// common
1403
output [addr_width:0]   fill_level;
1404
input rst, clk;
1405
wire [addr_width:1] wadr, radr;
1406
vl_cnt_bin_ce
1407
    # ( .length(addr_width))
1408
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1409
vl_cnt_bin_ce
1410
    # (.length(addr_width))
1411
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1412
vl_dpram_1r1w
1413
    # (.data_width(data_width), .addr_width(addr_width))
1414
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1415 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1416 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1417 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1418
endmodule
1419 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1420
// RAM is supposed to be larger than the two FIFOs
1421
// LFSR counters used adr pointers
1422
module vl_fifo_2r2w_sync_simplex (
1423
    // a side
1424
    a_d, a_wr, a_fifo_full,
1425
    a_q, a_rd, a_fifo_empty,
1426
    a_fill_level,
1427
    // b side
1428
    b_d, b_wr, b_fifo_full,
1429
    b_q, b_rd, b_fifo_empty,
1430
    b_fill_level,
1431
    // common
1432
    clk, rst
1433
    );
1434
parameter data_width = 8;
1435
parameter addr_width = 5;
1436
parameter fifo_full_level = (1<<addr_width)-1;
1437
// a side
1438
input  [data_width-1:0] a_d;
1439
input                   a_wr;
1440
output                  a_fifo_full;
1441
output [data_width-1:0] a_q;
1442
input                   a_rd;
1443
output                  a_fifo_empty;
1444
output [addr_width-1:0] a_fill_level;
1445
// b side
1446
input  [data_width-1:0] b_d;
1447
input                   b_wr;
1448
output                  b_fifo_full;
1449
output [data_width-1:0] b_q;
1450
input                   b_rd;
1451
output                  b_fifo_empty;
1452
output [addr_width-1:0] b_fill_level;
1453
input                   clk;
1454
input                   rst;
1455
// adr_gen
1456
wire [addr_width:1] a_wadr, a_radr;
1457
wire [addr_width:1] b_wadr, b_radr;
1458
// dpram
1459
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1460
vl_cnt_lfsr_ce
1461
    # ( .length(addr_width))
1462
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1463
vl_cnt_lfsr_ce
1464
    # (.length(addr_width))
1465
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1466
vl_cnt_lfsr_ce
1467
    # ( .length(addr_width))
1468
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1469
vl_cnt_lfsr_ce
1470
    # (.length(addr_width))
1471
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1472
// mux read or write adr to DPRAM
1473
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1474
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1475
vl_dpram_2r2w
1476
    # (.data_width(data_width), .addr_width(addr_width+1))
1477
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1478
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1479
vl_cnt_bin_ce_rew_zq_l1
1480 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1481 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1482
vl_cnt_bin_ce_rew_zq_l1
1483 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1484 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1485
endmodule
1486 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1487 11 unneback
   parameter addr_width = 4;
1488
   parameter N = addr_width-1;
1489 6 unneback
   parameter Q1 = 2'b00;
1490
   parameter Q2 = 2'b01;
1491
   parameter Q3 = 2'b11;
1492
   parameter Q4 = 2'b10;
1493
   parameter going_empty = 1'b0;
1494
   parameter going_full  = 1'b1;
1495
   input [N:0]  wptr, rptr;
1496 14 unneback
   output       fifo_empty;
1497 6 unneback
   output       fifo_full;
1498
   input        wclk, rclk, rst;
1499
   wire direction;
1500
   reg  direction_set, direction_clr;
1501
   wire async_empty, async_full;
1502
   wire fifo_full2;
1503 14 unneback
   wire fifo_empty2;
1504 6 unneback
   // direction_set
1505
   always @ (wptr[N:N-1] or rptr[N:N-1])
1506
     case ({wptr[N:N-1],rptr[N:N-1]})
1507
       {Q1,Q2} : direction_set <= 1'b1;
1508
       {Q2,Q3} : direction_set <= 1'b1;
1509
       {Q3,Q4} : direction_set <= 1'b1;
1510
       {Q4,Q1} : direction_set <= 1'b1;
1511
       default : direction_set <= 1'b0;
1512
     endcase
1513
   // direction_clear
1514
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1515
     if (rst)
1516
       direction_clr <= 1'b1;
1517
     else
1518
       case ({wptr[N:N-1],rptr[N:N-1]})
1519
         {Q2,Q1} : direction_clr <= 1'b1;
1520
         {Q3,Q2} : direction_clr <= 1'b1;
1521
         {Q4,Q3} : direction_clr <= 1'b1;
1522
         {Q1,Q4} : direction_clr <= 1'b1;
1523
         default : direction_clr <= 1'b0;
1524
       endcase
1525 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1526 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1527
   assign async_full  = (wptr == rptr) && (direction==going_full);
1528 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1529
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1530 6 unneback
/*
1531
   always @ (posedge wclk or posedge rst or posedge async_full)
1532
     if (rst)
1533
       {fifo_full, fifo_full2} <= 2'b00;
1534
     else if (async_full)
1535
       {fifo_full, fifo_full2} <= 2'b11;
1536
     else
1537
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1538
*/
1539 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1540 6 unneback
     if (async_empty)
1541
       {fifo_empty, fifo_empty2} <= 2'b11;
1542
     else
1543 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1544 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1545
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1546 27 unneback
endmodule // async_compb
1547 6 unneback
module vl_fifo_1r1w_async (
1548
    d, wr, fifo_full, wr_clk, wr_rst,
1549
    q, rd, fifo_empty, rd_clk, rd_rst
1550
    );
1551
parameter data_width = 18;
1552
parameter addr_width = 4;
1553
// write side
1554
input  [data_width-1:0] d;
1555
input                   wr;
1556
output                  fifo_full;
1557
input                   wr_clk;
1558
input                   wr_rst;
1559
// read side
1560
output [data_width-1:0] q;
1561
input                   rd;
1562
output                  fifo_empty;
1563
input                   rd_clk;
1564
input                   rd_rst;
1565
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1566 18 unneback
vl_cnt_gray_ce_bin
1567 6 unneback
    # ( .length(addr_width))
1568
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1569 18 unneback
vl_cnt_gray_ce_bin
1570 6 unneback
    # (.length(addr_width))
1571 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1572 7 unneback
vl_dpram_1r1w
1573 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1574
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1575
vl_fifo_cmp_async
1576
    # (.addr_width(addr_width))
1577
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1578
endmodule
1579 8 unneback
module vl_fifo_2r2w_async (
1580 6 unneback
    // a side
1581
    a_d, a_wr, a_fifo_full,
1582
    a_q, a_rd, a_fifo_empty,
1583
    a_clk, a_rst,
1584
    // b side
1585
    b_d, b_wr, b_fifo_full,
1586
    b_q, b_rd, b_fifo_empty,
1587
    b_clk, b_rst
1588
    );
1589
parameter data_width = 18;
1590
parameter addr_width = 4;
1591
// a side
1592
input  [data_width-1:0] a_d;
1593
input                   a_wr;
1594
output                  a_fifo_full;
1595
output [data_width-1:0] a_q;
1596
input                   a_rd;
1597
output                  a_fifo_empty;
1598
input                   a_clk;
1599
input                   a_rst;
1600
// b side
1601
input  [data_width-1:0] b_d;
1602
input                   b_wr;
1603
output                  b_fifo_full;
1604
output [data_width-1:0] b_q;
1605
input                   b_rd;
1606
output                  b_fifo_empty;
1607
input                   b_clk;
1608
input                   b_rst;
1609
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1610
vl_fifo_1r1w_async_a (
1611
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1612
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1613
    );
1614
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1615
vl_fifo_1r1w_async_b (
1616
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1617
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1618
    );
1619
endmodule
1620 8 unneback
module vl_fifo_2r2w_async_simplex (
1621 6 unneback
    // a side
1622
    a_d, a_wr, a_fifo_full,
1623
    a_q, a_rd, a_fifo_empty,
1624
    a_clk, a_rst,
1625
    // b side
1626
    b_d, b_wr, b_fifo_full,
1627
    b_q, b_rd, b_fifo_empty,
1628
    b_clk, b_rst
1629
    );
1630
parameter data_width = 18;
1631
parameter addr_width = 4;
1632
// a side
1633
input  [data_width-1:0] a_d;
1634
input                   a_wr;
1635
output                  a_fifo_full;
1636
output [data_width-1:0] a_q;
1637
input                   a_rd;
1638
output                  a_fifo_empty;
1639
input                   a_clk;
1640
input                   a_rst;
1641
// b side
1642
input  [data_width-1:0] b_d;
1643
input                   b_wr;
1644
output                  b_fifo_full;
1645
output [data_width-1:0] b_q;
1646
input                   b_rd;
1647
output                  b_fifo_empty;
1648
input                   b_clk;
1649
input                   b_rst;
1650
// adr_gen
1651
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1652
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1653
// dpram
1654
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1655 18 unneback
vl_cnt_gray_ce_bin
1656 6 unneback
    # ( .length(addr_width))
1657
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1658 18 unneback
vl_cnt_gray_ce_bin
1659 6 unneback
    # (.length(addr_width))
1660
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1661 18 unneback
vl_cnt_gray_ce_bin
1662 6 unneback
    # ( .length(addr_width))
1663
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1664 18 unneback
vl_cnt_gray_ce_bin
1665 6 unneback
    # (.length(addr_width))
1666
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1667
// mux read or write adr to DPRAM
1668
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1669
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1670 11 unneback
vl_dpram_2r2w
1671 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1672
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1673
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1674 11 unneback
vl_fifo_cmp_async
1675 6 unneback
    # (.addr_width(addr_width))
1676
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1677 11 unneback
vl_fifo_cmp_async
1678 6 unneback
    # (.addr_width(addr_width))
1679
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1680
endmodule
1681 12 unneback
//////////////////////////////////////////////////////////////////////
1682
////                                                              ////
1683
////  Versatile library, wishbone stuff                           ////
1684
////                                                              ////
1685
////  Description                                                 ////
1686
////  Wishbone compliant modules                                  ////
1687
////                                                              ////
1688
////                                                              ////
1689
////  To Do:                                                      ////
1690
////   -                                                          ////
1691
////                                                              ////
1692
////  Author(s):                                                  ////
1693
////      - Michael Unneback, unneback@opencores.org              ////
1694
////        ORSoC AB                                              ////
1695
////                                                              ////
1696
//////////////////////////////////////////////////////////////////////
1697
////                                                              ////
1698
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1699
////                                                              ////
1700
//// This source file may be used and distributed without         ////
1701
//// restriction provided that this copyright statement is not    ////
1702
//// removed from the file and that any derivative work contains  ////
1703
//// the original copyright notice and the associated disclaimer. ////
1704
////                                                              ////
1705
//// This source file is free software; you can redistribute it   ////
1706
//// and/or modify it under the terms of the GNU Lesser General   ////
1707
//// Public License as published by the Free Software Foundation; ////
1708
//// either version 2.1 of the License, or (at your option) any   ////
1709
//// later version.                                               ////
1710
////                                                              ////
1711
//// This source is distributed in the hope that it will be       ////
1712
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1713
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1714
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1715
//// details.                                                     ////
1716
////                                                              ////
1717
//// You should have received a copy of the GNU Lesser General    ////
1718
//// Public License along with this source; if not, download it   ////
1719
//// from http://www.opencores.org/lgpl.shtml                     ////
1720
////                                                              ////
1721
//////////////////////////////////////////////////////////////////////
1722
// async wb3 - wb3 bridge
1723
`timescale 1ns/1ns
1724 18 unneback
module vl_wb3wb3_bridge (
1725 12 unneback
        // wishbone slave side
1726
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1727
        // wishbone master side
1728
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1729
input [31:0] wbs_dat_i;
1730
input [31:2] wbs_adr_i;
1731
input [3:0]  wbs_sel_i;
1732
input [1:0]  wbs_bte_i;
1733
input [2:0]  wbs_cti_i;
1734
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1735
output [31:0] wbs_dat_o;
1736 14 unneback
output wbs_ack_o;
1737 12 unneback
input wbs_clk, wbs_rst;
1738
output [31:0] wbm_dat_o;
1739
output reg [31:2] wbm_adr_o;
1740
output [3:0]  wbm_sel_o;
1741
output reg [1:0]  wbm_bte_o;
1742
output reg [2:0]  wbm_cti_o;
1743 14 unneback
output reg wbm_we_o;
1744
output wbm_cyc_o;
1745 12 unneback
output wbm_stb_o;
1746
input [31:0]  wbm_dat_i;
1747
input wbm_ack_i;
1748
input wbm_clk, wbm_rst;
1749
parameter addr_width = 4;
1750
// bte
1751
parameter linear       = 2'b00;
1752
parameter wrap4        = 2'b01;
1753
parameter wrap8        = 2'b10;
1754
parameter wrap16       = 2'b11;
1755
// cti
1756
parameter classic      = 3'b000;
1757
parameter incburst     = 3'b010;
1758
parameter endofburst   = 3'b111;
1759
parameter wbs_adr  = 1'b0;
1760
parameter wbs_data = 1'b1;
1761 33 unneback
parameter wbm_adr0      = 2'b00;
1762
parameter wbm_adr1      = 2'b01;
1763
parameter wbm_data      = 2'b10;
1764
parameter wbm_data_wait = 2'b11;
1765 12 unneback
reg [1:0] wbs_bte_reg;
1766
reg wbs;
1767
wire wbs_eoc_alert, wbm_eoc_alert;
1768
reg wbs_eoc, wbm_eoc;
1769
reg [1:0] wbm;
1770 14 unneback
wire [1:16] wbs_count, wbm_count;
1771 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1772
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1773
reg a_rd_reg;
1774
wire b_rd_adr, b_rd_data;
1775 14 unneback
wire b_rd_data_reg;
1776
wire [35:0] temp;
1777 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1778
always @ (posedge wbs_clk or posedge wbs_rst)
1779
if (wbs_rst)
1780
        wbs_eoc <= 1'b0;
1781
else
1782
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1783
                wbs_eoc <= wbs_bte_i==linear;
1784
        else if (wbs_eoc_alert & (a_rd | a_wr))
1785
                wbs_eoc <= 1'b1;
1786 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1787 12 unneback
    cnt0 (
1788
        .cke(wbs_ack_o),
1789
        .clear(wbs_eoc),
1790
        .q(wbs_count),
1791
        .rst(wbs_rst),
1792
        .clk(wbs_clk));
1793
always @ (posedge wbs_clk or posedge wbs_rst)
1794
if (wbs_rst)
1795
        wbs <= wbs_adr;
1796
else
1797
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1798
                wbs <= wbs_data;
1799
        else if (wbs_eoc & wbs_ack_o)
1800
                wbs <= wbs_adr;
1801
// wbs FIFO
1802
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1803
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1804
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1805
              1'b0;
1806
assign a_rd = !a_fifo_empty;
1807
always @ (posedge wbs_clk or posedge wbs_rst)
1808
if (wbs_rst)
1809
        a_rd_reg <= 1'b0;
1810
else
1811
        a_rd_reg <= a_rd;
1812
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1813
assign wbs_dat_o = a_q[35:4];
1814
always @ (posedge wbs_clk or posedge wbs_rst)
1815
if (wbs_rst)
1816 13 unneback
        wbs_bte_reg <= 2'b00;
1817 12 unneback
else
1818 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1819 12 unneback
// wbm FIFO
1820
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1821
always @ (posedge wbm_clk or posedge wbm_rst)
1822
if (wbm_rst)
1823
        wbm_eoc <= 1'b0;
1824
else
1825
        if (wbm==wbm_adr0 & !b_fifo_empty)
1826
                wbm_eoc <= b_q[4:3] == linear;
1827
        else if (wbm_eoc_alert & wbm_ack_i)
1828
                wbm_eoc <= 1'b1;
1829
always @ (posedge wbm_clk or posedge wbm_rst)
1830
if (wbm_rst)
1831
        wbm <= wbm_adr0;
1832
else
1833 33 unneback
/*
1834 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1835
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1836
        (wbm==wbm_adr1 & !wbm_we_o) |
1837
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1838
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1839 33 unneback
*/
1840
    case (wbm)
1841
    wbm_adr0:
1842
        if (!b_fifo_empty)
1843
            wbm <= wbm_adr1;
1844
    wbm_adr1:
1845
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1846
            wbm <= wbm_data;
1847
    wbm_data:
1848
        if (wbm_ack_i & wbm_eoc)
1849
            wbm <= wbm_adr0;
1850
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1851
            wbm <= wbm_data_wait;
1852
    wbm_data_wait:
1853
        if (!b_fifo_empty)
1854
            wbm <= wbm_data;
1855
    endcase
1856 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1857
assign b_wr = !wbm_we_o & wbm_ack_i;
1858
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1859
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1860
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1861 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1862 12 unneback
                   1'b0;
1863
assign b_rd = b_rd_adr | b_rd_data;
1864 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1865
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1866 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1867 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1868 12 unneback
    cnt1 (
1869
        .cke(wbm_ack_i),
1870
        .clear(wbm_eoc),
1871
        .q(wbm_count),
1872
        .rst(wbm_rst),
1873
        .clk(wbm_clk));
1874 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1875
assign wbm_stb_o = (wbm==wbm_data);
1876 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1877
if (wbm_rst)
1878
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1879
else begin
1880
        if (wbm==wbm_adr0 & !b_fifo_empty)
1881
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1882
        else if (wbm_eoc_alert & wbm_ack_i)
1883
                wbm_cti_o <= endofburst;
1884
end
1885
//async_fifo_dw_simplex_top
1886
vl_fifo_2r2w_async_simplex
1887
# ( .data_width(36), .addr_width(addr_width))
1888
fifo (
1889
    // a side
1890
    .a_d(a_d),
1891
    .a_wr(a_wr),
1892
    .a_fifo_full(a_fifo_full),
1893
    .a_q(a_q),
1894
    .a_rd(a_rd),
1895
    .a_fifo_empty(a_fifo_empty),
1896
    .a_clk(wbs_clk),
1897
    .a_rst(wbs_rst),
1898
    // b side
1899
    .b_d(b_d),
1900
    .b_wr(b_wr),
1901
    .b_fifo_full(b_fifo_full),
1902
    .b_q(b_q),
1903
    .b_rd(b_rd),
1904
    .b_fifo_empty(b_fifo_empty),
1905
    .b_clk(wbm_clk),
1906
    .b_rst(wbm_rst)
1907
    );
1908
endmodule
1909 39 unneback
module vl_wb3_arbiter_type1 (
1910
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1911
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1912
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1913
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1914
    wb_clk, wb_rst
1915
);
1916
parameter nr_of_ports = 3;
1917
parameter adr_size = 26;
1918
parameter adr_lo   = 2;
1919
parameter dat_size = 32;
1920
parameter sel_size = dat_size/8;
1921
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1922
localparam dw = dat_size * nr_of_ports;
1923
localparam sw = sel_size * nr_of_ports;
1924
localparam cw = 3 * nr_of_ports;
1925
localparam bw = 2 * nr_of_ports;
1926
input  [dw-1:0] wbm_dat_o;
1927
input  [aw-1:0] wbm_adr_o;
1928
input  [sw-1:0] wbm_sel_o;
1929
input  [cw-1:0] wbm_cti_o;
1930
input  [bw-1:0] wbm_bte_o;
1931
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1932
output [dw-1:0] wbm_dat_i;
1933
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1934
output [dat_size-1:0] wbs_dat_i;
1935
output [adr_size-1:adr_lo] wbs_adr_i;
1936
output [sel_size-1:0] wbs_sel_i;
1937
output [2:0] wbs_cti_i;
1938
output [1:0] wbs_bte_i;
1939
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1940
input  [dat_size-1:0] wbs_dat_o;
1941
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1942
input wb_clk, wb_rst;
1943 44 unneback
reg  [nr_of_ports-1:0] select;
1944 39 unneback
wire [nr_of_ports-1:0] state;
1945
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1946
wire [nr_of_ports-1:0] sel;
1947
wire idle;
1948
genvar i;
1949
assign idle = !(|state);
1950
generate
1951
if (nr_of_ports == 2) begin
1952
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1953
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1954 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1955
    always @ (idle or wbm_cyc_o)
1956
    if (idle)
1957
        casex (wbm_cyc_o)
1958
        2'b1x : select = 2'b10;
1959
        2'b01 : select = 2'b01;
1960
        default : select = {nr_of_ports{1'b0}};
1961
        endcase
1962
    else
1963
        select = {nr_of_ports{1'b0}};
1964 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1965
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1966
end
1967
endgenerate
1968
generate
1969
if (nr_of_ports == 3) begin
1970
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1971
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1972 44 unneback
    always @ (idle or wbm_cyc_o)
1973
    if (idle)
1974
        casex (wbm_cyc_o)
1975
        3'b1xx : select = 3'b100;
1976
        3'b01x : select = 3'b010;
1977
        3'b001 : select = 3'b001;
1978
        default : select = {nr_of_ports{1'b0}};
1979
        endcase
1980
    else
1981
        select = {nr_of_ports{1'b0}};
1982
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1983 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1984
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1985
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1986
end
1987
endgenerate
1988
generate
1989 44 unneback
if (nr_of_ports == 4) begin
1990
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1991
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1992
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1993
    always @ (idle or wbm_cyc_o)
1994
    if (idle)
1995
        casex (wbm_cyc_o)
1996
        4'b1xxx : select = 4'b1000;
1997
        4'b01xx : select = 4'b0100;
1998
        4'b001x : select = 4'b0010;
1999
        4'b0001 : select = 4'b0001;
2000
        default : select = {nr_of_ports{1'b0}};
2001
        endcase
2002
    else
2003
        select = {nr_of_ports{1'b0}};
2004
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
2005
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2006
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2007
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2008
end
2009
endgenerate
2010
generate
2011
if (nr_of_ports == 5) begin
2012
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2013
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2014
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2015
    always @ (idle or wbm_cyc_o)
2016
    if (idle)
2017
        casex (wbm_cyc_o)
2018
        5'b1xxxx : select = 5'b10000;
2019
        5'b01xxx : select = 5'b01000;
2020
        5'b001xx : select = 5'b00100;
2021
        5'b0001x : select = 5'b00010;
2022
        5'b00001 : select = 5'b00001;
2023
        default : select = {nr_of_ports{1'b0}};
2024
        endcase
2025
    else
2026
        select = {nr_of_ports{1'b0}};
2027
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
2028
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
2029
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2030
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2031
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2032
end
2033
endgenerate
2034
generate
2035 39 unneback
for (i=0;i<nr_of_ports;i=i+1) begin
2036
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
2037
end
2038
endgenerate
2039
    assign sel = select | state;
2040
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
2041
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
2042
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
2043
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
2044
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
2045
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
2046
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
2047
    assign wbs_cyc_i = |sel;
2048
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
2049
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
2050
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
2051
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
2052
endmodule
2053 17 unneback
// WB ROM
2054 18 unneback
module vl_wb_boot_rom (
2055 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2056 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2057
    parameter adr_hi = 31;
2058
    parameter adr_lo = 28;
2059
    parameter adr_sel = 4'hf;
2060
    parameter addr_width = 5;
2061 33 unneback
/*
2062
`ifndef BOOT_ROM
2063
`define BOOT_ROM "boot_rom.v"
2064
`endif
2065
*/
2066 18 unneback
    input [adr_hi:2]    wb_adr_i;
2067
    input               wb_stb_i;
2068
    input               wb_cyc_i;
2069
    output [31:0]        wb_dat_o;
2070
    output              wb_ack_o;
2071
    output              hit_o;
2072
    input               wb_clk;
2073
    input               wb_rst;
2074
    wire hit;
2075
    reg [31:0] wb_dat;
2076
    reg wb_ack;
2077
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2078 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2079
    if (wb_rst)
2080 18 unneback
        wb_dat <= 32'h15000000;
2081 17 unneback
    else
2082 18 unneback
         case (wb_adr_i[addr_width-1:2])
2083 33 unneback
`ifdef BOOT_ROM
2084
`include `BOOT_ROM
2085
`endif
2086 17 unneback
           /*
2087
            // Zero r0 and jump to 0x00000100
2088 18 unneback
 
2089
            1 : wb_dat <= 32'hA8200000;
2090
            2 : wb_dat <= 32'hA8C00100;
2091
            3 : wb_dat <= 32'h44003000;
2092
            4 : wb_dat <= 32'h15000000;
2093 17 unneback
            */
2094
           default:
2095 18 unneback
             wb_dat <= 32'h00000000;
2096 17 unneback
         endcase // case (wb_adr_i)
2097
always @ (posedge wb_clk or posedge wb_rst)
2098
    if (wb_rst)
2099 18 unneback
        wb_ack <= 1'b0;
2100 17 unneback
    else
2101 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2102
assign hit_o = hit;
2103
assign wb_dat_o = wb_dat & {32{wb_ack}};
2104
assign wb_ack_o = wb_ack;
2105 17 unneback
endmodule
2106 32 unneback
module vl_wb_dpram (
2107
        // wishbone slave side a
2108
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
2109
        wbsa_clk, wbsa_rst,
2110
        // wishbone slave side a
2111
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
2112
        wbsb_clk, wbsb_rst);
2113
parameter data_width = 32;
2114
parameter addr_width = 8;
2115
parameter dat_o_mask_a = 1;
2116
parameter dat_o_mask_b = 1;
2117
input [31:0] wbsa_dat_i;
2118
input [addr_width-1:2] wbsa_adr_i;
2119
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2120
output [31:0] wbsa_dat_o;
2121
output wbsa_ack_o;
2122
input wbsa_clk, wbsa_rst;
2123
input [31:0] wbsb_dat_i;
2124
input [addr_width-1:2] wbsb_adr_i;
2125
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2126
output [31:0] wbsb_dat_o;
2127
output wbsb_ack_o;
2128
input wbsb_clk, wbsb_rst;
2129
wire wbsa_dat_tmp, wbsb_dat_tmp;
2130
vl_dpram_2r2w # (
2131 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
2132 32 unneback
dpram0(
2133
    .d_a(wbsa_dat_i),
2134
    .q_a(wbsa_dat_tmp),
2135
    .adr_a(wbsa_adr_i),
2136
    .we_a(wbsa_we_i),
2137
    .clk_a(wbsa_clk),
2138
    .d_b(wbsb_dat_i),
2139
    .q_b(wbsb_dat_tmp),
2140
    .adr_b(wbsb_adr_i),
2141
    .we_b(wbsb_we_i),
2142
    .clk_b(wbsb_clk) );
2143 33 unneback
generate if (dat_o_mask_a==1)
2144 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
2145
endgenerate
2146 33 unneback
generate if (dat_o_mask_a==0)
2147 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
2148
endgenerate
2149 33 unneback
generate if (dat_o_mask_b==1)
2150 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
2151
endgenerate
2152 33 unneback
generate if (dat_o_mask_b==0)
2153 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
2154
endgenerate
2155
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2156
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2157
endmodule
2158 18 unneback
//////////////////////////////////////////////////////////////////////
2159
////                                                              ////
2160
////  Arithmetic functions                                        ////
2161
////                                                              ////
2162
////  Description                                                 ////
2163
////  Arithmetic functions for ALU and DSP                        ////
2164
////                                                              ////
2165
////                                                              ////
2166
////  To Do:                                                      ////
2167
////   -                                                          ////
2168
////                                                              ////
2169
////  Author(s):                                                  ////
2170
////      - Michael Unneback, unneback@opencores.org              ////
2171
////        ORSoC AB                                              ////
2172
////                                                              ////
2173
//////////////////////////////////////////////////////////////////////
2174
////                                                              ////
2175
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2176
////                                                              ////
2177
//// This source file may be used and distributed without         ////
2178
//// restriction provided that this copyright statement is not    ////
2179
//// removed from the file and that any derivative work contains  ////
2180
//// the original copyright notice and the associated disclaimer. ////
2181
////                                                              ////
2182
//// This source file is free software; you can redistribute it   ////
2183
//// and/or modify it under the terms of the GNU Lesser General   ////
2184
//// Public License as published by the Free Software Foundation; ////
2185
//// either version 2.1 of the License, or (at your option) any   ////
2186
//// later version.                                               ////
2187
////                                                              ////
2188
//// This source is distributed in the hope that it will be       ////
2189
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2190
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2191
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2192
//// details.                                                     ////
2193
////                                                              ////
2194
//// You should have received a copy of the GNU Lesser General    ////
2195
//// Public License along with this source; if not, download it   ////
2196
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
2198
//////////////////////////////////////////////////////////////////////
2199
// signed multiplication
2200
module vl_mults (a,b,p);
2201
parameter operand_a_width = 18;
2202
parameter operand_b_width = 18;
2203
parameter result_hi = 35;
2204
parameter result_lo = 0;
2205
input [operand_a_width-1:0] a;
2206
input [operand_b_width-1:0] b;
2207
output [result_hi:result_lo] p;
2208
wire signed [operand_a_width-1:0] ai;
2209
wire signed [operand_b_width-1:0] bi;
2210
wire signed [operand_a_width+operand_b_width-1:0] result;
2211
    assign ai = a;
2212
    assign bi = b;
2213
    assign result = ai * bi;
2214
    assign p = result[result_hi:result_lo];
2215
endmodule
2216
module vl_mults18x18 (a,b,p);
2217
input [17:0] a,b;
2218
output [35:0] p;
2219
vl_mult
2220
    # (.operand_a_width(18), .operand_b_width(18))
2221
    mult0 (.a(a), .b(b), .p(p));
2222
endmodule
2223
// unsigned multiplication
2224
module vl_mult (a,b,p);
2225
parameter operand_a_width = 18;
2226
parameter operand_b_width = 18;
2227
parameter result_hi = 35;
2228
parameter result_lo = 0;
2229
input [operand_a_width-1:0] a;
2230
input [operand_b_width-1:0] b;
2231
output [result_hi:result_hi] p;
2232
wire [operand_a_width+operand_b_width-1:0] result;
2233
    assign result = a * b;
2234
    assign p = result[result_hi:result_lo];
2235
endmodule
2236
// shift unit
2237
// supporting the following shift functions
2238
//   SLL
2239
//   SRL
2240
//   SRA
2241
module vl_shift_unit_32( din, s, dout, opcode);
2242
input [31:0] din; // data in operand
2243
input [4:0] s; // shift operand
2244
input [1:0] opcode;
2245
output [31:0] dout;
2246
parameter opcode_sll = 2'b00;
2247
//parameter opcode_srl = 2'b01;
2248
parameter opcode_sra = 2'b10;
2249
//parameter opcode_ror = 2'b11;
2250
wire sll, sra;
2251
assign sll = opcode == opcode_sll;
2252
assign sra = opcode == opcode_sra;
2253
wire [15:1] s1;
2254
wire [3:0] sign;
2255
wire [7:0] tmp [0:3];
2256
// first stage is multiplier based
2257
// shift operand as fractional 8.7
2258
assign s1[15] = sll & s[2:0]==3'd7;
2259
assign s1[14] = sll & s[2:0]==3'd6;
2260
assign s1[13] = sll & s[2:0]==3'd5;
2261
assign s1[12] = sll & s[2:0]==3'd4;
2262
assign s1[11] = sll & s[2:0]==3'd3;
2263
assign s1[10] = sll & s[2:0]==3'd2;
2264
assign s1[ 9] = sll & s[2:0]==3'd1;
2265
assign s1[ 8] = s[2:0]==3'd0;
2266
assign s1[ 7] = !sll & s[2:0]==3'd1;
2267
assign s1[ 6] = !sll & s[2:0]==3'd2;
2268
assign s1[ 5] = !sll & s[2:0]==3'd3;
2269
assign s1[ 4] = !sll & s[2:0]==3'd4;
2270
assign s1[ 3] = !sll & s[2:0]==3'd5;
2271
assign s1[ 2] = !sll & s[2:0]==3'd6;
2272
assign s1[ 1] = !sll & s[2:0]==3'd7;
2273
assign sign[3] = din[31] & sra;
2274
assign sign[2] = sign[3] & (&din[31:24]);
2275
assign sign[1] = sign[2] & (&din[23:16]);
2276
assign sign[0] = sign[1] & (&din[15:8]);
2277
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2278
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2279
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2280
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2281
// second stage is multiplexer based
2282
// shift on byte level
2283
// mux byte 3
2284
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2285
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2286
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2287
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2288
                     {8{sign[3]}};
2289
// mux byte 2
2290
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2291
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2292
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2293
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2294
                     (s[4:3]==2'b01) ? tmp[3] :
2295
                     {8{sign[3]}};
2296
// mux byte 1
2297
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2298
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2299
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2300
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2301
                     (s[4:3]==2'b01) ? tmp[2] :
2302
                     (s[4:3]==2'b10) ? tmp[3] :
2303
                     {8{sign[3]}};
2304
// mux byte 0
2305
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2306
                     (sll) ?  {8{1'b0}}:
2307
                     (s[4:3]==2'b01) ? tmp[1] :
2308
                     (s[4:3]==2'b10) ? tmp[2] :
2309
                     tmp[3];
2310
endmodule
2311
// logic unit
2312
// supporting the following logic functions
2313
//    a and b
2314
//    a or  b
2315
//    a xor b
2316
//    not b
2317
module vl_logic_unit( a, b, result, opcode);
2318
parameter width = 32;
2319
parameter opcode_and = 2'b00;
2320
parameter opcode_or  = 2'b01;
2321
parameter opcode_xor = 2'b10;
2322
input [width-1:0] a,b;
2323
output [width-1:0] result;
2324
input [1:0] opcode;
2325
assign result = (opcode==opcode_and) ? a & b :
2326
                (opcode==opcode_or)  ? a | b :
2327
                (opcode==opcode_xor) ? a ^ b :
2328
                b;
2329
endmodule
2330
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2331
parameter width = 32;
2332
parameter opcode_add = 1'b0;
2333
parameter opcode_sub = 1'b1;
2334
input [width-1:0] a,b;
2335
input c_in, add_sub, sign;
2336
output [width-1:0] result;
2337
output c_out, z, ovfl;
2338
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2339
assign z = (result=={width{1'b0}});
2340
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2341
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2342
endmodule

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