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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 48

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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42 21 unneback
//altera
43 33 unneback
module vl_gbuf ( i, o);
44
input i;
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output o;
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assign o = i;
47
endmodule
48 6 unneback
 // ALTERA
49
 //ACTEL
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// sync reset
51 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
52 6 unneback
// output active high global reset sync with two DFFs 
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`timescale 1 ns/100 ps
54
module vl_sync_rst ( rst_n_i, rst_o, clk);
55
input rst_n_i, clk;
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output rst_o;
57 18 unneback
reg [1:0] tmp;
58 6 unneback
always @ (posedge clk or negedge rst_n_i)
59
if (!rst_n_i)
60 17 unneback
        tmp <= 2'b11;
61 6 unneback
else
62 33 unneback
        tmp <= {1'b0,tmp[1]};
63 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
64 6 unneback
endmodule
65
// vl_pll
66 32 unneback
///////////////////////////////////////////////////////////////////////////////
67
`timescale 1 ps/1 ps
68
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
69
parameter index = 0;
70
parameter number_of_clk = 1;
71
parameter period_time_0 = 20000;
72
parameter period_time_1 = 20000;
73
parameter period_time_2 = 20000;
74
parameter period_time_3 = 20000;
75
parameter period_time_4 = 20000;
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parameter lock_delay = 2000000;
77
input clk_i, rst_n_i;
78
output lock;
79
output reg [0:number_of_clk-1] clk_o;
80
output [0:number_of_clk-1] rst_o;
81 33 unneback
`ifdef SIM_PLL
82 32 unneback
always
83
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
84
generate if (number_of_clk > 1)
85
always
86
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
87
endgenerate
88
generate if (number_of_clk > 2)
89
always
90
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
91
endgenerate
92 33 unneback
generate if (number_of_clk > 3)
93 32 unneback
always
94
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
95
endgenerate
96 33 unneback
generate if (number_of_clk > 4)
97 32 unneback
always
98
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
99
endgenerate
100
genvar i;
101
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
102
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
103
end
104
endgenerate
105 33 unneback
//assign #lock_delay lock = rst_n_i;
106
assign lock = rst_n_i;
107 32 unneback
endmodule
108 33 unneback
`else
109
`ifdef VL_PLL0
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`ifdef VL_PLL0_CLK1
111
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
112
`endif
113
`ifdef VL_PLL0_CLK2
114
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL0_CLK3
117
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL0_CLK4
120
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
121
`endif
122
`ifdef VL_PLL0_CLK5
123
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
125
`endif
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`ifdef VL_PLL1
127
`ifdef VL_PLL1_CLK1
128
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
129
`endif
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`ifdef VL_PLL1_CLK2
131
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL1_CLK3
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL1_CLK4
137
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL1_CLK5
140
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL2
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`ifdef VL_PLL2_CLK1
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
146
`endif
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`ifdef VL_PLL2_CLK2
148
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
149
`endif
150
`ifdef VL_PLL2_CLK3
151
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
153
`ifdef VL_PLL2_CLK4
154
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
155
`endif
156
`ifdef VL_PLL2_CLK5
157
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
158
`endif
159
`endif
160
`ifdef VL_PLL3
161
`ifdef VL_PLL3_CLK1
162
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
163
`endif
164
`ifdef VL_PLL3_CLK2
165
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
166
`endif
167
`ifdef VL_PLL3_CLK3
168
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
169
`endif
170
`ifdef VL_PLL3_CLK4
171
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
172
`endif
173
`ifdef VL_PLL3_CLK5
174
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
175
`endif
176
`endif
177 32 unneback
genvar i;
178
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
179 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
180 32 unneback
end
181
endgenerate
182
endmodule
183 33 unneback
`endif
184 32 unneback
///////////////////////////////////////////////////////////////////////////////
185 6 unneback
 //altera
186
 //actel
187
//////////////////////////////////////////////////////////////////////
188
////                                                              ////
189
////  Versatile library, registers                                ////
190
////                                                              ////
191
////  Description                                                 ////
192
////  Different type of registers                                 ////
193
////                                                              ////
194
////                                                              ////
195
////  To Do:                                                      ////
196
////   - add more different registers                             ////
197
////                                                              ////
198
////  Author(s):                                                  ////
199
////      - Michael Unneback, unneback@opencores.org              ////
200
////        ORSoC AB                                              ////
201
////                                                              ////
202
//////////////////////////////////////////////////////////////////////
203
////                                                              ////
204
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
205
////                                                              ////
206
//// This source file may be used and distributed without         ////
207
//// restriction provided that this copyright statement is not    ////
208
//// removed from the file and that any derivative work contains  ////
209
//// the original copyright notice and the associated disclaimer. ////
210
////                                                              ////
211
//// This source file is free software; you can redistribute it   ////
212
//// and/or modify it under the terms of the GNU Lesser General   ////
213
//// Public License as published by the Free Software Foundation; ////
214
//// either version 2.1 of the License, or (at your option) any   ////
215
//// later version.                                               ////
216
////                                                              ////
217
//// This source is distributed in the hope that it will be       ////
218
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
219
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
220
//// PURPOSE.  See the GNU Lesser General Public License for more ////
221
//// details.                                                     ////
222
////                                                              ////
223
//// You should have received a copy of the GNU Lesser General    ////
224
//// Public License along with this source; if not, download it   ////
225
//// from http://www.opencores.org/lgpl.shtml                     ////
226
////                                                              ////
227
//////////////////////////////////////////////////////////////////////
228 18 unneback
module vl_dff ( d, q, clk, rst);
229 6 unneback
        parameter width = 1;
230
        parameter reset_value = 0;
231
        input [width-1:0] d;
232
        input clk, rst;
233
        output reg [width-1:0] q;
234
        always @ (posedge clk or posedge rst)
235
        if (rst)
236
                q <= reset_value;
237
        else
238
                q <= d;
239
endmodule
240 18 unneback
module vl_dff_array ( d, q, clk, rst);
241 6 unneback
        parameter width = 1;
242
        parameter depth = 2;
243
        parameter reset_value = 1'b0;
244
        input [width-1:0] d;
245
        input clk, rst;
246
        output [width-1:0] q;
247
        reg  [0:depth-1] q_tmp [width-1:0];
248
        integer i;
249
        always @ (posedge clk or posedge rst)
250
        if (rst) begin
251
            for (i=0;i<depth;i=i+1)
252
                q_tmp[i] <= {width{reset_value}};
253
        end else begin
254
            q_tmp[0] <= d;
255
            for (i=1;i<depth;i=i+1)
256
                q_tmp[i] <= q_tmp[i-1];
257
        end
258
    assign q = q_tmp[depth-1];
259
endmodule
260 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
261 6 unneback
        parameter width = 1;
262
        parameter reset_value = 0;
263
        input [width-1:0] d;
264
        input ce, clk, rst;
265
        output reg [width-1:0] q;
266
        always @ (posedge clk or posedge rst)
267
        if (rst)
268
                q <= reset_value;
269
        else
270
                if (ce)
271
                        q <= d;
272
endmodule
273 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
274 8 unneback
        parameter width = 1;
275
        parameter reset_value = 0;
276
        input [width-1:0] d;
277 10 unneback
        input ce, clear, clk, rst;
278 8 unneback
        output reg [width-1:0] q;
279
        always @ (posedge clk or posedge rst)
280
        if (rst)
281
            q <= reset_value;
282
        else
283
            if (ce)
284
                if (clear)
285
                    q <= {width{1'b0}};
286
                else
287
                    q <= d;
288
endmodule
289 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
        input [width-1:0] d;
293
        input ce, set, clk, rst;
294
        output reg [width-1:0] q;
295
        always @ (posedge clk or posedge rst)
296
        if (rst)
297
            q <= reset_value;
298
        else
299
            if (ce)
300
                if (set)
301
                    q <= {width{1'b1}};
302
                else
303
                    q <= d;
304
endmodule
305 29 unneback
module vl_spr ( sp, r, q, clk, rst);
306
        parameter width = 1;
307
        parameter reset_value = 0;
308
        input sp, r;
309
        output reg q;
310
        input clk, rst;
311
        always @ (posedge clk or posedge rst)
312
        if (rst)
313
            q <= reset_value;
314
        else
315
            if (sp)
316
                q <= 1'b1;
317
            else if (r)
318
                q <= 1'b0;
319
endmodule
320
module vl_srp ( s, rp, q, clk, rst);
321
        parameter width = 1;
322
        parameter reset_value = 0;
323
        input s, rp;
324
        output reg q;
325
        input clk, rst;
326
        always @ (posedge clk or posedge rst)
327
        if (rst)
328
            q <= reset_value;
329
        else
330
            if (rp)
331
                q <= 1'b0;
332
            else if (s)
333
                q <= 1'b1;
334
endmodule
335 6 unneback
// megafunction wizard: %LPM_FF%
336
// GENERATION: STANDARD
337
// VERSION: WM1.0
338
// MODULE: lpm_ff 
339
// ============================================================
340
// File Name: dff_sr.v
341
// Megafunction Name(s):
342
//                      lpm_ff
343
//
344
// Simulation Library Files(s):
345
//                      lpm
346
// ============================================================
347
// ************************************************************
348
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
349
//
350
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
351
// ************************************************************
352
//Copyright (C) 1991-2010 Altera Corporation
353
//Your use of Altera Corporation's design tools, logic functions 
354
//and other software and tools, and its AMPP partner logic 
355
//functions, and any output files from any of the foregoing 
356
//(including device programming or simulation files), and any 
357
//associated documentation or information are expressly subject 
358
//to the terms and conditions of the Altera Program License 
359
//Subscription Agreement, Altera MegaCore Function License 
360
//Agreement, or other applicable license agreement, including, 
361
//without limitation, that your use is for the sole purpose of 
362
//programming logic devices manufactured by Altera and sold by 
363
//Altera or its authorized distributors.  Please refer to the 
364
//applicable agreement for further details.
365
// synopsys translate_off
366
`timescale 1 ps / 1 ps
367
// synopsys translate_on
368 18 unneback
module vl_dff_sr (
369 6 unneback
        aclr,
370
        aset,
371
        clock,
372
        data,
373
        q);
374
        input     aclr;
375
        input     aset;
376
        input     clock;
377
        input     data;
378
        output    q;
379
        wire [0:0] sub_wire0;
380
        wire [0:0] sub_wire1 = sub_wire0[0:0];
381
        wire  q = sub_wire1;
382
        wire  sub_wire2 = data;
383
        wire  sub_wire3 = sub_wire2;
384
        lpm_ff  lpm_ff_component (
385
                                .aclr (aclr),
386
                                .clock (clock),
387
                                .data (sub_wire3),
388
                                .aset (aset),
389
                                .q (sub_wire0)
390
                                // synopsys translate_off
391
                                ,
392
                                .aload (),
393
                                .enable (),
394
                                .sclr (),
395
                                .sload (),
396
                                .sset ()
397
                                // synopsys translate_on
398
                                );
399
        defparam
400
                lpm_ff_component.lpm_fftype = "DFF",
401
                lpm_ff_component.lpm_type = "LPM_FF",
402
                lpm_ff_component.lpm_width = 1;
403
endmodule
404
// ============================================================
405
// CNX file retrieval info
406
// ============================================================
407
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
408
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
409
// Retrieval info: PRIVATE: ASET NUMERIC "1"
410
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
411
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
412
// Retrieval info: PRIVATE: DFF NUMERIC "1"
413
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
414
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
415
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
416
// Retrieval info: PRIVATE: SSET NUMERIC "0"
417
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
418
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
419
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
420
// Retrieval info: PRIVATE: nBit NUMERIC "1"
421
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
422
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
423
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
424
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
425
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
426
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
427
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
428
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
429
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
430
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
431
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
432
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
433
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
434
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
435
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
436
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
437
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
441
// Retrieval info: LIB_FILE: lpm
442
// LATCH
443
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
444 18 unneback
module vl_latch ( d, le, q, clk);
445 6 unneback
input d, le;
446
output q;
447
input clk;
448
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
449
endmodule
450 18 unneback
module vl_shreg ( d, q, clk, rst);
451 17 unneback
parameter depth = 10;
452
input d;
453
output q;
454
input clk, rst;
455
reg [1:depth] dffs;
456
always @ (posedge clk or posedge rst)
457
if (rst)
458
    dffs <= {depth{1'b0}};
459
else
460
    dffs <= {d,dffs[1:depth-1]};
461
assign q = dffs[depth];
462
endmodule
463 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
464 17 unneback
parameter depth = 10;
465
input d, ce;
466
output q;
467
input clk, rst;
468
reg [1:depth] dffs;
469
always @ (posedge clk or posedge rst)
470
if (rst)
471
    dffs <= {depth{1'b0}};
472
else
473
    if (ce)
474
        dffs <= {d,dffs[1:depth-1]};
475
assign q = dffs[depth];
476
endmodule
477 18 unneback
module vl_delay ( d, q, clk, rst);
478 15 unneback
parameter depth = 10;
479
input d;
480
output q;
481
input clk, rst;
482
reg [1:depth] dffs;
483
always @ (posedge clk or posedge rst)
484
if (rst)
485
    dffs <= {depth{1'b0}};
486
else
487
    dffs <= {d,dffs[1:depth-1]};
488
assign q = dffs[depth];
489
endmodule
490 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
491 17 unneback
parameter depth = 10;
492
input d;
493
output q, emptyflag;
494
input clk, rst;
495
reg [1:depth] dffs;
496
always @ (posedge clk or posedge rst)
497
if (rst)
498
    dffs <= {depth{1'b0}};
499
else
500
    dffs <= {d,dffs[1:depth-1]};
501
assign q = dffs[depth];
502
assign emptyflag = !(|dffs);
503
endmodule
504 6 unneback
//////////////////////////////////////////////////////////////////////
505
////                                                              ////
506 18 unneback
////  Logic functions                                             ////
507
////                                                              ////
508
////  Description                                                 ////
509
////  Logic functions such as multiplexers                        ////
510
////                                                              ////
511
////                                                              ////
512
////  To Do:                                                      ////
513
////   -                                                          ////
514
////                                                              ////
515
////  Author(s):                                                  ////
516
////      - Michael Unneback, unneback@opencores.org              ////
517
////        ORSoC AB                                              ////
518
////                                                              ////
519
//////////////////////////////////////////////////////////////////////
520
////                                                              ////
521
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
522
////                                                              ////
523
//// This source file may be used and distributed without         ////
524
//// restriction provided that this copyright statement is not    ////
525
//// removed from the file and that any derivative work contains  ////
526
//// the original copyright notice and the associated disclaimer. ////
527
////                                                              ////
528
//// This source file is free software; you can redistribute it   ////
529
//// and/or modify it under the terms of the GNU Lesser General   ////
530
//// Public License as published by the Free Software Foundation; ////
531
//// either version 2.1 of the License, or (at your option) any   ////
532
//// later version.                                               ////
533
////                                                              ////
534
//// This source is distributed in the hope that it will be       ////
535
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
536
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
537
//// PURPOSE.  See the GNU Lesser General Public License for more ////
538
//// details.                                                     ////
539
////                                                              ////
540
//// You should have received a copy of the GNU Lesser General    ////
541
//// Public License along with this source; if not, download it   ////
542
//// from http://www.opencores.org/lgpl.shtml                     ////
543
////                                                              ////
544
//////////////////////////////////////////////////////////////////////
545 36 unneback
module vl_mux_andor ( a, sel, dout);
546
parameter width = 32;
547
parameter nr_of_ports = 4;
548
input [nr_of_ports*width-1:0] a;
549
input [nr_of_ports-1:0] sel;
550
output reg [width-1:0] dout;
551 38 unneback
integer i,j;
552 36 unneback
always @ (a, sel)
553
begin
554
    dout = a[width-1:0] & {width{sel[0]}};
555 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
556
        for (j=0;j<width;j=j+1)
557
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
558 36 unneback
end
559
endmodule
560 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
561
parameter width = 32;
562 35 unneback
localparam nr_of_ports = 2;
563 34 unneback
input [width-1:0] a1, a0;
564
input [nr_of_ports-1:0] sel;
565
output [width-1:0] dout;
566 36 unneback
vl_mux_andor
567 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
568 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
569 34 unneback
endmodule
570
module vl_mux3_andor ( a2, a1, a0, sel, dout);
571
parameter width = 32;
572 35 unneback
localparam nr_of_ports = 3;
573 34 unneback
input [width-1:0] a2, a1, a0;
574
input [nr_of_ports-1:0] sel;
575
output [width-1:0] dout;
576 36 unneback
vl_mux_andor
577 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
578 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
579 34 unneback
endmodule
580 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
581
parameter width = 32;
582 35 unneback
localparam nr_of_ports = 4;
583 18 unneback
input [width-1:0] a3, a2, a1, a0;
584
input [nr_of_ports-1:0] sel;
585 22 unneback
output [width-1:0] dout;
586 36 unneback
vl_mux_andor
587 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
588 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
589 18 unneback
endmodule
590
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
591
parameter width = 32;
592 35 unneback
localparam nr_of_ports = 5;
593 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
594
input [nr_of_ports-1:0] sel;
595 22 unneback
output [width-1:0] dout;
596 36 unneback
vl_mux_andor
597 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
598 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
599 18 unneback
endmodule
600
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
601
parameter width = 32;
602 35 unneback
localparam nr_of_ports = 6;
603 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
604
input [nr_of_ports-1:0] sel;
605 22 unneback
output [width-1:0] dout;
606 36 unneback
vl_mux_andor
607 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
608 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
609 18 unneback
endmodule
610 43 unneback
module vl_parity_generate (data, parity);
611
parameter word_size = 32;
612
parameter chunk_size = 8;
613
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
614
input [word_size-1:0] data;
615
output reg [word_size/chunk_size-1:0] parity;
616
integer i,j;
617
always @ (data)
618
for (i=0;i<word_size/chunk_size;i=i+1) begin
619
    parity[i] = parity_type;
620
    for (j=0;j<chunk_size;j=j+1) begin
621 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
622 43 unneback
    end
623
end
624
endmodule
625
module vl_parity_check( data, parity, parity_error);
626
parameter word_size = 32;
627
parameter chunk_size = 8;
628
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
629
input [word_size-1:0] data;
630
input [word_size/chunk_size-1:0] parity;
631
output parity_error;
632 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
633 43 unneback
integer i,j;
634
always @ (data or parity)
635
for (i=0;i<word_size/chunk_size;i=i+1) begin
636
    error_flag[i] = parity[i] ^ parity_type;
637
    for (j=0;j<chunk_size;j=j+1) begin
638 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
639 43 unneback
    end
640
end
641
assign parity_error = |error_flag;
642
endmodule
643 18 unneback
//////////////////////////////////////////////////////////////////////
644
////                                                              ////
645 44 unneback
////  IO functions                                                ////
646
////                                                              ////
647
////  Description                                                 ////
648
////  IO functions such as IOB flip-flops                         ////
649
////                                                              ////
650
////                                                              ////
651
////  To Do:                                                      ////
652
////   -                                                          ////
653
////                                                              ////
654
////  Author(s):                                                  ////
655
////      - Michael Unneback, unneback@opencores.org              ////
656
////        ORSoC AB                                              ////
657
////                                                              ////
658
//////////////////////////////////////////////////////////////////////
659
////                                                              ////
660
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
661
////                                                              ////
662
//// This source file may be used and distributed without         ////
663
//// restriction provided that this copyright statement is not    ////
664
//// removed from the file and that any derivative work contains  ////
665
//// the original copyright notice and the associated disclaimer. ////
666
////                                                              ////
667
//// This source file is free software; you can redistribute it   ////
668
//// and/or modify it under the terms of the GNU Lesser General   ////
669
//// Public License as published by the Free Software Foundation; ////
670
//// either version 2.1 of the License, or (at your option) any   ////
671
//// later version.                                               ////
672
////                                                              ////
673
//// This source is distributed in the hope that it will be       ////
674
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
675
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
676
//// PURPOSE.  See the GNU Lesser General Public License for more ////
677
//// details.                                                     ////
678
////                                                              ////
679
//// You should have received a copy of the GNU Lesser General    ////
680
//// Public License along with this source; if not, download it   ////
681
//// from http://www.opencores.org/lgpl.shtml                     ////
682
////                                                              ////
683
//////////////////////////////////////////////////////////////////////
684 45 unneback
`timescale 1ns/1ns
685 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
686
parameter width = 1;
687 45 unneback
parameter reset_value = {width{1'b0}};
688
input  [width-1:0]  d_i;
689 44 unneback
output [width-1:0] o_pad;
690
input clk, rst;
691
wire [width-1:0] d_i_int `SYN_KEEP;
692 45 unneback
reg  [width-1:0] o_pad_int;
693 44 unneback
assign d_i_int = d_i;
694
genvar i;
695 45 unneback
generate
696 44 unneback
for (i=0;i<width;i=i+1) begin
697
    always @ (posedge clk or posedge rst)
698
    if (rst)
699 45 unneback
        o_pad_int[i] <= reset_value[i];
700 44 unneback
    else
701 45 unneback
        o_pad_int[i] <= d_i_int[i];
702
    assign #1 o_pad[i] = o_pad_int[i];
703 44 unneback
end
704
endgenerate
705
endmodule
706 45 unneback
`timescale 1ns/1ns
707 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
708
parameter width = 1;
709
input  [width-1:0] d_o;
710
output reg [width-1:0] d_i;
711
input oe;
712
inout [width-1:0] io_pad;
713
input clk, rst;
714
wire [width-1:0] oe_d `SYN_KEEP;
715
reg [width-1:0] oe_q;
716
reg [width-1:0] d_o_q;
717
assign oe_d = {width{oe}};
718
genvar i;
719
generate
720
for (i=0;i<width;i=i+1) begin
721
    always @ (posedge clk or posedge rst)
722
    if (rst)
723
        oe_q[i] <= 1'b0;
724
    else
725
        oe_q[i] <= oe_d[i];
726
    always @ (posedge clk or posedge rst)
727
    if (rst)
728
        d_o_q[i] <= 1'b0;
729
    else
730
        d_o_q[i] <= d_o[i];
731
    always @ (posedge clk or posedge rst)
732
    if (rst)
733
        d_i[i] <= 1'b0;
734
    else
735
        d_i[i] <= io_pad[i];
736 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
737 44 unneback
end
738
endgenerate
739
endmodule
740
//////////////////////////////////////////////////////////////////////
741
////                                                              ////
742 6 unneback
////  Versatile counter                                           ////
743
////                                                              ////
744
////  Description                                                 ////
745
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
746
////  counter                                                     ////
747
////                                                              ////
748
////  To Do:                                                      ////
749
////   - add LFSR with more taps                                  ////
750
////                                                              ////
751
////  Author(s):                                                  ////
752
////      - Michael Unneback, unneback@opencores.org              ////
753
////        ORSoC AB                                              ////
754
////                                                              ////
755
//////////////////////////////////////////////////////////////////////
756
////                                                              ////
757
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
758
////                                                              ////
759
//// This source file may be used and distributed without         ////
760
//// restriction provided that this copyright statement is not    ////
761
//// removed from the file and that any derivative work contains  ////
762
//// the original copyright notice and the associated disclaimer. ////
763
////                                                              ////
764
//// This source file is free software; you can redistribute it   ////
765
//// and/or modify it under the terms of the GNU Lesser General   ////
766
//// Public License as published by the Free Software Foundation; ////
767
//// either version 2.1 of the License, or (at your option) any   ////
768
//// later version.                                               ////
769
////                                                              ////
770
//// This source is distributed in the hope that it will be       ////
771
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
772
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
773
//// PURPOSE.  See the GNU Lesser General Public License for more ////
774
//// details.                                                     ////
775
////                                                              ////
776
//// You should have received a copy of the GNU Lesser General    ////
777
//// Public License along with this source; if not, download it   ////
778
//// from http://www.opencores.org/lgpl.shtml                     ////
779
////                                                              ////
780
//////////////////////////////////////////////////////////////////////
781
// binary counter
782 40 unneback
module vl_cnt_bin_ce (
783
 cke, q, rst, clk);
784 22 unneback
   parameter length = 4;
785 6 unneback
   input cke;
786
   output [length:1] q;
787
   input rst;
788
   input clk;
789
   parameter clear_value = 0;
790
   parameter set_value = 1;
791
   parameter wrap_value = 0;
792
   parameter level1_value = 15;
793
   reg  [length:1] qi;
794
   wire [length:1] q_next;
795
   assign q_next = qi + {{length-1{1'b0}},1'b1};
796
   always @ (posedge clk or posedge rst)
797
     if (rst)
798
       qi <= {length{1'b0}};
799
     else
800
     if (cke)
801
       qi <= q_next;
802
   assign q = qi;
803
endmodule
804
//////////////////////////////////////////////////////////////////////
805
////                                                              ////
806
////  Versatile counter                                           ////
807
////                                                              ////
808
////  Description                                                 ////
809
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
810
////  counter                                                     ////
811
////                                                              ////
812
////  To Do:                                                      ////
813
////   - add LFSR with more taps                                  ////
814
////                                                              ////
815
////  Author(s):                                                  ////
816
////      - Michael Unneback, unneback@opencores.org              ////
817
////        ORSoC AB                                              ////
818
////                                                              ////
819
//////////////////////////////////////////////////////////////////////
820
////                                                              ////
821
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
822
////                                                              ////
823
//// This source file may be used and distributed without         ////
824
//// restriction provided that this copyright statement is not    ////
825
//// removed from the file and that any derivative work contains  ////
826
//// the original copyright notice and the associated disclaimer. ////
827
////                                                              ////
828
//// This source file is free software; you can redistribute it   ////
829
//// and/or modify it under the terms of the GNU Lesser General   ////
830
//// Public License as published by the Free Software Foundation; ////
831
//// either version 2.1 of the License, or (at your option) any   ////
832
//// later version.                                               ////
833
////                                                              ////
834
//// This source is distributed in the hope that it will be       ////
835
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
836
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
837
//// PURPOSE.  See the GNU Lesser General Public License for more ////
838
//// details.                                                     ////
839
////                                                              ////
840
//// You should have received a copy of the GNU Lesser General    ////
841
//// Public License along with this source; if not, download it   ////
842
//// from http://www.opencores.org/lgpl.shtml                     ////
843
////                                                              ////
844
//////////////////////////////////////////////////////////////////////
845
// binary counter
846 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
847
 cke, rew, zq, level1, rst, clk);
848 6 unneback
   parameter length = 4;
849
   input cke;
850
   input rew;
851 25 unneback
   output reg zq;
852
   output reg level1;
853
   input rst;
854
   input clk;
855
   parameter clear_value = 0;
856
   parameter set_value = 1;
857
   parameter wrap_value = 1;
858
   parameter level1_value = 15;
859 29 unneback
   wire clear;
860 30 unneback
   assign clear = 1'b0;
861 25 unneback
   reg  [length:1] qi;
862
   wire  [length:1] q_next, q_next_fw, q_next_rew;
863
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
864
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
865
   assign q_next = rew ? q_next_rew : q_next_fw;
866
   always @ (posedge clk or posedge rst)
867
     if (rst)
868
       qi <= {length{1'b0}};
869
     else
870
     if (cke)
871
       qi <= q_next;
872
   always @ (posedge clk or posedge rst)
873
     if (rst)
874
       zq <= 1'b1;
875
     else
876
     if (cke)
877
       zq <= q_next == {length{1'b0}};
878
    always @ (posedge clk or posedge rst)
879
    if (rst)
880
        level1 <= 1'b0;
881
    else
882
    if (cke)
883 29 unneback
    if (clear)
884
        level1 <= 1'b0;
885
    else if (q_next == level1_value)
886 25 unneback
        level1 <= 1'b1;
887
    else if (qi == level1_value & rew)
888
        level1 <= 1'b0;
889
endmodule
890
//////////////////////////////////////////////////////////////////////
891
////                                                              ////
892
////  Versatile counter                                           ////
893
////                                                              ////
894
////  Description                                                 ////
895
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
896
////  counter                                                     ////
897
////                                                              ////
898
////  To Do:                                                      ////
899
////   - add LFSR with more taps                                  ////
900
////                                                              ////
901
////  Author(s):                                                  ////
902
////      - Michael Unneback, unneback@opencores.org              ////
903
////        ORSoC AB                                              ////
904
////                                                              ////
905
//////////////////////////////////////////////////////////////////////
906
////                                                              ////
907
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
908
////                                                              ////
909
//// This source file may be used and distributed without         ////
910
//// restriction provided that this copyright statement is not    ////
911
//// removed from the file and that any derivative work contains  ////
912
//// the original copyright notice and the associated disclaimer. ////
913
////                                                              ////
914
//// This source file is free software; you can redistribute it   ////
915
//// and/or modify it under the terms of the GNU Lesser General   ////
916
//// Public License as published by the Free Software Foundation; ////
917
//// either version 2.1 of the License, or (at your option) any   ////
918
//// later version.                                               ////
919
////                                                              ////
920
//// This source is distributed in the hope that it will be       ////
921
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
922
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
923
//// PURPOSE.  See the GNU Lesser General Public License for more ////
924
//// details.                                                     ////
925
////                                                              ////
926
//// You should have received a copy of the GNU Lesser General    ////
927
//// Public License along with this source; if not, download it   ////
928
//// from http://www.opencores.org/lgpl.shtml                     ////
929
////                                                              ////
930
//////////////////////////////////////////////////////////////////////
931
// binary counter
932 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
933
 cke, rew, q, zq, level1, rst, clk);
934 25 unneback
   parameter length = 4;
935
   input cke;
936
   input rew;
937
   output [length:1] q;
938
   output reg zq;
939
   output reg level1;
940
   input rst;
941
   input clk;
942
   parameter clear_value = 0;
943
   parameter set_value = 1;
944
   parameter wrap_value = 1;
945
   parameter level1_value = 15;
946 29 unneback
   wire clear;
947 30 unneback
   assign clear = 1'b0;
948 25 unneback
   reg  [length:1] qi;
949
   wire  [length:1] q_next, q_next_fw, q_next_rew;
950
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
951
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
952
   assign q_next = rew ? q_next_rew : q_next_fw;
953
   always @ (posedge clk or posedge rst)
954
     if (rst)
955
       qi <= {length{1'b0}};
956
     else
957
     if (cke)
958
       qi <= q_next;
959
   assign q = qi;
960
   always @ (posedge clk or posedge rst)
961
     if (rst)
962
       zq <= 1'b1;
963
     else
964
     if (cke)
965
       zq <= q_next == {length{1'b0}};
966
    always @ (posedge clk or posedge rst)
967
    if (rst)
968
        level1 <= 1'b0;
969
    else
970
    if (cke)
971 29 unneback
    if (clear)
972
        level1 <= 1'b0;
973
    else if (q_next == level1_value)
974 25 unneback
        level1 <= 1'b1;
975
    else if (qi == level1_value & rew)
976
        level1 <= 1'b0;
977
endmodule
978
//////////////////////////////////////////////////////////////////////
979
////                                                              ////
980
////  Versatile counter                                           ////
981
////                                                              ////
982
////  Description                                                 ////
983
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
984
////  counter                                                     ////
985
////                                                              ////
986
////  To Do:                                                      ////
987
////   - add LFSR with more taps                                  ////
988
////                                                              ////
989
////  Author(s):                                                  ////
990
////      - Michael Unneback, unneback@opencores.org              ////
991
////        ORSoC AB                                              ////
992
////                                                              ////
993
//////////////////////////////////////////////////////////////////////
994
////                                                              ////
995
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
996
////                                                              ////
997
//// This source file may be used and distributed without         ////
998
//// restriction provided that this copyright statement is not    ////
999
//// removed from the file and that any derivative work contains  ////
1000
//// the original copyright notice and the associated disclaimer. ////
1001
////                                                              ////
1002
//// This source file is free software; you can redistribute it   ////
1003
//// and/or modify it under the terms of the GNU Lesser General   ////
1004
//// Public License as published by the Free Software Foundation; ////
1005
//// either version 2.1 of the License, or (at your option) any   ////
1006
//// later version.                                               ////
1007
////                                                              ////
1008
//// This source is distributed in the hope that it will be       ////
1009
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1010
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1011
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1012
//// details.                                                     ////
1013
////                                                              ////
1014
//// You should have received a copy of the GNU Lesser General    ////
1015
//// Public License along with this source; if not, download it   ////
1016
//// from http://www.opencores.org/lgpl.shtml                     ////
1017
////                                                              ////
1018
//////////////////////////////////////////////////////////////////////
1019 6 unneback
// GRAY counter
1020 40 unneback
module vl_cnt_gray_ce_bin (
1021
 cke, q, q_bin, rst, clk);
1022 6 unneback
   parameter length = 4;
1023
   input cke;
1024
   output reg [length:1] q;
1025
   output [length:1] q_bin;
1026
   input rst;
1027
   input clk;
1028
   parameter clear_value = 0;
1029
   parameter set_value = 1;
1030
   parameter wrap_value = 8;
1031
   parameter level1_value = 15;
1032
   reg  [length:1] qi;
1033
   wire [length:1] q_next;
1034
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1035
   always @ (posedge clk or posedge rst)
1036
     if (rst)
1037
       qi <= {length{1'b0}};
1038
     else
1039
     if (cke)
1040
       qi <= q_next;
1041
   always @ (posedge clk or posedge rst)
1042
     if (rst)
1043
       q <= {length{1'b0}};
1044
     else
1045
       if (cke)
1046
         q <= (q_next>>1) ^ q_next;
1047
   assign q_bin = qi;
1048
endmodule
1049
//////////////////////////////////////////////////////////////////////
1050
////                                                              ////
1051
////  Versatile library, counters                                 ////
1052
////                                                              ////
1053
////  Description                                                 ////
1054
////  counters                                                    ////
1055
////                                                              ////
1056
////                                                              ////
1057
////  To Do:                                                      ////
1058
////   - add more counters                                        ////
1059
////                                                              ////
1060
////  Author(s):                                                  ////
1061
////      - Michael Unneback, unneback@opencores.org              ////
1062
////        ORSoC AB                                              ////
1063
////                                                              ////
1064
//////////////////////////////////////////////////////////////////////
1065
////                                                              ////
1066
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1067
////                                                              ////
1068
//// This source file may be used and distributed without         ////
1069
//// restriction provided that this copyright statement is not    ////
1070
//// removed from the file and that any derivative work contains  ////
1071
//// the original copyright notice and the associated disclaimer. ////
1072
////                                                              ////
1073
//// This source file is free software; you can redistribute it   ////
1074
//// and/or modify it under the terms of the GNU Lesser General   ////
1075
//// Public License as published by the Free Software Foundation; ////
1076
//// either version 2.1 of the License, or (at your option) any   ////
1077
//// later version.                                               ////
1078
////                                                              ////
1079
//// This source is distributed in the hope that it will be       ////
1080
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1081
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1082
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1083
//// details.                                                     ////
1084
////                                                              ////
1085
//// You should have received a copy of the GNU Lesser General    ////
1086
//// Public License along with this source; if not, download it   ////
1087
//// from http://www.opencores.org/lgpl.shtml                     ////
1088
////                                                              ////
1089
//////////////////////////////////////////////////////////////////////
1090 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1091 6 unneback
   parameter length = 4;
1092
   output reg [0:length-1] q;
1093
   input rst;
1094
   input clk;
1095
    always @ (posedge clk or posedge rst)
1096
    if (rst)
1097
        q <= {1'b1,{length-1{1'b0}}};
1098
    else
1099
        q <= {q[length-1],q[0:length-2]};
1100
endmodule
1101 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1102 6 unneback
   parameter length = 4;
1103
   input cke;
1104
   output reg [0:length-1] q;
1105
   input rst;
1106
   input clk;
1107
    always @ (posedge clk or posedge rst)
1108
    if (rst)
1109
        q <= {1'b1,{length-1{1'b0}}};
1110
    else
1111
        if (cke)
1112
            q <= {q[length-1],q[0:length-2]};
1113
endmodule
1114 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1115 6 unneback
   parameter length = 4;
1116
   input cke, clear;
1117
   output reg [0:length-1] q;
1118
   input rst;
1119
   input clk;
1120
    always @ (posedge clk or posedge rst)
1121
    if (rst)
1122
        q <= {1'b1,{length-1{1'b0}}};
1123
    else
1124
        if (cke)
1125
            if (clear)
1126
                q <= {1'b1,{length-1{1'b0}}};
1127
            else
1128
                q <= q >> 1;
1129
endmodule
1130 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1131 6 unneback
   parameter length = 4;
1132
   input cke, clear;
1133
   output reg [0:length-1] q;
1134
   input rst;
1135
   input clk;
1136
    always @ (posedge clk or posedge rst)
1137
    if (rst)
1138
        q <= {1'b1,{length-1{1'b0}}};
1139
    else
1140
        if (cke)
1141
            if (clear)
1142
                q <= {1'b1,{length-1{1'b0}}};
1143
            else
1144
            q <= {q[length-1],q[0:length-2]};
1145
endmodule
1146
//////////////////////////////////////////////////////////////////////
1147
////                                                              ////
1148
////  Versatile library, memories                                 ////
1149
////                                                              ////
1150
////  Description                                                 ////
1151
////  memories                                                    ////
1152
////                                                              ////
1153
////                                                              ////
1154
////  To Do:                                                      ////
1155
////   - add more memory types                                    ////
1156
////                                                              ////
1157
////  Author(s):                                                  ////
1158
////      - Michael Unneback, unneback@opencores.org              ////
1159
////        ORSoC AB                                              ////
1160
////                                                              ////
1161
//////////////////////////////////////////////////////////////////////
1162
////                                                              ////
1163
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1164
////                                                              ////
1165
//// This source file may be used and distributed without         ////
1166
//// restriction provided that this copyright statement is not    ////
1167
//// removed from the file and that any derivative work contains  ////
1168
//// the original copyright notice and the associated disclaimer. ////
1169
////                                                              ////
1170
//// This source file is free software; you can redistribute it   ////
1171
//// and/or modify it under the terms of the GNU Lesser General   ////
1172
//// Public License as published by the Free Software Foundation; ////
1173
//// either version 2.1 of the License, or (at your option) any   ////
1174
//// later version.                                               ////
1175
////                                                              ////
1176
//// This source is distributed in the hope that it will be       ////
1177
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1178
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1179
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1180
//// details.                                                     ////
1181
////                                                              ////
1182
//// You should have received a copy of the GNU Lesser General    ////
1183
//// Public License along with this source; if not, download it   ////
1184
//// from http://www.opencores.org/lgpl.shtml                     ////
1185
////                                                              ////
1186
//////////////////////////////////////////////////////////////////////
1187
/// ROM
1188 7 unneback
module vl_rom_init ( adr, q, clk);
1189
   parameter data_width = 32;
1190
   parameter addr_width = 8;
1191
   input [(addr_width-1):0]       adr;
1192
   output reg [(data_width-1):0] q;
1193
   input                         clk;
1194
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1195
   parameter memory_file = "vl_rom.vmem";
1196
   initial
1197
     begin
1198
        $readmemh(memory_file, rom);
1199
     end
1200
   always @ (posedge clk)
1201
     q <= rom[adr];
1202
endmodule
1203 6 unneback
// Single port RAM
1204
module vl_ram ( d, adr, we, q, clk);
1205
   parameter data_width = 32;
1206
   parameter addr_width = 8;
1207
   input [(data_width-1):0]      d;
1208
   input [(addr_width-1):0]       adr;
1209
   input                         we;
1210 7 unneback
   output reg [(data_width-1):0] q;
1211 6 unneback
   input                         clk;
1212
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1213 7 unneback
   parameter init = 0;
1214
   parameter memory_file = "vl_ram.vmem";
1215
   generate if (init) begin : init_mem
1216
   initial
1217
     begin
1218
        $readmemh(memory_file, ram);
1219
     end
1220
   end
1221
   endgenerate
1222 6 unneback
   always @ (posedge clk)
1223
   begin
1224
   if (we)
1225
     ram[adr] <= d;
1226
   q <= ram[adr];
1227
   end
1228
endmodule
1229 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1230
   parameter data_width = 32;
1231
   parameter addr_width = 8;
1232
   input [(data_width-1):0]      d;
1233
   input [(addr_width-1):0]       adr;
1234
   input [(addr_width/4)-1:0]    be;
1235
   input                         we;
1236
   output reg [(data_width-1):0] q;
1237
   input                         clk;
1238
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1239
   parameter init = 0;
1240
   parameter memory_file = "vl_ram.vmem";
1241
   generate if (init) begin : init_mem
1242
   initial
1243
     begin
1244
        $readmemh(memory_file, ram);
1245
     end
1246
   end
1247
   endgenerate
1248
   genvar i;
1249
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1250
      always @ (posedge clk)
1251
      if (we & be[i])
1252
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1253
   end
1254
   endgenerate
1255
   always @ (posedge clk)
1256
      q <= ram[adr];
1257
endmodule
1258
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1259 6 unneback
   parameter data_width = 32;
1260
   parameter addr_width = 8;
1261
   input [(data_width-1):0]      d_a;
1262
   input [(addr_width-1):0]       adr_a;
1263
   input [(addr_width-1):0]       adr_b;
1264
   input                         we_a;
1265
   output [(data_width-1):0]      q_b;
1266
   input                         clk_a, clk_b;
1267
   reg [(addr_width-1):0]         adr_b_reg;
1268
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1269 7 unneback
   parameter init = 0;
1270
   parameter memory_file = "vl_ram.vmem";
1271
   generate if (init) begin : init_mem
1272
   initial
1273
     begin
1274
        $readmemh(memory_file, ram);
1275
     end
1276
   end
1277
   endgenerate
1278 6 unneback
   always @ (posedge clk_a)
1279
   if (we_a)
1280
     ram[adr_a] <= d_a;
1281
   always @ (posedge clk_b)
1282
   adr_b_reg <= adr_b;
1283
   assign q_b = ram[adr_b_reg];
1284
endmodule
1285 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1286 6 unneback
   parameter data_width = 32;
1287
   parameter addr_width = 8;
1288
   input [(data_width-1):0]      d_a;
1289
   input [(addr_width-1):0]       adr_a;
1290
   input [(addr_width-1):0]       adr_b;
1291
   input                         we_a;
1292
   output [(data_width-1):0]      q_b;
1293
   output reg [(data_width-1):0] q_a;
1294
   input                         clk_a, clk_b;
1295
   reg [(data_width-1):0]         q_b;
1296
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1297 7 unneback
   parameter init = 0;
1298
   parameter memory_file = "vl_ram.vmem";
1299
   generate if (init) begin : init_mem
1300
   initial
1301
     begin
1302
        $readmemh(memory_file, ram);
1303
     end
1304
   end
1305
   endgenerate
1306 6 unneback
   always @ (posedge clk_a)
1307
     begin
1308
        q_a <= ram[adr_a];
1309
        if (we_a)
1310
             ram[adr_a] <= d_a;
1311
     end
1312
   always @ (posedge clk_b)
1313
          q_b <= ram[adr_b];
1314
endmodule
1315 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1316 6 unneback
   parameter data_width = 32;
1317
   parameter addr_width = 8;
1318
   input [(data_width-1):0]      d_a;
1319
   input [(addr_width-1):0]       adr_a;
1320
   input [(addr_width-1):0]       adr_b;
1321
   input                         we_a;
1322
   output [(data_width-1):0]      q_b;
1323
   input [(data_width-1):0]       d_b;
1324
   output reg [(data_width-1):0] q_a;
1325
   input                         we_b;
1326
   input                         clk_a, clk_b;
1327
   reg [(data_width-1):0]         q_b;
1328
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1329 7 unneback
   parameter init = 0;
1330
   parameter memory_file = "vl_ram.vmem";
1331
   generate if (init) begin : init_mem
1332
   initial
1333
     begin
1334
        $readmemh(memory_file, ram);
1335
     end
1336
   end
1337
   endgenerate
1338 6 unneback
   always @ (posedge clk_a)
1339
     begin
1340
        q_a <= ram[adr_a];
1341
        if (we_a)
1342
             ram[adr_a] <= d_a;
1343
     end
1344
   always @ (posedge clk_b)
1345
     begin
1346
        q_b <= ram[adr_b];
1347
        if (we_b)
1348
          ram[adr_b] <= d_b;
1349
     end
1350
endmodule
1351
// Content addresable memory, CAM
1352
// FIFO
1353 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1354
    d, wr, fifo_full,
1355
    q, rd, fifo_empty,
1356
    fill_level,
1357
    clk, rst
1358
    );
1359
parameter data_width = 18;
1360
parameter addr_width = 4;
1361
// write side
1362
input  [data_width-1:0] d;
1363
input                   wr;
1364
output                  fifo_full;
1365
// read side
1366
output [data_width-1:0] q;
1367
input                   rd;
1368
output                  fifo_empty;
1369
// common
1370
output [addr_width:0]   fill_level;
1371
input rst, clk;
1372
wire [addr_width:1] wadr, radr;
1373
vl_cnt_bin_ce
1374
    # ( .length(addr_width))
1375
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1376
vl_cnt_bin_ce
1377
    # (.length(addr_width))
1378
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1379
vl_dpram_1r1w
1380
    # (.data_width(data_width), .addr_width(addr_width))
1381
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1382 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1383 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1384 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1385
endmodule
1386 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1387
// RAM is supposed to be larger than the two FIFOs
1388
// LFSR counters used adr pointers
1389
module vl_fifo_2r2w_sync_simplex (
1390
    // a side
1391
    a_d, a_wr, a_fifo_full,
1392
    a_q, a_rd, a_fifo_empty,
1393
    a_fill_level,
1394
    // b side
1395
    b_d, b_wr, b_fifo_full,
1396
    b_q, b_rd, b_fifo_empty,
1397
    b_fill_level,
1398
    // common
1399
    clk, rst
1400
    );
1401
parameter data_width = 8;
1402
parameter addr_width = 5;
1403
parameter fifo_full_level = (1<<addr_width)-1;
1404
// a side
1405
input  [data_width-1:0] a_d;
1406
input                   a_wr;
1407
output                  a_fifo_full;
1408
output [data_width-1:0] a_q;
1409
input                   a_rd;
1410
output                  a_fifo_empty;
1411
output [addr_width-1:0] a_fill_level;
1412
// b side
1413
input  [data_width-1:0] b_d;
1414
input                   b_wr;
1415
output                  b_fifo_full;
1416
output [data_width-1:0] b_q;
1417
input                   b_rd;
1418
output                  b_fifo_empty;
1419
output [addr_width-1:0] b_fill_level;
1420
input                   clk;
1421
input                   rst;
1422
// adr_gen
1423
wire [addr_width:1] a_wadr, a_radr;
1424
wire [addr_width:1] b_wadr, b_radr;
1425
// dpram
1426
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1427
vl_cnt_lfsr_ce
1428
    # ( .length(addr_width))
1429
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1430
vl_cnt_lfsr_ce
1431
    # (.length(addr_width))
1432
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1433
vl_cnt_lfsr_ce
1434
    # ( .length(addr_width))
1435
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1436
vl_cnt_lfsr_ce
1437
    # (.length(addr_width))
1438
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1439
// mux read or write adr to DPRAM
1440
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1441
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1442
vl_dpram_2r2w
1443
    # (.data_width(data_width), .addr_width(addr_width+1))
1444
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1445
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1446
vl_cnt_bin_ce_rew_zq_l1
1447 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1448 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1449
vl_cnt_bin_ce_rew_zq_l1
1450 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1451 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1452
endmodule
1453 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1454 11 unneback
   parameter addr_width = 4;
1455
   parameter N = addr_width-1;
1456 6 unneback
   parameter Q1 = 2'b00;
1457
   parameter Q2 = 2'b01;
1458
   parameter Q3 = 2'b11;
1459
   parameter Q4 = 2'b10;
1460
   parameter going_empty = 1'b0;
1461
   parameter going_full  = 1'b1;
1462
   input [N:0]  wptr, rptr;
1463 14 unneback
   output       fifo_empty;
1464 6 unneback
   output       fifo_full;
1465
   input        wclk, rclk, rst;
1466
   wire direction;
1467
   reg  direction_set, direction_clr;
1468
   wire async_empty, async_full;
1469
   wire fifo_full2;
1470 14 unneback
   wire fifo_empty2;
1471 6 unneback
   // direction_set
1472
   always @ (wptr[N:N-1] or rptr[N:N-1])
1473
     case ({wptr[N:N-1],rptr[N:N-1]})
1474
       {Q1,Q2} : direction_set <= 1'b1;
1475
       {Q2,Q3} : direction_set <= 1'b1;
1476
       {Q3,Q4} : direction_set <= 1'b1;
1477
       {Q4,Q1} : direction_set <= 1'b1;
1478
       default : direction_set <= 1'b0;
1479
     endcase
1480
   // direction_clear
1481
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1482
     if (rst)
1483
       direction_clr <= 1'b1;
1484
     else
1485
       case ({wptr[N:N-1],rptr[N:N-1]})
1486
         {Q2,Q1} : direction_clr <= 1'b1;
1487
         {Q3,Q2} : direction_clr <= 1'b1;
1488
         {Q4,Q3} : direction_clr <= 1'b1;
1489
         {Q1,Q4} : direction_clr <= 1'b1;
1490
         default : direction_clr <= 1'b0;
1491
       endcase
1492 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1493 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1494
   assign async_full  = (wptr == rptr) && (direction==going_full);
1495 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1496
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1497 6 unneback
/*
1498
   always @ (posedge wclk or posedge rst or posedge async_full)
1499
     if (rst)
1500
       {fifo_full, fifo_full2} <= 2'b00;
1501
     else if (async_full)
1502
       {fifo_full, fifo_full2} <= 2'b11;
1503
     else
1504
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1505
*/
1506 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1507 6 unneback
     if (async_empty)
1508
       {fifo_empty, fifo_empty2} <= 2'b11;
1509
     else
1510 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1511 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1512
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1513 27 unneback
endmodule // async_compb
1514 6 unneback
module vl_fifo_1r1w_async (
1515
    d, wr, fifo_full, wr_clk, wr_rst,
1516
    q, rd, fifo_empty, rd_clk, rd_rst
1517
    );
1518
parameter data_width = 18;
1519
parameter addr_width = 4;
1520
// write side
1521
input  [data_width-1:0] d;
1522
input                   wr;
1523
output                  fifo_full;
1524
input                   wr_clk;
1525
input                   wr_rst;
1526
// read side
1527
output [data_width-1:0] q;
1528
input                   rd;
1529
output                  fifo_empty;
1530
input                   rd_clk;
1531
input                   rd_rst;
1532
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1533 18 unneback
vl_cnt_gray_ce_bin
1534 6 unneback
    # ( .length(addr_width))
1535
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1536 18 unneback
vl_cnt_gray_ce_bin
1537 6 unneback
    # (.length(addr_width))
1538 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1539 7 unneback
vl_dpram_1r1w
1540 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1541
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1542
vl_fifo_cmp_async
1543
    # (.addr_width(addr_width))
1544
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1545
endmodule
1546 8 unneback
module vl_fifo_2r2w_async (
1547 6 unneback
    // a side
1548
    a_d, a_wr, a_fifo_full,
1549
    a_q, a_rd, a_fifo_empty,
1550
    a_clk, a_rst,
1551
    // b side
1552
    b_d, b_wr, b_fifo_full,
1553
    b_q, b_rd, b_fifo_empty,
1554
    b_clk, b_rst
1555
    );
1556
parameter data_width = 18;
1557
parameter addr_width = 4;
1558
// a side
1559
input  [data_width-1:0] a_d;
1560
input                   a_wr;
1561
output                  a_fifo_full;
1562
output [data_width-1:0] a_q;
1563
input                   a_rd;
1564
output                  a_fifo_empty;
1565
input                   a_clk;
1566
input                   a_rst;
1567
// b side
1568
input  [data_width-1:0] b_d;
1569
input                   b_wr;
1570
output                  b_fifo_full;
1571
output [data_width-1:0] b_q;
1572
input                   b_rd;
1573
output                  b_fifo_empty;
1574
input                   b_clk;
1575
input                   b_rst;
1576
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1577
vl_fifo_1r1w_async_a (
1578
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1579
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1580
    );
1581
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1582
vl_fifo_1r1w_async_b (
1583
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1584
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1585
    );
1586
endmodule
1587 8 unneback
module vl_fifo_2r2w_async_simplex (
1588 6 unneback
    // a side
1589
    a_d, a_wr, a_fifo_full,
1590
    a_q, a_rd, a_fifo_empty,
1591
    a_clk, a_rst,
1592
    // b side
1593
    b_d, b_wr, b_fifo_full,
1594
    b_q, b_rd, b_fifo_empty,
1595
    b_clk, b_rst
1596
    );
1597
parameter data_width = 18;
1598
parameter addr_width = 4;
1599
// a side
1600
input  [data_width-1:0] a_d;
1601
input                   a_wr;
1602
output                  a_fifo_full;
1603
output [data_width-1:0] a_q;
1604
input                   a_rd;
1605
output                  a_fifo_empty;
1606
input                   a_clk;
1607
input                   a_rst;
1608
// b side
1609
input  [data_width-1:0] b_d;
1610
input                   b_wr;
1611
output                  b_fifo_full;
1612
output [data_width-1:0] b_q;
1613
input                   b_rd;
1614
output                  b_fifo_empty;
1615
input                   b_clk;
1616
input                   b_rst;
1617
// adr_gen
1618
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1619
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1620
// dpram
1621
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1622 18 unneback
vl_cnt_gray_ce_bin
1623 6 unneback
    # ( .length(addr_width))
1624
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1625 18 unneback
vl_cnt_gray_ce_bin
1626 6 unneback
    # (.length(addr_width))
1627
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1628 18 unneback
vl_cnt_gray_ce_bin
1629 6 unneback
    # ( .length(addr_width))
1630
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1631 18 unneback
vl_cnt_gray_ce_bin
1632 6 unneback
    # (.length(addr_width))
1633
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1634
// mux read or write adr to DPRAM
1635
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1636
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1637 11 unneback
vl_dpram_2r2w
1638 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1639
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1640
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1641 11 unneback
vl_fifo_cmp_async
1642 6 unneback
    # (.addr_width(addr_width))
1643
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1644 11 unneback
vl_fifo_cmp_async
1645 6 unneback
    # (.addr_width(addr_width))
1646
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1647
endmodule
1648 48 unneback
module vl_reg_file (
1649
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1650
);
1651
parameter data_width = 32;
1652
parameter addr_width = 5;
1653
input [addr_width-1:0] a1, a2, a3;
1654
input [data_width-1:0] wd3;
1655
input we3;
1656
output [data_width-1:0] rd1, rd2;
1657
input clk;
1658
vl_dpram_1r1w
1659
    # ( .data_width(data_width), .addr_width(addr_width))
1660
    ram1 (
1661
        .d_a(wd3),
1662
        .adr_a(a3),
1663
        .we_a(we3),
1664
        .clk_a(clk),
1665
        .q_b(rd1),
1666
        .adr_b(a1),
1667
        .clk_b(clk) );
1668
vl_dpram_1r1w
1669
    # ( .data_width(data_width), .addr_width(addr_width))
1670
    ram2 (
1671
        .d_a(wd3),
1672
        .adr_a(a3),
1673
        .we_a(we3),
1674
        .clk_a(clk),
1675
        .q_b(rd2),
1676
        .adr_b(a2),
1677
        .clk_b(clk) );
1678
endmodule
1679 12 unneback
//////////////////////////////////////////////////////////////////////
1680
////                                                              ////
1681
////  Versatile library, wishbone stuff                           ////
1682
////                                                              ////
1683
////  Description                                                 ////
1684
////  Wishbone compliant modules                                  ////
1685
////                                                              ////
1686
////                                                              ////
1687
////  To Do:                                                      ////
1688
////   -                                                          ////
1689
////                                                              ////
1690
////  Author(s):                                                  ////
1691
////      - Michael Unneback, unneback@opencores.org              ////
1692
////        ORSoC AB                                              ////
1693
////                                                              ////
1694
//////////////////////////////////////////////////////////////////////
1695
////                                                              ////
1696
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1697
////                                                              ////
1698
//// This source file may be used and distributed without         ////
1699
//// restriction provided that this copyright statement is not    ////
1700
//// removed from the file and that any derivative work contains  ////
1701
//// the original copyright notice and the associated disclaimer. ////
1702
////                                                              ////
1703
//// This source file is free software; you can redistribute it   ////
1704
//// and/or modify it under the terms of the GNU Lesser General   ////
1705
//// Public License as published by the Free Software Foundation; ////
1706
//// either version 2.1 of the License, or (at your option) any   ////
1707
//// later version.                                               ////
1708
////                                                              ////
1709
//// This source is distributed in the hope that it will be       ////
1710
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1711
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1712
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1713
//// details.                                                     ////
1714
////                                                              ////
1715
//// You should have received a copy of the GNU Lesser General    ////
1716
//// Public License along with this source; if not, download it   ////
1717
//// from http://www.opencores.org/lgpl.shtml                     ////
1718
////                                                              ////
1719
//////////////////////////////////////////////////////////////////////
1720
// async wb3 - wb3 bridge
1721
`timescale 1ns/1ns
1722 18 unneback
module vl_wb3wb3_bridge (
1723 12 unneback
        // wishbone slave side
1724
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1725
        // wishbone master side
1726
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1727
input [31:0] wbs_dat_i;
1728
input [31:2] wbs_adr_i;
1729
input [3:0]  wbs_sel_i;
1730
input [1:0]  wbs_bte_i;
1731
input [2:0]  wbs_cti_i;
1732
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1733
output [31:0] wbs_dat_o;
1734 14 unneback
output wbs_ack_o;
1735 12 unneback
input wbs_clk, wbs_rst;
1736
output [31:0] wbm_dat_o;
1737
output reg [31:2] wbm_adr_o;
1738
output [3:0]  wbm_sel_o;
1739
output reg [1:0]  wbm_bte_o;
1740
output reg [2:0]  wbm_cti_o;
1741 14 unneback
output reg wbm_we_o;
1742
output wbm_cyc_o;
1743 12 unneback
output wbm_stb_o;
1744
input [31:0]  wbm_dat_i;
1745
input wbm_ack_i;
1746
input wbm_clk, wbm_rst;
1747
parameter addr_width = 4;
1748
// bte
1749
parameter linear       = 2'b00;
1750
parameter wrap4        = 2'b01;
1751
parameter wrap8        = 2'b10;
1752
parameter wrap16       = 2'b11;
1753
// cti
1754
parameter classic      = 3'b000;
1755
parameter incburst     = 3'b010;
1756
parameter endofburst   = 3'b111;
1757
parameter wbs_adr  = 1'b0;
1758
parameter wbs_data = 1'b1;
1759 33 unneback
parameter wbm_adr0      = 2'b00;
1760
parameter wbm_adr1      = 2'b01;
1761
parameter wbm_data      = 2'b10;
1762
parameter wbm_data_wait = 2'b11;
1763 12 unneback
reg [1:0] wbs_bte_reg;
1764
reg wbs;
1765
wire wbs_eoc_alert, wbm_eoc_alert;
1766
reg wbs_eoc, wbm_eoc;
1767
reg [1:0] wbm;
1768 14 unneback
wire [1:16] wbs_count, wbm_count;
1769 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1770
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1771
reg a_rd_reg;
1772
wire b_rd_adr, b_rd_data;
1773 14 unneback
wire b_rd_data_reg;
1774
wire [35:0] temp;
1775 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1776
always @ (posedge wbs_clk or posedge wbs_rst)
1777
if (wbs_rst)
1778
        wbs_eoc <= 1'b0;
1779
else
1780
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1781
                wbs_eoc <= wbs_bte_i==linear;
1782
        else if (wbs_eoc_alert & (a_rd | a_wr))
1783
                wbs_eoc <= 1'b1;
1784 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1785 12 unneback
    cnt0 (
1786
        .cke(wbs_ack_o),
1787
        .clear(wbs_eoc),
1788
        .q(wbs_count),
1789
        .rst(wbs_rst),
1790
        .clk(wbs_clk));
1791
always @ (posedge wbs_clk or posedge wbs_rst)
1792
if (wbs_rst)
1793
        wbs <= wbs_adr;
1794
else
1795
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1796
                wbs <= wbs_data;
1797
        else if (wbs_eoc & wbs_ack_o)
1798
                wbs <= wbs_adr;
1799
// wbs FIFO
1800
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1801
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1802
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1803
              1'b0;
1804
assign a_rd = !a_fifo_empty;
1805
always @ (posedge wbs_clk or posedge wbs_rst)
1806
if (wbs_rst)
1807
        a_rd_reg <= 1'b0;
1808
else
1809
        a_rd_reg <= a_rd;
1810
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1811
assign wbs_dat_o = a_q[35:4];
1812
always @ (posedge wbs_clk or posedge wbs_rst)
1813
if (wbs_rst)
1814 13 unneback
        wbs_bte_reg <= 2'b00;
1815 12 unneback
else
1816 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1817 12 unneback
// wbm FIFO
1818
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1819
always @ (posedge wbm_clk or posedge wbm_rst)
1820
if (wbm_rst)
1821
        wbm_eoc <= 1'b0;
1822
else
1823
        if (wbm==wbm_adr0 & !b_fifo_empty)
1824
                wbm_eoc <= b_q[4:3] == linear;
1825
        else if (wbm_eoc_alert & wbm_ack_i)
1826
                wbm_eoc <= 1'b1;
1827
always @ (posedge wbm_clk or posedge wbm_rst)
1828
if (wbm_rst)
1829
        wbm <= wbm_adr0;
1830
else
1831 33 unneback
/*
1832 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1833
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1834
        (wbm==wbm_adr1 & !wbm_we_o) |
1835
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1836
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1837 33 unneback
*/
1838
    case (wbm)
1839
    wbm_adr0:
1840
        if (!b_fifo_empty)
1841
            wbm <= wbm_adr1;
1842
    wbm_adr1:
1843
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1844
            wbm <= wbm_data;
1845
    wbm_data:
1846
        if (wbm_ack_i & wbm_eoc)
1847
            wbm <= wbm_adr0;
1848
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1849
            wbm <= wbm_data_wait;
1850
    wbm_data_wait:
1851
        if (!b_fifo_empty)
1852
            wbm <= wbm_data;
1853
    endcase
1854 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1855
assign b_wr = !wbm_we_o & wbm_ack_i;
1856
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1857
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1858
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1859 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1860 12 unneback
                   1'b0;
1861
assign b_rd = b_rd_adr | b_rd_data;
1862 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1863
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1864 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1865 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1866 12 unneback
    cnt1 (
1867
        .cke(wbm_ack_i),
1868
        .clear(wbm_eoc),
1869
        .q(wbm_count),
1870
        .rst(wbm_rst),
1871
        .clk(wbm_clk));
1872 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1873
assign wbm_stb_o = (wbm==wbm_data);
1874 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1875
if (wbm_rst)
1876
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1877
else begin
1878
        if (wbm==wbm_adr0 & !b_fifo_empty)
1879
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1880
        else if (wbm_eoc_alert & wbm_ack_i)
1881
                wbm_cti_o <= endofburst;
1882
end
1883
//async_fifo_dw_simplex_top
1884
vl_fifo_2r2w_async_simplex
1885
# ( .data_width(36), .addr_width(addr_width))
1886
fifo (
1887
    // a side
1888
    .a_d(a_d),
1889
    .a_wr(a_wr),
1890
    .a_fifo_full(a_fifo_full),
1891
    .a_q(a_q),
1892
    .a_rd(a_rd),
1893
    .a_fifo_empty(a_fifo_empty),
1894
    .a_clk(wbs_clk),
1895
    .a_rst(wbs_rst),
1896
    // b side
1897
    .b_d(b_d),
1898
    .b_wr(b_wr),
1899
    .b_fifo_full(b_fifo_full),
1900
    .b_q(b_q),
1901
    .b_rd(b_rd),
1902
    .b_fifo_empty(b_fifo_empty),
1903
    .b_clk(wbm_clk),
1904
    .b_rst(wbm_rst)
1905
    );
1906
endmodule
1907 39 unneback
module vl_wb3_arbiter_type1 (
1908
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1909
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1910
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1911
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1912
    wb_clk, wb_rst
1913
);
1914
parameter nr_of_ports = 3;
1915
parameter adr_size = 26;
1916
parameter adr_lo   = 2;
1917
parameter dat_size = 32;
1918
parameter sel_size = dat_size/8;
1919
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1920
localparam dw = dat_size * nr_of_ports;
1921
localparam sw = sel_size * nr_of_ports;
1922
localparam cw = 3 * nr_of_ports;
1923
localparam bw = 2 * nr_of_ports;
1924
input  [dw-1:0] wbm_dat_o;
1925
input  [aw-1:0] wbm_adr_o;
1926
input  [sw-1:0] wbm_sel_o;
1927
input  [cw-1:0] wbm_cti_o;
1928
input  [bw-1:0] wbm_bte_o;
1929
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1930
output [dw-1:0] wbm_dat_i;
1931
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1932
output [dat_size-1:0] wbs_dat_i;
1933
output [adr_size-1:adr_lo] wbs_adr_i;
1934
output [sel_size-1:0] wbs_sel_i;
1935
output [2:0] wbs_cti_i;
1936
output [1:0] wbs_bte_i;
1937
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1938
input  [dat_size-1:0] wbs_dat_o;
1939
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1940
input wb_clk, wb_rst;
1941 44 unneback
reg  [nr_of_ports-1:0] select;
1942 39 unneback
wire [nr_of_ports-1:0] state;
1943
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1944
wire [nr_of_ports-1:0] sel;
1945
wire idle;
1946
genvar i;
1947
assign idle = !(|state);
1948
generate
1949
if (nr_of_ports == 2) begin
1950
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1951
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1952 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1953
    always @ (idle or wbm_cyc_o)
1954
    if (idle)
1955
        casex (wbm_cyc_o)
1956
        2'b1x : select = 2'b10;
1957
        2'b01 : select = 2'b01;
1958
        default : select = {nr_of_ports{1'b0}};
1959
        endcase
1960
    else
1961
        select = {nr_of_ports{1'b0}};
1962 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1963
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1964
end
1965
endgenerate
1966
generate
1967
if (nr_of_ports == 3) begin
1968
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1969
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1970 44 unneback
    always @ (idle or wbm_cyc_o)
1971
    if (idle)
1972
        casex (wbm_cyc_o)
1973
        3'b1xx : select = 3'b100;
1974
        3'b01x : select = 3'b010;
1975
        3'b001 : select = 3'b001;
1976
        default : select = {nr_of_ports{1'b0}};
1977
        endcase
1978
    else
1979
        select = {nr_of_ports{1'b0}};
1980
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1981 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1982
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1983
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1984
end
1985
endgenerate
1986
generate
1987 44 unneback
if (nr_of_ports == 4) begin
1988
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1989
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1990
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1991
    always @ (idle or wbm_cyc_o)
1992
    if (idle)
1993
        casex (wbm_cyc_o)
1994
        4'b1xxx : select = 4'b1000;
1995
        4'b01xx : select = 4'b0100;
1996
        4'b001x : select = 4'b0010;
1997
        4'b0001 : select = 4'b0001;
1998
        default : select = {nr_of_ports{1'b0}};
1999
        endcase
2000
    else
2001
        select = {nr_of_ports{1'b0}};
2002
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
2003
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2004
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2005
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2006
end
2007
endgenerate
2008
generate
2009
if (nr_of_ports == 5) begin
2010
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2011
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2012
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2013
    always @ (idle or wbm_cyc_o)
2014
    if (idle)
2015
        casex (wbm_cyc_o)
2016
        5'b1xxxx : select = 5'b10000;
2017
        5'b01xxx : select = 5'b01000;
2018
        5'b001xx : select = 5'b00100;
2019
        5'b0001x : select = 5'b00010;
2020
        5'b00001 : select = 5'b00001;
2021
        default : select = {nr_of_ports{1'b0}};
2022
        endcase
2023
    else
2024
        select = {nr_of_ports{1'b0}};
2025
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
2026
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
2027
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2028
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2029
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2030
end
2031
endgenerate
2032
generate
2033 39 unneback
for (i=0;i<nr_of_ports;i=i+1) begin
2034
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
2035
end
2036
endgenerate
2037
    assign sel = select | state;
2038
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
2039
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
2040
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
2041
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
2042
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
2043
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
2044
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
2045
    assign wbs_cyc_i = |sel;
2046
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
2047
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
2048
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
2049
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
2050
endmodule
2051 17 unneback
// WB ROM
2052 48 unneback
module vl_wb_b4_rom (
2053
    wb_adr_i, wb_stb_i, wb_cyc_i,
2054
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
2055
    parameter dat_width = 32;
2056
    parameter dat_default = 32'h15000000;
2057
    parameter adr_width = 32;
2058
/*
2059
`ifndef ROM
2060
`define ROM "rom.v"
2061
`endif
2062
*/
2063
    input [adr_width-1:2]   wb_adr_i;
2064
    input                   wb_stb_i;
2065
    input                   wb_cyc_i;
2066
    output [dat_width-1:0]  wb_dat_o;
2067
    reg [dat_width-1:0]     wb_dat_o;
2068
    output                  wb_ack_o;
2069
    reg                     wb_ack_o;
2070
    output                  stall_o;
2071
    input                   wb_clk;
2072
    input                   wb_rst;
2073
always @ (posedge wb_clk or posedge wb_rst)
2074
    if (wb_rst)
2075
        wb_dat_o <= {dat_width{1'b0}};
2076
    else
2077
         case (wb_adr_i[adr_width-1:2])
2078
`ifdef ROM
2079
`include `ROM
2080
`endif
2081
           default:
2082
             wb_dat_o <= dat_default;
2083
         endcase // case (wb_adr_i)
2084
always @ (posedge wb_clk or posedge wb_rst)
2085
    if (wb_rst)
2086
        wb_ack_o <= 1'b0;
2087
    else
2088
        wb_ack_o <= wb_stb_i & wb_cyc_i;
2089
assign stall_o = 1'b0;
2090
endmodule
2091
// WB ROM
2092 18 unneback
module vl_wb_boot_rom (
2093 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2094 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2095
    parameter adr_hi = 31;
2096
    parameter adr_lo = 28;
2097
    parameter adr_sel = 4'hf;
2098
    parameter addr_width = 5;
2099 33 unneback
/*
2100
`ifndef BOOT_ROM
2101
`define BOOT_ROM "boot_rom.v"
2102
`endif
2103
*/
2104 18 unneback
    input [adr_hi:2]    wb_adr_i;
2105
    input               wb_stb_i;
2106
    input               wb_cyc_i;
2107
    output [31:0]        wb_dat_o;
2108
    output              wb_ack_o;
2109
    output              hit_o;
2110
    input               wb_clk;
2111
    input               wb_rst;
2112
    wire hit;
2113
    reg [31:0] wb_dat;
2114
    reg wb_ack;
2115
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2116 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2117
    if (wb_rst)
2118 18 unneback
        wb_dat <= 32'h15000000;
2119 17 unneback
    else
2120 18 unneback
         case (wb_adr_i[addr_width-1:2])
2121 33 unneback
`ifdef BOOT_ROM
2122
`include `BOOT_ROM
2123
`endif
2124 17 unneback
           /*
2125
            // Zero r0 and jump to 0x00000100
2126 18 unneback
 
2127
            1 : wb_dat <= 32'hA8200000;
2128
            2 : wb_dat <= 32'hA8C00100;
2129
            3 : wb_dat <= 32'h44003000;
2130
            4 : wb_dat <= 32'h15000000;
2131 17 unneback
            */
2132
           default:
2133 18 unneback
             wb_dat <= 32'h00000000;
2134 17 unneback
         endcase // case (wb_adr_i)
2135
always @ (posedge wb_clk or posedge wb_rst)
2136
    if (wb_rst)
2137 18 unneback
        wb_ack <= 1'b0;
2138 17 unneback
    else
2139 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2140
assign hit_o = hit;
2141
assign wb_dat_o = wb_dat & {32{wb_ack}};
2142
assign wb_ack_o = wb_ack;
2143 17 unneback
endmodule
2144 32 unneback
module vl_wb_dpram (
2145
        // wishbone slave side a
2146
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
2147
        wbsa_clk, wbsa_rst,
2148
        // wishbone slave side a
2149
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
2150
        wbsb_clk, wbsb_rst);
2151
parameter data_width = 32;
2152
parameter addr_width = 8;
2153
parameter dat_o_mask_a = 1;
2154
parameter dat_o_mask_b = 1;
2155
input [31:0] wbsa_dat_i;
2156
input [addr_width-1:2] wbsa_adr_i;
2157
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2158
output [31:0] wbsa_dat_o;
2159
output wbsa_ack_o;
2160
input wbsa_clk, wbsa_rst;
2161
input [31:0] wbsb_dat_i;
2162
input [addr_width-1:2] wbsb_adr_i;
2163
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2164
output [31:0] wbsb_dat_o;
2165
output wbsb_ack_o;
2166
input wbsb_clk, wbsb_rst;
2167
wire wbsa_dat_tmp, wbsb_dat_tmp;
2168
vl_dpram_2r2w # (
2169 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
2170 32 unneback
dpram0(
2171
    .d_a(wbsa_dat_i),
2172
    .q_a(wbsa_dat_tmp),
2173
    .adr_a(wbsa_adr_i),
2174
    .we_a(wbsa_we_i),
2175
    .clk_a(wbsa_clk),
2176
    .d_b(wbsb_dat_i),
2177
    .q_b(wbsb_dat_tmp),
2178
    .adr_b(wbsb_adr_i),
2179
    .we_b(wbsb_we_i),
2180
    .clk_b(wbsb_clk) );
2181 33 unneback
generate if (dat_o_mask_a==1)
2182 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
2183
endgenerate
2184 33 unneback
generate if (dat_o_mask_a==0)
2185 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
2186
endgenerate
2187 33 unneback
generate if (dat_o_mask_b==1)
2188 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
2189
endgenerate
2190 33 unneback
generate if (dat_o_mask_b==0)
2191 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
2192
endgenerate
2193
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2194
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2195
endmodule
2196 18 unneback
//////////////////////////////////////////////////////////////////////
2197
////                                                              ////
2198
////  Arithmetic functions                                        ////
2199
////                                                              ////
2200
////  Description                                                 ////
2201
////  Arithmetic functions for ALU and DSP                        ////
2202
////                                                              ////
2203
////                                                              ////
2204
////  To Do:                                                      ////
2205
////   -                                                          ////
2206
////                                                              ////
2207
////  Author(s):                                                  ////
2208
////      - Michael Unneback, unneback@opencores.org              ////
2209
////        ORSoC AB                                              ////
2210
////                                                              ////
2211
//////////////////////////////////////////////////////////////////////
2212
////                                                              ////
2213
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2214
////                                                              ////
2215
//// This source file may be used and distributed without         ////
2216
//// restriction provided that this copyright statement is not    ////
2217
//// removed from the file and that any derivative work contains  ////
2218
//// the original copyright notice and the associated disclaimer. ////
2219
////                                                              ////
2220
//// This source file is free software; you can redistribute it   ////
2221
//// and/or modify it under the terms of the GNU Lesser General   ////
2222
//// Public License as published by the Free Software Foundation; ////
2223
//// either version 2.1 of the License, or (at your option) any   ////
2224
//// later version.                                               ////
2225
////                                                              ////
2226
//// This source is distributed in the hope that it will be       ////
2227
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2228
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2229
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2230
//// details.                                                     ////
2231
////                                                              ////
2232
//// You should have received a copy of the GNU Lesser General    ////
2233
//// Public License along with this source; if not, download it   ////
2234
//// from http://www.opencores.org/lgpl.shtml                     ////
2235
////                                                              ////
2236
//////////////////////////////////////////////////////////////////////
2237
// signed multiplication
2238
module vl_mults (a,b,p);
2239
parameter operand_a_width = 18;
2240
parameter operand_b_width = 18;
2241
parameter result_hi = 35;
2242
parameter result_lo = 0;
2243
input [operand_a_width-1:0] a;
2244
input [operand_b_width-1:0] b;
2245
output [result_hi:result_lo] p;
2246
wire signed [operand_a_width-1:0] ai;
2247
wire signed [operand_b_width-1:0] bi;
2248
wire signed [operand_a_width+operand_b_width-1:0] result;
2249
    assign ai = a;
2250
    assign bi = b;
2251
    assign result = ai * bi;
2252
    assign p = result[result_hi:result_lo];
2253
endmodule
2254
module vl_mults18x18 (a,b,p);
2255
input [17:0] a,b;
2256
output [35:0] p;
2257
vl_mult
2258
    # (.operand_a_width(18), .operand_b_width(18))
2259
    mult0 (.a(a), .b(b), .p(p));
2260
endmodule
2261
// unsigned multiplication
2262
module vl_mult (a,b,p);
2263
parameter operand_a_width = 18;
2264
parameter operand_b_width = 18;
2265
parameter result_hi = 35;
2266
parameter result_lo = 0;
2267
input [operand_a_width-1:0] a;
2268
input [operand_b_width-1:0] b;
2269
output [result_hi:result_hi] p;
2270
wire [operand_a_width+operand_b_width-1:0] result;
2271
    assign result = a * b;
2272
    assign p = result[result_hi:result_lo];
2273
endmodule
2274
// shift unit
2275
// supporting the following shift functions
2276
//   SLL
2277
//   SRL
2278
//   SRA
2279
module vl_shift_unit_32( din, s, dout, opcode);
2280
input [31:0] din; // data in operand
2281
input [4:0] s; // shift operand
2282
input [1:0] opcode;
2283
output [31:0] dout;
2284
parameter opcode_sll = 2'b00;
2285
//parameter opcode_srl = 2'b01;
2286
parameter opcode_sra = 2'b10;
2287
//parameter opcode_ror = 2'b11;
2288
wire sll, sra;
2289
assign sll = opcode == opcode_sll;
2290
assign sra = opcode == opcode_sra;
2291
wire [15:1] s1;
2292
wire [3:0] sign;
2293
wire [7:0] tmp [0:3];
2294
// first stage is multiplier based
2295
// shift operand as fractional 8.7
2296
assign s1[15] = sll & s[2:0]==3'd7;
2297
assign s1[14] = sll & s[2:0]==3'd6;
2298
assign s1[13] = sll & s[2:0]==3'd5;
2299
assign s1[12] = sll & s[2:0]==3'd4;
2300
assign s1[11] = sll & s[2:0]==3'd3;
2301
assign s1[10] = sll & s[2:0]==3'd2;
2302
assign s1[ 9] = sll & s[2:0]==3'd1;
2303
assign s1[ 8] = s[2:0]==3'd0;
2304
assign s1[ 7] = !sll & s[2:0]==3'd1;
2305
assign s1[ 6] = !sll & s[2:0]==3'd2;
2306
assign s1[ 5] = !sll & s[2:0]==3'd3;
2307
assign s1[ 4] = !sll & s[2:0]==3'd4;
2308
assign s1[ 3] = !sll & s[2:0]==3'd5;
2309
assign s1[ 2] = !sll & s[2:0]==3'd6;
2310
assign s1[ 1] = !sll & s[2:0]==3'd7;
2311
assign sign[3] = din[31] & sra;
2312
assign sign[2] = sign[3] & (&din[31:24]);
2313
assign sign[1] = sign[2] & (&din[23:16]);
2314
assign sign[0] = sign[1] & (&din[15:8]);
2315
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2316
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2317
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2318
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2319
// second stage is multiplexer based
2320
// shift on byte level
2321
// mux byte 3
2322
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2323
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2324
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2325
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2326
                     {8{sign[3]}};
2327
// mux byte 2
2328
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2329
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2330
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2331
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2332
                     (s[4:3]==2'b01) ? tmp[3] :
2333
                     {8{sign[3]}};
2334
// mux byte 1
2335
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2336
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2337
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2338
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2339
                     (s[4:3]==2'b01) ? tmp[2] :
2340
                     (s[4:3]==2'b10) ? tmp[3] :
2341
                     {8{sign[3]}};
2342
// mux byte 0
2343
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2344
                     (sll) ?  {8{1'b0}}:
2345
                     (s[4:3]==2'b01) ? tmp[1] :
2346
                     (s[4:3]==2'b10) ? tmp[2] :
2347
                     tmp[3];
2348
endmodule
2349
// logic unit
2350
// supporting the following logic functions
2351
//    a and b
2352
//    a or  b
2353
//    a xor b
2354
//    not b
2355
module vl_logic_unit( a, b, result, opcode);
2356
parameter width = 32;
2357
parameter opcode_and = 2'b00;
2358
parameter opcode_or  = 2'b01;
2359
parameter opcode_xor = 2'b10;
2360
input [width-1:0] a,b;
2361
output [width-1:0] result;
2362
input [1:0] opcode;
2363
assign result = (opcode==opcode_and) ? a & b :
2364
                (opcode==opcode_or)  ? a | b :
2365
                (opcode==opcode_xor) ? a ^ b :
2366
                b;
2367
endmodule

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