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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 65

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1 60 unneback
// default SYN_KEEP definition
2 6 unneback
//////////////////////////////////////////////////////////////////////
3
////                                                              ////
4
////  Versatile library, clock and reset                          ////
5
////                                                              ////
6
////  Description                                                 ////
7
////  Logic related to clock and reset                            ////
8
////                                                              ////
9
////                                                              ////
10
////  To Do:                                                      ////
11
////   - add more different registers                             ////
12
////                                                              ////
13
////  Author(s):                                                  ////
14
////      - Michael Unneback, unneback@opencores.org              ////
15
////        ORSoC AB                                              ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43 21 unneback
//altera
44 33 unneback
module vl_gbuf ( i, o);
45
input i;
46
output o;
47
assign o = i;
48
endmodule
49 6 unneback
 // ALTERA
50
 //ACTEL
51
// sync reset
52 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
53 6 unneback
// output active high global reset sync with two DFFs 
54
`timescale 1 ns/100 ps
55
module vl_sync_rst ( rst_n_i, rst_o, clk);
56
input rst_n_i, clk;
57
output rst_o;
58 18 unneback
reg [1:0] tmp;
59 6 unneback
always @ (posedge clk or negedge rst_n_i)
60
if (!rst_n_i)
61 17 unneback
        tmp <= 2'b11;
62 6 unneback
else
63 33 unneback
        tmp <= {1'b0,tmp[1]};
64 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
65 6 unneback
endmodule
66
// vl_pll
67 32 unneback
///////////////////////////////////////////////////////////////////////////////
68
`timescale 1 ps/1 ps
69
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
70
parameter index = 0;
71
parameter number_of_clk = 1;
72
parameter period_time_0 = 20000;
73
parameter period_time_1 = 20000;
74
parameter period_time_2 = 20000;
75
parameter period_time_3 = 20000;
76
parameter period_time_4 = 20000;
77
parameter lock_delay = 2000000;
78
input clk_i, rst_n_i;
79
output lock;
80
output reg [0:number_of_clk-1] clk_o;
81
output [0:number_of_clk-1] rst_o;
82 33 unneback
`ifdef SIM_PLL
83 32 unneback
always
84
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
85
generate if (number_of_clk > 1)
86
always
87
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
88
endgenerate
89
generate if (number_of_clk > 2)
90
always
91
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
92
endgenerate
93 33 unneback
generate if (number_of_clk > 3)
94 32 unneback
always
95
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
96
endgenerate
97 33 unneback
generate if (number_of_clk > 4)
98 32 unneback
always
99
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
100
endgenerate
101
genvar i;
102
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
103
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
104
end
105
endgenerate
106 33 unneback
//assign #lock_delay lock = rst_n_i;
107
assign lock = rst_n_i;
108 32 unneback
endmodule
109 33 unneback
`else
110
`ifdef VL_PLL0
111
`ifdef VL_PLL0_CLK1
112
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
113
`endif
114
`ifdef VL_PLL0_CLK2
115
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
116
`endif
117
`ifdef VL_PLL0_CLK3
118
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
119
`endif
120
`ifdef VL_PLL0_CLK4
121
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
122
`endif
123
`ifdef VL_PLL0_CLK5
124
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
125
`endif
126
`endif
127
`ifdef VL_PLL1
128
`ifdef VL_PLL1_CLK1
129
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
130
`endif
131
`ifdef VL_PLL1_CLK2
132
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
133
`endif
134
`ifdef VL_PLL1_CLK3
135
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
136
`endif
137
`ifdef VL_PLL1_CLK4
138
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
139
`endif
140
`ifdef VL_PLL1_CLK5
141
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
142
`endif
143
`endif
144
`ifdef VL_PLL2
145
`ifdef VL_PLL2_CLK1
146
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
147
`endif
148
`ifdef VL_PLL2_CLK2
149
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
150
`endif
151
`ifdef VL_PLL2_CLK3
152
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
153
`endif
154
`ifdef VL_PLL2_CLK4
155
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
156
`endif
157
`ifdef VL_PLL2_CLK5
158
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
159
`endif
160
`endif
161
`ifdef VL_PLL3
162
`ifdef VL_PLL3_CLK1
163
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
164
`endif
165
`ifdef VL_PLL3_CLK2
166
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
167
`endif
168
`ifdef VL_PLL3_CLK3
169
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
170
`endif
171
`ifdef VL_PLL3_CLK4
172
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
173
`endif
174
`ifdef VL_PLL3_CLK5
175
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
176
`endif
177
`endif
178 32 unneback
genvar i;
179
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
180 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
181 32 unneback
end
182
endgenerate
183
endmodule
184 33 unneback
`endif
185 32 unneback
///////////////////////////////////////////////////////////////////////////////
186 6 unneback
 //altera
187
 //actel
188
//////////////////////////////////////////////////////////////////////
189
////                                                              ////
190
////  Versatile library, registers                                ////
191
////                                                              ////
192
////  Description                                                 ////
193
////  Different type of registers                                 ////
194
////                                                              ////
195
////                                                              ////
196
////  To Do:                                                      ////
197
////   - add more different registers                             ////
198
////                                                              ////
199
////  Author(s):                                                  ////
200
////      - Michael Unneback, unneback@opencores.org              ////
201
////        ORSoC AB                                              ////
202
////                                                              ////
203
//////////////////////////////////////////////////////////////////////
204
////                                                              ////
205
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
206
////                                                              ////
207
//// This source file may be used and distributed without         ////
208
//// restriction provided that this copyright statement is not    ////
209
//// removed from the file and that any derivative work contains  ////
210
//// the original copyright notice and the associated disclaimer. ////
211
////                                                              ////
212
//// This source file is free software; you can redistribute it   ////
213
//// and/or modify it under the terms of the GNU Lesser General   ////
214
//// Public License as published by the Free Software Foundation; ////
215
//// either version 2.1 of the License, or (at your option) any   ////
216
//// later version.                                               ////
217
////                                                              ////
218
//// This source is distributed in the hope that it will be       ////
219
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
220
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
221
//// PURPOSE.  See the GNU Lesser General Public License for more ////
222
//// details.                                                     ////
223
////                                                              ////
224
//// You should have received a copy of the GNU Lesser General    ////
225
//// Public License along with this source; if not, download it   ////
226
//// from http://www.opencores.org/lgpl.shtml                     ////
227
////                                                              ////
228
//////////////////////////////////////////////////////////////////////
229 18 unneback
module vl_dff ( d, q, clk, rst);
230 6 unneback
        parameter width = 1;
231
        parameter reset_value = 0;
232
        input [width-1:0] d;
233
        input clk, rst;
234
        output reg [width-1:0] q;
235
        always @ (posedge clk or posedge rst)
236
        if (rst)
237
                q <= reset_value;
238
        else
239
                q <= d;
240
endmodule
241 18 unneback
module vl_dff_array ( d, q, clk, rst);
242 6 unneback
        parameter width = 1;
243
        parameter depth = 2;
244
        parameter reset_value = 1'b0;
245
        input [width-1:0] d;
246
        input clk, rst;
247
        output [width-1:0] q;
248
        reg  [0:depth-1] q_tmp [width-1:0];
249
        integer i;
250
        always @ (posedge clk or posedge rst)
251
        if (rst) begin
252
            for (i=0;i<depth;i=i+1)
253
                q_tmp[i] <= {width{reset_value}};
254
        end else begin
255
            q_tmp[0] <= d;
256
            for (i=1;i<depth;i=i+1)
257
                q_tmp[i] <= q_tmp[i-1];
258
        end
259
    assign q = q_tmp[depth-1];
260
endmodule
261 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
262 6 unneback
        parameter width = 1;
263
        parameter reset_value = 0;
264
        input [width-1:0] d;
265
        input ce, clk, rst;
266
        output reg [width-1:0] q;
267
        always @ (posedge clk or posedge rst)
268
        if (rst)
269
                q <= reset_value;
270
        else
271
                if (ce)
272
                        q <= d;
273
endmodule
274 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
275 8 unneback
        parameter width = 1;
276
        parameter reset_value = 0;
277
        input [width-1:0] d;
278 10 unneback
        input ce, clear, clk, rst;
279 8 unneback
        output reg [width-1:0] q;
280
        always @ (posedge clk or posedge rst)
281
        if (rst)
282
            q <= reset_value;
283
        else
284
            if (ce)
285
                if (clear)
286
                    q <= {width{1'b0}};
287
                else
288
                    q <= d;
289
endmodule
290 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
291
        parameter width = 1;
292
        parameter reset_value = 0;
293
        input [width-1:0] d;
294
        input ce, set, clk, rst;
295
        output reg [width-1:0] q;
296
        always @ (posedge clk or posedge rst)
297
        if (rst)
298
            q <= reset_value;
299
        else
300
            if (ce)
301
                if (set)
302
                    q <= {width{1'b1}};
303
                else
304
                    q <= d;
305
endmodule
306 29 unneback
module vl_spr ( sp, r, q, clk, rst);
307 64 unneback
        //parameter width = 1;
308
        parameter reset_value = 1'b0;
309 29 unneback
        input sp, r;
310
        output reg q;
311
        input clk, rst;
312
        always @ (posedge clk or posedge rst)
313
        if (rst)
314
            q <= reset_value;
315
        else
316
            if (sp)
317
                q <= 1'b1;
318
            else if (r)
319
                q <= 1'b0;
320
endmodule
321
module vl_srp ( s, rp, q, clk, rst);
322
        parameter width = 1;
323
        parameter reset_value = 0;
324
        input s, rp;
325
        output reg q;
326
        input clk, rst;
327
        always @ (posedge clk or posedge rst)
328
        if (rst)
329
            q <= reset_value;
330
        else
331
            if (rp)
332
                q <= 1'b0;
333
            else if (s)
334
                q <= 1'b1;
335
endmodule
336 6 unneback
// megafunction wizard: %LPM_FF%
337
// GENERATION: STANDARD
338
// VERSION: WM1.0
339
// MODULE: lpm_ff 
340
// ============================================================
341
// File Name: dff_sr.v
342
// Megafunction Name(s):
343
//                      lpm_ff
344
//
345
// Simulation Library Files(s):
346
//                      lpm
347
// ============================================================
348
// ************************************************************
349
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
350
//
351
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
352
// ************************************************************
353
//Copyright (C) 1991-2010 Altera Corporation
354
//Your use of Altera Corporation's design tools, logic functions 
355
//and other software and tools, and its AMPP partner logic 
356
//functions, and any output files from any of the foregoing 
357
//(including device programming or simulation files), and any 
358
//associated documentation or information are expressly subject 
359
//to the terms and conditions of the Altera Program License 
360
//Subscription Agreement, Altera MegaCore Function License 
361
//Agreement, or other applicable license agreement, including, 
362
//without limitation, that your use is for the sole purpose of 
363
//programming logic devices manufactured by Altera and sold by 
364
//Altera or its authorized distributors.  Please refer to the 
365
//applicable agreement for further details.
366
// synopsys translate_off
367
`timescale 1 ps / 1 ps
368
// synopsys translate_on
369 18 unneback
module vl_dff_sr (
370 6 unneback
        aclr,
371
        aset,
372
        clock,
373
        data,
374
        q);
375
        input     aclr;
376
        input     aset;
377
        input     clock;
378
        input     data;
379
        output    q;
380
        wire [0:0] sub_wire0;
381
        wire [0:0] sub_wire1 = sub_wire0[0:0];
382
        wire  q = sub_wire1;
383
        wire  sub_wire2 = data;
384
        wire  sub_wire3 = sub_wire2;
385
        lpm_ff  lpm_ff_component (
386
                                .aclr (aclr),
387
                                .clock (clock),
388
                                .data (sub_wire3),
389
                                .aset (aset),
390
                                .q (sub_wire0)
391
                                // synopsys translate_off
392
                                ,
393
                                .aload (),
394
                                .enable (),
395
                                .sclr (),
396
                                .sload (),
397
                                .sset ()
398
                                // synopsys translate_on
399
                                );
400
        defparam
401
                lpm_ff_component.lpm_fftype = "DFF",
402
                lpm_ff_component.lpm_type = "LPM_FF",
403
                lpm_ff_component.lpm_width = 1;
404
endmodule
405
// ============================================================
406
// CNX file retrieval info
407
// ============================================================
408
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
409
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
410
// Retrieval info: PRIVATE: ASET NUMERIC "1"
411
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
412
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
413
// Retrieval info: PRIVATE: DFF NUMERIC "1"
414
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
415
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
416
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
417
// Retrieval info: PRIVATE: SSET NUMERIC "0"
418
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
419
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
420
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
421
// Retrieval info: PRIVATE: nBit NUMERIC "1"
422
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
423
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
424
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
425
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
426
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
427
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
428
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
429
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
430
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
431
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
432
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
433
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
434
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
435
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
436
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
437
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
442
// Retrieval info: LIB_FILE: lpm
443
// LATCH
444
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
445 18 unneback
module vl_latch ( d, le, q, clk);
446 6 unneback
input d, le;
447
output q;
448
input clk;
449
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
450
endmodule
451 18 unneback
module vl_shreg ( d, q, clk, rst);
452 17 unneback
parameter depth = 10;
453
input d;
454
output q;
455
input clk, rst;
456
reg [1:depth] dffs;
457
always @ (posedge clk or posedge rst)
458
if (rst)
459
    dffs <= {depth{1'b0}};
460
else
461
    dffs <= {d,dffs[1:depth-1]};
462
assign q = dffs[depth];
463
endmodule
464 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
465 17 unneback
parameter depth = 10;
466
input d, ce;
467
output q;
468
input clk, rst;
469
reg [1:depth] dffs;
470
always @ (posedge clk or posedge rst)
471
if (rst)
472
    dffs <= {depth{1'b0}};
473
else
474
    if (ce)
475
        dffs <= {d,dffs[1:depth-1]};
476
assign q = dffs[depth];
477
endmodule
478 18 unneback
module vl_delay ( d, q, clk, rst);
479 15 unneback
parameter depth = 10;
480
input d;
481
output q;
482
input clk, rst;
483
reg [1:depth] dffs;
484
always @ (posedge clk or posedge rst)
485
if (rst)
486
    dffs <= {depth{1'b0}};
487
else
488
    dffs <= {d,dffs[1:depth-1]};
489
assign q = dffs[depth];
490
endmodule
491 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
492 17 unneback
parameter depth = 10;
493
input d;
494
output q, emptyflag;
495
input clk, rst;
496
reg [1:depth] dffs;
497
always @ (posedge clk or posedge rst)
498
if (rst)
499
    dffs <= {depth{1'b0}};
500
else
501
    dffs <= {d,dffs[1:depth-1]};
502
assign q = dffs[depth];
503
assign emptyflag = !(|dffs);
504
endmodule
505 6 unneback
//////////////////////////////////////////////////////////////////////
506
////                                                              ////
507 18 unneback
////  Logic functions                                             ////
508
////                                                              ////
509
////  Description                                                 ////
510
////  Logic functions such as multiplexers                        ////
511
////                                                              ////
512
////                                                              ////
513
////  To Do:                                                      ////
514
////   -                                                          ////
515
////                                                              ////
516
////  Author(s):                                                  ////
517
////      - Michael Unneback, unneback@opencores.org              ////
518
////        ORSoC AB                                              ////
519
////                                                              ////
520
//////////////////////////////////////////////////////////////////////
521
////                                                              ////
522
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
523
////                                                              ////
524
//// This source file may be used and distributed without         ////
525
//// restriction provided that this copyright statement is not    ////
526
//// removed from the file and that any derivative work contains  ////
527
//// the original copyright notice and the associated disclaimer. ////
528
////                                                              ////
529
//// This source file is free software; you can redistribute it   ////
530
//// and/or modify it under the terms of the GNU Lesser General   ////
531
//// Public License as published by the Free Software Foundation; ////
532
//// either version 2.1 of the License, or (at your option) any   ////
533
//// later version.                                               ////
534
////                                                              ////
535
//// This source is distributed in the hope that it will be       ////
536
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
537
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
538
//// PURPOSE.  See the GNU Lesser General Public License for more ////
539
//// details.                                                     ////
540
////                                                              ////
541
//// You should have received a copy of the GNU Lesser General    ////
542
//// Public License along with this source; if not, download it   ////
543
//// from http://www.opencores.org/lgpl.shtml                     ////
544
////                                                              ////
545
//////////////////////////////////////////////////////////////////////
546 36 unneback
module vl_mux_andor ( a, sel, dout);
547
parameter width = 32;
548
parameter nr_of_ports = 4;
549
input [nr_of_ports*width-1:0] a;
550
input [nr_of_ports-1:0] sel;
551
output reg [width-1:0] dout;
552 38 unneback
integer i,j;
553 36 unneback
always @ (a, sel)
554
begin
555
    dout = a[width-1:0] & {width{sel[0]}};
556 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
557
        for (j=0;j<width;j=j+1)
558
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
559 36 unneback
end
560
endmodule
561 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
562
parameter width = 32;
563 35 unneback
localparam nr_of_ports = 2;
564 34 unneback
input [width-1:0] a1, a0;
565
input [nr_of_ports-1:0] sel;
566
output [width-1:0] dout;
567 36 unneback
vl_mux_andor
568 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
569 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
570 34 unneback
endmodule
571
module vl_mux3_andor ( a2, a1, a0, sel, dout);
572
parameter width = 32;
573 35 unneback
localparam nr_of_ports = 3;
574 34 unneback
input [width-1:0] a2, a1, a0;
575
input [nr_of_ports-1:0] sel;
576
output [width-1:0] dout;
577 36 unneback
vl_mux_andor
578 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
579 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
580 34 unneback
endmodule
581 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
582
parameter width = 32;
583 35 unneback
localparam nr_of_ports = 4;
584 18 unneback
input [width-1:0] a3, a2, a1, a0;
585
input [nr_of_ports-1:0] sel;
586 22 unneback
output [width-1:0] dout;
587 36 unneback
vl_mux_andor
588 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
589 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
590 18 unneback
endmodule
591
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
592
parameter width = 32;
593 35 unneback
localparam nr_of_ports = 5;
594 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
595
input [nr_of_ports-1:0] sel;
596 22 unneback
output [width-1:0] dout;
597 36 unneback
vl_mux_andor
598 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
599 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
600 18 unneback
endmodule
601
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
602
parameter width = 32;
603 35 unneback
localparam nr_of_ports = 6;
604 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
605
input [nr_of_ports-1:0] sel;
606 22 unneback
output [width-1:0] dout;
607 36 unneback
vl_mux_andor
608 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
609 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
610 18 unneback
endmodule
611 43 unneback
module vl_parity_generate (data, parity);
612
parameter word_size = 32;
613
parameter chunk_size = 8;
614
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
615
input [word_size-1:0] data;
616
output reg [word_size/chunk_size-1:0] parity;
617
integer i,j;
618
always @ (data)
619
for (i=0;i<word_size/chunk_size;i=i+1) begin
620
    parity[i] = parity_type;
621
    for (j=0;j<chunk_size;j=j+1) begin
622 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
623 43 unneback
    end
624
end
625
endmodule
626
module vl_parity_check( data, parity, parity_error);
627
parameter word_size = 32;
628
parameter chunk_size = 8;
629
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
630
input [word_size-1:0] data;
631
input [word_size/chunk_size-1:0] parity;
632
output parity_error;
633 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
634 43 unneback
integer i,j;
635
always @ (data or parity)
636
for (i=0;i<word_size/chunk_size;i=i+1) begin
637
    error_flag[i] = parity[i] ^ parity_type;
638
    for (j=0;j<chunk_size;j=j+1) begin
639 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
640 43 unneback
    end
641
end
642
assign parity_error = |error_flag;
643
endmodule
644 18 unneback
//////////////////////////////////////////////////////////////////////
645
////                                                              ////
646 44 unneback
////  IO functions                                                ////
647
////                                                              ////
648
////  Description                                                 ////
649
////  IO functions such as IOB flip-flops                         ////
650
////                                                              ////
651
////                                                              ////
652
////  To Do:                                                      ////
653
////   -                                                          ////
654
////                                                              ////
655
////  Author(s):                                                  ////
656
////      - Michael Unneback, unneback@opencores.org              ////
657
////        ORSoC AB                                              ////
658
////                                                              ////
659
//////////////////////////////////////////////////////////////////////
660
////                                                              ////
661
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
662
////                                                              ////
663
//// This source file may be used and distributed without         ////
664
//// restriction provided that this copyright statement is not    ////
665
//// removed from the file and that any derivative work contains  ////
666
//// the original copyright notice and the associated disclaimer. ////
667
////                                                              ////
668
//// This source file is free software; you can redistribute it   ////
669
//// and/or modify it under the terms of the GNU Lesser General   ////
670
//// Public License as published by the Free Software Foundation; ////
671
//// either version 2.1 of the License, or (at your option) any   ////
672
//// later version.                                               ////
673
////                                                              ////
674
//// This source is distributed in the hope that it will be       ////
675
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
676
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
677
//// PURPOSE.  See the GNU Lesser General Public License for more ////
678
//// details.                                                     ////
679
////                                                              ////
680
//// You should have received a copy of the GNU Lesser General    ////
681
//// Public License along with this source; if not, download it   ////
682
//// from http://www.opencores.org/lgpl.shtml                     ////
683
////                                                              ////
684
//////////////////////////////////////////////////////////////////////
685 45 unneback
`timescale 1ns/1ns
686 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
687
parameter width = 1;
688 45 unneback
parameter reset_value = {width{1'b0}};
689
input  [width-1:0]  d_i;
690 44 unneback
output [width-1:0] o_pad;
691
input clk, rst;
692 60 unneback
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
693 45 unneback
reg  [width-1:0] o_pad_int;
694 44 unneback
assign d_i_int = d_i;
695
genvar i;
696 45 unneback
generate
697 44 unneback
for (i=0;i<width;i=i+1) begin
698
    always @ (posedge clk or posedge rst)
699
    if (rst)
700 45 unneback
        o_pad_int[i] <= reset_value[i];
701 44 unneback
    else
702 45 unneback
        o_pad_int[i] <= d_i_int[i];
703
    assign #1 o_pad[i] = o_pad_int[i];
704 44 unneback
end
705
endgenerate
706
endmodule
707 45 unneback
`timescale 1ns/1ns
708 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
709
parameter width = 1;
710
input  [width-1:0] d_o;
711
output reg [width-1:0] d_i;
712
input oe;
713
inout [width-1:0] io_pad;
714
input clk, rst;
715 60 unneback
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
716 44 unneback
reg [width-1:0] oe_q;
717
reg [width-1:0] d_o_q;
718
assign oe_d = {width{oe}};
719
genvar i;
720
generate
721
for (i=0;i<width;i=i+1) begin
722
    always @ (posedge clk or posedge rst)
723
    if (rst)
724
        oe_q[i] <= 1'b0;
725
    else
726
        oe_q[i] <= oe_d[i];
727
    always @ (posedge clk or posedge rst)
728
    if (rst)
729
        d_o_q[i] <= 1'b0;
730
    else
731
        d_o_q[i] <= d_o[i];
732
    always @ (posedge clk or posedge rst)
733
    if (rst)
734
        d_i[i] <= 1'b0;
735
    else
736
        d_i[i] <= io_pad[i];
737 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
738 44 unneback
end
739
endgenerate
740
endmodule
741
//////////////////////////////////////////////////////////////////////
742
////                                                              ////
743 6 unneback
////  Versatile counter                                           ////
744
////                                                              ////
745
////  Description                                                 ////
746
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
747
////  counter                                                     ////
748
////                                                              ////
749
////  To Do:                                                      ////
750
////   - add LFSR with more taps                                  ////
751
////                                                              ////
752
////  Author(s):                                                  ////
753
////      - Michael Unneback, unneback@opencores.org              ////
754
////        ORSoC AB                                              ////
755
////                                                              ////
756
//////////////////////////////////////////////////////////////////////
757
////                                                              ////
758
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
759
////                                                              ////
760
//// This source file may be used and distributed without         ////
761
//// restriction provided that this copyright statement is not    ////
762
//// removed from the file and that any derivative work contains  ////
763
//// the original copyright notice and the associated disclaimer. ////
764
////                                                              ////
765
//// This source file is free software; you can redistribute it   ////
766
//// and/or modify it under the terms of the GNU Lesser General   ////
767
//// Public License as published by the Free Software Foundation; ////
768
//// either version 2.1 of the License, or (at your option) any   ////
769
//// later version.                                               ////
770
////                                                              ////
771
//// This source is distributed in the hope that it will be       ////
772
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
773
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
774
//// PURPOSE.  See the GNU Lesser General Public License for more ////
775
//// details.                                                     ////
776
////                                                              ////
777
//// You should have received a copy of the GNU Lesser General    ////
778
//// Public License along with this source; if not, download it   ////
779
//// from http://www.opencores.org/lgpl.shtml                     ////
780
////                                                              ////
781
//////////////////////////////////////////////////////////////////////
782
// binary counter
783 40 unneback
module vl_cnt_bin_ce (
784
 cke, q, rst, clk);
785 22 unneback
   parameter length = 4;
786 6 unneback
   input cke;
787
   output [length:1] q;
788
   input rst;
789
   input clk;
790
   parameter clear_value = 0;
791
   parameter set_value = 1;
792
   parameter wrap_value = 0;
793
   parameter level1_value = 15;
794
   reg  [length:1] qi;
795
   wire [length:1] q_next;
796
   assign q_next = qi + {{length-1{1'b0}},1'b1};
797
   always @ (posedge clk or posedge rst)
798
     if (rst)
799
       qi <= {length{1'b0}};
800
     else
801
     if (cke)
802
       qi <= q_next;
803
   assign q = qi;
804
endmodule
805
//////////////////////////////////////////////////////////////////////
806
////                                                              ////
807
////  Versatile counter                                           ////
808
////                                                              ////
809
////  Description                                                 ////
810
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
811
////  counter                                                     ////
812
////                                                              ////
813
////  To Do:                                                      ////
814
////   - add LFSR with more taps                                  ////
815
////                                                              ////
816
////  Author(s):                                                  ////
817
////      - Michael Unneback, unneback@opencores.org              ////
818
////        ORSoC AB                                              ////
819
////                                                              ////
820
//////////////////////////////////////////////////////////////////////
821
////                                                              ////
822
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
823
////                                                              ////
824
//// This source file may be used and distributed without         ////
825
//// restriction provided that this copyright statement is not    ////
826
//// removed from the file and that any derivative work contains  ////
827
//// the original copyright notice and the associated disclaimer. ////
828
////                                                              ////
829
//// This source file is free software; you can redistribute it   ////
830
//// and/or modify it under the terms of the GNU Lesser General   ////
831
//// Public License as published by the Free Software Foundation; ////
832
//// either version 2.1 of the License, or (at your option) any   ////
833
//// later version.                                               ////
834
////                                                              ////
835
//// This source is distributed in the hope that it will be       ////
836
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
837
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
838
//// PURPOSE.  See the GNU Lesser General Public License for more ////
839
//// details.                                                     ////
840
////                                                              ////
841
//// You should have received a copy of the GNU Lesser General    ////
842
//// Public License along with this source; if not, download it   ////
843
//// from http://www.opencores.org/lgpl.shtml                     ////
844
////                                                              ////
845
//////////////////////////////////////////////////////////////////////
846
// binary counter
847 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
848
 cke, rew, zq, level1, rst, clk);
849 6 unneback
   parameter length = 4;
850
   input cke;
851
   input rew;
852 25 unneback
   output reg zq;
853
   output reg level1;
854
   input rst;
855
   input clk;
856
   parameter clear_value = 0;
857
   parameter set_value = 1;
858
   parameter wrap_value = 1;
859
   parameter level1_value = 15;
860 29 unneback
   wire clear;
861 30 unneback
   assign clear = 1'b0;
862 25 unneback
   reg  [length:1] qi;
863
   wire  [length:1] q_next, q_next_fw, q_next_rew;
864
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
865
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
866
   assign q_next = rew ? q_next_rew : q_next_fw;
867
   always @ (posedge clk or posedge rst)
868
     if (rst)
869
       qi <= {length{1'b0}};
870
     else
871
     if (cke)
872
       qi <= q_next;
873
   always @ (posedge clk or posedge rst)
874
     if (rst)
875
       zq <= 1'b1;
876
     else
877
     if (cke)
878
       zq <= q_next == {length{1'b0}};
879
    always @ (posedge clk or posedge rst)
880
    if (rst)
881
        level1 <= 1'b0;
882
    else
883
    if (cke)
884 29 unneback
    if (clear)
885
        level1 <= 1'b0;
886
    else if (q_next == level1_value)
887 25 unneback
        level1 <= 1'b1;
888
    else if (qi == level1_value & rew)
889
        level1 <= 1'b0;
890
endmodule
891
//////////////////////////////////////////////////////////////////////
892
////                                                              ////
893
////  Versatile counter                                           ////
894
////                                                              ////
895
////  Description                                                 ////
896
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
897
////  counter                                                     ////
898
////                                                              ////
899
////  To Do:                                                      ////
900
////   - add LFSR with more taps                                  ////
901
////                                                              ////
902
////  Author(s):                                                  ////
903
////      - Michael Unneback, unneback@opencores.org              ////
904
////        ORSoC AB                                              ////
905
////                                                              ////
906
//////////////////////////////////////////////////////////////////////
907
////                                                              ////
908
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
909
////                                                              ////
910
//// This source file may be used and distributed without         ////
911
//// restriction provided that this copyright statement is not    ////
912
//// removed from the file and that any derivative work contains  ////
913
//// the original copyright notice and the associated disclaimer. ////
914
////                                                              ////
915
//// This source file is free software; you can redistribute it   ////
916
//// and/or modify it under the terms of the GNU Lesser General   ////
917
//// Public License as published by the Free Software Foundation; ////
918
//// either version 2.1 of the License, or (at your option) any   ////
919
//// later version.                                               ////
920
////                                                              ////
921
//// This source is distributed in the hope that it will be       ////
922
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
923
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
924
//// PURPOSE.  See the GNU Lesser General Public License for more ////
925
//// details.                                                     ////
926
////                                                              ////
927
//// You should have received a copy of the GNU Lesser General    ////
928
//// Public License along with this source; if not, download it   ////
929
//// from http://www.opencores.org/lgpl.shtml                     ////
930
////                                                              ////
931
//////////////////////////////////////////////////////////////////////
932
// binary counter
933 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
934
 cke, rew, q, zq, level1, rst, clk);
935 25 unneback
   parameter length = 4;
936
   input cke;
937
   input rew;
938
   output [length:1] q;
939
   output reg zq;
940
   output reg level1;
941
   input rst;
942
   input clk;
943
   parameter clear_value = 0;
944
   parameter set_value = 1;
945
   parameter wrap_value = 1;
946
   parameter level1_value = 15;
947 29 unneback
   wire clear;
948 30 unneback
   assign clear = 1'b0;
949 25 unneback
   reg  [length:1] qi;
950
   wire  [length:1] q_next, q_next_fw, q_next_rew;
951
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
952
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
953
   assign q_next = rew ? q_next_rew : q_next_fw;
954
   always @ (posedge clk or posedge rst)
955
     if (rst)
956
       qi <= {length{1'b0}};
957
     else
958
     if (cke)
959
       qi <= q_next;
960
   assign q = qi;
961
   always @ (posedge clk or posedge rst)
962
     if (rst)
963
       zq <= 1'b1;
964
     else
965
     if (cke)
966
       zq <= q_next == {length{1'b0}};
967
    always @ (posedge clk or posedge rst)
968
    if (rst)
969
        level1 <= 1'b0;
970
    else
971
    if (cke)
972 29 unneback
    if (clear)
973
        level1 <= 1'b0;
974
    else if (q_next == level1_value)
975 25 unneback
        level1 <= 1'b1;
976
    else if (qi == level1_value & rew)
977
        level1 <= 1'b0;
978
endmodule
979
//////////////////////////////////////////////////////////////////////
980
////                                                              ////
981
////  Versatile counter                                           ////
982
////                                                              ////
983
////  Description                                                 ////
984
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
985
////  counter                                                     ////
986
////                                                              ////
987
////  To Do:                                                      ////
988
////   - add LFSR with more taps                                  ////
989
////                                                              ////
990
////  Author(s):                                                  ////
991
////      - Michael Unneback, unneback@opencores.org              ////
992
////        ORSoC AB                                              ////
993
////                                                              ////
994
//////////////////////////////////////////////////////////////////////
995
////                                                              ////
996
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
997
////                                                              ////
998
//// This source file may be used and distributed without         ////
999
//// restriction provided that this copyright statement is not    ////
1000
//// removed from the file and that any derivative work contains  ////
1001
//// the original copyright notice and the associated disclaimer. ////
1002
////                                                              ////
1003
//// This source file is free software; you can redistribute it   ////
1004
//// and/or modify it under the terms of the GNU Lesser General   ////
1005
//// Public License as published by the Free Software Foundation; ////
1006
//// either version 2.1 of the License, or (at your option) any   ////
1007
//// later version.                                               ////
1008
////                                                              ////
1009
//// This source is distributed in the hope that it will be       ////
1010
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1011
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1012
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1013
//// details.                                                     ////
1014
////                                                              ////
1015
//// You should have received a copy of the GNU Lesser General    ////
1016
//// Public License along with this source; if not, download it   ////
1017
//// from http://www.opencores.org/lgpl.shtml                     ////
1018
////                                                              ////
1019
//////////////////////////////////////////////////////////////////////
1020 6 unneback
// GRAY counter
1021 40 unneback
module vl_cnt_gray_ce_bin (
1022
 cke, q, q_bin, rst, clk);
1023 6 unneback
   parameter length = 4;
1024
   input cke;
1025
   output reg [length:1] q;
1026
   output [length:1] q_bin;
1027
   input rst;
1028
   input clk;
1029
   parameter clear_value = 0;
1030
   parameter set_value = 1;
1031
   parameter wrap_value = 8;
1032
   parameter level1_value = 15;
1033
   reg  [length:1] qi;
1034
   wire [length:1] q_next;
1035
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1036
   always @ (posedge clk or posedge rst)
1037
     if (rst)
1038
       qi <= {length{1'b0}};
1039
     else
1040
     if (cke)
1041
       qi <= q_next;
1042
   always @ (posedge clk or posedge rst)
1043
     if (rst)
1044
       q <= {length{1'b0}};
1045
     else
1046
       if (cke)
1047
         q <= (q_next>>1) ^ q_next;
1048
   assign q_bin = qi;
1049
endmodule
1050
//////////////////////////////////////////////////////////////////////
1051
////                                                              ////
1052
////  Versatile library, counters                                 ////
1053
////                                                              ////
1054
////  Description                                                 ////
1055
////  counters                                                    ////
1056
////                                                              ////
1057
////                                                              ////
1058
////  To Do:                                                      ////
1059
////   - add more counters                                        ////
1060
////                                                              ////
1061
////  Author(s):                                                  ////
1062
////      - Michael Unneback, unneback@opencores.org              ////
1063
////        ORSoC AB                                              ////
1064
////                                                              ////
1065
//////////////////////////////////////////////////////////////////////
1066
////                                                              ////
1067
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1068
////                                                              ////
1069
//// This source file may be used and distributed without         ////
1070
//// restriction provided that this copyright statement is not    ////
1071
//// removed from the file and that any derivative work contains  ////
1072
//// the original copyright notice and the associated disclaimer. ////
1073
////                                                              ////
1074
//// This source file is free software; you can redistribute it   ////
1075
//// and/or modify it under the terms of the GNU Lesser General   ////
1076
//// Public License as published by the Free Software Foundation; ////
1077
//// either version 2.1 of the License, or (at your option) any   ////
1078
//// later version.                                               ////
1079
////                                                              ////
1080
//// This source is distributed in the hope that it will be       ////
1081
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1082
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1083
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1084
//// details.                                                     ////
1085
////                                                              ////
1086
//// You should have received a copy of the GNU Lesser General    ////
1087
//// Public License along with this source; if not, download it   ////
1088
//// from http://www.opencores.org/lgpl.shtml                     ////
1089
////                                                              ////
1090
//////////////////////////////////////////////////////////////////////
1091 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1092 6 unneback
   parameter length = 4;
1093
   output reg [0:length-1] q;
1094
   input rst;
1095
   input clk;
1096
    always @ (posedge clk or posedge rst)
1097
    if (rst)
1098
        q <= {1'b1,{length-1{1'b0}}};
1099
    else
1100
        q <= {q[length-1],q[0:length-2]};
1101
endmodule
1102 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1103 6 unneback
   parameter length = 4;
1104
   input cke;
1105
   output reg [0:length-1] q;
1106
   input rst;
1107
   input clk;
1108
    always @ (posedge clk or posedge rst)
1109
    if (rst)
1110
        q <= {1'b1,{length-1{1'b0}}};
1111
    else
1112
        if (cke)
1113
            q <= {q[length-1],q[0:length-2]};
1114
endmodule
1115 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1116 6 unneback
   parameter length = 4;
1117
   input cke, clear;
1118
   output reg [0:length-1] q;
1119
   input rst;
1120
   input clk;
1121
    always @ (posedge clk or posedge rst)
1122
    if (rst)
1123
        q <= {1'b1,{length-1{1'b0}}};
1124
    else
1125
        if (cke)
1126
            if (clear)
1127
                q <= {1'b1,{length-1{1'b0}}};
1128
            else
1129
                q <= q >> 1;
1130
endmodule
1131 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1132 6 unneback
   parameter length = 4;
1133
   input cke, clear;
1134
   output reg [0:length-1] q;
1135
   input rst;
1136
   input clk;
1137
    always @ (posedge clk or posedge rst)
1138
    if (rst)
1139
        q <= {1'b1,{length-1{1'b0}}};
1140
    else
1141
        if (cke)
1142
            if (clear)
1143
                q <= {1'b1,{length-1{1'b0}}};
1144
            else
1145
            q <= {q[length-1],q[0:length-2]};
1146
endmodule
1147
//////////////////////////////////////////////////////////////////////
1148
////                                                              ////
1149
////  Versatile library, memories                                 ////
1150
////                                                              ////
1151
////  Description                                                 ////
1152
////  memories                                                    ////
1153
////                                                              ////
1154
////                                                              ////
1155
////  To Do:                                                      ////
1156
////   - add more memory types                                    ////
1157
////                                                              ////
1158
////  Author(s):                                                  ////
1159
////      - Michael Unneback, unneback@opencores.org              ////
1160
////        ORSoC AB                                              ////
1161
////                                                              ////
1162
//////////////////////////////////////////////////////////////////////
1163
////                                                              ////
1164
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1165
////                                                              ////
1166
//// This source file may be used and distributed without         ////
1167
//// restriction provided that this copyright statement is not    ////
1168
//// removed from the file and that any derivative work contains  ////
1169
//// the original copyright notice and the associated disclaimer. ////
1170
////                                                              ////
1171
//// This source file is free software; you can redistribute it   ////
1172
//// and/or modify it under the terms of the GNU Lesser General   ////
1173
//// Public License as published by the Free Software Foundation; ////
1174
//// either version 2.1 of the License, or (at your option) any   ////
1175
//// later version.                                               ////
1176
////                                                              ////
1177
//// This source is distributed in the hope that it will be       ////
1178
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1179
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1180
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1181
//// details.                                                     ////
1182
////                                                              ////
1183
//// You should have received a copy of the GNU Lesser General    ////
1184
//// Public License along with this source; if not, download it   ////
1185
//// from http://www.opencores.org/lgpl.shtml                     ////
1186
////                                                              ////
1187
//////////////////////////////////////////////////////////////////////
1188
/// ROM
1189 7 unneback
module vl_rom_init ( adr, q, clk);
1190
   parameter data_width = 32;
1191
   parameter addr_width = 8;
1192
   input [(addr_width-1):0]       adr;
1193
   output reg [(data_width-1):0] q;
1194
   input                         clk;
1195
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1196
   parameter memory_file = "vl_rom.vmem";
1197
   initial
1198
     begin
1199
        $readmemh(memory_file, rom);
1200
     end
1201
   always @ (posedge clk)
1202
     q <= rom[adr];
1203
endmodule
1204 6 unneback
// Single port RAM
1205
module vl_ram ( d, adr, we, q, clk);
1206
   parameter data_width = 32;
1207
   parameter addr_width = 8;
1208
   input [(data_width-1):0]      d;
1209
   input [(addr_width-1):0]       adr;
1210
   input                         we;
1211 7 unneback
   output reg [(data_width-1):0] q;
1212 6 unneback
   input                         clk;
1213
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1214 7 unneback
   parameter init = 0;
1215
   parameter memory_file = "vl_ram.vmem";
1216
   generate if (init) begin : init_mem
1217
   initial
1218
     begin
1219
        $readmemh(memory_file, ram);
1220
     end
1221
   end
1222
   endgenerate
1223 6 unneback
   always @ (posedge clk)
1224
   begin
1225
   if (we)
1226
     ram[adr] <= d;
1227
   q <= ram[adr];
1228
   end
1229
endmodule
1230 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1231
   parameter data_width = 32;
1232
   parameter addr_width = 8;
1233
   input [(data_width-1):0]      d;
1234
   input [(addr_width-1):0]       adr;
1235
   input [(addr_width/4)-1:0]    be;
1236
   input                         we;
1237
   output reg [(data_width-1):0] q;
1238
   input                         clk;
1239 65 unneback
`ifdef SYSTEMVERILOG
1240
   logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
1241
`else
1242 7 unneback
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1243 65 unneback
`endif
1244 60 unneback
   parameter memory_init = 0;
1245 7 unneback
   parameter memory_file = "vl_ram.vmem";
1246 60 unneback
   generate if (memory_init) begin : init_mem
1247 7 unneback
   initial
1248
     begin
1249
        $readmemh(memory_file, ram);
1250
     end
1251
   end
1252
   endgenerate
1253 60 unneback
`ifdef SYSTEMVERILOG
1254
// use a multi-dimensional packed array
1255
//to model individual bytes within the word
1256
always_ff@(posedge clk)
1257
begin
1258
    if(we) begin // note: we should have a for statement to support any bus width
1259 65 unneback
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
1260
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
1261
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
1262
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
1263 60 unneback
    end
1264 65 unneback
    q <= ram[adr];
1265 60 unneback
end
1266
`else
1267 7 unneback
   genvar i;
1268
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1269
      always @ (posedge clk)
1270
      if (we & be[i])
1271
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1272
   end
1273
   endgenerate
1274
   always @ (posedge clk)
1275
      q <= ram[adr];
1276 60 unneback
`endif
1277 7 unneback
endmodule
1278
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1279 6 unneback
   parameter data_width = 32;
1280
   parameter addr_width = 8;
1281
   input [(data_width-1):0]      d_a;
1282
   input [(addr_width-1):0]       adr_a;
1283
   input [(addr_width-1):0]       adr_b;
1284
   input                         we_a;
1285
   output [(data_width-1):0]      q_b;
1286
   input                         clk_a, clk_b;
1287
   reg [(addr_width-1):0]         adr_b_reg;
1288
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1289 7 unneback
   parameter init = 0;
1290
   parameter memory_file = "vl_ram.vmem";
1291
   generate if (init) begin : init_mem
1292
   initial
1293
     begin
1294
        $readmemh(memory_file, ram);
1295
     end
1296
   end
1297
   endgenerate
1298 6 unneback
   always @ (posedge clk_a)
1299
   if (we_a)
1300
     ram[adr_a] <= d_a;
1301
   always @ (posedge clk_b)
1302
   adr_b_reg <= adr_b;
1303
   assign q_b = ram[adr_b_reg];
1304
endmodule
1305 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1306 6 unneback
   parameter data_width = 32;
1307
   parameter addr_width = 8;
1308
   input [(data_width-1):0]      d_a;
1309
   input [(addr_width-1):0]       adr_a;
1310
   input [(addr_width-1):0]       adr_b;
1311
   input                         we_a;
1312
   output [(data_width-1):0]      q_b;
1313
   output reg [(data_width-1):0] q_a;
1314
   input                         clk_a, clk_b;
1315
   reg [(data_width-1):0]         q_b;
1316
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1317 7 unneback
   parameter init = 0;
1318
   parameter memory_file = "vl_ram.vmem";
1319
   generate if (init) begin : init_mem
1320
   initial
1321
     begin
1322
        $readmemh(memory_file, ram);
1323
     end
1324
   end
1325
   endgenerate
1326 6 unneback
   always @ (posedge clk_a)
1327
     begin
1328
        q_a <= ram[adr_a];
1329
        if (we_a)
1330
             ram[adr_a] <= d_a;
1331
     end
1332
   always @ (posedge clk_b)
1333
          q_b <= ram[adr_b];
1334
endmodule
1335 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1336 6 unneback
   parameter data_width = 32;
1337
   parameter addr_width = 8;
1338
   input [(data_width-1):0]      d_a;
1339
   input [(addr_width-1):0]       adr_a;
1340
   input [(addr_width-1):0]       adr_b;
1341
   input                         we_a;
1342
   output [(data_width-1):0]      q_b;
1343
   input [(data_width-1):0]       d_b;
1344
   output reg [(data_width-1):0] q_a;
1345
   input                         we_b;
1346
   input                         clk_a, clk_b;
1347
   reg [(data_width-1):0]         q_b;
1348
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1349 7 unneback
   parameter init = 0;
1350
   parameter memory_file = "vl_ram.vmem";
1351
   generate if (init) begin : init_mem
1352
   initial
1353
     begin
1354
        $readmemh(memory_file, ram);
1355
     end
1356
   end
1357
   endgenerate
1358 6 unneback
   always @ (posedge clk_a)
1359
     begin
1360
        q_a <= ram[adr_a];
1361
        if (we_a)
1362
             ram[adr_a] <= d_a;
1363
     end
1364
   always @ (posedge clk_b)
1365
     begin
1366
        q_b <= ram[adr_b];
1367
        if (we_b)
1368
          ram[adr_b] <= d_b;
1369
     end
1370
endmodule
1371
// Content addresable memory, CAM
1372
// FIFO
1373 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1374
    d, wr, fifo_full,
1375
    q, rd, fifo_empty,
1376
    fill_level,
1377
    clk, rst
1378
    );
1379
parameter data_width = 18;
1380
parameter addr_width = 4;
1381
// write side
1382
input  [data_width-1:0] d;
1383
input                   wr;
1384
output                  fifo_full;
1385
// read side
1386
output [data_width-1:0] q;
1387
input                   rd;
1388
output                  fifo_empty;
1389
// common
1390
output [addr_width:0]   fill_level;
1391
input rst, clk;
1392
wire [addr_width:1] wadr, radr;
1393
vl_cnt_bin_ce
1394
    # ( .length(addr_width))
1395
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1396
vl_cnt_bin_ce
1397
    # (.length(addr_width))
1398
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1399
vl_dpram_1r1w
1400
    # (.data_width(data_width), .addr_width(addr_width))
1401
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1402 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1403 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1404 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1405
endmodule
1406 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1407
// RAM is supposed to be larger than the two FIFOs
1408
// LFSR counters used adr pointers
1409
module vl_fifo_2r2w_sync_simplex (
1410
    // a side
1411
    a_d, a_wr, a_fifo_full,
1412
    a_q, a_rd, a_fifo_empty,
1413
    a_fill_level,
1414
    // b side
1415
    b_d, b_wr, b_fifo_full,
1416
    b_q, b_rd, b_fifo_empty,
1417
    b_fill_level,
1418
    // common
1419
    clk, rst
1420
    );
1421
parameter data_width = 8;
1422
parameter addr_width = 5;
1423
parameter fifo_full_level = (1<<addr_width)-1;
1424
// a side
1425
input  [data_width-1:0] a_d;
1426
input                   a_wr;
1427
output                  a_fifo_full;
1428
output [data_width-1:0] a_q;
1429
input                   a_rd;
1430
output                  a_fifo_empty;
1431
output [addr_width-1:0] a_fill_level;
1432
// b side
1433
input  [data_width-1:0] b_d;
1434
input                   b_wr;
1435
output                  b_fifo_full;
1436
output [data_width-1:0] b_q;
1437
input                   b_rd;
1438
output                  b_fifo_empty;
1439
output [addr_width-1:0] b_fill_level;
1440
input                   clk;
1441
input                   rst;
1442
// adr_gen
1443
wire [addr_width:1] a_wadr, a_radr;
1444
wire [addr_width:1] b_wadr, b_radr;
1445
// dpram
1446
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1447
vl_cnt_lfsr_ce
1448
    # ( .length(addr_width))
1449
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1450
vl_cnt_lfsr_ce
1451
    # (.length(addr_width))
1452
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1453
vl_cnt_lfsr_ce
1454
    # ( .length(addr_width))
1455
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1456
vl_cnt_lfsr_ce
1457
    # (.length(addr_width))
1458
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1459
// mux read or write adr to DPRAM
1460
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1461
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1462
vl_dpram_2r2w
1463
    # (.data_width(data_width), .addr_width(addr_width+1))
1464
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1465
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1466
vl_cnt_bin_ce_rew_zq_l1
1467 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1468 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1469
vl_cnt_bin_ce_rew_zq_l1
1470 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1471 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1472
endmodule
1473 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1474 11 unneback
   parameter addr_width = 4;
1475
   parameter N = addr_width-1;
1476 6 unneback
   parameter Q1 = 2'b00;
1477
   parameter Q2 = 2'b01;
1478
   parameter Q3 = 2'b11;
1479
   parameter Q4 = 2'b10;
1480
   parameter going_empty = 1'b0;
1481
   parameter going_full  = 1'b1;
1482
   input [N:0]  wptr, rptr;
1483 14 unneback
   output       fifo_empty;
1484 6 unneback
   output       fifo_full;
1485
   input        wclk, rclk, rst;
1486
   wire direction;
1487
   reg  direction_set, direction_clr;
1488
   wire async_empty, async_full;
1489
   wire fifo_full2;
1490 14 unneback
   wire fifo_empty2;
1491 6 unneback
   // direction_set
1492
   always @ (wptr[N:N-1] or rptr[N:N-1])
1493
     case ({wptr[N:N-1],rptr[N:N-1]})
1494
       {Q1,Q2} : direction_set <= 1'b1;
1495
       {Q2,Q3} : direction_set <= 1'b1;
1496
       {Q3,Q4} : direction_set <= 1'b1;
1497
       {Q4,Q1} : direction_set <= 1'b1;
1498
       default : direction_set <= 1'b0;
1499
     endcase
1500
   // direction_clear
1501
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1502
     if (rst)
1503
       direction_clr <= 1'b1;
1504
     else
1505
       case ({wptr[N:N-1],rptr[N:N-1]})
1506
         {Q2,Q1} : direction_clr <= 1'b1;
1507
         {Q3,Q2} : direction_clr <= 1'b1;
1508
         {Q4,Q3} : direction_clr <= 1'b1;
1509
         {Q1,Q4} : direction_clr <= 1'b1;
1510
         default : direction_clr <= 1'b0;
1511
       endcase
1512 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1513 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1514
   assign async_full  = (wptr == rptr) && (direction==going_full);
1515 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1516
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1517 6 unneback
/*
1518
   always @ (posedge wclk or posedge rst or posedge async_full)
1519
     if (rst)
1520
       {fifo_full, fifo_full2} <= 2'b00;
1521
     else if (async_full)
1522
       {fifo_full, fifo_full2} <= 2'b11;
1523
     else
1524
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1525
*/
1526 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1527 6 unneback
     if (async_empty)
1528
       {fifo_empty, fifo_empty2} <= 2'b11;
1529
     else
1530 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1531 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1532
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1533 27 unneback
endmodule // async_compb
1534 6 unneback
module vl_fifo_1r1w_async (
1535
    d, wr, fifo_full, wr_clk, wr_rst,
1536
    q, rd, fifo_empty, rd_clk, rd_rst
1537
    );
1538
parameter data_width = 18;
1539
parameter addr_width = 4;
1540
// write side
1541
input  [data_width-1:0] d;
1542
input                   wr;
1543
output                  fifo_full;
1544
input                   wr_clk;
1545
input                   wr_rst;
1546
// read side
1547
output [data_width-1:0] q;
1548
input                   rd;
1549
output                  fifo_empty;
1550
input                   rd_clk;
1551
input                   rd_rst;
1552
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1553 18 unneback
vl_cnt_gray_ce_bin
1554 6 unneback
    # ( .length(addr_width))
1555
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1556 18 unneback
vl_cnt_gray_ce_bin
1557 6 unneback
    # (.length(addr_width))
1558 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1559 7 unneback
vl_dpram_1r1w
1560 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1561
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1562
vl_fifo_cmp_async
1563
    # (.addr_width(addr_width))
1564
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1565
endmodule
1566 8 unneback
module vl_fifo_2r2w_async (
1567 6 unneback
    // a side
1568
    a_d, a_wr, a_fifo_full,
1569
    a_q, a_rd, a_fifo_empty,
1570
    a_clk, a_rst,
1571
    // b side
1572
    b_d, b_wr, b_fifo_full,
1573
    b_q, b_rd, b_fifo_empty,
1574
    b_clk, b_rst
1575
    );
1576
parameter data_width = 18;
1577
parameter addr_width = 4;
1578
// a side
1579
input  [data_width-1:0] a_d;
1580
input                   a_wr;
1581
output                  a_fifo_full;
1582
output [data_width-1:0] a_q;
1583
input                   a_rd;
1584
output                  a_fifo_empty;
1585
input                   a_clk;
1586
input                   a_rst;
1587
// b side
1588
input  [data_width-1:0] b_d;
1589
input                   b_wr;
1590
output                  b_fifo_full;
1591
output [data_width-1:0] b_q;
1592
input                   b_rd;
1593
output                  b_fifo_empty;
1594
input                   b_clk;
1595
input                   b_rst;
1596
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1597
vl_fifo_1r1w_async_a (
1598
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1599
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1600
    );
1601
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1602
vl_fifo_1r1w_async_b (
1603
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1604
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1605
    );
1606
endmodule
1607 8 unneback
module vl_fifo_2r2w_async_simplex (
1608 6 unneback
    // a side
1609
    a_d, a_wr, a_fifo_full,
1610
    a_q, a_rd, a_fifo_empty,
1611
    a_clk, a_rst,
1612
    // b side
1613
    b_d, b_wr, b_fifo_full,
1614
    b_q, b_rd, b_fifo_empty,
1615
    b_clk, b_rst
1616
    );
1617
parameter data_width = 18;
1618
parameter addr_width = 4;
1619
// a side
1620
input  [data_width-1:0] a_d;
1621
input                   a_wr;
1622
output                  a_fifo_full;
1623
output [data_width-1:0] a_q;
1624
input                   a_rd;
1625
output                  a_fifo_empty;
1626
input                   a_clk;
1627
input                   a_rst;
1628
// b side
1629
input  [data_width-1:0] b_d;
1630
input                   b_wr;
1631
output                  b_fifo_full;
1632
output [data_width-1:0] b_q;
1633
input                   b_rd;
1634
output                  b_fifo_empty;
1635
input                   b_clk;
1636
input                   b_rst;
1637
// adr_gen
1638
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1639
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1640
// dpram
1641
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1642 18 unneback
vl_cnt_gray_ce_bin
1643 6 unneback
    # ( .length(addr_width))
1644
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1645 18 unneback
vl_cnt_gray_ce_bin
1646 6 unneback
    # (.length(addr_width))
1647
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1648 18 unneback
vl_cnt_gray_ce_bin
1649 6 unneback
    # ( .length(addr_width))
1650
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1651 18 unneback
vl_cnt_gray_ce_bin
1652 6 unneback
    # (.length(addr_width))
1653
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1654
// mux read or write adr to DPRAM
1655
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1656
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1657 11 unneback
vl_dpram_2r2w
1658 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1659
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1660
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1661 11 unneback
vl_fifo_cmp_async
1662 6 unneback
    # (.addr_width(addr_width))
1663
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1664 11 unneback
vl_fifo_cmp_async
1665 6 unneback
    # (.addr_width(addr_width))
1666
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1667
endmodule
1668 48 unneback
module vl_reg_file (
1669
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1670
);
1671
parameter data_width = 32;
1672
parameter addr_width = 5;
1673
input [addr_width-1:0] a1, a2, a3;
1674
input [data_width-1:0] wd3;
1675
input we3;
1676
output [data_width-1:0] rd1, rd2;
1677
input clk;
1678
vl_dpram_1r1w
1679
    # ( .data_width(data_width), .addr_width(addr_width))
1680
    ram1 (
1681
        .d_a(wd3),
1682
        .adr_a(a3),
1683
        .we_a(we3),
1684
        .clk_a(clk),
1685
        .q_b(rd1),
1686
        .adr_b(a1),
1687
        .clk_b(clk) );
1688
vl_dpram_1r1w
1689
    # ( .data_width(data_width), .addr_width(addr_width))
1690
    ram2 (
1691
        .d_a(wd3),
1692
        .adr_a(a3),
1693
        .we_a(we3),
1694
        .clk_a(clk),
1695
        .q_b(rd2),
1696
        .adr_b(a2),
1697
        .clk_b(clk) );
1698
endmodule
1699 12 unneback
//////////////////////////////////////////////////////////////////////
1700
////                                                              ////
1701
////  Versatile library, wishbone stuff                           ////
1702
////                                                              ////
1703
////  Description                                                 ////
1704
////  Wishbone compliant modules                                  ////
1705
////                                                              ////
1706
////                                                              ////
1707
////  To Do:                                                      ////
1708
////   -                                                          ////
1709
////                                                              ////
1710
////  Author(s):                                                  ////
1711
////      - Michael Unneback, unneback@opencores.org              ////
1712
////        ORSoC AB                                              ////
1713
////                                                              ////
1714
//////////////////////////////////////////////////////////////////////
1715
////                                                              ////
1716
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1717
////                                                              ////
1718
//// This source file may be used and distributed without         ////
1719
//// restriction provided that this copyright statement is not    ////
1720
//// removed from the file and that any derivative work contains  ////
1721
//// the original copyright notice and the associated disclaimer. ////
1722
////                                                              ////
1723
//// This source file is free software; you can redistribute it   ////
1724
//// and/or modify it under the terms of the GNU Lesser General   ////
1725
//// Public License as published by the Free Software Foundation; ////
1726
//// either version 2.1 of the License, or (at your option) any   ////
1727
//// later version.                                               ////
1728
////                                                              ////
1729
//// This source is distributed in the hope that it will be       ////
1730
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1731
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1732
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1733
//// details.                                                     ////
1734
////                                                              ////
1735
//// You should have received a copy of the GNU Lesser General    ////
1736
//// Public License along with this source; if not, download it   ////
1737
//// from http://www.opencores.org/lgpl.shtml                     ////
1738
////                                                              ////
1739
//////////////////////////////////////////////////////////////////////
1740
// async wb3 - wb3 bridge
1741
`timescale 1ns/1ns
1742 18 unneback
module vl_wb3wb3_bridge (
1743 12 unneback
        // wishbone slave side
1744
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1745
        // wishbone master side
1746
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1747
input [31:0] wbs_dat_i;
1748
input [31:2] wbs_adr_i;
1749
input [3:0]  wbs_sel_i;
1750
input [1:0]  wbs_bte_i;
1751
input [2:0]  wbs_cti_i;
1752
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1753
output [31:0] wbs_dat_o;
1754 14 unneback
output wbs_ack_o;
1755 12 unneback
input wbs_clk, wbs_rst;
1756
output [31:0] wbm_dat_o;
1757
output reg [31:2] wbm_adr_o;
1758
output [3:0]  wbm_sel_o;
1759
output reg [1:0]  wbm_bte_o;
1760
output reg [2:0]  wbm_cti_o;
1761 14 unneback
output reg wbm_we_o;
1762
output wbm_cyc_o;
1763 12 unneback
output wbm_stb_o;
1764
input [31:0]  wbm_dat_i;
1765
input wbm_ack_i;
1766
input wbm_clk, wbm_rst;
1767
parameter addr_width = 4;
1768
// bte
1769
parameter linear       = 2'b00;
1770
parameter wrap4        = 2'b01;
1771
parameter wrap8        = 2'b10;
1772
parameter wrap16       = 2'b11;
1773
// cti
1774
parameter classic      = 3'b000;
1775
parameter incburst     = 3'b010;
1776
parameter endofburst   = 3'b111;
1777
parameter wbs_adr  = 1'b0;
1778
parameter wbs_data = 1'b1;
1779 33 unneback
parameter wbm_adr0      = 2'b00;
1780
parameter wbm_adr1      = 2'b01;
1781
parameter wbm_data      = 2'b10;
1782
parameter wbm_data_wait = 2'b11;
1783 12 unneback
reg [1:0] wbs_bte_reg;
1784
reg wbs;
1785
wire wbs_eoc_alert, wbm_eoc_alert;
1786
reg wbs_eoc, wbm_eoc;
1787
reg [1:0] wbm;
1788 14 unneback
wire [1:16] wbs_count, wbm_count;
1789 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1790
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1791
reg a_rd_reg;
1792
wire b_rd_adr, b_rd_data;
1793 14 unneback
wire b_rd_data_reg;
1794
wire [35:0] temp;
1795 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1796
always @ (posedge wbs_clk or posedge wbs_rst)
1797
if (wbs_rst)
1798
        wbs_eoc <= 1'b0;
1799
else
1800
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1801
                wbs_eoc <= wbs_bte_i==linear;
1802
        else if (wbs_eoc_alert & (a_rd | a_wr))
1803
                wbs_eoc <= 1'b1;
1804 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1805 12 unneback
    cnt0 (
1806
        .cke(wbs_ack_o),
1807
        .clear(wbs_eoc),
1808
        .q(wbs_count),
1809
        .rst(wbs_rst),
1810
        .clk(wbs_clk));
1811
always @ (posedge wbs_clk or posedge wbs_rst)
1812
if (wbs_rst)
1813
        wbs <= wbs_adr;
1814
else
1815
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1816
                wbs <= wbs_data;
1817
        else if (wbs_eoc & wbs_ack_o)
1818
                wbs <= wbs_adr;
1819
// wbs FIFO
1820
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1821
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1822
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1823
              1'b0;
1824
assign a_rd = !a_fifo_empty;
1825
always @ (posedge wbs_clk or posedge wbs_rst)
1826
if (wbs_rst)
1827
        a_rd_reg <= 1'b0;
1828
else
1829
        a_rd_reg <= a_rd;
1830
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1831
assign wbs_dat_o = a_q[35:4];
1832
always @ (posedge wbs_clk or posedge wbs_rst)
1833
if (wbs_rst)
1834 13 unneback
        wbs_bte_reg <= 2'b00;
1835 12 unneback
else
1836 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1837 12 unneback
// wbm FIFO
1838
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1839
always @ (posedge wbm_clk or posedge wbm_rst)
1840
if (wbm_rst)
1841
        wbm_eoc <= 1'b0;
1842
else
1843
        if (wbm==wbm_adr0 & !b_fifo_empty)
1844
                wbm_eoc <= b_q[4:3] == linear;
1845
        else if (wbm_eoc_alert & wbm_ack_i)
1846
                wbm_eoc <= 1'b1;
1847
always @ (posedge wbm_clk or posedge wbm_rst)
1848
if (wbm_rst)
1849
        wbm <= wbm_adr0;
1850
else
1851 33 unneback
/*
1852 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1853
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1854
        (wbm==wbm_adr1 & !wbm_we_o) |
1855
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1856
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1857 33 unneback
*/
1858
    case (wbm)
1859
    wbm_adr0:
1860
        if (!b_fifo_empty)
1861
            wbm <= wbm_adr1;
1862
    wbm_adr1:
1863
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1864
            wbm <= wbm_data;
1865
    wbm_data:
1866
        if (wbm_ack_i & wbm_eoc)
1867
            wbm <= wbm_adr0;
1868
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1869
            wbm <= wbm_data_wait;
1870
    wbm_data_wait:
1871
        if (!b_fifo_empty)
1872
            wbm <= wbm_data;
1873
    endcase
1874 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1875
assign b_wr = !wbm_we_o & wbm_ack_i;
1876
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1877
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1878
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1879 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1880 12 unneback
                   1'b0;
1881
assign b_rd = b_rd_adr | b_rd_data;
1882 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1883
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1884 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1885 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1886 12 unneback
    cnt1 (
1887
        .cke(wbm_ack_i),
1888
        .clear(wbm_eoc),
1889
        .q(wbm_count),
1890
        .rst(wbm_rst),
1891
        .clk(wbm_clk));
1892 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1893
assign wbm_stb_o = (wbm==wbm_data);
1894 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1895
if (wbm_rst)
1896
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1897
else begin
1898
        if (wbm==wbm_adr0 & !b_fifo_empty)
1899
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1900
        else if (wbm_eoc_alert & wbm_ack_i)
1901
                wbm_cti_o <= endofburst;
1902
end
1903
//async_fifo_dw_simplex_top
1904
vl_fifo_2r2w_async_simplex
1905
# ( .data_width(36), .addr_width(addr_width))
1906
fifo (
1907
    // a side
1908
    .a_d(a_d),
1909
    .a_wr(a_wr),
1910
    .a_fifo_full(a_fifo_full),
1911
    .a_q(a_q),
1912
    .a_rd(a_rd),
1913
    .a_fifo_empty(a_fifo_empty),
1914
    .a_clk(wbs_clk),
1915
    .a_rst(wbs_rst),
1916
    // b side
1917
    .b_d(b_d),
1918
    .b_wr(b_wr),
1919
    .b_fifo_full(b_fifo_full),
1920
    .b_q(b_q),
1921
    .b_rd(b_rd),
1922
    .b_fifo_empty(b_fifo_empty),
1923
    .b_clk(wbm_clk),
1924
    .b_rst(wbm_rst)
1925
    );
1926
endmodule
1927 39 unneback
module vl_wb3_arbiter_type1 (
1928
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1929
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1930
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1931
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1932
    wb_clk, wb_rst
1933
);
1934
parameter nr_of_ports = 3;
1935
parameter adr_size = 26;
1936
parameter adr_lo   = 2;
1937
parameter dat_size = 32;
1938
parameter sel_size = dat_size/8;
1939
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1940
localparam dw = dat_size * nr_of_ports;
1941
localparam sw = sel_size * nr_of_ports;
1942
localparam cw = 3 * nr_of_ports;
1943
localparam bw = 2 * nr_of_ports;
1944
input  [dw-1:0] wbm_dat_o;
1945
input  [aw-1:0] wbm_adr_o;
1946
input  [sw-1:0] wbm_sel_o;
1947
input  [cw-1:0] wbm_cti_o;
1948
input  [bw-1:0] wbm_bte_o;
1949
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1950
output [dw-1:0] wbm_dat_i;
1951
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1952
output [dat_size-1:0] wbs_dat_i;
1953
output [adr_size-1:adr_lo] wbs_adr_i;
1954
output [sel_size-1:0] wbs_sel_i;
1955
output [2:0] wbs_cti_i;
1956
output [1:0] wbs_bte_i;
1957
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1958
input  [dat_size-1:0] wbs_dat_o;
1959
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1960
input wb_clk, wb_rst;
1961 44 unneback
reg  [nr_of_ports-1:0] select;
1962 39 unneback
wire [nr_of_ports-1:0] state;
1963
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1964
wire [nr_of_ports-1:0] sel;
1965
wire idle;
1966
genvar i;
1967
assign idle = !(|state);
1968
generate
1969
if (nr_of_ports == 2) begin
1970
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1971
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1972 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1973
    always @ (idle or wbm_cyc_o)
1974
    if (idle)
1975
        casex (wbm_cyc_o)
1976
        2'b1x : select = 2'b10;
1977
        2'b01 : select = 2'b01;
1978
        default : select = {nr_of_ports{1'b0}};
1979
        endcase
1980
    else
1981
        select = {nr_of_ports{1'b0}};
1982 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1983
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1984
end
1985
endgenerate
1986
generate
1987
if (nr_of_ports == 3) begin
1988
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1989
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1990 44 unneback
    always @ (idle or wbm_cyc_o)
1991
    if (idle)
1992
        casex (wbm_cyc_o)
1993
        3'b1xx : select = 3'b100;
1994
        3'b01x : select = 3'b010;
1995
        3'b001 : select = 3'b001;
1996
        default : select = {nr_of_ports{1'b0}};
1997
        endcase
1998
    else
1999
        select = {nr_of_ports{1'b0}};
2000
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2001 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2002
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2003
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2004
end
2005
endgenerate
2006
generate
2007 44 unneback
if (nr_of_ports == 4) begin
2008
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2009
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2010
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2011
    always @ (idle or wbm_cyc_o)
2012
    if (idle)
2013
        casex (wbm_cyc_o)
2014
        4'b1xxx : select = 4'b1000;
2015
        4'b01xx : select = 4'b0100;
2016
        4'b001x : select = 4'b0010;
2017
        4'b0001 : select = 4'b0001;
2018
        default : select = {nr_of_ports{1'b0}};
2019
        endcase
2020
    else
2021
        select = {nr_of_ports{1'b0}};
2022
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
2023
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2024
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2025
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2026
end
2027
endgenerate
2028
generate
2029
if (nr_of_ports == 5) begin
2030
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2031
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2032
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2033
    always @ (idle or wbm_cyc_o)
2034
    if (idle)
2035
        casex (wbm_cyc_o)
2036
        5'b1xxxx : select = 5'b10000;
2037
        5'b01xxx : select = 5'b01000;
2038
        5'b001xx : select = 5'b00100;
2039
        5'b0001x : select = 5'b00010;
2040
        5'b00001 : select = 5'b00001;
2041
        default : select = {nr_of_ports{1'b0}};
2042
        endcase
2043
    else
2044
        select = {nr_of_ports{1'b0}};
2045
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
2046
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
2047
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2048
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2049
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2050
end
2051
endgenerate
2052
generate
2053 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
2054 39 unneback
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
2055
end
2056
endgenerate
2057
    assign sel = select | state;
2058
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
2059
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
2060
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
2061
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
2062
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
2063
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
2064
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
2065
    assign wbs_cyc_i = |sel;
2066
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
2067
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
2068
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
2069
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
2070
endmodule
2071 49 unneback
// WB RAM with byte enable
2072 59 unneback
module vl_wb_b3_ram_be (
2073 61 unneback
    wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
2074 59 unneback
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
2075 60 unneback
parameter nr_of_ports = 3;
2076
parameter wb_arbiter_type = 1;
2077
parameter adr_size = 26;
2078
parameter adr_lo   = 2;
2079
parameter dat_size = 32;
2080
parameter memory_init = 1;
2081
parameter memory_file = "vl_ram.vmem";
2082
localparam aw = (adr_size - adr_lo) * nr_of_ports;
2083
localparam dw = dat_size * nr_of_ports;
2084
localparam sw = dat_size/8 * nr_of_ports;
2085
localparam cw = 3 * nr_of_ports;
2086
localparam bw = 2 * nr_of_ports;
2087
input [dw-1:0] wb_dat_i;
2088
input [aw-1:0] wb_adr_i;
2089
input [cw-1:0] wb_cti_i;
2090 61 unneback
input [bw-1:0] wb_bte_i;
2091 60 unneback
input [sw-1:0] wb_sel_i;
2092
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
2093
output [dw-1:0] wb_dat_o;
2094 59 unneback
output wb_ack_o;
2095
input wb_clk, wb_rst;
2096 60 unneback
wire [sw-1:0] cke;
2097
// local wb slave
2098
wire [dat_size-1:0] wbs_dat_i;
2099
wire [adr_size-1:0] wbs_adr_i;
2100
wire [2:0] wbs_cti_i;
2101 61 unneback
wire [1:0] wbs_bte_i;
2102 60 unneback
wire [(dat_size/8)-1:0] wbs_sel_i;
2103
wire  wbs_we_i, wbs_stb_i, wbs_cyc_i;
2104
wire [dat_size-1:0] wbs_dat_o;
2105
reg wbs_ack_o;
2106 59 unneback
generate
2107 60 unneback
if (nr_of_ports == 1) begin
2108
    assign wbs_dat_i = wb_dat_i;
2109
    assign wbs_adr_i = wb_adr_i;
2110
    assign wbs_cti_i = wb_cti_i;
2111
    assign wbs_sel_i = wb_sel_i;
2112
    assign wbs_we_i  = wb_we_i;
2113
    assign wbs_stb_i = wb_stb_i;
2114
    assign wbs_cyc_i = wb_cyc_i;
2115
    assign wb_dat_o  = wbs_dat_o;
2116
    assign wb_ack_o  = wbs_ack_o;
2117 59 unneback
end
2118
endgenerate
2119 60 unneback
generate
2120
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin
2121
vl_wb3_arbiter_type1 wb_arbiter0(
2122
    .wbm_dat_o(wb_dat_i),
2123
    .wbm_adr_o(wb_adr_i),
2124
    .wbm_sel_o(wb_sel_i),
2125
    .wbm_cti_o(wb_cti_i),
2126
    .wbm_bte_o(wb_bte_i),
2127
    .wbm_we_o(wb_we_i),
2128
    .wbm_stb_o(wb_stb_i),
2129
    .wbm_cyc_o(wb_cyc_i),
2130
    .wbm_dat_i(wb_dat_o),
2131
    .wbm_ack_i(wb_ack_o),
2132
    .wbm_err_i(),
2133
    .wbm_rty_i(),
2134
    .wbs_dat_i(wbs_dat_i),
2135
    .wbs_adr_i(wbs_adr_i),
2136
    .wbs_sel_i(wbs_sel_i),
2137
    .wbs_cti_i(wbs_cti_i),
2138
    .wbs_bte_i(wbs_bte_i),
2139
    .wbs_we_i(wbs_we_i),
2140
    .wbs_stb_i(wbs_stb_i),
2141
    .wbs_cyc_i(wbs_cyc_i),
2142
    .wbs_dat_o(wbs_dat_o),
2143
    .wbs_ack_o(wbs_ack_o),
2144
    .wbs_err_o(1'b0),
2145
    .wbs_rty_o(1'b0),
2146
    .wb_clk(wb_clk),
2147
    .wb_rst(wb_rst)
2148
);
2149
end
2150
endgenerate
2151
vl_ram_be # (
2152
    .data_width(dat_size),
2153
    .addr_width(adr_size),
2154
    .memory_init(1),
2155
    .memory_file("memory_file"))
2156
ram0(
2157
    .d(wbs_dat_i),
2158
    .adr(wbs_adr_i[adr_size-1:2]),
2159
    .be(wbs_sel_i),
2160
    .we(wbs_we_i),
2161
    .q(wbs_dat_o),
2162
    .clk(wb_clk)
2163
);
2164 59 unneback
always @ (posedge wb_clk or posedge wb_rst)
2165
if (wb_rst)
2166 60 unneback
    wbs_ack_o <= 1'b0;
2167 59 unneback
else
2168 60 unneback
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
2169
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
2170 59 unneback
    else
2171 60 unneback
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
2172 59 unneback
endmodule
2173
// WB RAM with byte enable
2174 49 unneback
module vl_wb_b4_ram_be (
2175
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
2176 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
2177 49 unneback
    parameter dat_width = 32;
2178
    parameter adr_width = 8;
2179
input [dat_width-1:0] wb_dat_i;
2180
input [adr_width-1:0] wb_adr_i;
2181
input [dat_width/8-1:0] wb_sel_i;
2182
input wb_we_i, wb_stb_i, wb_cyc_i;
2183
output [dat_width-1:0] wb_dat_o;
2184 51 unneback
reg [dat_width-1:0] wb_dat_o;
2185 52 unneback
output wb_stall_o;
2186 49 unneback
output wb_ack_o;
2187
reg wb_ack_o;
2188
input wb_clk, wb_rst;
2189 56 unneback
wire [dat_width/8-1:0] cke;
2190 49 unneback
generate
2191
if (dat_width==32) begin
2192 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
2193
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
2194
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
2195
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
2196 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
2197 49 unneback
    always @ (posedge wb_clk)
2198
    begin
2199 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
2200
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
2201
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
2202
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
2203 49 unneback
    end
2204 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
2205
    begin
2206
        if (wb_rst)
2207
            wb_dat_o <= 32'h0;
2208
        else
2209
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
2210
    end
2211 49 unneback
end
2212
endgenerate
2213 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
2214 55 unneback
if (wb_rst)
2215 52 unneback
    wb_ack_o <= 1'b0;
2216
else
2217 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
2218 52 unneback
assign wb_stall_o = 1'b0;
2219 49 unneback
endmodule
2220 17 unneback
// WB ROM
2221 48 unneback
module vl_wb_b4_rom (
2222
    wb_adr_i, wb_stb_i, wb_cyc_i,
2223
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
2224
    parameter dat_width = 32;
2225
    parameter dat_default = 32'h15000000;
2226
    parameter adr_width = 32;
2227
/*
2228
`ifndef ROM
2229
`define ROM "rom.v"
2230
`endif
2231
*/
2232
    input [adr_width-1:2]   wb_adr_i;
2233
    input                   wb_stb_i;
2234
    input                   wb_cyc_i;
2235
    output [dat_width-1:0]  wb_dat_o;
2236
    reg [dat_width-1:0]     wb_dat_o;
2237
    output                  wb_ack_o;
2238
    reg                     wb_ack_o;
2239
    output                  stall_o;
2240
    input                   wb_clk;
2241
    input                   wb_rst;
2242
always @ (posedge wb_clk or posedge wb_rst)
2243
    if (wb_rst)
2244
        wb_dat_o <= {dat_width{1'b0}};
2245
    else
2246
         case (wb_adr_i[adr_width-1:2])
2247
`ifdef ROM
2248
`include `ROM
2249
`endif
2250
           default:
2251
             wb_dat_o <= dat_default;
2252
         endcase // case (wb_adr_i)
2253
always @ (posedge wb_clk or posedge wb_rst)
2254
    if (wb_rst)
2255
        wb_ack_o <= 1'b0;
2256
    else
2257
        wb_ack_o <= wb_stb_i & wb_cyc_i;
2258
assign stall_o = 1'b0;
2259
endmodule
2260
// WB ROM
2261 18 unneback
module vl_wb_boot_rom (
2262 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2263 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2264
    parameter adr_hi = 31;
2265
    parameter adr_lo = 28;
2266
    parameter adr_sel = 4'hf;
2267
    parameter addr_width = 5;
2268 33 unneback
/*
2269
`ifndef BOOT_ROM
2270
`define BOOT_ROM "boot_rom.v"
2271
`endif
2272
*/
2273 18 unneback
    input [adr_hi:2]    wb_adr_i;
2274
    input               wb_stb_i;
2275
    input               wb_cyc_i;
2276
    output [31:0]        wb_dat_o;
2277
    output              wb_ack_o;
2278
    output              hit_o;
2279
    input               wb_clk;
2280
    input               wb_rst;
2281
    wire hit;
2282
    reg [31:0] wb_dat;
2283
    reg wb_ack;
2284
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2285 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2286
    if (wb_rst)
2287 18 unneback
        wb_dat <= 32'h15000000;
2288 17 unneback
    else
2289 18 unneback
         case (wb_adr_i[addr_width-1:2])
2290 33 unneback
`ifdef BOOT_ROM
2291
`include `BOOT_ROM
2292
`endif
2293 17 unneback
           /*
2294
            // Zero r0 and jump to 0x00000100
2295 18 unneback
 
2296
            1 : wb_dat <= 32'hA8200000;
2297
            2 : wb_dat <= 32'hA8C00100;
2298
            3 : wb_dat <= 32'h44003000;
2299
            4 : wb_dat <= 32'h15000000;
2300 17 unneback
            */
2301
           default:
2302 18 unneback
             wb_dat <= 32'h00000000;
2303 17 unneback
         endcase // case (wb_adr_i)
2304
always @ (posedge wb_clk or posedge wb_rst)
2305
    if (wb_rst)
2306 18 unneback
        wb_ack <= 1'b0;
2307 17 unneback
    else
2308 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2309
assign hit_o = hit;
2310
assign wb_dat_o = wb_dat & {32{wb_ack}};
2311
assign wb_ack_o = wb_ack;
2312 17 unneback
endmodule
2313 32 unneback
module vl_wb_dpram (
2314
        // wishbone slave side a
2315
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
2316
        wbsa_clk, wbsa_rst,
2317
        // wishbone slave side a
2318
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
2319
        wbsb_clk, wbsb_rst);
2320
parameter data_width = 32;
2321
parameter addr_width = 8;
2322
parameter dat_o_mask_a = 1;
2323
parameter dat_o_mask_b = 1;
2324
input [31:0] wbsa_dat_i;
2325
input [addr_width-1:2] wbsa_adr_i;
2326
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2327
output [31:0] wbsa_dat_o;
2328
output wbsa_ack_o;
2329
input wbsa_clk, wbsa_rst;
2330
input [31:0] wbsb_dat_i;
2331
input [addr_width-1:2] wbsb_adr_i;
2332
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2333
output [31:0] wbsb_dat_o;
2334
output wbsb_ack_o;
2335
input wbsb_clk, wbsb_rst;
2336
wire wbsa_dat_tmp, wbsb_dat_tmp;
2337
vl_dpram_2r2w # (
2338 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
2339 32 unneback
dpram0(
2340
    .d_a(wbsa_dat_i),
2341
    .q_a(wbsa_dat_tmp),
2342
    .adr_a(wbsa_adr_i),
2343
    .we_a(wbsa_we_i),
2344
    .clk_a(wbsa_clk),
2345
    .d_b(wbsb_dat_i),
2346
    .q_b(wbsb_dat_tmp),
2347
    .adr_b(wbsb_adr_i),
2348
    .we_b(wbsb_we_i),
2349
    .clk_b(wbsb_clk) );
2350 33 unneback
generate if (dat_o_mask_a==1)
2351 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
2352
endgenerate
2353 33 unneback
generate if (dat_o_mask_a==0)
2354 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
2355
endgenerate
2356 33 unneback
generate if (dat_o_mask_b==1)
2357 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
2358
endgenerate
2359 33 unneback
generate if (dat_o_mask_b==0)
2360 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
2361
endgenerate
2362
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2363
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2364
endmodule
2365 18 unneback
//////////////////////////////////////////////////////////////////////
2366
////                                                              ////
2367
////  Arithmetic functions                                        ////
2368
////                                                              ////
2369
////  Description                                                 ////
2370
////  Arithmetic functions for ALU and DSP                        ////
2371
////                                                              ////
2372
////                                                              ////
2373
////  To Do:                                                      ////
2374
////   -                                                          ////
2375
////                                                              ////
2376
////  Author(s):                                                  ////
2377
////      - Michael Unneback, unneback@opencores.org              ////
2378
////        ORSoC AB                                              ////
2379
////                                                              ////
2380
//////////////////////////////////////////////////////////////////////
2381
////                                                              ////
2382
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2383
////                                                              ////
2384
//// This source file may be used and distributed without         ////
2385
//// restriction provided that this copyright statement is not    ////
2386
//// removed from the file and that any derivative work contains  ////
2387
//// the original copyright notice and the associated disclaimer. ////
2388
////                                                              ////
2389
//// This source file is free software; you can redistribute it   ////
2390
//// and/or modify it under the terms of the GNU Lesser General   ////
2391
//// Public License as published by the Free Software Foundation; ////
2392
//// either version 2.1 of the License, or (at your option) any   ////
2393
//// later version.                                               ////
2394
////                                                              ////
2395
//// This source is distributed in the hope that it will be       ////
2396
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2397
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2398
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2399
//// details.                                                     ////
2400
////                                                              ////
2401
//// You should have received a copy of the GNU Lesser General    ////
2402
//// Public License along with this source; if not, download it   ////
2403
//// from http://www.opencores.org/lgpl.shtml                     ////
2404
////                                                              ////
2405
//////////////////////////////////////////////////////////////////////
2406
// signed multiplication
2407
module vl_mults (a,b,p);
2408
parameter operand_a_width = 18;
2409
parameter operand_b_width = 18;
2410
parameter result_hi = 35;
2411
parameter result_lo = 0;
2412
input [operand_a_width-1:0] a;
2413
input [operand_b_width-1:0] b;
2414
output [result_hi:result_lo] p;
2415
wire signed [operand_a_width-1:0] ai;
2416
wire signed [operand_b_width-