OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 unneback 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  Versatile library, clock and reset                          ////
4 
////                                                              ////
5 
////  Description                                                 ////
6 
////  Logic related to clock and reset                            ////
7 
////                                                              ////
8 
////                                                              ////
9 
////  To Do:                                                      ////
10 
////   - add more different registers                             ////
11 
////                                                              ////
12 
////  Author(s):                                                  ////
13 
////      - Michael Unneback, unneback@opencores.org              ////
14 
////        ORSoC AB                                              ////
15 
////                                                              ////
16 
//////////////////////////////////////////////////////////////////////
17 
////                                                              ////
18 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19 
////                                                              ////
20 
//// This source file may be used and distributed without         ////
21 
//// restriction provided that this copyright statement is not    ////
22 
//// removed from the file and that any derivative work contains  ////
23 
//// the original copyright notice and the associated disclaimer. ////
24 
////                                                              ////
25 
//// This source file is free software; you can redistribute it   ////
26 
//// and/or modify it under the terms of the GNU Lesser General   ////
27 
//// Public License as published by the Free Software Foundation; ////
28 
//// either version 2.1 of the License, or (at your option) any   ////
29 
//// later version.                                               ////
30 
////                                                              ////
31 
//// This source is distributed in the hope that it will be       ////
32 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35 
//// details.                                                     ////
36 
////                                                              ////
37 
//// You should have received a copy of the GNU Lesser General    ////
38 
//// Public License along with this source; if not, download it   ////
39 
//// from http://www.opencores.org/lgpl.shtml                     ////
40 
////                                                              ////
41 
//////////////////////////////////////////////////////////////////////
42 
// Global buffer
43 
// usage:
44 
// use to enable global buffers for high fan out signals such as clock and reset
45 
altera
46 
 // ALTERA
47 
 //ACTEL
48 
// sync reset
49 
// input active lo async reset, normally from external reset generetaor and/or switch
50 
// output active high global reset sync with two DFFs
51 
`timescale 1 ns/100 ps
52 
module vl_sync_rst ( rst_n_i, rst_o, clk);
53 
input rst_n_i, clk;
54 
output rst_o;
55 
reg [0:1] tmp;
56 
always @ (posedge clk or negedge rst_n_i)
57 
if (!rst_n_i)
58 
        tmp <= 2'b00;
59 
else
60 
        tmp <= {1'b1,tmp[0]};
61 
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
62 
endmodule
63 
// vl_pll
64 
 //altera
65 
 //actel
66 
//////////////////////////////////////////////////////////////////////
67 
////                                                              ////
68 
////  Versatile library, registers                                ////
69 
////                                                              ////
70 
////  Description                                                 ////
71 
////  Different type of registers                                 ////
72 
////                                                              ////
73 
////                                                              ////
74 
////  To Do:                                                      ////
75 
////   - add more different registers                             ////
76 
////                                                              ////
77 
////  Author(s):                                                  ////
78 
////      - Michael Unneback, unneback@opencores.org              ////
79 
////        ORSoC AB                                              ////
80 
////                                                              ////
81 
//////////////////////////////////////////////////////////////////////
82 
////                                                              ////
83 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84 
////                                                              ////
85 
//// This source file may be used and distributed without         ////
86 
//// restriction provided that this copyright statement is not    ////
87 
//// removed from the file and that any derivative work contains  ////
88 
//// the original copyright notice and the associated disclaimer. ////
89 
////                                                              ////
90 
//// This source file is free software; you can redistribute it   ////
91 
//// and/or modify it under the terms of the GNU Lesser General   ////
92 
//// Public License as published by the Free Software Foundation; ////
93 
//// either version 2.1 of the License, or (at your option) any   ////
94 
//// later version.                                               ////
95 
////                                                              ////
96 
//// This source is distributed in the hope that it will be       ////
97 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100 
//// details.                                                     ////
101 
////                                                              ////
102 
//// You should have received a copy of the GNU Lesser General    ////
103 
//// Public License along with this source; if not, download it   ////
104 
//// from http://www.opencores.org/lgpl.shtml                     ////
105 
////                                                              ////
106 
//////////////////////////////////////////////////////////////////////
107 
module dff ( d, q, clk, rst);
108 
        parameter width = 1;
109 
        parameter reset_value = 0;
110 
        input [width-1:0] d;
111 
        input clk, rst;
112 
        output reg [width-1:0] q;
113 
        always @ (posedge clk or posedge rst)
114 
        if (rst)
115 
                q <= reset_value;
116 
        else
117 
                q <= d;
118 
endmodule
119 
module dff_array ( d, q, clk, rst);
120 
        parameter width = 1;
121 
        parameter depth = 2;
122 
        parameter reset_value = 1'b0;
123 
        input [width-1:0] d;
124 
        input clk, rst;
125 
        output [width-1:0] q;
126 
        reg  [0:depth-1] q_tmp [width-1:0];
127 
        integer i;
128 
        always @ (posedge clk or posedge rst)
129 
        if (rst) begin
130 
            for (i=0;i<depth;i=i+1)
131 
                q_tmp[i] <= {width{reset_value}};
132 
        end else begin
133 
            q_tmp[0] <= d;
134 
            for (i=1;i<depth;i=i+1)
135 
                q_tmp[i] <= q_tmp[i-1];
136 
        end
137 
    assign q = q_tmp[depth-1];
138 
endmodule
139 
module dff_ce ( d, ce, q, clk, rst);
140 
        parameter width = 1;
141 
        parameter reset_value = 0;
142 
        input [width-1:0] d;
143 
        input ce, clk, rst;
144 
        output reg [width-1:0] q;
145 
        always @ (posedge clk or posedge rst)
146 
        if (rst)
147 
                q <= reset_value;
148 
        else
149 
                if (ce)
150 
                        q <= d;
151 
endmodule
152 
// megafunction wizard: %LPM_FF%
153 
// GENERATION: STANDARD
154 
// VERSION: WM1.0
155 
// MODULE: lpm_ff
156 
// ============================================================
157 
// File Name: dff_sr.v
158 
// Megafunction Name(s):
159 
//                      lpm_ff
160 
//
161 
// Simulation Library Files(s):
162 
//                      lpm
163 
// ============================================================
164 
// ************************************************************
165 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
166 
//
167 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
168 
// ************************************************************
169 
//Copyright (C) 1991-2010 Altera Corporation
170 
//Your use of Altera Corporation's design tools, logic functions
171 
//and other software and tools, and its AMPP partner logic
172 
//functions, and any output files from any of the foregoing
173 
//(including device programming or simulation files), and any
174 
//associated documentation or information are expressly subject
175 
//to the terms and conditions of the Altera Program License
176 
//Subscription Agreement, Altera MegaCore Function License
177 
//Agreement, or other applicable license agreement, including,
178 
//without limitation, that your use is for the sole purpose of
179 
//programming logic devices manufactured by Altera and sold by
180 
//Altera or its authorized distributors.  Please refer to the
181 
//applicable agreement for further details.
182 
// synopsys translate_off
183 
`timescale 1 ps / 1 ps
184 
// synopsys translate_on
185 
module dff_sr (
186 
        aclr,
187 
        aset,
188 
        clock,
189 
        data,
190 
        q);
191 
        input     aclr;
192 
        input     aset;
193 
        input     clock;
194 
        input     data;
195 
        output    q;
196 
        wire [0:0] sub_wire0;
197 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
198 
        wire  q = sub_wire1;
199 
        wire  sub_wire2 = data;
200 
        wire  sub_wire3 = sub_wire2;
201 
        lpm_ff  lpm_ff_component (
202 
                                .aclr (aclr),
203 
                                .clock (clock),
204 
                                .data (sub_wire3),
205 
                                .aset (aset),
206 
                                .q (sub_wire0)
207 
                                // synopsys translate_off
208 
                                ,
209 
                                .aload (),
210 
                                .enable (),
211 
                                .sclr (),
212 
                                .sload (),
213 
                                .sset ()
214 
                                // synopsys translate_on
215 
                                );
216 
        defparam
217 
                lpm_ff_component.lpm_fftype = "DFF",
218 
                lpm_ff_component.lpm_type = "LPM_FF",
219 
                lpm_ff_component.lpm_width = 1;
220 
endmodule
221 
// ============================================================
222 
// CNX file retrieval info
223 
// ============================================================
224 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
225 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
226 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
227 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
228 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
229 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
230 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
231 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
232 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
233 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
234 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
235 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
236 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
237 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
238 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
239 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
240 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
241 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
242 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
243 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
244 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
245 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
246 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
247 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
248 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
249 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
250 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
251 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
252 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
253 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
254 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
255 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
256 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
257 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
258 
// Retrieval info: LIB_FILE: lpm
259 
// LATCH
260 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
261 
module latch ( d, le, q, clk);
262 
input d, le;
263 
output q;
264 
input clk;
265 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
266 
endmodule
267 
//////////////////////////////////////////////////////////////////////
268 
////                                                              ////
269 
////  Versatile counter                                           ////
270 
////                                                              ////
271 
////  Description                                                 ////
272 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
273 
////  counter                                                     ////
274 
////                                                              ////
275 
////  To Do:                                                      ////
276 
////   - add LFSR with more taps                                  ////
277 
////                                                              ////
278 
////  Author(s):                                                  ////
279 
////      - Michael Unneback, unneback@opencores.org              ////
280 
////        ORSoC AB                                              ////
281 
////                                                              ////
282 
//////////////////////////////////////////////////////////////////////
283 
////                                                              ////
284 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
285 
////                                                              ////
286 
//// This source file may be used and distributed without         ////
287 
//// restriction provided that this copyright statement is not    ////
288 
//// removed from the file and that any derivative work contains  ////
289 
//// the original copyright notice and the associated disclaimer. ////
290 
////                                                              ////
291 
//// This source file is free software; you can redistribute it   ////
292 
//// and/or modify it under the terms of the GNU Lesser General   ////
293 
//// Public License as published by the Free Software Foundation; ////
294 
//// either version 2.1 of the License, or (at your option) any   ////
295 
//// later version.                                               ////
296 
////                                                              ////
297 
//// This source is distributed in the hope that it will be       ////
298 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
299 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
300 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
301 
//// details.                                                     ////
302 
////                                                              ////
303 
//// You should have received a copy of the GNU Lesser General    ////
304 
//// Public License along with this source; if not, download it   ////
305 
//// from http://www.opencores.org/lgpl.shtml                     ////
306 
////                                                              ////
307 
//////////////////////////////////////////////////////////////////////
308 
// binary counter
309 
module cnt_bin_ce ( cke, q, rst, clk);
310 
   parameter length = 4;
311 
   input cke;
312 
   output [length:1] q;
313 
   input rst;
314 
   input clk;
315 
   parameter clear_value = 0;
316 
   parameter set_value = 1;
317 
   parameter wrap_value = 0;
318 
   parameter level1_value = 15;
319 
   reg  [length:1] qi;
320 
   wire [length:1] q_next;
321 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
322 
   always @ (posedge clk or posedge rst)
323 
     if (rst)
324 
       qi <= {length{1'b0}};
325 
     else
326 
     if (cke)
327 
       qi <= q_next;
328 
   assign q = qi;
329 
endmodule
330 
//////////////////////////////////////////////////////////////////////
331 
////                                                              ////
332 
////  Versatile counter                                           ////
333 
////                                                              ////
334 
////  Description                                                 ////
335 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
336 
////  counter                                                     ////
337 
////                                                              ////
338 
////  To Do:                                                      ////
339 
////   - add LFSR with more taps                                  ////
340 
////                                                              ////
341 
////  Author(s):                                                  ////
342 
////      - Michael Unneback, unneback@opencores.org              ////
343 
////        ORSoC AB                                              ////
344 
////                                                              ////
345 
//////////////////////////////////////////////////////////////////////
346 
////                                                              ////
347 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
348 
////                                                              ////
349 
//// This source file may be used and distributed without         ////
350 
//// restriction provided that this copyright statement is not    ////
351 
//// removed from the file and that any derivative work contains  ////
352 
//// the original copyright notice and the associated disclaimer. ////
353 
////                                                              ////
354 
//// This source file is free software; you can redistribute it   ////
355 
//// and/or modify it under the terms of the GNU Lesser General   ////
356 
//// Public License as published by the Free Software Foundation; ////
357 
//// either version 2.1 of the License, or (at your option) any   ////
358 
//// later version.                                               ////
359 
////                                                              ////
360 
//// This source is distributed in the hope that it will be       ////
361 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
362 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
363 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
364 
//// details.                                                     ////
365 
////                                                              ////
366 
//// You should have received a copy of the GNU Lesser General    ////
367 
//// Public License along with this source; if not, download it   ////
368 
//// from http://www.opencores.org/lgpl.shtml                     ////
369 
////                                                              ////
370 
//////////////////////////////////////////////////////////////////////
371 
// binary counter
372 
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
373 
   parameter length = 4;
374 
   input clear;
375 
   input cke;
376 
   output [length:1] q;
377 
   input rst;
378 
   input clk;
379 
   parameter clear_value = 0;
380 
   parameter set_value = 1;
381 
   parameter wrap_value = 0;
382 
   parameter level1_value = 15;
383 
   reg  [length:1] qi;
384 
   wire [length:1] q_next;
385 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
386 
   always @ (posedge clk or posedge rst)
387 
     if (rst)
388 
       qi <= {length{1'b0}};
389 
     else
390 
     if (cke)
391 
       qi <= q_next;
392 
   assign q = qi;
393 
endmodule
394 
//////////////////////////////////////////////////////////////////////
395 
////                                                              ////
396 
////  Versatile counter                                           ////
397 
////                                                              ////
398 
////  Description                                                 ////
399 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
400 
////  counter                                                     ////
401 
////                                                              ////
402 
////  To Do:                                                      ////
403 
////   - add LFSR with more taps                                  ////
404 
////                                                              ////
405 
////  Author(s):                                                  ////
406 
////      - Michael Unneback, unneback@opencores.org              ////
407 
////        ORSoC AB                                              ////
408 
////                                                              ////
409 
//////////////////////////////////////////////////////////////////////
410 
////                                                              ////
411 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
412 
////                                                              ////
413 
//// This source file may be used and distributed without         ////
414 
//// restriction provided that this copyright statement is not    ////
415 
//// removed from the file and that any derivative work contains  ////
416 
//// the original copyright notice and the associated disclaimer. ////
417 
////                                                              ////
418 
//// This source file is free software; you can redistribute it   ////
419 
//// and/or modify it under the terms of the GNU Lesser General   ////
420 
//// Public License as published by the Free Software Foundation; ////
421 
//// either version 2.1 of the License, or (at your option) any   ////
422 
//// later version.                                               ////
423 
////                                                              ////
424 
//// This source is distributed in the hope that it will be       ////
425 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
426 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
427 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
428 
//// details.                                                     ////
429 
////                                                              ////
430 
//// You should have received a copy of the GNU Lesser General    ////
431 
//// Public License along with this source; if not, download it   ////
432 
//// from http://www.opencores.org/lgpl.shtml                     ////
433 
////                                                              ////
434 
//////////////////////////////////////////////////////////////////////
435 
// binary counter
436 
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
437 
   parameter length = 4;
438 
   input clear;
439 
   input set;
440 
   input cke;
441 
   input rew;
442 
   output [length:1] q;
443 
   input rst;
444 
   input clk;
445 
   parameter clear_value = 0;
446 
   parameter set_value = 1;
447 
   parameter wrap_value = 0;
448 
   parameter level1_value = 15;
449 
   reg  [length:1] qi;
450 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
451 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
452 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
453 
   assign q_next = rew ? q_next_rew : q_next_fw;
454 
   always @ (posedge clk or posedge rst)
455 
     if (rst)
456 
       qi <= {length{1'b0}};
457 
     else
458 
     if (cke)
459 
       qi <= q_next;
460 
   assign q = qi;
461 
endmodule
462 
//////////////////////////////////////////////////////////////////////
463 
////                                                              ////
464 
////  Versatile counter                                           ////
465 
////                                                              ////
466 
////  Description                                                 ////
467 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
468 
////  counter                                                     ////
469 
////                                                              ////
470 
////  To Do:                                                      ////
471 
////   - add LFSR with more taps                                  ////
472 
////                                                              ////
473 
////  Author(s):                                                  ////
474 
////      - Michael Unneback, unneback@opencores.org              ////
475 
////        ORSoC AB                                              ////
476 
////                                                              ////
477 
//////////////////////////////////////////////////////////////////////
478 
////                                                              ////
479 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
480 
////                                                              ////
481 
//// This source file may be used and distributed without         ////
482 
//// restriction provided that this copyright statement is not    ////
483 
//// removed from the file and that any derivative work contains  ////
484 
//// the original copyright notice and the associated disclaimer. ////
485 
////                                                              ////
486 
//// This source file is free software; you can redistribute it   ////
487 
//// and/or modify it under the terms of the GNU Lesser General   ////
488 
//// Public License as published by the Free Software Foundation; ////
489 
//// either version 2.1 of the License, or (at your option) any   ////
490 
//// later version.                                               ////
491 
////                                                              ////
492 
//// This source is distributed in the hope that it will be       ////
493 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
494 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
495 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
496 
//// details.                                                     ////
497 
////                                                              ////
498 
//// You should have received a copy of the GNU Lesser General    ////
499 
//// Public License along with this source; if not, download it   ////
500 
//// from http://www.opencores.org/lgpl.shtml                     ////
501 
////                                                              ////
502 
//////////////////////////////////////////////////////////////////////
503 
// binary counter
504 
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
505 
   parameter length = 4;
506 
   input cke;
507 
   input rew;
508 
   output reg level1;
509 
   input rst;
510 
   input clk;
511 
   parameter clear_value = 0;
512 
   parameter set_value = 1;
513 
   parameter wrap_value = 1;
514 
   parameter level1_value = 15;
515 
   reg  [length:1] qi;
516 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
517 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
518 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
519 
   assign q_next = rew ? q_next_rew : q_next_fw;
520 
   always @ (posedge clk or posedge rst)
521 
     if (rst)
522 
       qi <= {length{1'b0}};
523 
     else
524 
     if (cke)
525 
       qi <= q_next;
526 
    always @ (posedge clk or posedge rst)
527 
    if (rst)
528 
        level1 <= 1'b0;
529 
    else
530 
    if (cke)
531 
    if (q_next == level1_value)
532 
        level1 <= 1'b1;
533 
    else if (qi == level1_value & rew)
534 
        level1 <= 1'b0;
535 
endmodule
536 
//////////////////////////////////////////////////////////////////////
537 
////                                                              ////
538 
////  Versatile counter                                           ////
539 
////                                                              ////
540 
////  Description                                                 ////
541 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
542 
////  counter                                                     ////
543 
////                                                              ////
544 
////  To Do:                                                      ////
545 
////   - add LFSR with more taps                                  ////
546 
////                                                              ////
547 
////  Author(s):                                                  ////
548 
////      - Michael Unneback, unneback@opencores.org              ////
549 
////        ORSoC AB                                              ////
550 
////                                                              ////
551 
//////////////////////////////////////////////////////////////////////
552 
////                                                              ////
553 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
554 
////                                                              ////
555 
//// This source file may be used and distributed without         ////
556 
//// restriction provided that this copyright statement is not    ////
557 
//// removed from the file and that any derivative work contains  ////
558 
//// the original copyright notice and the associated disclaimer. ////
559 
////                                                              ////
560 
//// This source file is free software; you can redistribute it   ////
561 
//// and/or modify it under the terms of the GNU Lesser General   ////
562 
//// Public License as published by the Free Software Foundation; ////
563 
//// either version 2.1 of the License, or (at your option) any   ////
564 
//// later version.                                               ////
565 
////                                                              ////
566 
//// This source is distributed in the hope that it will be       ////
567 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
568 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
569 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
570 
//// details.                                                     ////
571 
////                                                              ////
572 
//// You should have received a copy of the GNU Lesser General    ////
573 
//// Public License along with this source; if not, download it   ////
574 
//// from http://www.opencores.org/lgpl.shtml                     ////
575 
////                                                              ////
576 
//////////////////////////////////////////////////////////////////////
577 
// LFSR counter
578 
module cnt_lfsr_zq ( zq, rst, clk);
579 
   parameter length = 4;
580 
   output reg zq;
581 
   input rst;
582 
   input clk;
583 
   parameter clear_value = 0;
584 
   parameter set_value = 1;
585 
   parameter wrap_value = 8;
586 
   parameter level1_value = 15;
587 
   reg  [length:1] qi;
588 
   reg lfsr_fb;
589 
   wire [length:1] q_next;
590 
   reg [32:1] polynom;
591 
   integer i;
592 
   always @ (qi)
593 
   begin
594 
        case (length)
595 
         2: polynom = 32'b11;                               // 0x3
596 
         3: polynom = 32'b110;                              // 0x6
597 
         4: polynom = 32'b1100;                             // 0xC
598 
         5: polynom = 32'b10100;                            // 0x14
599 
         6: polynom = 32'b110000;                           // 0x30
600 
         7: polynom = 32'b1100000;                          // 0x60
601 
         8: polynom = 32'b10111000;                         // 0xb8
602 
         9: polynom = 32'b100010000;                        // 0x110
603 
        10: polynom = 32'b1001000000;                       // 0x240
604 
        11: polynom = 32'b10100000000;                      // 0x500
605 
        12: polynom = 32'b100000101001;                     // 0x829
606 
        13: polynom = 32'b1000000001100;                    // 0x100C
607 
        14: polynom = 32'b10000000010101;                   // 0x2015
608 
        15: polynom = 32'b110000000000000;                  // 0x6000
609 
        16: polynom = 32'b1101000000001000;                 // 0xD008
610 
        17: polynom = 32'b10010000000000000;                // 0x12000
611 
        18: polynom = 32'b100000010000000000;               // 0x20400
612 
        19: polynom = 32'b1000000000000100011;              // 0x40023
613 
        20: polynom = 32'b10000010000000000000;             // 0x82000
614 
        21: polynom = 32'b101000000000000000000;            // 0x140000
615 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
616 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
617 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
618 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
619 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
620 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
621 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
622 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
623 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
624 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
625 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
626 
        default: polynom = 32'b0;
627 
        endcase
628 
        lfsr_fb = qi[length];
629 
        for (i=length-1; i>=1; i=i-1) begin
630 
            if (polynom[i])
631 
                lfsr_fb = lfsr_fb  ~^ qi[i];
632 
        end
633 
    end
634 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
635 
   always @ (posedge clk or posedge rst)
636 
     if (rst)
637 
       qi <= {length{1'b0}};
638 
     else
639 
       qi <= q_next;
640 
   always @ (posedge clk or posedge rst)
641 
     if (rst)
642 
       zq <= 1'b1;
643 
     else
644 
       zq <= q_next == {length{1'b0}};
645 
endmodule
646 
//////////////////////////////////////////////////////////////////////
647 
////                                                              ////
648 
////  Versatile counter                                           ////
649 
////                                                              ////
650 
////  Description                                                 ////
651 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
652 
////  counter                                                     ////
653 
////                                                              ////
654 
////  To Do:                                                      ////
655 
////   - add LFSR with more taps                                  ////
656 
////                                                              ////
657 
////  Author(s):                                                  ////
658 
////      - Michael Unneback, unneback@opencores.org              ////
659 
////        ORSoC AB                                              ////
660 
////                                                              ////
661 
//////////////////////////////////////////////////////////////////////
662 
////                                                              ////
663 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
664 
////                                                              ////
665 
//// This source file may be used and distributed without         ////
666 
//// restriction provided that this copyright statement is not    ////
667 
//// removed from the file and that any derivative work contains  ////
668 
//// the original copyright notice and the associated disclaimer. ////
669 
////                                                              ////
670 
//// This source file is free software; you can redistribute it   ////
671 
//// and/or modify it under the terms of the GNU Lesser General   ////
672 
//// Public License as published by the Free Software Foundation; ////
673 
//// either version 2.1 of the License, or (at your option) any   ////
674 
//// later version.                                               ////
675 
////                                                              ////
676 
//// This source is distributed in the hope that it will be       ////
677 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
678 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
679 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
680 
//// details.                                                     ////
681 
////                                                              ////
682 
//// You should have received a copy of the GNU Lesser General    ////
683 
//// Public License along with this source; if not, download it   ////
684 
//// from http://www.opencores.org/lgpl.shtml                     ////
685 
////                                                              ////
686 
//////////////////////////////////////////////////////////////////////
687 
// LFSR counter
688 
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
689 
   parameter length = 4;
690 
   input cke;
691 
   output reg zq;
692 
   input rst;
693 
   input clk;
694 
   parameter clear_value = 0;
695 
   parameter set_value = 1;
696 
   parameter wrap_value = 8;
697 
   parameter level1_value = 15;
698 
   reg  [length:1] qi;
699 
   reg lfsr_fb;
700 
   wire [length:1] q_next;
701 
   reg [32:1] polynom;
702 
   integer i;
703 
   always @ (qi)
704 
   begin
705 
        case (length)
706 
         2: polynom = 32'b11;                               // 0x3
707 
         3: polynom = 32'b110;                              // 0x6
708 
         4: polynom = 32'b1100;                             // 0xC
709 
         5: polynom = 32'b10100;                            // 0x14
710 
         6: polynom = 32'b110000;                           // 0x30
711 
         7: polynom = 32'b1100000;                          // 0x60
712 
         8: polynom = 32'b10111000;                         // 0xb8
713 
         9: polynom = 32'b100010000;                        // 0x110
714 
        10: polynom = 32'b1001000000;                       // 0x240
715 
        11: polynom = 32'b10100000000;                      // 0x500
716 
        12: polynom = 32'b100000101001;                     // 0x829
717 
        13: polynom = 32'b1000000001100;                    // 0x100C
718 
        14: polynom = 32'b10000000010101;                   // 0x2015
719 
        15: polynom = 32'b110000000000000;                  // 0x6000
720 
        16: polynom = 32'b1101000000001000;                 // 0xD008
721 
        17: polynom = 32'b10010000000000000;                // 0x12000
722 
        18: polynom = 32'b100000010000000000;               // 0x20400
723 
        19: polynom = 32'b1000000000000100011;              // 0x40023
724 
        20: polynom = 32'b10000010000000000000;             // 0x82000
725 
        21: polynom = 32'b101000000000000000000;            // 0x140000
726 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
727 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
728 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
729 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
730 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
731 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
732 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
733 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
734 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
735 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
736 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
737 
        default: polynom = 32'b0;
738 
        endcase
739 
        lfsr_fb = qi[length];
740 
        for (i=length-1; i>=1; i=i-1) begin
741 
            if (polynom[i])
742 
                lfsr_fb = lfsr_fb  ~^ qi[i];
743 
        end
744 
    end
745 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
746 
   always @ (posedge clk or posedge rst)
747 
     if (rst)
748 
       qi <= {length{1'b0}};
749 
     else
750 
     if (cke)
751 
       qi <= q_next;
752 
   always @ (posedge clk or posedge rst)
753 
     if (rst)
754 
       zq <= 1'b1;
755 
     else
756 
     if (cke)
757 
       zq <= q_next == {length{1'b0}};
758 
endmodule
759 
//////////////////////////////////////////////////////////////////////
760 
////                                                              ////
761 
////  Versatile counter                                           ////
762 
////                                                              ////
763 
////  Description                                                 ////
764 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
765 
////  counter                                                     ////
766 
////                                                              ////
767 
////  To Do:                                                      ////
768 
////   - add LFSR with more taps                                  ////
769 
////                                                              ////
770 
////  Author(s):                                                  ////
771 
////      - Michael Unneback, unneback@opencores.org              ////
772 
////        ORSoC AB                                              ////
773 
////                                                              ////
774 
//////////////////////////////////////////////////////////////////////
775 
////                                                              ////
776 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
777 
////                                                              ////
778 
//// This source file may be used and distributed without         ////
779 
//// restriction provided that this copyright statement is not    ////
780 
//// removed from the file and that any derivative work contains  ////
781 
//// the original copyright notice and the associated disclaimer. ////
782 
////                                                              ////
783 
//// This source file is free software; you can redistribute it   ////
784 
//// and/or modify it under the terms of the GNU Lesser General   ////
785 
//// Public License as published by the Free Software Foundation; ////
786 
//// either version 2.1 of the License, or (at your option) any   ////
787 
//// later version.                                               ////
788 
////                                                              ////
789 
//// This source is distributed in the hope that it will be       ////
790 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
791 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
792 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
793 
//// details.                                                     ////
794 
////                                                              ////
795 
//// You should have received a copy of the GNU Lesser General    ////
796 
//// Public License along with this source; if not, download it   ////
797 
//// from http://www.opencores.org/lgpl.shtml                     ////
798 
////                                                              ////
799 
//////////////////////////////////////////////////////////////////////
800 
// LFSR counter
801 
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
802 
   parameter length = 4;
803 
   input cke;
804 
   input rew;
805 
   output reg level1;
806 
   input rst;
807 
   input clk;
808 
   parameter clear_value = 0;
809 
   parameter set_value = 1;
810 
   parameter wrap_value = 8;
811 
   parameter level1_value = 15;
812 
   reg  [length:1] qi;
813 
   reg lfsr_fb, lfsr_fb_rew;
814 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
815 
   reg [32:1] polynom_rew;
816 
   integer j;
817 
   reg [32:1] polynom;
818 
   integer i;
819 
   always @ (qi)
820 
   begin
821 
        case (length)
822 
         2: polynom = 32'b11;                               // 0x3
823 
         3: polynom = 32'b110;                              // 0x6
824 
         4: polynom = 32'b1100;                             // 0xC
825 
         5: polynom = 32'b10100;                            // 0x14
826 
         6: polynom = 32'b110000;                           // 0x30
827 
         7: polynom = 32'b1100000;                          // 0x60
828 
         8: polynom = 32'b10111000;                         // 0xb8
829 
         9: polynom = 32'b100010000;                        // 0x110
830 
        10: polynom = 32'b1001000000;                       // 0x240
831 
        11: polynom = 32'b10100000000;                      // 0x500
832 
        12: polynom = 32'b100000101001;                     // 0x829
833 
        13: polynom = 32'b1000000001100;                    // 0x100C
834 
        14: polynom = 32'b10000000010101;                   // 0x2015
835 
        15: polynom = 32'b110000000000000;                  // 0x6000
836 
        16: polynom = 32'b1101000000001000;                 // 0xD008
837 
        17: polynom = 32'b10010000000000000;                // 0x12000
838 
        18: polynom = 32'b100000010000000000;               // 0x20400
839 
        19: polynom = 32'b1000000000000100011;              // 0x40023
840 
        20: polynom = 32'b10000010000000000000;             // 0x82000
841 
        21: polynom = 32'b101000000000000000000;            // 0x140000
842 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
843 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
844 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
845 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
846 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
847 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
848 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
849 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
850 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
851 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
852 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
853 
        default: polynom = 32'b0;
854 
        endcase
855 
        lfsr_fb = qi[length];
856 
        for (i=length-1; i>=1; i=i-1) begin
857 
            if (polynom[i])
858 
                lfsr_fb = lfsr_fb  ~^ qi[i];
859 
        end
860 
    end
861 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
862 
   always @ (qi)
863 
   begin
864 
        case (length)
865 
         2: polynom_rew = 32'b11;
866 
         3: polynom_rew = 32'b110;
867 
         4: polynom_rew = 32'b1100;
868 
         5: polynom_rew = 32'b10100;
869 
         6: polynom_rew = 32'b110000;
870 
         7: polynom_rew = 32'b1100000;
871 
         8: polynom_rew = 32'b10111000;
872 
         9: polynom_rew = 32'b100010000;
873 
        10: polynom_rew = 32'b1001000000;
874 
        11: polynom_rew = 32'b10100000000;
875 
        12: polynom_rew = 32'b100000101001;
876 
        13: polynom_rew = 32'b1000000001100;
877 
        14: polynom_rew = 32'b10000000010101;
878 
        15: polynom_rew = 32'b110000000000000;
879 
        16: polynom_rew = 32'b1101000000001000;
880 
        17: polynom_rew = 32'b10010000000000000;
881 
        18: polynom_rew = 32'b100000010000000000;
882 
        19: polynom_rew = 32'b1000000000000100011;
883 
        20: polynom_rew = 32'b10000010000000000000;
884 
        21: polynom_rew = 32'b101000000000000000000;
885 
        22: polynom_rew = 32'b1100000000000000000000;
886 
        23: polynom_rew = 32'b10000100000000000000000;
887 
        24: polynom_rew = 32'b111000010000000000000000;
888 
        25: polynom_rew = 32'b1001000000000000000000000;
889 
        26: polynom_rew = 32'b10000000000000000000100011;
890 
        27: polynom_rew = 32'b100000000000000000000010011;
891 
        28: polynom_rew = 32'b1100100000000000000000000000;
892 
        29: polynom_rew = 32'b10100000000000000000000000000;
893 
        30: polynom_rew = 32'b100000000000000000000000101001;
894 
        31: polynom_rew = 32'b1001000000000000000000000000000;
895 
        32: polynom_rew = 32'b10000000001000000000000000000011;
896 
        default: polynom_rew = 32'b0;
897 
        endcase
898 
        // rotate left
899 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
900 
        lfsr_fb_rew = qi[length];
901 
        for (i=length-1; i>=1; i=i-1) begin
902 
            if (polynom_rew[i])
903 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
904 
        end
905 
    end
906 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
907 
   assign q_next = rew ? q_next_rew : q_next_fw;
908 
   always @ (posedge clk or posedge rst)
909 
     if (rst)
910 
       qi <= {length{1'b0}};
911 
     else
912 
     if (cke)
913 
       qi <= q_next;
914 
    always @ (posedge clk or posedge rst)
915 
    if (rst)
916 
        level1 <= 1'b0;
917 
    else
918 
    if (cke)
919 
    if (q_next == level1_value)
920 
        level1 <= 1'b1;
921 
    else if (qi == level1_value & rew)
922 
        level1 <= 1'b0;
923 
endmodule
924 
//////////////////////////////////////////////////////////////////////
925 
////                                                              ////
926 
////  Versatile counter                                           ////
927 
////                                                              ////
928 
////  Description                                                 ////
929 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
930 
////  counter                                                     ////
931 
////                                                              ////
932 
////  To Do:                                                      ////
933 
////   - add LFSR with more taps                                  ////
934 
////                                                              ////
935 
////  Author(s):                                                  ////
936 
////      - Michael Unneback, unneback@opencores.org              ////
937 
////        ORSoC AB                                              ////
938 
////                                                              ////
939 
//////////////////////////////////////////////////////////////////////
940 
////                                                              ////
941 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
942 
////                                                              ////
943 
//// This source file may be used and distributed without         ////
944 
//// restriction provided that this copyright statement is not    ////
945 
//// removed from the file and that any derivative work contains  ////
946 
//// the original copyright notice and the associated disclaimer. ////
947 
////                                                              ////
948 
//// This source file is free software; you can redistribute it   ////
949 
//// and/or modify it under the terms of the GNU Lesser General   ////
950 
//// Public License as published by the Free Software Foundation; ////
951 
//// either version 2.1 of the License, or (at your option) any   ////
952 
//// later version.                                               ////
953 
////                                                              ////
954 
//// This source is distributed in the hope that it will be       ////
955 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
956 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
957 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
958 
//// details.                                                     ////
959 
////                                                              ////
960 
//// You should have received a copy of the GNU Lesser General    ////
961 
//// Public License along with this source; if not, download it   ////
962 
//// from http://www.opencores.org/lgpl.shtml                     ////
963 
////                                                              ////
964 
//////////////////////////////////////////////////////////////////////
965 
// GRAY counter
966 
module cnt_gray ( q, rst, clk);
967 
   parameter length = 4;
968 
   output reg [length:1] q;
969 
   input rst;
970 
   input clk;
971 
   parameter clear_value = 0;
972 
   parameter set_value = 1;
973 
   parameter wrap_value = 8;
974 
   parameter level1_value = 15;
975 
   reg  [length:1] qi;
976 
   wire [length:1] q_next;
977 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
978 
   always @ (posedge clk or posedge rst)
979 
     if (rst)
980 
       qi <= {length{1'b0}};
981 
     else
982 
       qi <= q_next;
983 
   always @ (posedge clk or posedge rst)
984 
     if (rst)
985 
       q <= {length{1'b0}};
986 
     else
987 
         q <= (q_next>>1) ^ q_next;
988 
endmodule
989 
//////////////////////////////////////////////////////////////////////
990 
////                                                              ////
991 
////  Versatile counter                                           ////
992 
////                                                              ////
993 
////  Description                                                 ////
994 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
995 
////  counter                                                     ////
996 
////                                                              ////
997 
////  To Do:                                                      ////
998 
////   - add LFSR with more taps                                  ////
999 
////                                                              ////
1000 
////  Author(s):                                                  ////
1001 
////      - Michael Unneback, unneback@opencores.org              ////
1002 
////        ORSoC AB                                              ////
1003 
////                                                              ////
1004 
//////////////////////////////////////////////////////////////////////
1005 
////                                                              ////
1006 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1007 
////                                                              ////
1008 
//// This source file may be used and distributed without         ////
1009 
//// restriction provided that this copyright statement is not    ////
1010 
//// removed from the file and that any derivative work contains  ////
1011 
//// the original copyright notice and the associated disclaimer. ////
1012 
////                                                              ////
1013 
//// This source file is free software; you can redistribute it   ////
1014 
//// and/or modify it under the terms of the GNU Lesser General   ////
1015 
//// Public License as published by the Free Software Foundation; ////
1016 
//// either version 2.1 of the License, or (at your option) any   ////
1017 
//// later version.                                               ////
1018 
////                                                              ////
1019 
//// This source is distributed in the hope that it will be       ////
1020 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1021 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1022 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1023 
//// details.                                                     ////
1024 
////                                                              ////
1025 
//// You should have received a copy of the GNU Lesser General    ////
1026 
//// Public License along with this source; if not, download it   ////
1027 
//// from http://www.opencores.org/lgpl.shtml                     ////
1028 
////                                                              ////
1029 
//////////////////////////////////////////////////////////////////////
1030 
// GRAY counter
1031 
module cnt_gray_ce ( cke, q, rst, clk);
1032 
   parameter length = 4;
1033 
   input cke;
1034 
   output reg [length:1] q;
1035 
   input rst;
1036 
   input clk;
1037 
   parameter clear_value = 0;
1038 
   parameter set_value = 1;
1039 
   parameter wrap_value = 8;
1040 
   parameter level1_value = 15;
1041 
   reg  [length:1] qi;
1042 
   wire [length:1] q_next;
1043 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1044 
   always @ (posedge clk or posedge rst)
1045 
     if (rst)
1046 
       qi <= {length{1'b0}};
1047 
     else
1048 
     if (cke)
1049 
       qi <= q_next;
1050 
   always @ (posedge clk or posedge rst)
1051 
     if (rst)
1052 
       q <= {length{1'b0}};
1053 
     else
1054 
       if (cke)
1055 
         q <= (q_next>>1) ^ q_next;
1056 
endmodule
1057 
//////////////////////////////////////////////////////////////////////
1058 
////                                                              ////
1059 
////  Versatile counter                                           ////
1060 
////                                                              ////
1061 
////  Description                                                 ////
1062 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1063 
////  counter                                                     ////
1064 
////                                                              ////
1065 
////  To Do:                                                      ////
1066 
////   - add LFSR with more taps                                  ////
1067 
////                                                              ////
1068 
////  Author(s):                                                  ////
1069 
////      - Michael Unneback, unneback@opencores.org              ////
1070 
////        ORSoC AB                                              ////
1071 
////                                                              ////
1072 
//////////////////////////////////////////////////////////////////////
1073 
////                                                              ////
1074 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1075 
////                                                              ////
1076 
//// This source file may be used and distributed without         ////
1077 
//// restriction provided that this copyright statement is not    ////
1078 
//// removed from the file and that any derivative work contains  ////
1079 
//// the original copyright notice and the associated disclaimer. ////
1080 
////                                                              ////
1081 
//// This source file is free software; you can redistribute it   ////
1082 
//// and/or modify it under the terms of the GNU Lesser General   ////
1083 
//// Public License as published by the Free Software Foundation; ////
1084 
//// either version 2.1 of the License, or (at your option) any   ////
1085 
//// later version.                                               ////
1086 
////                                                              ////
1087 
//// This source is distributed in the hope that it will be       ////
1088 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1089 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1090 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1091 
//// details.                                                     ////
1092 
////                                                              ////
1093 
//// You should have received a copy of the GNU Lesser General    ////
1094 
//// Public License along with this source; if not, download it   ////
1095 
//// from http://www.opencores.org/lgpl.shtml                     ////
1096 
////                                                              ////
1097 
//////////////////////////////////////////////////////////////////////
1098 
// GRAY counter
1099 
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1100 
   parameter length = 4;
1101 
   input cke;
1102 
   output reg [length:1] q;
1103 
   output [length:1] q_bin;
1104 
   input rst;
1105 
   input clk;
1106 
   parameter clear_value = 0;
1107 
   parameter set_value = 1;
1108 
   parameter wrap_value = 8;
1109 
   parameter level1_value = 15;
1110 
   reg  [length:1] qi;
1111 
   wire [length:1] q_next;
1112 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1113 
   always @ (posedge clk or posedge rst)
1114 
     if (rst)
1115 
       qi <= {length{1'b0}};
1116 
     else
1117 
     if (cke)
1118 
       qi <= q_next;
1119 
   always @ (posedge clk or posedge rst)
1120 
     if (rst)
1121 
       q <= {length{1'b0}};
1122 
     else
1123 
       if (cke)
1124 
         q <= (q_next>>1) ^ q_next;
1125 
   assign q_bin = qi;
1126 
endmodule
1127 
//////////////////////////////////////////////////////////////////////
1128 
////                                                              ////
1129 
////  Versatile library, counters                                 ////
1130 
////                                                              ////
1131 
////  Description                                                 ////
1132 
////  counters                                                    ////
1133 
////                                                              ////
1134 
////                                                              ////
1135 
////  To Do:                                                      ////
1136 
////   - add more counters                                        ////
1137 
////                                                              ////
1138 
////  Author(s):                                                  ////
1139 
////      - Michael Unneback, unneback@opencores.org              ////
1140 
////        ORSoC AB                                              ////
1141 
////                                                              ////
1142 
//////////////////////////////////////////////////////////////////////
1143 
////                                                              ////
1144 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1145 
////                                                              ////
1146 
//// This source file may be used and distributed without         ////
1147 
//// restriction provided that this copyright statement is not    ////
1148 
//// removed from the file and that any derivative work contains  ////
1149 
//// the original copyright notice and the associated disclaimer. ////
1150 
////                                                              ////
1151 
//// This source file is free software; you can redistribute it   ////
1152 
//// and/or modify it under the terms of the GNU Lesser General   ////
1153 
//// Public License as published by the Free Software Foundation; ////
1154 
//// either version 2.1 of the License, or (at your option) any   ////
1155 
//// later version.                                               ////
1156 
////                                                              ////
1157 
//// This source is distributed in the hope that it will be       ////
1158 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1159 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1160 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1161 
//// details.                                                     ////
1162 
////                                                              ////
1163 
//// You should have received a copy of the GNU Lesser General    ////
1164 
//// Public License along with this source; if not, download it   ////
1165 
//// from http://www.opencores.org/lgpl.shtml                     ////
1166 
////                                                              ////
1167 
//////////////////////////////////////////////////////////////////////
1168 
module cnt_shreg_wrap ( q, rst, clk);
1169 
   parameter length = 4;
1170 
   output reg [0:length-1] q;
1171 
   input rst;
1172 
   input clk;
1173 
    always @ (posedge clk or posedge rst)
1174 
    if (rst)
1175 
        q <= {1'b1,{length-1{1'b0}}};
1176 
    else
1177 
        q <= {q[length-1],q[0:length-2]};
1178 
endmodule
1179 
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1180 
   parameter length = 4;
1181 
   input cke;
1182 
   output reg [0:length-1] q;
1183 
   input rst;
1184 
   input clk;
1185 
    always @ (posedge clk or posedge rst)
1186 
    if (rst)
1187 
        q <= {1'b1,{length-1{1'b0}}};
1188 
    else
1189 
        if (cke)
1190 
            q <= {q[length-1],q[0:length-2]};
1191 
endmodule
1192 
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1193 
   parameter length = 4;
1194 
   input cke, clear;
1195 
   output reg [0:length-1] q;
1196 
   input rst;
1197 
   input clk;
1198 
    always @ (posedge clk or posedge rst)
1199 
    if (rst)
1200 
        q <= {1'b1,{length-1{1'b0}}};
1201 
    else
1202 
        if (cke)
1203 
            if (clear)
1204 
                q <= {1'b1,{length-1{1'b0}}};
1205 
            else
1206 
                q <= q >> 1;
1207 
endmodule
1208 
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1209 
   parameter length = 4;
1210 
   input cke, clear;
1211 
   output reg [0:length-1] q;
1212 
   input rst;
1213 
   input clk;
1214 
    always @ (posedge clk or posedge rst)
1215 
    if (rst)
1216 
        q <= {1'b1,{length-1{1'b0}}};
1217 
    else
1218 
        if (cke)
1219 
            if (clear)
1220 
                q <= {1'b1,{length-1{1'b0}}};
1221 
            else
1222 
            q <= {q[length-1],q[0:length-2]};
1223 
endmodule
1224 
//////////////////////////////////////////////////////////////////////
1225 
////                                                              ////
1226 
////  Versatile library, memories                                 ////
1227 
////                                                              ////
1228 
////  Description                                                 ////
1229 
////  memories                                                    ////
1230 
////                                                              ////
1231 
////                                                              ////
1232 
////  To Do:                                                      ////
1233 
////   - add more memory types                                    ////
1234 
////                                                              ////
1235 
////  Author(s):                                                  ////
1236 
////      - Michael Unneback, unneback@opencores.org              ////
1237 
////        ORSoC AB                                              ////
1238 
////                                                              ////
1239 
//////////////////////////////////////////////////////////////////////
1240 
////                                                              ////
1241 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1242 
////                                                              ////
1243 
//// This source file may be used and distributed without         ////
1244 
//// restriction provided that this copyright statement is not    ////
1245 
//// removed from the file and that any derivative work contains  ////
1246 
//// the original copyright notice and the associated disclaimer. ////
1247 
////                                                              ////
1248 
//// This source file is free software; you can redistribute it   ////
1249 
//// and/or modify it under the terms of the GNU Lesser General   ////
1250 
//// Public License as published by the Free Software Foundation; ////
1251 
//// either version 2.1 of the License, or (at your option) any   ////
1252 
//// later version.                                               ////
1253 
////                                                              ////
1254 
//// This source is distributed in the hope that it will be       ////
1255 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1256 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1257 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1258 
//// details.                                                     ////
1259 
////                                                              ////
1260 
//// You should have received a copy of the GNU Lesser General    ////
1261 
//// Public License along with this source; if not, download it   ////
1262 
//// from http://www.opencores.org/lgpl.shtml                     ////
1263 
////                                                              ////
1264 
//////////////////////////////////////////////////////////////////////
1265 
/// ROM
1266 7 unneback 
module vl_rom_init ( adr, q, clk);
1267 
   parameter data_width = 32;
1268 
   parameter addr_width = 8;
1269 
   input [(addr_width-1):0]       adr;
1270 
   output reg [(data_width-1):0] q;
1271 
   input                         clk;
1272 
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1273 
   parameter memory_file = "vl_rom.vmem";
1274 
   initial
1275 
     begin
1276 
        $readmemh(memory_file, rom);
1277 
     end
1278 
   always @ (posedge clk)
1279 
     q <= rom[adr];
1280 
endmodule
1281 
module vl_rom ( adr, q, clk);
1282 6 unneback 
parameter data_width = 32;
1283 
parameter addr_width = 4;
1284 
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1285 
    {32'h18000000},
1286 
    {32'hA8200000},
1287 
    {32'hA8200000},
1288 
    {32'hA8200000},
1289 
    {32'h44003000},
1290 
    {32'h15000000},
1291 
    {32'h15000000},
1292 
    {32'h15000000},
1293 
    {32'h15000000},
1294 
    {32'h15000000},
1295 
    {32'h15000000},
1296 
    {32'h15000000},
1297 
    {32'h15000000},
1298 
    {32'h15000000},
1299 
    {32'h15000000},
1300 
    {32'h15000000}};
1301 7 unneback 
input [addr_width-1:0] adr;
1302 6 unneback 
output reg [data_width-1:0] q;
1303 
input clk;
1304 
always @ (posedge clk)
1305 7 unneback 
    q <= data[adr];
1306 6 unneback 
endmodule
1307 
// Single port RAM
1308 
module vl_ram ( d, adr, we, q, clk);
1309 
   parameter data_width = 32;
1310 
   parameter addr_width = 8;
1311 
   input [(data_width-1):0]      d;
1312 
   input [(addr_width-1):0]       adr;
1313 
   input                         we;
1314 7 unneback 
   output reg [(data_width-1):0] q;
1315 6 unneback 
   input                         clk;
1316 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1317 7 unneback 
   parameter init = 0;
1318 
   parameter memory_file = "vl_ram.vmem";
1319 
   generate if (init) begin : init_mem
1320 
   initial
1321 
     begin
1322 
        $readmemh(memory_file, ram);
1323 
     end
1324 
   end
1325 
   endgenerate
1326 6 unneback 
   always @ (posedge clk)
1327 
   begin
1328 
   if (we)
1329 
     ram[adr] <= d;
1330 
   q <= ram[adr];
1331 
   end
1332 
endmodule
1333 7 unneback 
module vl_ram_be ( d, adr, be, we, q, clk);
1334 
   parameter data_width = 32;
1335 
   parameter addr_width = 8;
1336 
   input [(data_width-1):0]      d;
1337 
   input [(addr_width-1):0]       adr;
1338 
   input [(addr_width/4)-1:0]    be;
1339 
   input                         we;
1340 
   output reg [(data_width-1):0] q;
1341 
   input                         clk;
1342 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1343 
   parameter init = 0;
1344 
   parameter memory_file = "vl_ram.vmem";
1345 
   generate if (init) begin : init_mem
1346 
   initial
1347 
     begin
1348 
        $readmemh(memory_file, ram);
1349 
     end
1350 
   end
1351 
   endgenerate
1352 
   genvar i;
1353 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1354 
      always @ (posedge clk)
1355 
      if (we & be[i])
1356 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1357 
   end
1358 
   endgenerate
1359 
   always @ (posedge clk)
1360 
      q <= ram[adr];
1361 
endmodule
1362 6 unneback 
// Dual port RAM
1363 
// ACTEL FPGA should not use logic to handle rw collision
1364 7 unneback 
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1365 6 unneback 
   parameter data_width = 32;
1366 
   parameter addr_width = 8;
1367 
   input [(data_width-1):0]      d_a;
1368 
   input [(addr_width-1):0]       adr_a;
1369 
   input [(addr_width-1):0]       adr_b;
1370 
   input                         we_a;
1371 
   output [(data_width-1):0]      q_b;
1372 
   input                         clk_a, clk_b;
1373 
   reg [(addr_width-1):0]         adr_b_reg;
1374 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1375 7 unneback 
   parameter init = 0;
1376 
   parameter memory_file = "vl_ram.vmem";
1377 
   generate if (init) begin : init_mem
1378 
   initial
1379 
     begin
1380 
        $readmemh(memory_file, ram);
1381 
     end
1382 
   end
1383 
   endgenerate
1384 6 unneback 
   always @ (posedge clk_a)
1385 
   if (we_a)
1386 
     ram[adr_a] <= d_a;
1387 
   always @ (posedge clk_b)
1388 
   adr_b_reg <= adr_b;
1389 
   assign q_b = ram[adr_b_reg];
1390 
endmodule
1391 7 unneback 
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1392 6 unneback 
   parameter data_width = 32;
1393 
   parameter addr_width = 8;
1394 
   input [(data_width-1):0]      d_a;
1395 
   input [(addr_width-1):0]       adr_a;
1396 
   input [(addr_width-1):0]       adr_b;
1397 
   input                         we_a;
1398 
   output [(data_width-1):0]      q_b;
1399 
   output reg [(data_width-1):0] q_a;
1400 
   input                         clk_a, clk_b;
1401 
   reg [(data_width-1):0]         q_b;
1402 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1403 7 unneback 
   parameter init = 0;
1404 
   parameter memory_file = "vl_ram.vmem";
1405 
   generate if (init) begin : init_mem
1406 
   initial
1407 
     begin
1408 
        $readmemh(memory_file, ram);
1409 
     end
1410 
   end
1411 
   endgenerate
1412 6 unneback 
   always @ (posedge clk_a)
1413 
     begin
1414 
        q_a <= ram[adr_a];
1415 
        if (we_a)
1416 
             ram[adr_a] <= d_a;
1417 
     end
1418 
   always @ (posedge clk_b)
1419 
          q_b <= ram[adr_b];
1420 
endmodule
1421 7 unneback 
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1422 6 unneback 
   parameter data_width = 32;
1423 
   parameter addr_width = 8;
1424 
   input [(data_width-1):0]      d_a;
1425 
   input [(addr_width-1):0]       adr_a;
1426 
   input [(addr_width-1):0]       adr_b;
1427 
   input                         we_a;
1428 
   output [(data_width-1):0]      q_b;
1429 
   input [(data_width-1):0]       d_b;
1430 
   output reg [(data_width-1):0] q_a;
1431 
   input                         we_b;
1432 
   input                         clk_a, clk_b;
1433 
   reg [(data_width-1):0]         q_b;
1434 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1435 7 unneback 
   parameter init = 0;
1436 
   parameter memory_file = "vl_ram.vmem";
1437 
   generate if (init) begin : init_mem
1438 
   initial
1439 
     begin
1440 
        $readmemh(memory_file, ram);
1441 
     end
1442 
   end
1443 
   endgenerate
1444 6 unneback 
   always @ (posedge clk_a)
1445 
     begin
1446 
        q_a <= ram[adr_a];
1447 
        if (we_a)
1448 
             ram[adr_a] <= d_a;
1449 
     end
1450 
   always @ (posedge clk_b)
1451 
     begin
1452 
        q_b <= ram[adr_b];
1453 
        if (we_b)
1454 
          ram[adr_b] <= d_b;
1455 
     end
1456 
endmodule
1457 
// Content addresable memory, CAM
1458 
// FIFO
1459 
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1460 
   parameter ADDR_WIDTH = 4;
1461 
   parameter N = ADDR_WIDTH-1;
1462 
   parameter Q1 = 2'b00;
1463 
   parameter Q2 = 2'b01;
1464 
   parameter Q3 = 2'b11;
1465 
   parameter Q4 = 2'b10;
1466 
   parameter going_empty = 1'b0;
1467 
   parameter going_full  = 1'b1;
1468 
   input [N:0]  wptr, rptr;
1469 
   output reg   fifo_empty;
1470 
   output       fifo_full;
1471 
   input        wclk, rclk, rst;
1472 
   wire direction;
1473 
   reg  direction_set, direction_clr;
1474 
   wire async_empty, async_full;
1475 
   wire fifo_full2;
1476 
   reg  fifo_empty2;
1477 
   // direction_set
1478 
   always @ (wptr[N:N-1] or rptr[N:N-1])
1479 
     case ({wptr[N:N-1],rptr[N:N-1]})
1480 
       {Q1,Q2} : direction_set <= 1'b1;
1481 
       {Q2,Q3} : direction_set <= 1'b1;
1482 
       {Q3,Q4} : direction_set <= 1'b1;
1483 
       {Q4,Q1} : direction_set <= 1'b1;
1484 
       default : direction_set <= 1'b0;
1485 
     endcase
1486 
   // direction_clear
1487 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1488 
     if (rst)
1489 
       direction_clr <= 1'b1;
1490 
     else
1491 
       case ({wptr[N:N-1],rptr[N:N-1]})
1492 
         {Q2,Q1} : direction_clr <= 1'b1;
1493 
         {Q3,Q2} : direction_clr <= 1'b1;
1494 
         {Q4,Q3} : direction_clr <= 1'b1;
1495 
         {Q1,Q4} : direction_clr <= 1'b1;
1496 
         default : direction_clr <= 1'b0;
1497 
       endcase
1498 
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1499 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1500 
   assign async_full  = (wptr == rptr) && (direction==going_full);
1501 
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1502 
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1503 
/*
1504 
   always @ (posedge wclk or posedge rst or posedge async_full)
1505 
     if (rst)
1506 
       {fifo_full, fifo_full2} <= 2'b00;
1507 
     else if (async_full)
1508 
       {fifo_full, fifo_full2} <= 2'b11;
1509 
     else
1510 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1511 
*/
1512 
   always @ (posedge rclk or posedge async_empty)
1513 
     if (async_empty)
1514 
       {fifo_empty, fifo_empty2} <= 2'b11;
1515 
     else
1516 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
1517 
endmodule // async_comp
1518 
module vl_fifo_1r1w_async (
1519 
    d, wr, fifo_full, wr_clk, wr_rst,
1520 
    q, rd, fifo_empty, rd_clk, rd_rst
1521 
    );
1522 
parameter data_width = 18;
1523 
parameter addr_width = 4;
1524 
// write side
1525 
input  [data_width-1:0] d;
1526 
input                   wr;
1527 
output                  fifo_full;
1528 
input                   wr_clk;
1529 
input                   wr_rst;
1530 
// read side
1531 
output [data_width-1:0] q;
1532 
input                   rd;
1533 
output                  fifo_empty;
1534 
input                   rd_clk;
1535 
input                   rd_rst;
1536 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1537 
vl_fifo_1r1w_async (
1538 
    d, wr, fifo_full, wr_clk, wr_rst,
1539 
    q, rd, fifo_empty, rd_clk, rd_rst
1540 
    );
1541 7 unneback 
cnt_gray_ce_bin
1542 6 unneback 
    # ( .length(addr_width))
1543 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1544 7 unneback 
cnt_gray_ce_bin
1545 6 unneback 
    # (.length(addr_width))
1546 
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1547 7 unneback 
vl_dpram_1r1w
1548 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
1549 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1550 
vl_fifo_cmp_async
1551 
    # (.addr_width(addr_width))
1552 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1553 
endmodule
1554 
module vl_fifo_2r2w (
1555 
    // a side
1556 
    a_d, a_wr, a_fifo_full,
1557 
    a_q, a_rd, a_fifo_empty,
1558 
    a_clk, a_rst,
1559 
    // b side
1560 
    b_d, b_wr, b_fifo_full,
1561 
    b_q, b_rd, b_fifo_empty,
1562 
    b_clk, b_rst
1563 
    );
1564 
parameter data_width = 18;
1565 
parameter addr_width = 4;
1566 
// a side
1567 
input  [data_width-1:0] a_d;
1568 
input                   a_wr;
1569 
output                  a_fifo_full;
1570 
output [data_width-1:0] a_q;
1571 
input                   a_rd;
1572 
output                  a_fifo_empty;
1573 
input                   a_clk;
1574 
input                   a_rst;
1575 
// b side
1576 
input  [data_width-1:0] b_d;
1577 
input                   b_wr;
1578 
output                  b_fifo_full;
1579 
output [data_width-1:0] b_q;
1580 
input                   b_rd;
1581 
output                  b_fifo_empty;
1582 
input                   b_clk;
1583 
input                   b_rst;
1584 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1585 
vl_fifo_1r1w_async_a (
1586 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1587 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1588 
    );
1589 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1590 
vl_fifo_1r1w_async_b (
1591 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1592 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1593 
    );
1594 
endmodule
1595 
module vl_fifo_2r2w_simplex (
1596 
    // a side
1597 
    a_d, a_wr, a_fifo_full,
1598 
    a_q, a_rd, a_fifo_empty,
1599 
    a_clk, a_rst,
1600 
    // b side
1601 
    b_d, b_wr, b_fifo_full,
1602 
    b_q, b_rd, b_fifo_empty,
1603 
    b_clk, b_rst
1604 
    );
1605 
parameter data_width = 18;
1606 
parameter addr_width = 4;
1607 
// a side
1608 
input  [data_width-1:0] a_d;
1609 
input                   a_wr;
1610 
output                  a_fifo_full;
1611 
output [data_width-1:0] a_q;
1612 
input                   a_rd;
1613 
output                  a_fifo_empty;
1614 
input                   a_clk;
1615 
input                   a_rst;
1616 
// b side
1617 
input  [data_width-1:0] b_d;
1618 
input                   b_wr;
1619 
output                  b_fifo_full;
1620 
output [data_width-1:0] b_q;
1621 
input                   b_rd;
1622 
output                  b_fifo_empty;
1623 
input                   b_clk;
1624 
input                   b_rst;
1625 
// adr_gen
1626 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1627 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1628 
// dpram
1629 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1630 7 unneback 
cnt_gray_ce_bin
1631 6 unneback 
    # ( .length(addr_width))
1632 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1633 7 unneback 
cnt_gray_ce_bin
1634 6 unneback 
    # (.length(addr_width))
1635 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1636 7 unneback 
cnt_gray_ce_bin
1637 6 unneback 
    # ( .length(addr_width))
1638 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1639 7 unneback 
cnt_gray_ce_bin
1640 6 unneback 
    # (.length(addr_width))
1641 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1642 
// mux read or write adr to DPRAM
1643 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1644 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1645 7 unneback 
vl_dp_ram_2r2w
1646 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
1647 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1648 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1649 
vl_fifo_async_cmp
1650 
    # (.addr_width(addr_width))
1651 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1652 7 unneback 
vl_fifo_async_cmp
1653 6 unneback 
    # (.addr_width(addr_width))
1654 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1655 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.