OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 91

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 60 unneback
// default SYN_KEEP definition
2 6 unneback
//////////////////////////////////////////////////////////////////////
3
////                                                              ////
4
////  Versatile library, clock and reset                          ////
5
////                                                              ////
6
////  Description                                                 ////
7
////  Logic related to clock and reset                            ////
8
////                                                              ////
9
////                                                              ////
10
////  To Do:                                                      ////
11
////   - add more different registers                             ////
12
////                                                              ////
13
////  Author(s):                                                  ////
14
////      - Michael Unneback, unneback@opencores.org              ////
15
////        ORSoC AB                                              ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43 21 unneback
//altera
44 33 unneback
module vl_gbuf ( i, o);
45
input i;
46
output o;
47
assign o = i;
48
endmodule
49 6 unneback
 // ALTERA
50
 //ACTEL
51
// sync reset
52 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
53 6 unneback
// output active high global reset sync with two DFFs 
54
`timescale 1 ns/100 ps
55
module vl_sync_rst ( rst_n_i, rst_o, clk);
56
input rst_n_i, clk;
57
output rst_o;
58 18 unneback
reg [1:0] tmp;
59 6 unneback
always @ (posedge clk or negedge rst_n_i)
60
if (!rst_n_i)
61 17 unneback
        tmp <= 2'b11;
62 6 unneback
else
63 33 unneback
        tmp <= {1'b0,tmp[1]};
64 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
65 6 unneback
endmodule
66
// vl_pll
67 32 unneback
///////////////////////////////////////////////////////////////////////////////
68
`timescale 1 ps/1 ps
69
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
70
parameter index = 0;
71
parameter number_of_clk = 1;
72
parameter period_time_0 = 20000;
73
parameter period_time_1 = 20000;
74
parameter period_time_2 = 20000;
75
parameter period_time_3 = 20000;
76
parameter period_time_4 = 20000;
77
parameter lock_delay = 2000000;
78
input clk_i, rst_n_i;
79
output lock;
80
output reg [0:number_of_clk-1] clk_o;
81
output [0:number_of_clk-1] rst_o;
82 33 unneback
`ifdef SIM_PLL
83 32 unneback
always
84
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
85
generate if (number_of_clk > 1)
86
always
87
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
88
endgenerate
89
generate if (number_of_clk > 2)
90
always
91
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
92
endgenerate
93 33 unneback
generate if (number_of_clk > 3)
94 32 unneback
always
95
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
96
endgenerate
97 33 unneback
generate if (number_of_clk > 4)
98 32 unneback
always
99
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
100
endgenerate
101
genvar i;
102
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
103
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
104
end
105
endgenerate
106 33 unneback
//assign #lock_delay lock = rst_n_i;
107
assign lock = rst_n_i;
108 32 unneback
endmodule
109 33 unneback
`else
110
`ifdef VL_PLL0
111
`ifdef VL_PLL0_CLK1
112
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
113
`endif
114
`ifdef VL_PLL0_CLK2
115
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
116
`endif
117
`ifdef VL_PLL0_CLK3
118
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
119
`endif
120
`ifdef VL_PLL0_CLK4
121
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
122
`endif
123
`ifdef VL_PLL0_CLK5
124
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
125
`endif
126
`endif
127
`ifdef VL_PLL1
128
`ifdef VL_PLL1_CLK1
129
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
130
`endif
131
`ifdef VL_PLL1_CLK2
132
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
133
`endif
134
`ifdef VL_PLL1_CLK3
135
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
136
`endif
137
`ifdef VL_PLL1_CLK4
138
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
139
`endif
140
`ifdef VL_PLL1_CLK5
141
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
142
`endif
143
`endif
144
`ifdef VL_PLL2
145
`ifdef VL_PLL2_CLK1
146
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
147
`endif
148
`ifdef VL_PLL2_CLK2
149
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
150
`endif
151
`ifdef VL_PLL2_CLK3
152
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
153
`endif
154
`ifdef VL_PLL2_CLK4
155
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
156
`endif
157
`ifdef VL_PLL2_CLK5
158
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
159
`endif
160
`endif
161
`ifdef VL_PLL3
162
`ifdef VL_PLL3_CLK1
163
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
164
`endif
165
`ifdef VL_PLL3_CLK2
166
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
167
`endif
168
`ifdef VL_PLL3_CLK3
169
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
170
`endif
171
`ifdef VL_PLL3_CLK4
172
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
173
`endif
174
`ifdef VL_PLL3_CLK5
175
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
176
`endif
177
`endif
178 32 unneback
genvar i;
179
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
180 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
181 32 unneback
end
182
endgenerate
183
endmodule
184 33 unneback
`endif
185 32 unneback
///////////////////////////////////////////////////////////////////////////////
186 6 unneback
 //altera
187
 //actel
188
//////////////////////////////////////////////////////////////////////
189
////                                                              ////
190
////  Versatile library, registers                                ////
191
////                                                              ////
192
////  Description                                                 ////
193
////  Different type of registers                                 ////
194
////                                                              ////
195
////                                                              ////
196
////  To Do:                                                      ////
197
////   - add more different registers                             ////
198
////                                                              ////
199
////  Author(s):                                                  ////
200
////      - Michael Unneback, unneback@opencores.org              ////
201
////        ORSoC AB                                              ////
202
////                                                              ////
203
//////////////////////////////////////////////////////////////////////
204
////                                                              ////
205
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
206
////                                                              ////
207
//// This source file may be used and distributed without         ////
208
//// restriction provided that this copyright statement is not    ////
209
//// removed from the file and that any derivative work contains  ////
210
//// the original copyright notice and the associated disclaimer. ////
211
////                                                              ////
212
//// This source file is free software; you can redistribute it   ////
213
//// and/or modify it under the terms of the GNU Lesser General   ////
214
//// Public License as published by the Free Software Foundation; ////
215
//// either version 2.1 of the License, or (at your option) any   ////
216
//// later version.                                               ////
217
////                                                              ////
218
//// This source is distributed in the hope that it will be       ////
219
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
220
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
221
//// PURPOSE.  See the GNU Lesser General Public License for more ////
222
//// details.                                                     ////
223
////                                                              ////
224
//// You should have received a copy of the GNU Lesser General    ////
225
//// Public License along with this source; if not, download it   ////
226
//// from http://www.opencores.org/lgpl.shtml                     ////
227
////                                                              ////
228
//////////////////////////////////////////////////////////////////////
229 18 unneback
module vl_dff ( d, q, clk, rst);
230 6 unneback
        parameter width = 1;
231
        parameter reset_value = 0;
232
        input [width-1:0] d;
233
        input clk, rst;
234
        output reg [width-1:0] q;
235
        always @ (posedge clk or posedge rst)
236
        if (rst)
237
                q <= reset_value;
238
        else
239
                q <= d;
240
endmodule
241 18 unneback
module vl_dff_array ( d, q, clk, rst);
242 6 unneback
        parameter width = 1;
243
        parameter depth = 2;
244
        parameter reset_value = 1'b0;
245
        input [width-1:0] d;
246
        input clk, rst;
247
        output [width-1:0] q;
248
        reg  [0:depth-1] q_tmp [width-1:0];
249
        integer i;
250
        always @ (posedge clk or posedge rst)
251
        if (rst) begin
252
            for (i=0;i<depth;i=i+1)
253
                q_tmp[i] <= {width{reset_value}};
254
        end else begin
255
            q_tmp[0] <= d;
256
            for (i=1;i<depth;i=i+1)
257
                q_tmp[i] <= q_tmp[i-1];
258
        end
259
    assign q = q_tmp[depth-1];
260
endmodule
261 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
262 6 unneback
        parameter width = 1;
263
        parameter reset_value = 0;
264
        input [width-1:0] d;
265
        input ce, clk, rst;
266
        output reg [width-1:0] q;
267
        always @ (posedge clk or posedge rst)
268
        if (rst)
269
                q <= reset_value;
270
        else
271
                if (ce)
272
                        q <= d;
273
endmodule
274 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
275 8 unneback
        parameter width = 1;
276
        parameter reset_value = 0;
277
        input [width-1:0] d;
278 10 unneback
        input ce, clear, clk, rst;
279 8 unneback
        output reg [width-1:0] q;
280
        always @ (posedge clk or posedge rst)
281
        if (rst)
282
            q <= reset_value;
283
        else
284
            if (ce)
285
                if (clear)
286
                    q <= {width{1'b0}};
287
                else
288
                    q <= d;
289
endmodule
290 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
291
        parameter width = 1;
292
        parameter reset_value = 0;
293
        input [width-1:0] d;
294
        input ce, set, clk, rst;
295
        output reg [width-1:0] q;
296
        always @ (posedge clk or posedge rst)
297
        if (rst)
298
            q <= reset_value;
299
        else
300
            if (ce)
301
                if (set)
302
                    q <= {width{1'b1}};
303
                else
304
                    q <= d;
305
endmodule
306 29 unneback
module vl_spr ( sp, r, q, clk, rst);
307 64 unneback
        //parameter width = 1;
308
        parameter reset_value = 1'b0;
309 29 unneback
        input sp, r;
310
        output reg q;
311
        input clk, rst;
312
        always @ (posedge clk or posedge rst)
313
        if (rst)
314
            q <= reset_value;
315
        else
316
            if (sp)
317
                q <= 1'b1;
318
            else if (r)
319
                q <= 1'b0;
320
endmodule
321
module vl_srp ( s, rp, q, clk, rst);
322
        parameter width = 1;
323
        parameter reset_value = 0;
324
        input s, rp;
325
        output reg q;
326
        input clk, rst;
327
        always @ (posedge clk or posedge rst)
328
        if (rst)
329
            q <= reset_value;
330
        else
331
            if (rp)
332
                q <= 1'b0;
333
            else if (s)
334
                q <= 1'b1;
335
endmodule
336 6 unneback
// megafunction wizard: %LPM_FF%
337
// GENERATION: STANDARD
338
// VERSION: WM1.0
339
// MODULE: lpm_ff 
340
// ============================================================
341
// File Name: dff_sr.v
342
// Megafunction Name(s):
343
//                      lpm_ff
344
//
345
// Simulation Library Files(s):
346
//                      lpm
347
// ============================================================
348
// ************************************************************
349
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
350
//
351
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
352
// ************************************************************
353
//Copyright (C) 1991-2010 Altera Corporation
354
//Your use of Altera Corporation's design tools, logic functions 
355
//and other software and tools, and its AMPP partner logic 
356
//functions, and any output files from any of the foregoing 
357
//(including device programming or simulation files), and any 
358
//associated documentation or information are expressly subject 
359
//to the terms and conditions of the Altera Program License 
360
//Subscription Agreement, Altera MegaCore Function License 
361
//Agreement, or other applicable license agreement, including, 
362
//without limitation, that your use is for the sole purpose of 
363
//programming logic devices manufactured by Altera and sold by 
364
//Altera or its authorized distributors.  Please refer to the 
365
//applicable agreement for further details.
366
// synopsys translate_off
367
`timescale 1 ps / 1 ps
368
// synopsys translate_on
369 18 unneback
module vl_dff_sr (
370 6 unneback
        aclr,
371
        aset,
372
        clock,
373
        data,
374
        q);
375
        input     aclr;
376
        input     aset;
377
        input     clock;
378
        input     data;
379
        output    q;
380
        wire [0:0] sub_wire0;
381
        wire [0:0] sub_wire1 = sub_wire0[0:0];
382
        wire  q = sub_wire1;
383
        wire  sub_wire2 = data;
384
        wire  sub_wire3 = sub_wire2;
385
        lpm_ff  lpm_ff_component (
386
                                .aclr (aclr),
387
                                .clock (clock),
388
                                .data (sub_wire3),
389
                                .aset (aset),
390
                                .q (sub_wire0)
391
                                // synopsys translate_off
392
                                ,
393
                                .aload (),
394
                                .enable (),
395
                                .sclr (),
396
                                .sload (),
397
                                .sset ()
398
                                // synopsys translate_on
399
                                );
400
        defparam
401
                lpm_ff_component.lpm_fftype = "DFF",
402
                lpm_ff_component.lpm_type = "LPM_FF",
403
                lpm_ff_component.lpm_width = 1;
404
endmodule
405
// ============================================================
406
// CNX file retrieval info
407
// ============================================================
408
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
409
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
410
// Retrieval info: PRIVATE: ASET NUMERIC "1"
411
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
412
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
413
// Retrieval info: PRIVATE: DFF NUMERIC "1"
414
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
415
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
416
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
417
// Retrieval info: PRIVATE: SSET NUMERIC "0"
418
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
419
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
420
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
421
// Retrieval info: PRIVATE: nBit NUMERIC "1"
422
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
423
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
424
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
425
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
426
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
427
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
428
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
429
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
430
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
431
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
432
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
433
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
434
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
435
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
436
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
437
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
442
// Retrieval info: LIB_FILE: lpm
443
// LATCH
444
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
445 18 unneback
module vl_latch ( d, le, q, clk);
446 6 unneback
input d, le;
447
output q;
448
input clk;
449
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
450
endmodule
451 18 unneback
module vl_shreg ( d, q, clk, rst);
452 17 unneback
parameter depth = 10;
453
input d;
454
output q;
455
input clk, rst;
456
reg [1:depth] dffs;
457
always @ (posedge clk or posedge rst)
458
if (rst)
459
    dffs <= {depth{1'b0}};
460
else
461
    dffs <= {d,dffs[1:depth-1]};
462
assign q = dffs[depth];
463
endmodule
464 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
465 17 unneback
parameter depth = 10;
466
input d, ce;
467
output q;
468
input clk, rst;
469
reg [1:depth] dffs;
470
always @ (posedge clk or posedge rst)
471
if (rst)
472
    dffs <= {depth{1'b0}};
473
else
474
    if (ce)
475
        dffs <= {d,dffs[1:depth-1]};
476
assign q = dffs[depth];
477
endmodule
478 18 unneback
module vl_delay ( d, q, clk, rst);
479 15 unneback
parameter depth = 10;
480
input d;
481
output q;
482
input clk, rst;
483
reg [1:depth] dffs;
484
always @ (posedge clk or posedge rst)
485
if (rst)
486
    dffs <= {depth{1'b0}};
487
else
488
    dffs <= {d,dffs[1:depth-1]};
489
assign q = dffs[depth];
490
endmodule
491 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
492 17 unneback
parameter depth = 10;
493
input d;
494
output q, emptyflag;
495
input clk, rst;
496
reg [1:depth] dffs;
497
always @ (posedge clk or posedge rst)
498
if (rst)
499
    dffs <= {depth{1'b0}};
500
else
501
    dffs <= {d,dffs[1:depth-1]};
502
assign q = dffs[depth];
503
assign emptyflag = !(|dffs);
504
endmodule
505 6 unneback
//////////////////////////////////////////////////////////////////////
506
////                                                              ////
507 18 unneback
////  Logic functions                                             ////
508
////                                                              ////
509
////  Description                                                 ////
510
////  Logic functions such as multiplexers                        ////
511
////                                                              ////
512
////                                                              ////
513
////  To Do:                                                      ////
514
////   -                                                          ////
515
////                                                              ////
516
////  Author(s):                                                  ////
517
////      - Michael Unneback, unneback@opencores.org              ////
518
////        ORSoC AB                                              ////
519
////                                                              ////
520
//////////////////////////////////////////////////////////////////////
521
////                                                              ////
522
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
523
////                                                              ////
524
//// This source file may be used and distributed without         ////
525
//// restriction provided that this copyright statement is not    ////
526
//// removed from the file and that any derivative work contains  ////
527
//// the original copyright notice and the associated disclaimer. ////
528
////                                                              ////
529
//// This source file is free software; you can redistribute it   ////
530
//// and/or modify it under the terms of the GNU Lesser General   ////
531
//// Public License as published by the Free Software Foundation; ////
532
//// either version 2.1 of the License, or (at your option) any   ////
533
//// later version.                                               ////
534
////                                                              ////
535
//// This source is distributed in the hope that it will be       ////
536
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
537
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
538
//// PURPOSE.  See the GNU Lesser General Public License for more ////
539
//// details.                                                     ////
540
////                                                              ////
541
//// You should have received a copy of the GNU Lesser General    ////
542
//// Public License along with this source; if not, download it   ////
543
//// from http://www.opencores.org/lgpl.shtml                     ////
544
////                                                              ////
545
//////////////////////////////////////////////////////////////////////
546 36 unneback
module vl_mux_andor ( a, sel, dout);
547
parameter width = 32;
548
parameter nr_of_ports = 4;
549
input [nr_of_ports*width-1:0] a;
550
input [nr_of_ports-1:0] sel;
551
output reg [width-1:0] dout;
552 38 unneback
integer i,j;
553 36 unneback
always @ (a, sel)
554
begin
555
    dout = a[width-1:0] & {width{sel[0]}};
556 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
557
        for (j=0;j<width;j=j+1)
558
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
559 36 unneback
end
560
endmodule
561 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
562
parameter width = 32;
563 35 unneback
localparam nr_of_ports = 2;
564 34 unneback
input [width-1:0] a1, a0;
565
input [nr_of_ports-1:0] sel;
566
output [width-1:0] dout;
567 36 unneback
vl_mux_andor
568 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
569 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
570 34 unneback
endmodule
571
module vl_mux3_andor ( a2, a1, a0, sel, dout);
572
parameter width = 32;
573 35 unneback
localparam nr_of_ports = 3;
574 34 unneback
input [width-1:0] a2, a1, a0;
575
input [nr_of_ports-1:0] sel;
576
output [width-1:0] dout;
577 36 unneback
vl_mux_andor
578 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
579 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
580 34 unneback
endmodule
581 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
582
parameter width = 32;
583 35 unneback
localparam nr_of_ports = 4;
584 18 unneback
input [width-1:0] a3, a2, a1, a0;
585
input [nr_of_ports-1:0] sel;
586 22 unneback
output [width-1:0] dout;
587 36 unneback
vl_mux_andor
588 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
589 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
590 18 unneback
endmodule
591
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
592
parameter width = 32;
593 35 unneback
localparam nr_of_ports = 5;
594 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
595
input [nr_of_ports-1:0] sel;
596 22 unneback
output [width-1:0] dout;
597 36 unneback
vl_mux_andor
598 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
599 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
600 18 unneback
endmodule
601
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
602
parameter width = 32;
603 35 unneback
localparam nr_of_ports = 6;
604 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
605
input [nr_of_ports-1:0] sel;
606 22 unneback
output [width-1:0] dout;
607 36 unneback
vl_mux_andor
608 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
609 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
610 18 unneback
endmodule
611 43 unneback
module vl_parity_generate (data, parity);
612
parameter word_size = 32;
613
parameter chunk_size = 8;
614
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
615
input [word_size-1:0] data;
616
output reg [word_size/chunk_size-1:0] parity;
617
integer i,j;
618
always @ (data)
619
for (i=0;i<word_size/chunk_size;i=i+1) begin
620
    parity[i] = parity_type;
621
    for (j=0;j<chunk_size;j=j+1) begin
622 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
623 43 unneback
    end
624
end
625
endmodule
626
module vl_parity_check( data, parity, parity_error);
627
parameter word_size = 32;
628
parameter chunk_size = 8;
629
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
630
input [word_size-1:0] data;
631
input [word_size/chunk_size-1:0] parity;
632
output parity_error;
633 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
634 43 unneback
integer i,j;
635
always @ (data or parity)
636
for (i=0;i<word_size/chunk_size;i=i+1) begin
637
    error_flag[i] = parity[i] ^ parity_type;
638
    for (j=0;j<chunk_size;j=j+1) begin
639 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
640 43 unneback
    end
641
end
642
assign parity_error = |error_flag;
643
endmodule
644 18 unneback
//////////////////////////////////////////////////////////////////////
645
////                                                              ////
646 44 unneback
////  IO functions                                                ////
647
////                                                              ////
648
////  Description                                                 ////
649
////  IO functions such as IOB flip-flops                         ////
650
////                                                              ////
651
////                                                              ////
652
////  To Do:                                                      ////
653
////   -                                                          ////
654
////                                                              ////
655
////  Author(s):                                                  ////
656
////      - Michael Unneback, unneback@opencores.org              ////
657
////        ORSoC AB                                              ////
658
////                                                              ////
659
//////////////////////////////////////////////////////////////////////
660
////                                                              ////
661
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
662
////                                                              ////
663
//// This source file may be used and distributed without         ////
664
//// restriction provided that this copyright statement is not    ////
665
//// removed from the file and that any derivative work contains  ////
666
//// the original copyright notice and the associated disclaimer. ////
667
////                                                              ////
668
//// This source file is free software; you can redistribute it   ////
669
//// and/or modify it under the terms of the GNU Lesser General   ////
670
//// Public License as published by the Free Software Foundation; ////
671
//// either version 2.1 of the License, or (at your option) any   ////
672
//// later version.                                               ////
673
////                                                              ////
674
//// This source is distributed in the hope that it will be       ////
675
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
676
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
677
//// PURPOSE.  See the GNU Lesser General Public License for more ////
678
//// details.                                                     ////
679
////                                                              ////
680
//// You should have received a copy of the GNU Lesser General    ////
681
//// Public License along with this source; if not, download it   ////
682
//// from http://www.opencores.org/lgpl.shtml                     ////
683
////                                                              ////
684
//////////////////////////////////////////////////////////////////////
685 45 unneback
`timescale 1ns/1ns
686 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
687
parameter width = 1;
688 45 unneback
parameter reset_value = {width{1'b0}};
689
input  [width-1:0]  d_i;
690 44 unneback
output [width-1:0] o_pad;
691
input clk, rst;
692 60 unneback
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
693 45 unneback
reg  [width-1:0] o_pad_int;
694 44 unneback
assign d_i_int = d_i;
695
genvar i;
696 45 unneback
generate
697 44 unneback
for (i=0;i<width;i=i+1) begin
698
    always @ (posedge clk or posedge rst)
699
    if (rst)
700 45 unneback
        o_pad_int[i] <= reset_value[i];
701 44 unneback
    else
702 45 unneback
        o_pad_int[i] <= d_i_int[i];
703
    assign #1 o_pad[i] = o_pad_int[i];
704 44 unneback
end
705
endgenerate
706
endmodule
707 45 unneback
`timescale 1ns/1ns
708 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
709
parameter width = 1;
710
input  [width-1:0] d_o;
711
output reg [width-1:0] d_i;
712
input oe;
713
inout [width-1:0] io_pad;
714
input clk, rst;
715 60 unneback
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
716 44 unneback
reg [width-1:0] oe_q;
717
reg [width-1:0] d_o_q;
718
assign oe_d = {width{oe}};
719
genvar i;
720
generate
721
for (i=0;i<width;i=i+1) begin
722
    always @ (posedge clk or posedge rst)
723
    if (rst)
724
        oe_q[i] <= 1'b0;
725
    else
726
        oe_q[i] <= oe_d[i];
727
    always @ (posedge clk or posedge rst)
728
    if (rst)
729
        d_o_q[i] <= 1'b0;
730
    else
731
        d_o_q[i] <= d_o[i];
732
    always @ (posedge clk or posedge rst)
733
    if (rst)
734
        d_i[i] <= 1'b0;
735
    else
736
        d_i[i] <= io_pad[i];
737 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
738 44 unneback
end
739
endgenerate
740
endmodule
741
//////////////////////////////////////////////////////////////////////
742
////                                                              ////
743 6 unneback
////  Versatile counter                                           ////
744
////                                                              ////
745
////  Description                                                 ////
746
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
747
////  counter                                                     ////
748
////                                                              ////
749
////  To Do:                                                      ////
750
////   - add LFSR with more taps                                  ////
751
////                                                              ////
752
////  Author(s):                                                  ////
753
////      - Michael Unneback, unneback@opencores.org              ////
754
////        ORSoC AB                                              ////
755
////                                                              ////
756
//////////////////////////////////////////////////////////////////////
757
////                                                              ////
758
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
759
////                                                              ////
760
//// This source file may be used and distributed without         ////
761
//// restriction provided that this copyright statement is not    ////
762
//// removed from the file and that any derivative work contains  ////
763
//// the original copyright notice and the associated disclaimer. ////
764
////                                                              ////
765
//// This source file is free software; you can redistribute it   ////
766
//// and/or modify it under the terms of the GNU Lesser General   ////
767
//// Public License as published by the Free Software Foundation; ////
768
//// either version 2.1 of the License, or (at your option) any   ////
769
//// later version.                                               ////
770
////                                                              ////
771
//// This source is distributed in the hope that it will be       ////
772
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
773
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
774
//// PURPOSE.  See the GNU Lesser General Public License for more ////
775
//// details.                                                     ////
776
////                                                              ////
777
//// You should have received a copy of the GNU Lesser General    ////
778
//// Public License along with this source; if not, download it   ////
779
//// from http://www.opencores.org/lgpl.shtml                     ////
780
////                                                              ////
781
//////////////////////////////////////////////////////////////////////
782
// binary counter
783 40 unneback
module vl_cnt_bin_ce (
784
 cke, q, rst, clk);
785 22 unneback
   parameter length = 4;
786 6 unneback
   input cke;
787
   output [length:1] q;
788
   input rst;
789
   input clk;
790
   parameter clear_value = 0;
791
   parameter set_value = 1;
792
   parameter wrap_value = 0;
793
   parameter level1_value = 15;
794
   reg  [length:1] qi;
795
   wire [length:1] q_next;
796
   assign q_next = qi + {{length-1{1'b0}},1'b1};
797
   always @ (posedge clk or posedge rst)
798
     if (rst)
799
       qi <= {length{1'b0}};
800
     else
801
     if (cke)
802
       qi <= q_next;
803
   assign q = qi;
804
endmodule
805
//////////////////////////////////////////////////////////////////////
806
////                                                              ////
807
////  Versatile counter                                           ////
808
////                                                              ////
809
////  Description                                                 ////
810
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
811
////  counter                                                     ////
812
////                                                              ////
813
////  To Do:                                                      ////
814
////   - add LFSR with more taps                                  ////
815
////                                                              ////
816
////  Author(s):                                                  ////
817
////      - Michael Unneback, unneback@opencores.org              ////
818
////        ORSoC AB                                              ////
819
////                                                              ////
820
//////////////////////////////////////////////////////////////////////
821
////                                                              ////
822
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
823
////                                                              ////
824
//// This source file may be used and distributed without         ////
825
//// restriction provided that this copyright statement is not    ////
826
//// removed from the file and that any derivative work contains  ////
827
//// the original copyright notice and the associated disclaimer. ////
828
////                                                              ////
829
//// This source file is free software; you can redistribute it   ////
830
//// and/or modify it under the terms of the GNU Lesser General   ////
831
//// Public License as published by the Free Software Foundation; ////
832
//// either version 2.1 of the License, or (at your option) any   ////
833
//// later version.                                               ////
834
////                                                              ////
835
//// This source is distributed in the hope that it will be       ////
836
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
837
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
838
//// PURPOSE.  See the GNU Lesser General Public License for more ////
839
//// details.                                                     ////
840
////                                                              ////
841
//// You should have received a copy of the GNU Lesser General    ////
842
//// Public License along with this source; if not, download it   ////
843
//// from http://www.opencores.org/lgpl.shtml                     ////
844
////                                                              ////
845
//////////////////////////////////////////////////////////////////////
846
// binary counter
847 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
848
 cke, rew, zq, level1, rst, clk);
849 6 unneback
   parameter length = 4;
850
   input cke;
851
   input rew;
852 25 unneback
   output reg zq;
853
   output reg level1;
854
   input rst;
855
   input clk;
856
   parameter clear_value = 0;
857
   parameter set_value = 1;
858
   parameter wrap_value = 1;
859
   parameter level1_value = 15;
860 29 unneback
   wire clear;
861 30 unneback
   assign clear = 1'b0;
862 25 unneback
   reg  [length:1] qi;
863
   wire  [length:1] q_next, q_next_fw, q_next_rew;
864
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
865
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
866
   assign q_next = rew ? q_next_rew : q_next_fw;
867
   always @ (posedge clk or posedge rst)
868
     if (rst)
869
       qi <= {length{1'b0}};
870
     else
871
     if (cke)
872
       qi <= q_next;
873
   always @ (posedge clk or posedge rst)
874
     if (rst)
875
       zq <= 1'b1;
876
     else
877
     if (cke)
878
       zq <= q_next == {length{1'b0}};
879
    always @ (posedge clk or posedge rst)
880
    if (rst)
881
        level1 <= 1'b0;
882
    else
883
    if (cke)
884 29 unneback
    if (clear)
885
        level1 <= 1'b0;
886
    else if (q_next == level1_value)
887 25 unneback
        level1 <= 1'b1;
888
    else if (qi == level1_value & rew)
889
        level1 <= 1'b0;
890
endmodule
891
//////////////////////////////////////////////////////////////////////
892
////                                                              ////
893
////  Versatile counter                                           ////
894
////                                                              ////
895
////  Description                                                 ////
896
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
897
////  counter                                                     ////
898
////                                                              ////
899
////  To Do:                                                      ////
900
////   - add LFSR with more taps                                  ////
901
////                                                              ////
902
////  Author(s):                                                  ////
903
////      - Michael Unneback, unneback@opencores.org              ////
904
////        ORSoC AB                                              ////
905
////                                                              ////
906
//////////////////////////////////////////////////////////////////////
907
////                                                              ////
908
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
909
////                                                              ////
910
//// This source file may be used and distributed without         ////
911
//// restriction provided that this copyright statement is not    ////
912
//// removed from the file and that any derivative work contains  ////
913
//// the original copyright notice and the associated disclaimer. ////
914
////                                                              ////
915
//// This source file is free software; you can redistribute it   ////
916
//// and/or modify it under the terms of the GNU Lesser General   ////
917
//// Public License as published by the Free Software Foundation; ////
918
//// either version 2.1 of the License, or (at your option) any   ////
919
//// later version.                                               ////
920
////                                                              ////
921
//// This source is distributed in the hope that it will be       ////
922
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
923
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
924
//// PURPOSE.  See the GNU Lesser General Public License for more ////
925
//// details.                                                     ////
926
////                                                              ////
927
//// You should have received a copy of the GNU Lesser General    ////
928
//// Public License along with this source; if not, download it   ////
929
//// from http://www.opencores.org/lgpl.shtml                     ////
930
////                                                              ////
931
//////////////////////////////////////////////////////////////////////
932
// binary counter
933 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
934
 cke, rew, q, zq, level1, rst, clk);
935 25 unneback
   parameter length = 4;
936
   input cke;
937
   input rew;
938
   output [length:1] q;
939
   output reg zq;
940
   output reg level1;
941
   input rst;
942
   input clk;
943
   parameter clear_value = 0;
944
   parameter set_value = 1;
945
   parameter wrap_value = 1;
946
   parameter level1_value = 15;
947 29 unneback
   wire clear;
948 30 unneback
   assign clear = 1'b0;
949 25 unneback
   reg  [length:1] qi;
950
   wire  [length:1] q_next, q_next_fw, q_next_rew;
951
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
952
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
953
   assign q_next = rew ? q_next_rew : q_next_fw;
954
   always @ (posedge clk or posedge rst)
955
     if (rst)
956
       qi <= {length{1'b0}};
957
     else
958
     if (cke)
959
       qi <= q_next;
960
   assign q = qi;
961
   always @ (posedge clk or posedge rst)
962
     if (rst)
963
       zq <= 1'b1;
964
     else
965
     if (cke)
966
       zq <= q_next == {length{1'b0}};
967
    always @ (posedge clk or posedge rst)
968
    if (rst)
969
        level1 <= 1'b0;
970
    else
971
    if (cke)
972 29 unneback
    if (clear)
973
        level1 <= 1'b0;
974
    else if (q_next == level1_value)
975 25 unneback
        level1 <= 1'b1;
976
    else if (qi == level1_value & rew)
977
        level1 <= 1'b0;
978
endmodule
979
//////////////////////////////////////////////////////////////////////
980
////                                                              ////
981
////  Versatile counter                                           ////
982
////                                                              ////
983
////  Description                                                 ////
984
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
985
////  counter                                                     ////
986
////                                                              ////
987
////  To Do:                                                      ////
988
////   - add LFSR with more taps                                  ////
989
////                                                              ////
990
////  Author(s):                                                  ////
991
////      - Michael Unneback, unneback@opencores.org              ////
992
////        ORSoC AB                                              ////
993
////                                                              ////
994
//////////////////////////////////////////////////////////////////////
995
////                                                              ////
996
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
997
////                                                              ////
998
//// This source file may be used and distributed without         ////
999
//// restriction provided that this copyright statement is not    ////
1000
//// removed from the file and that any derivative work contains  ////
1001
//// the original copyright notice and the associated disclaimer. ////
1002
////                                                              ////
1003
//// This source file is free software; you can redistribute it   ////
1004
//// and/or modify it under the terms of the GNU Lesser General   ////
1005
//// Public License as published by the Free Software Foundation; ////
1006
//// either version 2.1 of the License, or (at your option) any   ////
1007
//// later version.                                               ////
1008
////                                                              ////
1009
//// This source is distributed in the hope that it will be       ////
1010
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1011
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1012
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1013
//// details.                                                     ////
1014
////                                                              ////
1015
//// You should have received a copy of the GNU Lesser General    ////
1016
//// Public License along with this source; if not, download it   ////
1017
//// from http://www.opencores.org/lgpl.shtml                     ////
1018
////                                                              ////
1019
//////////////////////////////////////////////////////////////////////
1020 75 unneback
// LFSR counter
1021
module vl_cnt_lfsr_ce (
1022
 cke, zq, rst, clk);
1023
   parameter length = 4;
1024
   input cke;
1025
   output reg zq;
1026
   input rst;
1027
   input clk;
1028
   parameter clear_value = 0;
1029
   parameter set_value = 1;
1030
   parameter wrap_value = 0;
1031
   parameter level1_value = 15;
1032
   reg  [length:1] qi;
1033
   reg lfsr_fb;
1034
   wire [length:1] q_next;
1035
   reg [32:1] polynom;
1036
   integer i;
1037
   always @ (qi)
1038
   begin
1039
        case (length)
1040
         2: polynom = 32'b11;                               // 0x3
1041
         3: polynom = 32'b110;                              // 0x6
1042
         4: polynom = 32'b1100;                             // 0xC
1043
         5: polynom = 32'b10100;                            // 0x14
1044
         6: polynom = 32'b110000;                           // 0x30
1045
         7: polynom = 32'b1100000;                          // 0x60
1046
         8: polynom = 32'b10111000;                         // 0xb8
1047
         9: polynom = 32'b100010000;                        // 0x110
1048
        10: polynom = 32'b1001000000;                       // 0x240
1049
        11: polynom = 32'b10100000000;                      // 0x500
1050
        12: polynom = 32'b100000101001;                     // 0x829
1051
        13: polynom = 32'b1000000001100;                    // 0x100C
1052
        14: polynom = 32'b10000000010101;                   // 0x2015
1053
        15: polynom = 32'b110000000000000;                  // 0x6000
1054
        16: polynom = 32'b1101000000001000;                 // 0xD008
1055
        17: polynom = 32'b10010000000000000;                // 0x12000
1056
        18: polynom = 32'b100000010000000000;               // 0x20400
1057
        19: polynom = 32'b1000000000000100011;              // 0x40023
1058
        20: polynom = 32'b10010000000000000000;             // 0x90000
1059
        21: polynom = 32'b101000000000000000000;            // 0x140000
1060
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1061
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1062
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1063
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1064
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1065
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1066
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1067
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1068
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1069
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1070
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1071
        default: polynom = 32'b0;
1072
        endcase
1073
        lfsr_fb = qi[length];
1074
        for (i=length-1; i>=1; i=i-1) begin
1075
            if (polynom[i])
1076
                lfsr_fb = lfsr_fb  ~^ qi[i];
1077
        end
1078
    end
1079
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1080
   always @ (posedge clk or posedge rst)
1081
     if (rst)
1082
       qi <= {length{1'b0}};
1083
     else
1084
     if (cke)
1085
       qi <= q_next;
1086
   always @ (posedge clk or posedge rst)
1087
     if (rst)
1088
       zq <= 1'b1;
1089
     else
1090
     if (cke)
1091
       zq <= q_next == {length{1'b0}};
1092
endmodule
1093
//////////////////////////////////////////////////////////////////////
1094
////                                                              ////
1095
////  Versatile counter                                           ////
1096
////                                                              ////
1097
////  Description                                                 ////
1098
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1099
////  counter                                                     ////
1100
////                                                              ////
1101
////  To Do:                                                      ////
1102
////   - add LFSR with more taps                                  ////
1103
////                                                              ////
1104
////  Author(s):                                                  ////
1105
////      - Michael Unneback, unneback@opencores.org              ////
1106
////        ORSoC AB                                              ////
1107
////                                                              ////
1108
//////////////////////////////////////////////////////////////////////
1109
////                                                              ////
1110
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1111
////                                                              ////
1112
//// This source file may be used and distributed without         ////
1113
//// restriction provided that this copyright statement is not    ////
1114
//// removed from the file and that any derivative work contains  ////
1115
//// the original copyright notice and the associated disclaimer. ////
1116
////                                                              ////
1117
//// This source file is free software; you can redistribute it   ////
1118
//// and/or modify it under the terms of the GNU Lesser General   ////
1119
//// Public License as published by the Free Software Foundation; ////
1120
//// either version 2.1 of the License, or (at your option) any   ////
1121
//// later version.                                               ////
1122
////                                                              ////
1123
//// This source is distributed in the hope that it will be       ////
1124
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1125
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1126
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1127
//// details.                                                     ////
1128
////                                                              ////
1129
//// You should have received a copy of the GNU Lesser General    ////
1130
//// Public License along with this source; if not, download it   ////
1131
//// from http://www.opencores.org/lgpl.shtml                     ////
1132
////                                                              ////
1133
//////////////////////////////////////////////////////////////////////
1134 6 unneback
// GRAY counter
1135 40 unneback
module vl_cnt_gray_ce_bin (
1136
 cke, q, q_bin, rst, clk);
1137 6 unneback
   parameter length = 4;
1138
   input cke;
1139
   output reg [length:1] q;
1140
   output [length:1] q_bin;
1141
   input rst;
1142
   input clk;
1143
   parameter clear_value = 0;
1144
   parameter set_value = 1;
1145
   parameter wrap_value = 8;
1146
   parameter level1_value = 15;
1147
   reg  [length:1] qi;
1148
   wire [length:1] q_next;
1149
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1150
   always @ (posedge clk or posedge rst)
1151
     if (rst)
1152
       qi <= {length{1'b0}};
1153
     else
1154
     if (cke)
1155
       qi <= q_next;
1156
   always @ (posedge clk or posedge rst)
1157
     if (rst)
1158
       q <= {length{1'b0}};
1159
     else
1160
       if (cke)
1161
         q <= (q_next>>1) ^ q_next;
1162
   assign q_bin = qi;
1163
endmodule
1164
//////////////////////////////////////////////////////////////////////
1165
////                                                              ////
1166
////  Versatile library, counters                                 ////
1167
////                                                              ////
1168
////  Description                                                 ////
1169
////  counters                                                    ////
1170
////                                                              ////
1171
////                                                              ////
1172
////  To Do:                                                      ////
1173
////   - add more counters                                        ////
1174
////                                                              ////
1175
////  Author(s):                                                  ////
1176
////      - Michael Unneback, unneback@opencores.org              ////
1177
////        ORSoC AB                                              ////
1178
////                                                              ////
1179
//////////////////////////////////////////////////////////////////////
1180
////                                                              ////
1181
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1182
////                                                              ////
1183
//// This source file may be used and distributed without         ////
1184
//// restriction provided that this copyright statement is not    ////
1185
//// removed from the file and that any derivative work contains  ////
1186
//// the original copyright notice and the associated disclaimer. ////
1187
////                                                              ////
1188
//// This source file is free software; you can redistribute it   ////
1189
//// and/or modify it under the terms of the GNU Lesser General   ////
1190
//// Public License as published by the Free Software Foundation; ////
1191
//// either version 2.1 of the License, or (at your option) any   ////
1192
//// later version.                                               ////
1193
////                                                              ////
1194
//// This source is distributed in the hope that it will be       ////
1195
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1196
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1197
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1198
//// details.                                                     ////
1199
////                                                              ////
1200
//// You should have received a copy of the GNU Lesser General    ////
1201
//// Public License along with this source; if not, download it   ////
1202
//// from http://www.opencores.org/lgpl.shtml                     ////
1203
////                                                              ////
1204
//////////////////////////////////////////////////////////////////////
1205 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1206 6 unneback
   parameter length = 4;
1207
   output reg [0:length-1] q;
1208
   input rst;
1209
   input clk;
1210
    always @ (posedge clk or posedge rst)
1211
    if (rst)
1212
        q <= {1'b1,{length-1{1'b0}}};
1213
    else
1214
        q <= {q[length-1],q[0:length-2]};
1215
endmodule
1216 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1217 6 unneback
   parameter length = 4;
1218
   input cke;
1219
   output reg [0:length-1] q;
1220
   input rst;
1221
   input clk;
1222
    always @ (posedge clk or posedge rst)
1223
    if (rst)
1224
        q <= {1'b1,{length-1{1'b0}}};
1225
    else
1226
        if (cke)
1227
            q <= {q[length-1],q[0:length-2]};
1228
endmodule
1229 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1230 6 unneback
   parameter length = 4;
1231
   input cke, clear;
1232
   output reg [0:length-1] q;
1233
   input rst;
1234
   input clk;
1235
    always @ (posedge clk or posedge rst)
1236
    if (rst)
1237
        q <= {1'b1,{length-1{1'b0}}};
1238
    else
1239
        if (cke)
1240
            if (clear)
1241
                q <= {1'b1,{length-1{1'b0}}};
1242
            else
1243
                q <= q >> 1;
1244
endmodule
1245 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1246 6 unneback
   parameter length = 4;
1247
   input cke, clear;
1248
   output reg [0:length-1] q;
1249
   input rst;
1250
   input clk;
1251
    always @ (posedge clk or posedge rst)
1252
    if (rst)
1253
        q <= {1'b1,{length-1{1'b0}}};
1254
    else
1255
        if (cke)
1256
            if (clear)
1257
                q <= {1'b1,{length-1{1'b0}}};
1258
            else
1259
            q <= {q[length-1],q[0:length-2]};
1260
endmodule
1261
//////////////////////////////////////////////////////////////////////
1262
////                                                              ////
1263
////  Versatile library, memories                                 ////
1264
////                                                              ////
1265
////  Description                                                 ////
1266
////  memories                                                    ////
1267
////                                                              ////
1268
////                                                              ////
1269
////  To Do:                                                      ////
1270
////   - add more memory types                                    ////
1271
////                                                              ////
1272
////  Author(s):                                                  ////
1273
////      - Michael Unneback, unneback@opencores.org              ////
1274
////        ORSoC AB                                              ////
1275
////                                                              ////
1276
//////////////////////////////////////////////////////////////////////
1277
////                                                              ////
1278
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1279
////                                                              ////
1280
//// This source file may be used and distributed without         ////
1281
//// restriction provided that this copyright statement is not    ////
1282
//// removed from the file and that any derivative work contains  ////
1283
//// the original copyright notice and the associated disclaimer. ////
1284
////                                                              ////
1285
//// This source file is free software; you can redistribute it   ////
1286
//// and/or modify it under the terms of the GNU Lesser General   ////
1287
//// Public License as published by the Free Software Foundation; ////
1288
//// either version 2.1 of the License, or (at your option) any   ////
1289
//// later version.                                               ////
1290
////                                                              ////
1291
//// This source is distributed in the hope that it will be       ////
1292
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1293
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1294
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1295
//// details.                                                     ////
1296
////                                                              ////
1297
//// You should have received a copy of the GNU Lesser General    ////
1298
//// Public License along with this source; if not, download it   ////
1299
//// from http://www.opencores.org/lgpl.shtml                     ////
1300
////                                                              ////
1301
//////////////////////////////////////////////////////////////////////
1302
/// ROM
1303 7 unneback
module vl_rom_init ( adr, q, clk);
1304
   parameter data_width = 32;
1305
   parameter addr_width = 8;
1306 75 unneback
   parameter mem_size = 1<<addr_width;
1307 7 unneback
   input [(addr_width-1):0]       adr;
1308
   output reg [(data_width-1):0] q;
1309
   input                         clk;
1310 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1311 7 unneback
   parameter memory_file = "vl_rom.vmem";
1312
   initial
1313
     begin
1314
        $readmemh(memory_file, rom);
1315
     end
1316
   always @ (posedge clk)
1317
     q <= rom[adr];
1318
endmodule
1319 6 unneback
// Single port RAM
1320
module vl_ram ( d, adr, we, q, clk);
1321
   parameter data_width = 32;
1322
   parameter addr_width = 8;
1323 75 unneback
   parameter mem_size = 1<<addr_width;
1324 6 unneback
   input [(data_width-1):0]      d;
1325
   input [(addr_width-1):0]       adr;
1326
   input                         we;
1327 7 unneback
   output reg [(data_width-1):0] q;
1328 6 unneback
   input                         clk;
1329 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
1330 7 unneback
   parameter init = 0;
1331
   parameter memory_file = "vl_ram.vmem";
1332
   generate if (init) begin : init_mem
1333
   initial
1334
     begin
1335
        $readmemh(memory_file, ram);
1336
     end
1337
   end
1338
   endgenerate
1339 6 unneback
   always @ (posedge clk)
1340
   begin
1341
   if (we)
1342
     ram[adr] <= d;
1343
   q <= ram[adr];
1344
   end
1345
endmodule
1346 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1347 7 unneback
   parameter data_width = 32;
1348 72 unneback
   parameter addr_width = 6;
1349 75 unneback
   parameter mem_size = 1<<addr_width;
1350 7 unneback
   input [(data_width-1):0]      d;
1351
   input [(addr_width-1):0]       adr;
1352 73 unneback
   input [(data_width/8)-1:0]    be;
1353 7 unneback
   input                         we;
1354
   output reg [(data_width-1):0] q;
1355
   input                         clk;
1356 65 unneback
`ifdef SYSTEMVERILOG
1357 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
1358 65 unneback
`else
1359 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1360
    wire [data_width/8-1:0] cke;
1361 65 unneback
`endif
1362 60 unneback
   parameter memory_init = 0;
1363 7 unneback
   parameter memory_file = "vl_ram.vmem";
1364 60 unneback
   generate if (memory_init) begin : init_mem
1365 7 unneback
   initial
1366
     begin
1367
        $readmemh(memory_file, ram);
1368
     end
1369
   end
1370
   endgenerate
1371 60 unneback
`ifdef SYSTEMVERILOG
1372
// use a multi-dimensional packed array
1373
//to model individual bytes within the word
1374
always_ff@(posedge clk)
1375
begin
1376
    if(we) begin // note: we should have a for statement to support any bus width
1377 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1378
        if(be[2]) ram[adr][2] <= d[23:16];
1379
        if(be[1]) ram[adr][1] <= d[15:8];
1380
        if(be[0]) ram[adr][0] <= d[7:0];
1381 60 unneback
    end
1382 90 unneback
        q <= ram[adr];
1383 60 unneback
end
1384
`else
1385 85 unneback
assign cke = {data_width/8{we}} & be;
1386 7 unneback
   genvar i;
1387 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1388 7 unneback
      always @ (posedge clk)
1389 85 unneback
      if (cke[i])
1390 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1391
   end
1392
   endgenerate
1393
   always @ (posedge clk)
1394
      q <= ram[adr];
1395 60 unneback
`endif
1396 85 unneback
   // Function to access RAM (for use by Verilator).
1397
   function [31:0] get_mem;
1398
      // verilator public
1399 90 unneback
      input [addr_width-1:0]             addr;
1400 85 unneback
      get_mem = ram[addr];
1401
   endfunction // get_mem
1402
   // Function to write RAM (for use by Verilator).
1403
   function set_mem;
1404
      // verilator public
1405 90 unneback
      input [addr_width-1:0]             addr;
1406
      input [data_width-1:0]             data;
1407 85 unneback
      ram[addr] = data;
1408
   endfunction // set_mem
1409 7 unneback
endmodule
1410
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1411 6 unneback
   parameter data_width = 32;
1412
   parameter addr_width = 8;
1413 75 unneback
   parameter mem_size = 1<<addr_width;
1414 6 unneback
   input [(data_width-1):0]      d_a;
1415
   input [(addr_width-1):0]       adr_a;
1416
   input [(addr_width-1):0]       adr_b;
1417
   input                         we_a;
1418
   output [(data_width-1):0]      q_b;
1419
   input                         clk_a, clk_b;
1420
   reg [(addr_width-1):0]         adr_b_reg;
1421 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] ;
1422 7 unneback
   parameter init = 0;
1423
   parameter memory_file = "vl_ram.vmem";
1424
   generate if (init) begin : init_mem
1425
   initial
1426
     begin
1427
        $readmemh(memory_file, ram);
1428
     end
1429
   end
1430
   endgenerate
1431 6 unneback
   always @ (posedge clk_a)
1432
   if (we_a)
1433
     ram[adr_a] <= d_a;
1434
   always @ (posedge clk_b)
1435
   adr_b_reg <= adr_b;
1436
   assign q_b = ram[adr_b_reg];
1437
endmodule
1438 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1439 6 unneback
   parameter data_width = 32;
1440
   parameter addr_width = 8;
1441 75 unneback
   parameter mem_size = 1<<addr_width;
1442 6 unneback
   input [(data_width-1):0]      d_a;
1443
   input [(addr_width-1):0]       adr_a;
1444
   input [(addr_width-1):0]       adr_b;
1445
   input                         we_a;
1446
   output [(data_width-1):0]      q_b;
1447
   output reg [(data_width-1):0] q_a;
1448
   input                         clk_a, clk_b;
1449
   reg [(data_width-1):0]         q_b;
1450 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] ;
1451 7 unneback
   parameter init = 0;
1452
   parameter memory_file = "vl_ram.vmem";
1453
   generate if (init) begin : init_mem
1454
   initial
1455
     begin
1456
        $readmemh(memory_file, ram);
1457
     end
1458
   end
1459
   endgenerate
1460 6 unneback
   always @ (posedge clk_a)
1461
     begin
1462
        q_a <= ram[adr_a];
1463
        if (we_a)
1464
             ram[adr_a] <= d_a;
1465
     end
1466
   always @ (posedge clk_b)
1467
          q_b <= ram[adr_b];
1468
endmodule
1469 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1470 6 unneback
   parameter data_width = 32;
1471
   parameter addr_width = 8;
1472 75 unneback
   parameter mem_size = 1<<addr_width;
1473 6 unneback
   input [(data_width-1):0]      d_a;
1474
   input [(addr_width-1):0]       adr_a;
1475
   input [(addr_width-1):0]       adr_b;
1476
   input                         we_a;
1477
   output [(data_width-1):0]      q_b;
1478
   input [(data_width-1):0]       d_b;
1479
   output reg [(data_width-1):0] q_a;
1480
   input                         we_b;
1481
   input                         clk_a, clk_b;
1482
   reg [(data_width-1):0]         q_b;
1483 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] ;
1484 7 unneback
   parameter init = 0;
1485
   parameter memory_file = "vl_ram.vmem";
1486
   generate if (init) begin : init_mem
1487
   initial
1488
     begin
1489
        $readmemh(memory_file, ram);
1490
     end
1491
   end
1492
   endgenerate
1493 6 unneback
   always @ (posedge clk_a)
1494
     begin
1495
        q_a <= ram[adr_a];
1496
        if (we_a)
1497
             ram[adr_a] <= d_a;
1498
     end
1499
   always @ (posedge clk_b)
1500
     begin
1501
        q_b <= ram[adr_b];
1502
        if (we_b)
1503
          ram[adr_b] <= d_b;
1504
     end
1505
endmodule
1506 91 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, re_a, we_a, clk_a, d_b, q_b, adr_b, re_b, we_b, clk_b );
1507 75 unneback
   parameter a_data_width = 32;
1508
   parameter a_addr_width = 8;
1509 91 unneback
   parameter b_data_width = 32;
1510
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1511
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
1512 75 unneback
   input [(a_data_width-1):0]      d_a;
1513 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1514
   input [(a_data_width/8-1):0]    be_a;
1515
   input                           re_a;
1516
   input                           we_a;
1517 75 unneback
   output reg [(a_data_width-1):0] q_a;
1518 91 unneback
   input [(b_data_width-1):0]       d_b;
1519
   input [(b_addr_width-1):0]       adr_b;
1520
   input                           re_b,we_b;
1521
   output [(b_data_width-1):0]      q_b;
1522
   input                           clk_a, clk_b;
1523
`ifdef SYSTEMVERILOG
1524
// use a multi-dimensional packed array
1525
//to model individual bytes within the word
1526 75 unneback
generate
1527 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1528
   logic [3:0][7:0] ram [0:mem_size-1];
1529
    reg [a_addr_width-1:0] rd_adr_a;
1530
    reg [b_addr_width-1:0] rd_adr_b;
1531
    always_ff@(posedge clk_a)
1532
    begin
1533
        if(we_a) begin
1534
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1535
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1536
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1537
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1538
        end
1539
    end
1540
    always@(posedge clk_a or posedge rst)
1541
    if (rst)
1542
        rd_adr_a <= 0;
1543
    else if (re_a)
1544
        rd_adr_a <= adr_a;
1545
    assign q_a = ram[rd_adr_a];
1546
    always_ff@(posedge clk_b)
1547
    if(we_b)
1548
        ram[adr_b] <= d_b;
1549
    always@(posedge clk_b or posedge rst)
1550
    if (rst)
1551
        rd_adr_b <= 0;
1552
    else if (re_b)
1553
        rd_adr_b <= adr_b;
1554
    assign q_b = ram[rd_adr_b];
1555 75 unneback
end
1556
endgenerate
1557 91 unneback
`else
1558
`endif
1559 75 unneback
endmodule
1560 6 unneback
// FIFO
1561 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1562
    d, wr, fifo_full,
1563
    q, rd, fifo_empty,
1564
    fill_level,
1565
    clk, rst
1566
    );
1567
parameter data_width = 18;
1568
parameter addr_width = 4;
1569
// write side
1570
input  [data_width-1:0] d;
1571
input                   wr;
1572
output                  fifo_full;
1573
// read side
1574
output [data_width-1:0] q;
1575
input                   rd;
1576
output                  fifo_empty;
1577
// common
1578
output [addr_width:0]   fill_level;
1579
input rst, clk;
1580
wire [addr_width:1] wadr, radr;
1581
vl_cnt_bin_ce
1582
    # ( .length(addr_width))
1583
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1584
vl_cnt_bin_ce
1585
    # (.length(addr_width))
1586
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1587
vl_dpram_1r1w
1588
    # (.data_width(data_width), .addr_width(addr_width))
1589
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1590 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1591 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1592 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1593
endmodule
1594 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1595
// RAM is supposed to be larger than the two FIFOs
1596
// LFSR counters used adr pointers
1597
module vl_fifo_2r2w_sync_simplex (
1598
    // a side
1599
    a_d, a_wr, a_fifo_full,
1600
    a_q, a_rd, a_fifo_empty,
1601
    a_fill_level,
1602
    // b side
1603
    b_d, b_wr, b_fifo_full,
1604
    b_q, b_rd, b_fifo_empty,
1605
    b_fill_level,
1606
    // common
1607
    clk, rst
1608
    );
1609
parameter data_width = 8;
1610
parameter addr_width = 5;
1611
parameter fifo_full_level = (1<<addr_width)-1;
1612
// a side
1613
input  [data_width-1:0] a_d;
1614
input                   a_wr;
1615
output                  a_fifo_full;
1616
output [data_width-1:0] a_q;
1617
input                   a_rd;
1618
output                  a_fifo_empty;
1619
output [addr_width-1:0] a_fill_level;
1620
// b side
1621
input  [data_width-1:0] b_d;
1622
input                   b_wr;
1623
output                  b_fifo_full;
1624
output [data_width-1:0] b_q;
1625
input                   b_rd;
1626
output                  b_fifo_empty;
1627
output [addr_width-1:0] b_fill_level;
1628
input                   clk;
1629
input                   rst;
1630
// adr_gen
1631
wire [addr_width:1] a_wadr, a_radr;
1632
wire [addr_width:1] b_wadr, b_radr;
1633
// dpram
1634
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1635
vl_cnt_lfsr_ce
1636
    # ( .length(addr_width))
1637
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1638
vl_cnt_lfsr_ce
1639
    # (.length(addr_width))
1640
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1641
vl_cnt_lfsr_ce
1642
    # ( .length(addr_width))
1643
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1644
vl_cnt_lfsr_ce
1645
    # (.length(addr_width))
1646
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1647
// mux read or write adr to DPRAM
1648
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1649
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1650
vl_dpram_2r2w
1651
    # (.data_width(data_width), .addr_width(addr_width+1))
1652
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1653
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1654
vl_cnt_bin_ce_rew_zq_l1
1655 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1656 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1657
vl_cnt_bin_ce_rew_zq_l1
1658 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1659 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1660
endmodule
1661 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1662 11 unneback
   parameter addr_width = 4;
1663
   parameter N = addr_width-1;
1664 6 unneback
   parameter Q1 = 2'b00;
1665
   parameter Q2 = 2'b01;
1666
   parameter Q3 = 2'b11;
1667
   parameter Q4 = 2'b10;
1668
   parameter going_empty = 1'b0;
1669
   parameter going_full  = 1'b1;
1670
   input [N:0]  wptr, rptr;
1671 14 unneback
   output       fifo_empty;
1672 6 unneback
   output       fifo_full;
1673
   input        wclk, rclk, rst;
1674
   wire direction;
1675
   reg  direction_set, direction_clr;
1676
   wire async_empty, async_full;
1677
   wire fifo_full2;
1678 14 unneback
   wire fifo_empty2;
1679 6 unneback
   // direction_set
1680
   always @ (wptr[N:N-1] or rptr[N:N-1])
1681
     case ({wptr[N:N-1],rptr[N:N-1]})
1682
       {Q1,Q2} : direction_set <= 1'b1;
1683
       {Q2,Q3} : direction_set <= 1'b1;
1684
       {Q3,Q4} : direction_set <= 1'b1;
1685
       {Q4,Q1} : direction_set <= 1'b1;
1686
       default : direction_set <= 1'b0;
1687
     endcase
1688
   // direction_clear
1689
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1690
     if (rst)
1691
       direction_clr <= 1'b1;
1692
     else
1693
       case ({wptr[N:N-1],rptr[N:N-1]})
1694
         {Q2,Q1} : direction_clr <= 1'b1;
1695
         {Q3,Q2} : direction_clr <= 1'b1;
1696
         {Q4,Q3} : direction_clr <= 1'b1;
1697
         {Q1,Q4} : direction_clr <= 1'b1;
1698
         default : direction_clr <= 1'b0;
1699
       endcase
1700 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1701 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1702
   assign async_full  = (wptr == rptr) && (direction==going_full);
1703 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1704
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1705 6 unneback
/*
1706
   always @ (posedge wclk or posedge rst or posedge async_full)
1707
     if (rst)
1708
       {fifo_full, fifo_full2} <= 2'b00;
1709
     else if (async_full)
1710
       {fifo_full, fifo_full2} <= 2'b11;
1711
     else
1712
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1713
*/
1714 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1715 6 unneback
     if (async_empty)
1716
       {fifo_empty, fifo_empty2} <= 2'b11;
1717
     else
1718 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1719 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1720
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1721 27 unneback
endmodule // async_compb
1722 6 unneback
module vl_fifo_1r1w_async (
1723
    d, wr, fifo_full, wr_clk, wr_rst,
1724
    q, rd, fifo_empty, rd_clk, rd_rst
1725
    );
1726
parameter data_width = 18;
1727
parameter addr_width = 4;
1728
// write side
1729
input  [data_width-1:0] d;
1730
input                   wr;
1731
output                  fifo_full;
1732
input                   wr_clk;
1733
input                   wr_rst;
1734
// read side
1735
output [data_width-1:0] q;
1736
input                   rd;
1737
output                  fifo_empty;
1738
input                   rd_clk;
1739
input                   rd_rst;
1740
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1741 18 unneback
vl_cnt_gray_ce_bin
1742 6 unneback
    # ( .length(addr_width))
1743
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1744 18 unneback
vl_cnt_gray_ce_bin
1745 6 unneback
    # (.length(addr_width))
1746 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1747 7 unneback
vl_dpram_1r1w
1748 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1749
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1750
vl_fifo_cmp_async
1751
    # (.addr_width(addr_width))
1752
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1753
endmodule
1754 8 unneback
module vl_fifo_2r2w_async (
1755 6 unneback
    // a side
1756
    a_d, a_wr, a_fifo_full,
1757
    a_q, a_rd, a_fifo_empty,
1758
    a_clk, a_rst,
1759
    // b side
1760
    b_d, b_wr, b_fifo_full,
1761
    b_q, b_rd, b_fifo_empty,
1762
    b_clk, b_rst
1763
    );
1764
parameter data_width = 18;
1765
parameter addr_width = 4;
1766
// a side
1767
input  [data_width-1:0] a_d;
1768
input                   a_wr;
1769
output                  a_fifo_full;
1770
output [data_width-1:0] a_q;
1771
input                   a_rd;
1772
output                  a_fifo_empty;
1773
input                   a_clk;
1774
input                   a_rst;
1775
// b side
1776
input  [data_width-1:0] b_d;
1777
input                   b_wr;
1778
output                  b_fifo_full;
1779
output [data_width-1:0] b_q;
1780
input                   b_rd;
1781
output                  b_fifo_empty;
1782
input                   b_clk;
1783
input                   b_rst;
1784
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1785
vl_fifo_1r1w_async_a (
1786
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1787
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1788
    );
1789
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1790
vl_fifo_1r1w_async_b (
1791
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1792
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1793
    );
1794
endmodule
1795 8 unneback
module vl_fifo_2r2w_async_simplex (
1796 6 unneback
    // a side
1797
    a_d, a_wr, a_fifo_full,
1798
    a_q, a_rd, a_fifo_empty,
1799
    a_clk, a_rst,
1800
    // b side
1801
    b_d, b_wr, b_fifo_full,
1802
    b_q, b_rd, b_fifo_empty,
1803
    b_clk, b_rst
1804
    );
1805
parameter data_width = 18;
1806
parameter addr_width = 4;
1807
// a side
1808
input  [data_width-1:0] a_d;
1809
input                   a_wr;
1810
output                  a_fifo_full;
1811
output [data_width-1:0] a_q;
1812
input                   a_rd;
1813
output                  a_fifo_empty;
1814
input                   a_clk;
1815
input                   a_rst;
1816
// b side
1817
input  [data_width-1:0] b_d;
1818
input                   b_wr;
1819
output                  b_fifo_full;
1820
output [data_width-1:0] b_q;
1821
input                   b_rd;
1822
output                  b_fifo_empty;
1823
input                   b_clk;
1824
input                   b_rst;
1825
// adr_gen
1826
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1827
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1828
// dpram
1829
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1830 18 unneback
vl_cnt_gray_ce_bin
1831 6 unneback
    # ( .length(addr_width))
1832
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1833 18 unneback
vl_cnt_gray_ce_bin
1834 6 unneback
    # (.length(addr_width))
1835
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1836 18 unneback
vl_cnt_gray_ce_bin
1837 6 unneback
    # ( .length(addr_width))
1838
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1839 18 unneback
vl_cnt_gray_ce_bin
1840 6 unneback
    # (.length(addr_width))
1841
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1842
// mux read or write adr to DPRAM
1843
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1844
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1845 11 unneback
vl_dpram_2r2w
1846 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1847
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1848
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1849 11 unneback
vl_fifo_cmp_async
1850 6 unneback
    # (.addr_width(addr_width))
1851
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1852 11 unneback
vl_fifo_cmp_async
1853 6 unneback
    # (.addr_width(addr_width))
1854
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1855
endmodule
1856 48 unneback
module vl_reg_file (
1857
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1858
);
1859
parameter data_width = 32;
1860
parameter addr_width = 5;
1861
input [addr_width-1:0] a1, a2, a3;
1862
input [data_width-1:0] wd3;
1863
input we3;
1864
output [data_width-1:0] rd1, rd2;
1865
input clk;
1866
vl_dpram_1r1w
1867
    # ( .data_width(data_width), .addr_width(addr_width))
1868
    ram1 (
1869
        .d_a(wd3),
1870
        .adr_a(a3),
1871
        .we_a(we3),
1872
        .clk_a(clk),
1873
        .q_b(rd1),
1874
        .adr_b(a1),
1875
        .clk_b(clk) );
1876
vl_dpram_1r1w
1877
    # ( .data_width(data_width), .addr_width(addr_width))
1878
    ram2 (
1879
        .d_a(wd3),
1880
        .adr_a(a3),
1881
        .we_a(we3),
1882
        .clk_a(clk),
1883
        .q_b(rd2),
1884
        .adr_b(a2),
1885
        .clk_b(clk) );
1886
endmodule
1887 12 unneback
//////////////////////////////////////////////////////////////////////
1888
////                                                              ////
1889
////  Versatile library, wishbone stuff                           ////
1890
////                                                              ////
1891
////  Description                                                 ////
1892
////  Wishbone compliant modules                                  ////
1893
////                                                              ////
1894
////                                                              ////
1895
////  To Do:                                                      ////
1896
////   -                                                          ////
1897
////                                                              ////
1898
////  Author(s):                                                  ////
1899
////      - Michael Unneback, unneback@opencores.org              ////
1900
////        ORSoC AB                                              ////
1901
////                                                              ////
1902
//////////////////////////////////////////////////////////////////////
1903
////                                                              ////
1904
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1905
////                                                              ////
1906
//// This source file may be used and distributed without         ////
1907
//// restriction provided that this copyright statement is not    ////
1908
//// removed from the file and that any derivative work contains  ////
1909
//// the original copyright notice and the associated disclaimer. ////
1910
////                                                              ////
1911
//// This source file is free software; you can redistribute it   ////
1912
//// and/or modify it under the terms of the GNU Lesser General   ////
1913
//// Public License as published by the Free Software Foundation; ////
1914
//// either version 2.1 of the License, or (at your option) any   ////
1915
//// later version.                                               ////
1916
////                                                              ////
1917
//// This source is distributed in the hope that it will be       ////
1918
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1919
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1920
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1921
//// details.                                                     ////
1922
////                                                              ////
1923
//// You should have received a copy of the GNU Lesser General    ////
1924
//// Public License along with this source; if not, download it   ////
1925
//// from http://www.opencores.org/lgpl.shtml                     ////
1926
////                                                              ////
1927
//////////////////////////////////////////////////////////////////////
1928
// async wb3 - wb3 bridge
1929
`timescale 1ns/1ns
1930 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
1931 83 unneback
parameter adr_width = 10;
1932
parameter max_burst_width = 4;
1933 85 unneback
input cyc_i, stb_i, we_i;
1934 83 unneback
input [2:0] cti_i;
1935
input [1:0] bte_i;
1936
input [adr_width-1:0] adr_i;
1937
output [adr_width-1:0] adr_o;
1938
output ack_o;
1939
input clk, rst;
1940
reg [adr_width-1:0] adr;
1941 90 unneback
wire [max_burst_width-1:0] to_adr;
1942 91 unneback
reg [max_burst_width-1:0] last_adr;
1943
reg [1:0] last_cycle;
1944
localparam idle = 2'b00;
1945
localparam cyc  = 2'b01;
1946
localparam ws   = 2'b10;
1947
localparam eoc  = 2'b11;
1948
always @ (posedge clk or posedge rst)
1949
if (rst)
1950
    last_adr <= {max_burst_width{1'b0}};
1951
else
1952
    if (stb_i)
1953
        last_adr <=adr_o;
1954 83 unneback
generate
1955
if (max_burst_width==0) begin : inst_0
1956
    reg ack_o;
1957
    assign adr_o = adr_i;
1958
    always @ (posedge clk or posedge rst)
1959
    if (rst)
1960
        ack_o <= 1'b0;
1961
    else
1962
        ack_o <= cyc_i & stb_i & !ack_o;
1963
end else begin
1964
    always @ (posedge clk or posedge rst)
1965
    if (rst)
1966
        last_cycle <= idle;
1967
    else
1968
        last_cycle <= (!cyc_i) ? idle :
1969
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
1970
                      (cyc_i & !stb_i) ? ws :
1971
                      cyc;
1972
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
1973 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
1974 91 unneback
                                        (!stb_i) ? last_adr :
1975 85 unneback
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
1976
                                        adr[max_burst_width-1:0];
1977 90 unneback
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
1978 83 unneback
end
1979
endgenerate
1980
generate
1981
if (max_burst_width==2) begin : inst_2
1982
    always @ (posedge clk or posedge rst)
1983
    if (rst)
1984
        adr <= 2'h0;
1985
    else
1986
        if (cyc_i & stb_i)
1987
            adr[1:0] <= to_adr[1:0] + 2'd1;
1988
        else
1989
            adr <= to_adr[1:0];
1990
end
1991
endgenerate
1992
generate
1993
if (max_burst_width==3) begin : inst_3
1994
    always @ (posedge clk or posedge rst)
1995
    if (rst)
1996
        adr <= 3'h0;
1997
    else
1998
        if (cyc_i & stb_i)
1999
            case (bte_i)
2000
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
2001
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
2002
            endcase
2003
        else
2004
            adr <= to_adr[2:0];
2005
end
2006
endgenerate
2007
generate
2008
if (max_burst_width==4) begin : inst_4
2009
    always @ (posedge clk or posedge rst)
2010
    if (rst)
2011
        adr <= 4'h0;
2012
    else
2013 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
2014 83 unneback
            case (bte_i)
2015
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
2016
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
2017
            default: adr[3:0] <= to_adr + 4'd1;
2018
            endcase
2019
        else
2020
            adr <= to_adr[3:0];
2021
end
2022
endgenerate
2023
generate
2024
if (adr_width > max_burst_width) begin : pass_through
2025
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
2026
end
2027
endgenerate
2028
endmodule
2029
// async wb3 - wb3 bridge
2030
`timescale 1ns/1ns
2031 18 unneback
module vl_wb3wb3_bridge (
2032 12 unneback
        // wishbone slave side
2033
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2034
        // wishbone master side
2035
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2036
input [31:0] wbs_dat_i;
2037
input [31:2] wbs_adr_i;
2038
input [3:0]  wbs_sel_i;
2039
input [1:0]  wbs_bte_i;
2040
input [2:0]  wbs_cti_i;
2041
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2042
output [31:0] wbs_dat_o;
2043 14 unneback
output wbs_ack_o;
2044 12 unneback
input wbs_clk, wbs_rst;
2045
output [31:0] wbm_dat_o;
2046
output reg [31:2] wbm_adr_o;
2047
output [3:0]  wbm_sel_o;
2048
output reg [1:0]  wbm_bte_o;
2049
output reg [2:0]  wbm_cti_o;
2050 14 unneback
output reg wbm_we_o;
2051
output wbm_cyc_o;
2052 12 unneback
output wbm_stb_o;
2053
input [31:0]  wbm_dat_i;
2054
input wbm_ack_i;
2055
input wbm_clk, wbm_rst;
2056
parameter addr_width = 4;
2057
// bte
2058
parameter linear       = 2'b00;
2059
parameter wrap4        = 2'b01;
2060
parameter wrap8        = 2'b10;
2061
parameter wrap16       = 2'b11;
2062
// cti
2063
parameter classic      = 3'b000;
2064
parameter incburst     = 3'b010;
2065
parameter endofburst   = 3'b111;
2066
parameter wbs_adr  = 1'b0;
2067
parameter wbs_data = 1'b1;
2068 33 unneback
parameter wbm_adr0      = 2'b00;
2069
parameter wbm_adr1      = 2'b01;
2070
parameter wbm_data      = 2'b10;
2071
parameter wbm_data_wait = 2'b11;
2072 12 unneback
reg [1:0] wbs_bte_reg;
2073
reg wbs;
2074
wire wbs_eoc_alert, wbm_eoc_alert;
2075
reg wbs_eoc, wbm_eoc;
2076
reg [1:0] wbm;
2077 14 unneback
wire [1:16] wbs_count, wbm_count;
2078 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2079
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2080
reg a_rd_reg;
2081
wire b_rd_adr, b_rd_data;
2082 14 unneback
wire b_rd_data_reg;
2083
wire [35:0] temp;
2084 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2085
always @ (posedge wbs_clk or posedge wbs_rst)
2086
if (wbs_rst)
2087
        wbs_eoc <= 1'b0;
2088
else
2089
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2090 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
2091 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
2092
                wbs_eoc <= 1'b1;
2093 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2094 12 unneback
    cnt0 (
2095
        .cke(wbs_ack_o),
2096
        .clear(wbs_eoc),
2097
        .q(wbs_count),
2098
        .rst(wbs_rst),
2099
        .clk(wbs_clk));
2100
always @ (posedge wbs_clk or posedge wbs_rst)
2101
if (wbs_rst)
2102
        wbs <= wbs_adr;
2103
else
2104 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
2105 12 unneback
                wbs <= wbs_data;
2106
        else if (wbs_eoc & wbs_ack_o)
2107
                wbs <= wbs_adr;
2108
// wbs FIFO
2109 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
2110
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
2111 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2112
              1'b0;
2113
assign a_rd = !a_fifo_empty;
2114
always @ (posedge wbs_clk or posedge wbs_rst)
2115
if (wbs_rst)
2116
        a_rd_reg <= 1'b0;
2117
else
2118
        a_rd_reg <= a_rd;
2119
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2120
assign wbs_dat_o = a_q[35:4];
2121
always @ (posedge wbs_clk or posedge wbs_rst)
2122
if (wbs_rst)
2123 13 unneback
        wbs_bte_reg <= 2'b00;
2124 12 unneback
else
2125 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2126 12 unneback
// wbm FIFO
2127
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2128
always @ (posedge wbm_clk or posedge wbm_rst)
2129
if (wbm_rst)
2130
        wbm_eoc <= 1'b0;
2131
else
2132
        if (wbm==wbm_adr0 & !b_fifo_empty)
2133
                wbm_eoc <= b_q[4:3] == linear;
2134
        else if (wbm_eoc_alert & wbm_ack_i)
2135
                wbm_eoc <= 1'b1;
2136
always @ (posedge wbm_clk or posedge wbm_rst)
2137
if (wbm_rst)
2138
        wbm <= wbm_adr0;
2139
else
2140 33 unneback
/*
2141 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2142
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2143
        (wbm==wbm_adr1 & !wbm_we_o) |
2144
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2145
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2146 33 unneback
*/
2147
    case (wbm)
2148
    wbm_adr0:
2149
        if (!b_fifo_empty)
2150
            wbm <= wbm_adr1;
2151
    wbm_adr1:
2152
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
2153
            wbm <= wbm_data;
2154
    wbm_data:
2155
        if (wbm_ack_i & wbm_eoc)
2156
            wbm <= wbm_adr0;
2157
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
2158
            wbm <= wbm_data_wait;
2159
    wbm_data_wait:
2160
        if (!b_fifo_empty)
2161
            wbm <= wbm_data;
2162
    endcase
2163 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
2164
assign b_wr = !wbm_we_o & wbm_ack_i;
2165
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2166
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2167
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2168 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
2169 12 unneback
                   1'b0;
2170
assign b_rd = b_rd_adr | b_rd_data;
2171 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2172
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2173 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2174 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2175 12 unneback
    cnt1 (
2176
        .cke(wbm_ack_i),
2177
        .clear(wbm_eoc),
2178
        .q(wbm_count),
2179
        .rst(wbm_rst),
2180
        .clk(wbm_clk));
2181 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
2182
assign wbm_stb_o = (wbm==wbm_data);
2183 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
2184
if (wbm_rst)
2185
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2186
else begin
2187
        if (wbm==wbm_adr0 & !b_fifo_empty)
2188
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2189
        else if (wbm_eoc_alert & wbm_ack_i)
2190
                wbm_cti_o <= endofburst;
2191
end
2192
//async_fifo_dw_simplex_top
2193
vl_fifo_2r2w_async_simplex
2194
# ( .data_width(36), .addr_width(addr_width))
2195
fifo (
2196
    // a side
2197
    .a_d(a_d),
2198
    .a_wr(a_wr),
2199
    .a_fifo_full(a_fifo_full),
2200
    .a_q(a_q),
2201
    .a_rd(a_rd),
2202
    .a_fifo_empty(a_fifo_empty),
2203
    .a_clk(wbs_clk),
2204
    .a_rst(wbs_rst),
2205
    // b side
2206
    .b_d(b_d),
2207
    .b_wr(b_wr),
2208
    .b_fifo_full(b_fifo_full),
2209
    .b_q(b_q),
2210
    .b_rd(b_rd),
2211
    .b_fifo_empty(b_fifo_empty),
2212
    .b_clk(wbm_clk),
2213
    .b_rst(wbm_rst)
2214
    );
2215
endmodule
2216 75 unneback
module vl_wb3avalon_bridge (
2217
        // wishbone slave side
2218
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2219 77 unneback
        // avalon master side
2220 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
2221 85 unneback
parameter linewrapburst = 1'b0;
2222 75 unneback
input [31:0] wbs_dat_i;
2223
input [31:2] wbs_adr_i;
2224
input [3:0]  wbs_sel_i;
2225
input [1:0]  wbs_bte_i;
2226
input [2:0]  wbs_cti_i;
2227 83 unneback
input wbs_we_i;
2228
input wbs_cyc_i;
2229
input wbs_stb_i;
2230 75 unneback
output [31:0] wbs_dat_o;
2231
output wbs_ack_o;
2232
input wbs_clk, wbs_rst;
2233
input [31:0] readdata;
2234
output [31:0] writedata;
2235
output [31:2] address;
2236
output [3:0]  be;
2237
output write;
2238 81 unneback
output read;
2239 75 unneback
output beginbursttransfer;
2240
output [3:0] burstcount;
2241
input readdatavalid;
2242
input waitrequest;
2243
input clk;
2244
input rst;
2245
wire [1:0] wbm_bte_o;
2246
wire [2:0] wbm_cti_o;
2247
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
2248
reg last_cyc;
2249 79 unneback
reg [3:0] counter;
2250 82 unneback
reg read_busy;
2251 75 unneback
always @ (posedge clk or posedge rst)
2252
if (rst)
2253
    last_cyc <= 1'b0;
2254
else
2255
    last_cyc <= wbm_cyc_o;
2256 79 unneback
always @ (posedge clk or posedge rst)
2257
if (rst)
2258 82 unneback
    read_busy <= 1'b0;
2259 79 unneback
else
2260 82 unneback
    if (read & !waitrequest)
2261
        read_busy <= 1'b1;
2262
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
2263
        read_busy <= 1'b0;
2264
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
2265 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
2266
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
2267
                    (wbm_bte_o==2'b10) ? 4'd8 :
2268 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
2269
                    4'd1;
2270 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
2271 79 unneback
always @ (posedge clk or posedge rst)
2272
if (rst) begin
2273
    counter <= 4'd0;
2274
end else
2275 80 unneback
    if (wbm_we_o) begin
2276
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
2277 85 unneback
            counter <= burstcount -4'd1;
2278 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
2279
            counter <= burstcount;
2280
        end else if (!waitrequest & wbm_stb_o) begin
2281
            counter <= counter - 4'd1;
2282
        end
2283 82 unneback
    end
2284 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
2285 77 unneback
vl_wb3wb3_bridge wbwb3inst (
2286 75 unneback
    // wishbone slave side
2287
    .wbs_dat_i(wbs_dat_i),
2288
    .wbs_adr_i(wbs_adr_i),
2289
    .wbs_sel_i(wbs_sel_i),
2290
    .wbs_bte_i(wbs_bte_i),
2291
    .wbs_cti_i(wbs_cti_i),
2292
    .wbs_we_i(wbs_we_i),
2293
    .wbs_cyc_i(wbs_cyc_i),
2294
    .wbs_stb_i(wbs_stb_i),
2295
    .wbs_dat_o(wbs_dat_o),
2296
    .wbs_ack_o(wbs_ack_o),
2297
    .wbs_clk(wbs_clk),
2298
    .wbs_rst(wbs_rst),
2299
    // wishbone master side
2300
    .wbm_dat_o(writedata),
2301 78 unneback
    .wbm_adr_o(address),
2302 75 unneback
    .wbm_sel_o(be),
2303
    .wbm_bte_o(wbm_bte_o),
2304
    .wbm_cti_o(wbm_cti_o),
2305
    .wbm_we_o(wbm_we_o),
2306
    .wbm_cyc_o(wbm_cyc_o),
2307
    .wbm_stb_o(wbm_stb_o),
2308
    .wbm_dat_i(readdata),
2309
    .wbm_ack_i(wbm_ack_i),
2310
    .wbm_clk(clk),
2311
    .wbm_rst(rst));
2312
endmodule
2313 39 unneback
module vl_wb3_arbiter_type1 (
2314
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
2315
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
2316
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
2317
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
2318
    wb_clk, wb_rst
2319
);
2320
parameter nr_of_ports = 3;
2321
parameter adr_size = 26;
2322
parameter adr_lo   = 2;
2323
parameter dat_size = 32;
2324
parameter sel_size = dat_size/8;
2325
localparam aw = (adr_size - adr_lo) * nr_of_ports;
2326
localparam dw = dat_size * nr_of_ports;
2327
localparam sw = sel_size * nr_of_ports;
2328
localparam cw = 3 * nr_of_ports;
2329
localparam bw = 2 * nr_of_ports;
2330
input  [dw-1:0] wbm_dat_o;
2331
input  [aw-1:0] wbm_adr_o;
2332
input  [sw-1:0] wbm_sel_o;
2333
input  [cw-1:0] wbm_cti_o;
2334
input  [bw-1:0] wbm_bte_o;
2335
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
2336
output [dw-1:0] wbm_dat_i;
2337
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
2338
output [dat_size-1:0] wbs_dat_i;
2339
output [adr_size-1:adr_lo] wbs_adr_i;
2340
output [sel_size-1:0] wbs_sel_i;
2341
output [2:0] wbs_cti_i;
2342
output [1:0] wbs_bte_i;
2343
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
2344
input  [dat_size-1:0] wbs_dat_o;
2345
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
2346
input wb_clk, wb_rst;
2347 44 unneback
reg  [nr_of_ports-1:0] select;
2348 39 unneback
wire [nr_of_ports-1:0] state;
2349
wire [nr_of_ports-1:0] eoc; // end-of-cycle
2350
wire [nr_of_ports-1:0] sel;
2351
wire idle;
2352
genvar i;
2353
assign idle = !(|state);
2354
generate
2355
if (nr_of_ports == 2) begin
2356
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
2357
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2358 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2359
    always @ (idle or wbm_cyc_o)
2360
    if (idle)
2361
        casex (wbm_cyc_o)
2362
        2'b1x : select = 2'b10;
2363
        2'b01 : select = 2'b01;
2364
        default : select = {nr_of_ports{1'b0}};
2365
        endcase
2366
    else
2367
        select = {nr_of_ports{1'b0}};
2368 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2369
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2370
end
2371
endgenerate
2372
generate
2373
if (nr_of_ports == 3) begin
2374
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2375
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2376 44 unneback
    always @ (idle or wbm_cyc_o)
2377
    if (idle)
2378
        casex (wbm_cyc_o)
2379
        3'b1xx : select = 3'b100;
2380
        3'b01x : select = 3'b010;
2381
        3'b001 : select = 3'b001;
2382
        default : select = {nr_of_ports{1'b0}};
2383
        endcase
2384
    else
2385
        select = {nr_of_ports{1'b0}};
2386
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2387 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
2388
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
2389
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
2390
end
2391
endgenerate
2392
generate
2393 44 unneback
if (nr_of_ports == 4) begin
2394
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
2395
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
2396
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
2397
    always @ (idle or wbm_cyc_o)
2398
    if (idle)
2399
        casex (wbm_cyc_o)
2400
        4'b1xxx : select = 4'b1000;
2401
        4'b01xx : select = 4'b0100;
2402
        4'b001x : select = 4'b0010;
2403
        4'b0001 : select = 4'b0001;
2404
        default : select = {nr_of_ports{1'b0}};
2405
        endcase
2406
    else
2407
        select = {nr_of_ports{1'b0}};
2408
    assign eoc[3] = (wbm_ack_i[3] &