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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
`timescale 1ns/1ns
45
`define MODULE wb_adr_inc
46 84 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
47 75 unneback
`undef MODULE
48 83 unneback
parameter adr_width = 10;
49
parameter max_burst_width = 4;
50 84 unneback
input cyc_i, stb_i, we_i;
51 83 unneback
input [2:0] cti_i;
52
input [1:0] bte_i;
53
input [adr_width-1:0] adr_i;
54
output [adr_width-1:0] adr_o;
55
output ack_o;
56
input clk, rst;
57 75 unneback
 
58 83 unneback
reg [adr_width-1:0] adr;
59 90 unneback
wire [max_burst_width-1:0] to_adr;
60 91 unneback
reg [max_burst_width-1:0] last_adr;
61 92 unneback
reg last_cycle;
62
localparam idle_or_eoc = 1'b0;
63
localparam cyc_or_ws   = 1'b1;
64 90 unneback
 
65 91 unneback
always @ (posedge clk or posedge rst)
66
if (rst)
67
    last_adr <= {max_burst_width{1'b0}};
68
else
69
    if (stb_i)
70 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
71 91 unneback
 
72 83 unneback
generate
73
if (max_burst_width==0) begin : inst_0
74 96 unneback
 
75
        reg ack_o;
76
        assign adr_o = adr_i;
77
        always @ (posedge clk or posedge rst)
78
        if (rst)
79
            ack_o <= 1'b0;
80
        else
81
            ack_o <= cyc_i & stb_i & !ack_o;
82
 
83 83 unneback
end else begin
84
 
85
    always @ (posedge clk or posedge rst)
86
    if (rst)
87 92 unneback
        last_cycle <= idle_or_eoc;
88 83 unneback
    else
89 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
90
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
91
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
92
                      cyc_or_ws; // cyc
93
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
94 84 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
95 91 unneback
                                        (!stb_i) ? last_adr :
96 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
97 84 unneback
                                        adr[max_burst_width-1:0];
98 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
99 96 unneback
 
100 83 unneback
end
101
endgenerate
102
 
103
generate
104
if (max_burst_width==2) begin : inst_2
105
    always @ (posedge clk or posedge rst)
106
    if (rst)
107
        adr <= 2'h0;
108
    else
109
        if (cyc_i & stb_i)
110
            adr[1:0] <= to_adr[1:0] + 2'd1;
111 75 unneback
        else
112 83 unneback
            adr <= to_adr[1:0];
113
end
114
endgenerate
115
 
116
generate
117
if (max_burst_width==3) begin : inst_3
118
    always @ (posedge clk or posedge rst)
119
    if (rst)
120
        adr <= 3'h0;
121
    else
122
        if (cyc_i & stb_i)
123
            case (bte_i)
124
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
125
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
126 75 unneback
            endcase
127 83 unneback
        else
128
            adr <= to_adr[2:0];
129
end
130
endgenerate
131
 
132
generate
133
if (max_burst_width==4) begin : inst_4
134
    always @ (posedge clk or posedge rst)
135
    if (rst)
136
        adr <= 4'h0;
137
    else
138 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
139 83 unneback
            case (bte_i)
140
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
141
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
142
            default: adr[3:0] <= to_adr + 4'd1;
143
            endcase
144
        else
145
            adr <= to_adr[3:0];
146
end
147
endgenerate
148
 
149
generate
150
if (adr_width > max_burst_width) begin : pass_through
151
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
152
end
153
endgenerate
154
 
155
endmodule
156 75 unneback
`endif
157
 
158 40 unneback
`ifdef WB3WB3_BRIDGE
159 12 unneback
// async wb3 - wb3 bridge
160
`timescale 1ns/1ns
161 40 unneback
`define MODULE wb3wb3_bridge
162
module `BASE`MODULE (
163
`undef MODULE
164 12 unneback
        // wishbone slave side
165
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
166
        // wishbone master side
167
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
168
 
169 94 unneback
parameter style = "FIFO"; // valid: simple, FIFO
170
parameter addr_width = 4;
171
 
172 12 unneback
input [31:0] wbs_dat_i;
173
input [31:2] wbs_adr_i;
174
input [3:0]  wbs_sel_i;
175
input [1:0]  wbs_bte_i;
176
input [2:0]  wbs_cti_i;
177
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
178
output [31:0] wbs_dat_o;
179 14 unneback
output wbs_ack_o;
180 12 unneback
input wbs_clk, wbs_rst;
181
 
182
output [31:0] wbm_dat_o;
183
output reg [31:2] wbm_adr_o;
184
output [3:0]  wbm_sel_o;
185
output reg [1:0]  wbm_bte_o;
186
output reg [2:0]  wbm_cti_o;
187 14 unneback
output reg wbm_we_o;
188
output wbm_cyc_o;
189 12 unneback
output wbm_stb_o;
190
input [31:0]  wbm_dat_i;
191
input wbm_ack_i;
192
input wbm_clk, wbm_rst;
193
 
194
// bte
195
parameter linear       = 2'b00;
196
parameter wrap4        = 2'b01;
197
parameter wrap8        = 2'b10;
198
parameter wrap16       = 2'b11;
199
// cti
200
parameter classic      = 3'b000;
201
parameter incburst     = 3'b010;
202
parameter endofburst   = 3'b111;
203
 
204 94 unneback
localparam wbs_adr  = 1'b0;
205
localparam wbs_data = 1'b1;
206 12 unneback
 
207 94 unneback
localparam wbm_adr0      = 2'b00;
208
localparam wbm_adr1      = 2'b01;
209
localparam wbm_data      = 2'b10;
210
localparam wbm_data_wait = 2'b11;
211 12 unneback
 
212
reg [1:0] wbs_bte_reg;
213
reg wbs;
214
wire wbs_eoc_alert, wbm_eoc_alert;
215
reg wbs_eoc, wbm_eoc;
216
reg [1:0] wbm;
217
 
218 14 unneback
wire [1:16] wbs_count, wbm_count;
219 12 unneback
 
220
wire [35:0] a_d, a_q, b_d, b_q;
221
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
222
reg a_rd_reg;
223
wire b_rd_adr, b_rd_data;
224 14 unneback
wire b_rd_data_reg;
225
wire [35:0] temp;
226 12 unneback
 
227
`define WE 5
228
`define BTE 4:3
229
`define CTI 2:0
230
 
231
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
232
always @ (posedge wbs_clk or posedge wbs_rst)
233
if (wbs_rst)
234
        wbs_eoc <= 1'b0;
235
else
236
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
237 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
238 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
239
                wbs_eoc <= 1'b1;
240
 
241 40 unneback
`define MODULE cnt_shreg_ce_clear
242
`BASE`MODULE # ( .length(16))
243
`undef MODULE
244 12 unneback
    cnt0 (
245
        .cke(wbs_ack_o),
246
        .clear(wbs_eoc),
247
        .q(wbs_count),
248
        .rst(wbs_rst),
249
        .clk(wbs_clk));
250
 
251
always @ (posedge wbs_clk or posedge wbs_rst)
252
if (wbs_rst)
253
        wbs <= wbs_adr;
254
else
255 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
256 12 unneback
                wbs <= wbs_data;
257
        else if (wbs_eoc & wbs_ack_o)
258
                wbs <= wbs_adr;
259
 
260
// wbs FIFO
261 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
262
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
263 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
264
              1'b0;
265
assign a_rd = !a_fifo_empty;
266
always @ (posedge wbs_clk or posedge wbs_rst)
267
if (wbs_rst)
268
        a_rd_reg <= 1'b0;
269
else
270
        a_rd_reg <= a_rd;
271
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
272
 
273
assign wbs_dat_o = a_q[35:4];
274
 
275
always @ (posedge wbs_clk or posedge wbs_rst)
276
if (wbs_rst)
277 13 unneback
        wbs_bte_reg <= 2'b00;
278 12 unneback
else
279 13 unneback
        wbs_bte_reg <= wbs_bte_i;
280 12 unneback
 
281
// wbm FIFO
282
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
283
always @ (posedge wbm_clk or posedge wbm_rst)
284
if (wbm_rst)
285
        wbm_eoc <= 1'b0;
286
else
287
        if (wbm==wbm_adr0 & !b_fifo_empty)
288
                wbm_eoc <= b_q[`BTE] == linear;
289
        else if (wbm_eoc_alert & wbm_ack_i)
290
                wbm_eoc <= 1'b1;
291
 
292
always @ (posedge wbm_clk or posedge wbm_rst)
293
if (wbm_rst)
294
        wbm <= wbm_adr0;
295
else
296 33 unneback
/*
297 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
298
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
299
        (wbm==wbm_adr1 & !wbm_we_o) |
300
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
301
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
302 33 unneback
*/
303
    case (wbm)
304
    wbm_adr0:
305
        if (!b_fifo_empty)
306
            wbm <= wbm_adr1;
307
    wbm_adr1:
308
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
309
            wbm <= wbm_data;
310
    wbm_data:
311
        if (wbm_ack_i & wbm_eoc)
312
            wbm <= wbm_adr0;
313
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
314
            wbm <= wbm_data_wait;
315
    wbm_data_wait:
316
        if (!b_fifo_empty)
317
            wbm <= wbm_data;
318
    endcase
319 12 unneback
 
320
assign b_d = {wbm_dat_i,4'b1111};
321
assign b_wr = !wbm_we_o & wbm_ack_i;
322
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
323
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
324
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
325 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
326 12 unneback
                   1'b0;
327
assign b_rd = b_rd_adr | b_rd_data;
328
 
329 40 unneback
`define MODULE dff
330
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
331
`undef MODULE
332
`define MODULE dff_ce
333
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
334
`undef MODULE
335 12 unneback
 
336
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
337
 
338 40 unneback
`define MODULE cnt_shreg_ce_clear
339 42 unneback
`BASE`MODULE # ( .length(16))
340 40 unneback
`undef MODULE
341 12 unneback
    cnt1 (
342
        .cke(wbm_ack_i),
343
        .clear(wbm_eoc),
344
        .q(wbm_count),
345
        .rst(wbm_rst),
346
        .clk(wbm_clk));
347
 
348 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
349
assign wbm_stb_o = (wbm==wbm_data);
350 12 unneback
 
351
always @ (posedge wbm_clk or posedge wbm_rst)
352
if (wbm_rst)
353
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
354
else begin
355
        if (wbm==wbm_adr0 & !b_fifo_empty)
356
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
357
        else if (wbm_eoc_alert & wbm_ack_i)
358
                wbm_cti_o <= endofburst;
359
end
360
 
361
//async_fifo_dw_simplex_top
362 40 unneback
`define MODULE fifo_2r2w_async_simplex
363
`BASE`MODULE
364
`undef MODULE
365 12 unneback
# ( .data_width(36), .addr_width(addr_width))
366
fifo (
367
    // a side
368
    .a_d(a_d),
369
    .a_wr(a_wr),
370
    .a_fifo_full(a_fifo_full),
371
    .a_q(a_q),
372
    .a_rd(a_rd),
373
    .a_fifo_empty(a_fifo_empty),
374
    .a_clk(wbs_clk),
375
    .a_rst(wbs_rst),
376
    // b side
377
    .b_d(b_d),
378
    .b_wr(b_wr),
379
    .b_fifo_full(b_fifo_full),
380
    .b_q(b_q),
381
    .b_rd(b_rd),
382
    .b_fifo_empty(b_fifo_empty),
383
    .b_clk(wbm_clk),
384
    .b_rst(wbm_rst)
385
    );
386
 
387
endmodule
388 40 unneback
`undef WE
389
`undef BTE
390
`undef CTI
391
`endif
392 17 unneback
 
393 75 unneback
`ifdef WB3AVALON_BRIDGE
394
`define MODULE wb3avalon_bridge
395
module `BASE`MODULE (
396
`undef MODULE
397
        // wishbone slave side
398
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
399 77 unneback
        // avalon master side
400 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
401
 
402 84 unneback
parameter linewrapburst = 1'b0;
403
 
404 75 unneback
input [31:0] wbs_dat_i;
405
input [31:2] wbs_adr_i;
406
input [3:0]  wbs_sel_i;
407
input [1:0]  wbs_bte_i;
408
input [2:0]  wbs_cti_i;
409 83 unneback
input wbs_we_i;
410
input wbs_cyc_i;
411
input wbs_stb_i;
412 75 unneback
output [31:0] wbs_dat_o;
413
output wbs_ack_o;
414
input wbs_clk, wbs_rst;
415
 
416
input [31:0] readdata;
417
output [31:0] writedata;
418
output [31:2] address;
419
output [3:0]  be;
420
output write;
421 81 unneback
output read;
422 75 unneback
output beginbursttransfer;
423
output [3:0] burstcount;
424
input readdatavalid;
425
input waitrequest;
426
input clk;
427
input rst;
428
 
429
wire [1:0] wbm_bte_o;
430
wire [2:0] wbm_cti_o;
431
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
432
reg last_cyc;
433 79 unneback
reg [3:0] counter;
434 82 unneback
reg read_busy;
435 75 unneback
 
436
always @ (posedge clk or posedge rst)
437
if (rst)
438
    last_cyc <= 1'b0;
439
else
440
    last_cyc <= wbm_cyc_o;
441
 
442 79 unneback
always @ (posedge clk or posedge rst)
443
if (rst)
444 82 unneback
    read_busy <= 1'b0;
445 79 unneback
else
446 82 unneback
    if (read & !waitrequest)
447
        read_busy <= 1'b1;
448
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
449
        read_busy <= 1'b0;
450
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
451 81 unneback
 
452 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
453
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
454
                    (wbm_bte_o==2'b10) ? 4'd8 :
455 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
456
                    4'd1;
457 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
458 75 unneback
 
459 79 unneback
always @ (posedge clk or posedge rst)
460
if (rst) begin
461
    counter <= 4'd0;
462
end else
463 80 unneback
    if (wbm_we_o) begin
464
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
465 84 unneback
            counter <= burstcount -4'd1;
466 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
467
            counter <= burstcount;
468
        end else if (!waitrequest & wbm_stb_o) begin
469
            counter <= counter - 4'd1;
470
        end
471 82 unneback
    end
472 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
473 79 unneback
 
474 75 unneback
`define MODULE wb3wb3_bridge
475 77 unneback
`BASE`MODULE wbwb3inst (
476 75 unneback
`undef MODULE
477
    // wishbone slave side
478
    .wbs_dat_i(wbs_dat_i),
479
    .wbs_adr_i(wbs_adr_i),
480
    .wbs_sel_i(wbs_sel_i),
481
    .wbs_bte_i(wbs_bte_i),
482
    .wbs_cti_i(wbs_cti_i),
483
    .wbs_we_i(wbs_we_i),
484
    .wbs_cyc_i(wbs_cyc_i),
485
    .wbs_stb_i(wbs_stb_i),
486
    .wbs_dat_o(wbs_dat_o),
487
    .wbs_ack_o(wbs_ack_o),
488
    .wbs_clk(wbs_clk),
489
    .wbs_rst(wbs_rst),
490
    // wishbone master side
491
    .wbm_dat_o(writedata),
492 78 unneback
    .wbm_adr_o(address),
493 75 unneback
    .wbm_sel_o(be),
494
    .wbm_bte_o(wbm_bte_o),
495
    .wbm_cti_o(wbm_cti_o),
496
    .wbm_we_o(wbm_we_o),
497
    .wbm_cyc_o(wbm_cyc_o),
498
    .wbm_stb_o(wbm_stb_o),
499
    .wbm_dat_i(readdata),
500
    .wbm_ack_i(wbm_ack_i),
501
    .wbm_clk(clk),
502
    .wbm_rst(rst));
503
 
504
 
505
endmodule
506
`endif
507
 
508 40 unneback
`ifdef WB3_ARBITER_TYPE1
509
`define MODULE wb3_arbiter_type1
510 42 unneback
module `BASE`MODULE (
511 40 unneback
`undef MODULE
512 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
513
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
514
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
515
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
516
    wb_clk, wb_rst
517
);
518
 
519
parameter nr_of_ports = 3;
520
parameter adr_size = 26;
521
parameter adr_lo   = 2;
522
parameter dat_size = 32;
523
parameter sel_size = dat_size/8;
524
 
525
localparam aw = (adr_size - adr_lo) * nr_of_ports;
526
localparam dw = dat_size * nr_of_ports;
527
localparam sw = sel_size * nr_of_ports;
528
localparam cw = 3 * nr_of_ports;
529
localparam bw = 2 * nr_of_ports;
530
 
531
input  [dw-1:0] wbm_dat_o;
532
input  [aw-1:0] wbm_adr_o;
533
input  [sw-1:0] wbm_sel_o;
534
input  [cw-1:0] wbm_cti_o;
535
input  [bw-1:0] wbm_bte_o;
536
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
537
output [dw-1:0] wbm_dat_i;
538
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
539
 
540
output [dat_size-1:0] wbs_dat_i;
541
output [adr_size-1:adr_lo] wbs_adr_i;
542
output [sel_size-1:0] wbs_sel_i;
543
output [2:0] wbs_cti_i;
544
output [1:0] wbs_bte_i;
545
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
546
input  [dat_size-1:0] wbs_dat_o;
547
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
548
 
549
input wb_clk, wb_rst;
550
 
551 44 unneback
reg  [nr_of_ports-1:0] select;
552 39 unneback
wire [nr_of_ports-1:0] state;
553
wire [nr_of_ports-1:0] eoc; // end-of-cycle
554
wire [nr_of_ports-1:0] sel;
555
wire idle;
556
 
557
genvar i;
558
 
559
assign idle = !(|state);
560
 
561
generate
562
if (nr_of_ports == 2) begin
563
 
564
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
565
 
566
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
567
 
568 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
569
 
570
    always @ (idle or wbm_cyc_o)
571
    if (idle)
572
        casex (wbm_cyc_o)
573
        2'b1x : select = 2'b10;
574
        2'b01 : select = 2'b01;
575
        default : select = {nr_of_ports{1'b0}};
576
        endcase
577
    else
578
        select = {nr_of_ports{1'b0}};
579
 
580 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
581
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
582
 
583
end
584
endgenerate
585
 
586
generate
587
if (nr_of_ports == 3) begin
588
 
589
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
590
 
591
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
592
 
593 44 unneback
    always @ (idle or wbm_cyc_o)
594
    if (idle)
595
        casex (wbm_cyc_o)
596
        3'b1xx : select = 3'b100;
597
        3'b01x : select = 3'b010;
598
        3'b001 : select = 3'b001;
599
        default : select = {nr_of_ports{1'b0}};
600
        endcase
601
    else
602
        select = {nr_of_ports{1'b0}};
603
 
604
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
605 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
606
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
607
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
608
 
609
end
610
endgenerate
611
 
612
generate
613 44 unneback
if (nr_of_ports == 4) begin
614
 
615
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
616
 
617
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
618
 
619
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
620
 
621
    always @ (idle or wbm_cyc_o)
622
    if (idle)
623
        casex (wbm_cyc_o)
624
        4'b1xxx : select = 4'b1000;
625
        4'b01xx : select = 4'b0100;
626
        4'b001x : select = 4'b0010;
627
        4'b0001 : select = 4'b0001;
628
        default : select = {nr_of_ports{1'b0}};
629
        endcase
630
    else
631
        select = {nr_of_ports{1'b0}};
632
 
633
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
634
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
635
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
636
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
637
 
638
end
639
endgenerate
640
 
641
generate
642
if (nr_of_ports == 5) begin
643
 
644
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
645
 
646
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
647
 
648
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
649
 
650
    always @ (idle or wbm_cyc_o)
651
    if (idle)
652
        casex (wbm_cyc_o)
653
        5'b1xxxx : select = 5'b10000;
654
        5'b01xxx : select = 5'b01000;
655
        5'b001xx : select = 5'b00100;
656
        5'b0001x : select = 5'b00010;
657
        5'b00001 : select = 5'b00001;
658
        default : select = {nr_of_ports{1'b0}};
659
        endcase
660
    else
661
        select = {nr_of_ports{1'b0}};
662
 
663
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
664
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
665
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
666
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
667
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
668
 
669
end
670
endgenerate
671
 
672
generate
673 67 unneback
if (nr_of_ports == 6) begin
674
 
675
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
676
 
677
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
678
 
679
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
680
 
681
    always @ (idle or wbm_cyc_o)
682
    if (idle)
683
        casex (wbm_cyc_o)
684
        6'b1xxxxx : select = 6'b100000;
685
        6'b01xxxx : select = 6'b010000;
686
        6'b001xxx : select = 6'b001000;
687
        6'b0001xx : select = 6'b000100;
688
        6'b00001x : select = 6'b000010;
689
        6'b000001 : select = 6'b000001;
690
        default : select = {nr_of_ports{1'b0}};
691
        endcase
692
    else
693
        select = {nr_of_ports{1'b0}};
694
 
695
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
696
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
697
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
698
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
699
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
700
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
701
 
702
end
703
endgenerate
704
 
705
generate
706
if (nr_of_ports == 7) begin
707
 
708
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
709
 
710
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
711
 
712
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
713
 
714
    always @ (idle or wbm_cyc_o)
715
    if (idle)
716
        casex (wbm_cyc_o)
717
        7'b1xxxxxx : select = 7'b1000000;
718
        7'b01xxxxx : select = 7'b0100000;
719
        7'b001xxxx : select = 7'b0010000;
720
        7'b0001xxx : select = 7'b0001000;
721
        7'b00001xx : select = 7'b0000100;
722
        7'b000001x : select = 7'b0000010;
723
        7'b0000001 : select = 7'b0000001;
724
        default : select = {nr_of_ports{1'b0}};
725
        endcase
726
    else
727
        select = {nr_of_ports{1'b0}};
728
 
729
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
730
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
731
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
732
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
733
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
734
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
735
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
736
 
737
end
738
endgenerate
739
 
740
generate
741
if (nr_of_ports == 8) begin
742
 
743
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
744
 
745
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
746
 
747
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
748
 
749
    always @ (idle or wbm_cyc_o)
750
    if (idle)
751
        casex (wbm_cyc_o)
752
        8'b1xxxxxxx : select = 8'b10000000;
753
        8'b01xxxxxx : select = 8'b01000000;
754
        8'b001xxxxx : select = 8'b00100000;
755
        8'b0001xxxx : select = 8'b00010000;
756
        8'b00001xxx : select = 8'b00001000;
757
        8'b000001xx : select = 8'b00000100;
758
        8'b0000001x : select = 8'b00000010;
759
        8'b00000001 : select = 8'b00000001;
760
        default : select = {nr_of_ports{1'b0}};
761
        endcase
762
    else
763
        select = {nr_of_ports{1'b0}};
764
 
765
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
766
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
767
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
768
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
769
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
770
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
771
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
772
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
773
 
774
end
775
endgenerate
776
 
777
generate
778 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
779 42 unneback
`define MODULE spr
780
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
781
`undef MODULE
782 39 unneback
end
783
endgenerate
784
 
785
    assign sel = select | state;
786
 
787 40 unneback
`define MODULE mux_andor
788
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
789
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
790
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
791
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
792
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
793
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
794
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
795
`undef MODULE
796 39 unneback
    assign wbs_cyc_i = |sel;
797
 
798
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
799
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
800
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
801
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
802
 
803
endmodule
804 40 unneback
`endif
805 39 unneback
 
806 60 unneback
`ifdef WB_B3_RAM_BE
807 49 unneback
// WB RAM with byte enable
808 59 unneback
`define MODULE wb_b3_ram_be
809
module `BASE`MODULE (
810
`undef MODULE
811 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
812
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
813 59 unneback
 
814 68 unneback
parameter adr_size = 16;
815 84 unneback
parameter mem_size = 1<<adr_size;
816 60 unneback
parameter dat_size = 32;
817 83 unneback
parameter max_burst_width = 4;
818 60 unneback
parameter memory_init = 1;
819
parameter memory_file = "vl_ram.vmem";
820 59 unneback
 
821 84 unneback
localparam aw = (adr_size);
822 69 unneback
localparam dw = dat_size;
823
localparam sw = dat_size/8;
824
localparam cw = 3;
825
localparam bw = 2;
826 60 unneback
 
827 70 unneback
input [dw-1:0] wbs_dat_i;
828
input [aw-1:0] wbs_adr_i;
829
input [cw-1:0] wbs_cti_i;
830
input [bw-1:0] wbs_bte_i;
831
input [sw-1:0] wbs_sel_i;
832
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
833
output [dw-1:0] wbs_dat_o;
834
output wbs_ack_o;
835 71 unneback
input wb_clk, wb_rst;
836 59 unneback
 
837 83 unneback
wire [aw-1:0] adr;
838 59 unneback
 
839 60 unneback
`define MODULE ram_be
840
`BASE`MODULE # (
841
    .data_width(dat_size),
842 83 unneback
    .addr_width(aw),
843 69 unneback
    .mem_size(mem_size),
844 68 unneback
    .memory_init(memory_init),
845
    .memory_file(memory_file))
846 60 unneback
ram0(
847
`undef MODULE
848
    .d(wbs_dat_i),
849 83 unneback
    .adr(adr),
850 60 unneback
    .be(wbs_sel_i),
851 86 unneback
    .we(wbs_we_i & wbs_ack_o),
852 60 unneback
    .q(wbs_dat_o),
853
    .clk(wb_clk)
854
);
855
 
856 83 unneback
`define MODULE wb_adr_inc
857
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
858
    .cyc_i(wbs_cyc_i),
859
    .stb_i(wbs_stb_i),
860
    .cti_i(wbs_cti_i),
861
    .bte_i(wbs_bte_i),
862
    .adr_i(wbs_adr_i),
863 84 unneback
    .we_i(wbs_we_i),
864 83 unneback
    .ack_o(wbs_ack_o),
865
    .adr_o(adr),
866
    .clk(wb_clk),
867
    .rst(wb_rst));
868
`undef MODULE
869 60 unneback
 
870 59 unneback
endmodule
871
`endif
872
 
873
`ifdef WB_B4_RAM_BE
874
// WB RAM with byte enable
875 49 unneback
`define MODULE wb_b4_ram_be
876
module `BASE`MODULE (
877
`undef MODULE
878
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
879 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
880 49 unneback
 
881 100 unneback
parameter dat_width = 32;
882
parameter adr_width = 8;
883
parameter mem_size = 1<<adr_width;
884
parameter memory_init = 0;
885
parameter memory_file = "vl_ram.v";
886
parameter debug = 0;
887 49 unneback
 
888
input [dat_width-1:0] wb_dat_i;
889
input [adr_width-1:0] wb_adr_i;
890
input [dat_width/8-1:0] wb_sel_i;
891
input wb_we_i, wb_stb_i, wb_cyc_i;
892
output [dat_width-1:0] wb_dat_o;
893 52 unneback
output wb_stall_o;
894 49 unneback
output wb_ack_o;
895
reg wb_ack_o;
896
input wb_clk, wb_rst;
897
 
898 56 unneback
wire [dat_width/8-1:0] cke;
899
 
900 100 unneback
`define MODULE ram_be
901
`BASE`MODULE # (
902
    .data_width(dat_width),
903
    .addr_width(adr_width),
904
    .mem_size(mem_size),
905
    .memory_init(memory_init),
906
    .memory_file(memory_file))
907
ram0(
908
`undef MODULE
909
    .d(wb_dat_i),
910
    .adr(wb_adr_i),
911
    .be(wb_sel_i),
912
    .we(wb_we_i & wb_stb_i & wb_cyc_i),
913
    .q(wb_dat_o),
914
    .clk(wb_clk)
915
);
916 49 unneback
 
917 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
918 55 unneback
if (wb_rst)
919 52 unneback
    wb_ack_o <= 1'b0;
920
else
921 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
922 52 unneback
 
923
assign wb_stall_o = 1'b0;
924
 
925 49 unneback
endmodule
926
`endif
927
 
928 48 unneback
`ifdef WB_B4_ROM
929
// WB ROM
930
`define MODULE wb_b4_rom
931
module `BASE`MODULE (
932
`undef MODULE
933
    wb_adr_i, wb_stb_i, wb_cyc_i,
934
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
935
 
936
    parameter dat_width = 32;
937
    parameter dat_default = 32'h15000000;
938
    parameter adr_width = 32;
939
 
940
/*
941
//E2_ifndef ROM
942
//E2_define ROM "rom.v"
943
//E2_endif
944
*/
945
    input [adr_width-1:2]   wb_adr_i;
946
    input                   wb_stb_i;
947
    input                   wb_cyc_i;
948
    output [dat_width-1:0]  wb_dat_o;
949
    reg [dat_width-1:0]     wb_dat_o;
950
    output                  wb_ack_o;
951
    reg                     wb_ack_o;
952
    output                  stall_o;
953
    input                   wb_clk;
954
    input                   wb_rst;
955
 
956
always @ (posedge wb_clk or posedge wb_rst)
957
    if (wb_rst)
958
        wb_dat_o <= {dat_width{1'b0}};
959
    else
960
         case (wb_adr_i[adr_width-1:2])
961
//E2_ifdef ROM
962
//E2_include `ROM
963
//E2_endif
964
           default:
965
             wb_dat_o <= dat_default;
966
 
967
         endcase // case (wb_adr_i)
968
 
969
 
970
always @ (posedge wb_clk or posedge wb_rst)
971
    if (wb_rst)
972
        wb_ack_o <= 1'b0;
973
    else
974
        wb_ack_o <= wb_stb_i & wb_cyc_i;
975
 
976
assign stall_o = 1'b0;
977
 
978
endmodule
979
`endif
980
 
981
 
982 40 unneback
`ifdef WB_BOOT_ROM
983 17 unneback
// WB ROM
984 40 unneback
`define MODULE wb_boot_rom
985
module `BASE`MODULE (
986
`undef MODULE
987 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
988 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
989 17 unneback
 
990 18 unneback
    parameter adr_hi = 31;
991
    parameter adr_lo = 28;
992
    parameter adr_sel = 4'hf;
993
    parameter addr_width = 5;
994 33 unneback
/*
995 17 unneback
//E2_ifndef BOOT_ROM
996
//E2_define BOOT_ROM "boot_rom.v"
997
//E2_endif
998 33 unneback
*/
999 18 unneback
    input [adr_hi:2]    wb_adr_i;
1000
    input               wb_stb_i;
1001
    input               wb_cyc_i;
1002
    output [31:0]        wb_dat_o;
1003
    output              wb_ack_o;
1004
    output              hit_o;
1005
    input               wb_clk;
1006
    input               wb_rst;
1007
 
1008
    wire hit;
1009
    reg [31:0] wb_dat;
1010
    reg wb_ack;
1011
 
1012
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1013 17 unneback
 
1014
always @ (posedge wb_clk or posedge wb_rst)
1015
    if (wb_rst)
1016 18 unneback
        wb_dat <= 32'h15000000;
1017 17 unneback
    else
1018 18 unneback
         case (wb_adr_i[addr_width-1:2])
1019 33 unneback
//E2_ifdef BOOT_ROM
1020 17 unneback
//E2_include `BOOT_ROM
1021 33 unneback
//E2_endif
1022 17 unneback
           /*
1023
            // Zero r0 and jump to 0x00000100
1024 18 unneback
 
1025
            1 : wb_dat <= 32'hA8200000;
1026
            2 : wb_dat <= 32'hA8C00100;
1027
            3 : wb_dat <= 32'h44003000;
1028
            4 : wb_dat <= 32'h15000000;
1029 17 unneback
            */
1030
           default:
1031 18 unneback
             wb_dat <= 32'h00000000;
1032 17 unneback
 
1033
         endcase // case (wb_adr_i)
1034
 
1035
 
1036
always @ (posedge wb_clk or posedge wb_rst)
1037
    if (wb_rst)
1038 18 unneback
        wb_ack <= 1'b0;
1039 17 unneback
    else
1040 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1041 17 unneback
 
1042 18 unneback
assign hit_o = hit;
1043
assign wb_dat_o = wb_dat & {32{wb_ack}};
1044
assign wb_ack_o = wb_ack;
1045
 
1046 17 unneback
endmodule
1047 40 unneback
`endif
1048 32 unneback
 
1049 92 unneback
`ifdef WB_B3_DPRAM
1050
`define MODULE wb_b3_dpram
1051 40 unneback
module `BASE`MODULE (
1052
`undef MODULE
1053 32 unneback
        // wishbone slave side a
1054 92 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1055 32 unneback
        wbsa_clk, wbsa_rst,
1056 92 unneback
        // wishbone slave side b
1057
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1058 32 unneback
        wbsb_clk, wbsb_rst);
1059
 
1060 92 unneback
parameter data_width_a = 32;
1061
parameter data_width_b = data_width_a;
1062
parameter addr_width_a = 8;
1063
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
1064
   parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
1065
parameter max_burst_width_a = 4;
1066
parameter max_burst_width_b = max_burst_width_a;
1067 32 unneback
 
1068 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
1069
input [addr_width_a-1:0] wbsa_adr_i;
1070
input [data_width_a/8-1:0] wbsa_sel_i;
1071
input [2:0] wbsa_cti_i;
1072
input [1:0] wbsa_bte_i;
1073 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1074 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
1075 32 unneback
output wbsa_ack_o;
1076
input wbsa_clk, wbsa_rst;
1077
 
1078 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
1079
input [addr_width_b-1:0] wbsb_adr_i;
1080
input [data_width_b/8-1:0] wbsb_sel_i;
1081
input [2:0] wbsb_cti_i;
1082
input [1:0] wbsb_bte_i;
1083 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1084 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
1085 32 unneback
output wbsb_ack_o;
1086
input wbsb_clk, wbsb_rst;
1087
 
1088 92 unneback
wire [addr_width_a-1:0] adr_a;
1089
wire [addr_width_b-1:0] adr_b;
1090 32 unneback
 
1091 92 unneback
`define MODULE wb_adr_inc
1092
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
1093
    .cyc_i(wbsa_cyc_i),
1094
    .stb_i(wbsa_stb_i),
1095
    .cti_i(wbsa_cti_i),
1096
    .bte_i(wbsa_bte_i),
1097
    .adr_i(wbsa_adr_i),
1098
    .we_i(wbsa_we_i),
1099
    .ack_o(wbsa_ack_o),
1100
    .adr_o(adr_a),
1101
    .clk(wbsa_clk),
1102
    .rst(wbsa_rst));
1103
 
1104
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
1105
    .cyc_i(wbsb_cyc_i),
1106
    .stb_i(wbsb_stb_i),
1107
    .cti_i(wbsb_cti_i),
1108
    .bte_i(wbsb_bte_i),
1109
    .adr_i(wbsb_adr_i),
1110
    .we_i(wbsb_we_i),
1111
    .ack_o(wbsb_ack_o),
1112
    .adr_o(adr_b),
1113
    .clk(wbsb_clk),
1114
    .rst(wbsb_rst));
1115 40 unneback
`undef MODULE
1116 92 unneback
 
1117
`define MODULE dpram_be_2r2w
1118
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
1119
`undef MODULE
1120
ram_i (
1121 32 unneback
    .d_a(wbsa_dat_i),
1122 92 unneback
    .q_a(wbsa_dat_o),
1123
    .adr_a(adr_a),
1124
    .be_a(wbsa_sel_i),
1125
    .we_a(wbsa_we_i & wbsa_ack_o),
1126 32 unneback
    .clk_a(wbsa_clk),
1127
    .d_b(wbsb_dat_i),
1128 92 unneback
    .q_b(wbsb_dat_o),
1129
    .adr_b(adr_b),
1130
    .be_b(wbsb_sel_i),
1131
    .we_b(wbsb_we_i & wbsb_ack_o),
1132 32 unneback
    .clk_b(wbsb_clk) );
1133
 
1134
endmodule
1135 40 unneback
`endif
1136 94 unneback
 
1137 96 unneback
`ifdef WBB3_WBB4_CACHE
1138
`define MODULE wbb3_wbb4_cache
1139
module `BASE`MODULE (
1140 98 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1141
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
1142 96 unneback
);
1143
`undef MODULE
1144
 
1145
parameter dw_s = 32;
1146
parameter aw_s = 24;
1147
parameter dw_m = dw_s;
1148 100 unneback
localparam aw_m = dw_s * aw_s / dw_m;
1149
parameter wbs_max_burst_width = 4;
1150 96 unneback
 
1151 97 unneback
parameter async = 1; // wbs_clk != wbm_clk
1152
 
1153 96 unneback
parameter nr_of_ways = 1;
1154 97 unneback
parameter aw_offset = 4; // 4 => 16 words per cache line
1155
parameter aw_slot = 10;
1156 100 unneback
 
1157
parameter valid_mem = 0;
1158
parameter debug = 0;
1159
 
1160
localparam aw_b_offset = aw_offset * dw_s / dw_m;
1161 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
1162 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
1163 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
1164 97 unneback
`define SIZE2WIDTH wbm_burst_size
1165
localparam wbm_burst_width `SIZE2WIDTH_EXPR
1166
`undef SIZE2WIDTH
1167
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
1168
`define SIZE2WIDTH nr_of_wbm_burst
1169
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
1170
`undef SIZE2WIDTH
1171 100 unneback
 
1172 96 unneback
input [dw_s-1:0] wbs_dat_i;
1173
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
1174 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
1175 96 unneback
input [2:0] wbs_cti_i;
1176
input [1:0] wbs_bte_i;
1177 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
1178 96 unneback
output [dw_s-1:0] wbs_dat_o;
1179
output wbs_ack_o;
1180
input wbs_clk, wbs_rst;
1181
 
1182
output [dw_m-1:0] wbm_dat_o;
1183
output [aw_m-1:0] wbm_adr_o;
1184
output [dw_m/8-1:0] wbm_sel_o;
1185
output [2:0] wbm_cti_o;
1186
output [1:0] wbm_bte_o;
1187 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
1188 96 unneback
input [dw_m-1:0] wbm_dat_i;
1189
input wbm_ack_i;
1190
input wbm_stall_i;
1191
input wbm_clk, wbm_rst;
1192
 
1193 100 unneback
wire valid, dirty, hit;
1194 97 unneback
wire [aw_tag-1:0] tag;
1195
wire tag_mem_we;
1196
wire [aw_tag-1:0] wbs_adr_tag;
1197
wire [aw_slot-1:0] wbs_adr_slot;
1198 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
1199
wire [aw_s-1:0] wbs_adr;
1200 96 unneback
 
1201 97 unneback
reg [1:0] state;
1202
localparam idle = 2'h0;
1203
localparam rdwr = 2'h1;
1204
localparam push = 2'h2;
1205
localparam pull = 2'h3;
1206
wire eoc;
1207
 
1208
// cdc
1209
wire done, mem_alert, mem_done;
1210
 
1211 98 unneback
// wbm side
1212
reg [aw_m-1:0] wbm_radr;
1213
reg [aw_m-1:0] wbm_wadr;
1214 100 unneback
wire [aw_slot-1:0] wbm_adr;
1215 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
1216
 
1217 100 unneback
reg [2:0] phase;
1218
// phase = {we,stb,cyc}
1219
localparam wbm_wait     = 3'b000;
1220
localparam wbm_wr       = 3'b111;
1221
localparam wbm_wr_drain = 3'b101;
1222
localparam wbm_rd       = 3'b011;
1223
localparam wbm_rd_drain = 3'b001;
1224 98 unneback
 
1225 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
1226
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
1227
 
1228 100 unneback
generate
1229
if (valid_mem==0) begin : no_valid_mem
1230
assign valid = 1'b1;
1231
end else begin : valid_mem_inst
1232
`define MODULE dpram_1r1w
1233 97 unneback
`BASE`MODULE
1234 100 unneback
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
1235
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
1236
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
1237 97 unneback
`undef MODULE
1238 100 unneback
end
1239
endgenerate
1240 97 unneback
 
1241 100 unneback
`define MODULE dpram_1r1w
1242
`BASE`MODULE
1243
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
1244
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
1245
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
1246
assign hit = wbs_adr_tag == tag;
1247
`undef MODULE
1248
 
1249
`define MODULE dpram_1r2w
1250
`BASE`MODULE
1251
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
1252
    dirty_mem (
1253
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
1254
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
1255
`undef MODULE
1256
 
1257 96 unneback
`define MODULE wb_adr_inc
1258 100 unneback
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
1259
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
1260
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
1261 96 unneback
    .cti_i(wbs_cti_i),
1262
    .bte_i(wbs_bte_i),
1263
    .adr_i(wbs_adr_i),
1264 97 unneback
    .we_i (wbs_we_i),
1265 96 unneback
    .ack_o(wbs_ack_o),
1266 97 unneback
    .adr_o(wbs_adr),
1267 100 unneback
    .clk(wbs_clk),
1268
    .rst(wbs_rst));
1269 96 unneback
`undef MODULE
1270
 
1271 97 unneback
`define MODULE dpram_be_2r2w
1272
`BASE`MODULE
1273 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
1274
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(wbs_cyc_i &  wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
1275
                .d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
1276
//                .d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
1277 97 unneback
`undef MODULE
1278
 
1279
always @ (posedge wbs_clk or posedge wbs_rst)
1280
if (wbs_rst)
1281 98 unneback
    state <= idle;
1282 97 unneback
else
1283
    case (state)
1284
    idle:
1285
        if (wbs_cyc_i)
1286
            state <= rdwr;
1287
    rdwr:
1288 100 unneback
        casex ({valid, hit, dirty, eoc})
1289
        4'b0xxx: state <= pull;
1290
        4'b11x1: state <= idle;
1291
        4'b101x: state <= push;
1292
        4'b100x: state <= pull;
1293
        endcase
1294 97 unneback
    push:
1295
        if (done)
1296
            state <= rdwr;
1297
    pull:
1298
        if (done)
1299
            state <= rdwr;
1300
    default: state <= idle;
1301
    endcase
1302
 
1303
// cdc
1304
generate
1305
if (async==1) begin : cdc0
1306
`define MODULE cdc
1307 100 unneback
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
1308 97 unneback
`undef MODULE
1309
end
1310
else begin : nocdc
1311 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
1312 97 unneback
    assign done = mem_done;
1313
end
1314
endgenerate
1315
 
1316
// FSM generating a number of burts 4 cycles
1317
// actual number depends on data width ratio
1318
// nr_of_wbm_burst
1319 100 unneback
reg [wbm_burst_width-1:0]       cnt_rw, cnt_ack;
1320 97 unneback
 
1321
always @ (posedge wbm_clk or posedge wbm_rst)
1322
if (wbm_rst)
1323 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
1324 97 unneback
else
1325 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
1326
        cnt_rw <= cnt_rw + 1;
1327 97 unneback
 
1328 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1329
if (wbm_rst)
1330 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
1331 98 unneback
else
1332 100 unneback
    if (wbm_ack_i)
1333
        cnt_ack <= cnt_ack + 1;
1334 97 unneback
 
1335 100 unneback
generate
1336
if (nr_of_wbm_burst_width==0) begin : one_burst
1337
 
1338 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1339
if (wbm_rst)
1340
    phase <= wbm_wait;
1341
else
1342
    case (phase)
1343
    wbm_wait:
1344
        if (mem_alert)
1345 100 unneback
            if (state==push)
1346
                phase <= wbm_wr;
1347
            else
1348
                phase <= wbm_rd;
1349 98 unneback
    wbm_wr:
1350 100 unneback
        if (&cnt_rw)
1351
            phase <= wbm_wr_drain;
1352
    wbm_wr_drain:
1353
        if (&cnt_ack)
1354 98 unneback
            phase <= wbm_rd;
1355
    wbm_rd:
1356 100 unneback
        if (&cnt_rw)
1357
            phase <= wbm_rd_drain;
1358
    wbm_rd_drain:
1359
        if (&cnt_ack)
1360
            phase <= wbm_wait;
1361 98 unneback
    default: phase <= wbm_wait;
1362
    endcase
1363
 
1364 100 unneback
    assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
1365
 
1366
end else begin : multiple_burst
1367
 
1368
reg [nr_of_wbm_burst_width-1:0] cnt_burst;
1369
 
1370
end
1371
endgenerate
1372
 
1373
 
1374
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
1375
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
1376
assign wbm_sel_o = {dw_m/8{1'b1}};
1377
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
1378 98 unneback
assign wbm_bte_o = bte;
1379 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
1380 98 unneback
 
1381 96 unneback
endmodule
1382
`endif

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