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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
`timescale 1ns/1ns
45
`define MODULE wb_adr_inc
46 84 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
47 75 unneback
`undef MODULE
48 83 unneback
parameter adr_width = 10;
49
parameter max_burst_width = 4;
50 84 unneback
input cyc_i, stb_i, we_i;
51 83 unneback
input [2:0] cti_i;
52
input [1:0] bte_i;
53
input [adr_width-1:0] adr_i;
54
output [adr_width-1:0] adr_o;
55
output ack_o;
56
input clk, rst;
57 75 unneback
 
58 83 unneback
reg [adr_width-1:0] adr;
59 90 unneback
wire [max_burst_width-1:0] to_adr;
60 91 unneback
reg [max_burst_width-1:0] last_adr;
61 92 unneback
reg last_cycle;
62
localparam idle_or_eoc = 1'b0;
63
localparam cyc_or_ws   = 1'b1;
64 90 unneback
 
65 91 unneback
always @ (posedge clk or posedge rst)
66
if (rst)
67
    last_adr <= {max_burst_width{1'b0}};
68
else
69
    if (stb_i)
70 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
71 91 unneback
 
72 83 unneback
generate
73
if (max_burst_width==0) begin : inst_0
74 96 unneback
 
75
        reg ack_o;
76
        assign adr_o = adr_i;
77
        always @ (posedge clk or posedge rst)
78
        if (rst)
79
            ack_o <= 1'b0;
80
        else
81
            ack_o <= cyc_i & stb_i & !ack_o;
82
 
83 83 unneback
end else begin
84
 
85
    always @ (posedge clk or posedge rst)
86
    if (rst)
87 92 unneback
        last_cycle <= idle_or_eoc;
88 83 unneback
    else
89 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
90
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
91
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
92
                      cyc_or_ws; // cyc
93
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
94 84 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
95 91 unneback
                                        (!stb_i) ? last_adr :
96 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
97 84 unneback
                                        adr[max_burst_width-1:0];
98 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
99 96 unneback
 
100 83 unneback
end
101
endgenerate
102
 
103
generate
104
if (max_burst_width==2) begin : inst_2
105
    always @ (posedge clk or posedge rst)
106
    if (rst)
107
        adr <= 2'h0;
108
    else
109
        if (cyc_i & stb_i)
110
            adr[1:0] <= to_adr[1:0] + 2'd1;
111 75 unneback
        else
112 83 unneback
            adr <= to_adr[1:0];
113
end
114
endgenerate
115
 
116
generate
117
if (max_burst_width==3) begin : inst_3
118
    always @ (posedge clk or posedge rst)
119
    if (rst)
120
        adr <= 3'h0;
121
    else
122
        if (cyc_i & stb_i)
123
            case (bte_i)
124
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
125
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
126 75 unneback
            endcase
127 83 unneback
        else
128
            adr <= to_adr[2:0];
129
end
130
endgenerate
131
 
132
generate
133
if (max_burst_width==4) begin : inst_4
134
    always @ (posedge clk or posedge rst)
135
    if (rst)
136
        adr <= 4'h0;
137
    else
138 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
139 83 unneback
            case (bte_i)
140
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
141
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
142
            default: adr[3:0] <= to_adr + 4'd1;
143
            endcase
144
        else
145
            adr <= to_adr[3:0];
146
end
147
endgenerate
148
 
149
generate
150
if (adr_width > max_burst_width) begin : pass_through
151
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
152
end
153
endgenerate
154
 
155
endmodule
156 75 unneback
`endif
157
 
158 40 unneback
`ifdef WB3WB3_BRIDGE
159 12 unneback
// async wb3 - wb3 bridge
160
`timescale 1ns/1ns
161 40 unneback
`define MODULE wb3wb3_bridge
162
module `BASE`MODULE (
163
`undef MODULE
164 12 unneback
        // wishbone slave side
165
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
166
        // wishbone master side
167
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
168
 
169 94 unneback
parameter style = "FIFO"; // valid: simple, FIFO
170
parameter addr_width = 4;
171
 
172 12 unneback
input [31:0] wbs_dat_i;
173
input [31:2] wbs_adr_i;
174
input [3:0]  wbs_sel_i;
175
input [1:0]  wbs_bte_i;
176
input [2:0]  wbs_cti_i;
177
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
178
output [31:0] wbs_dat_o;
179 14 unneback
output wbs_ack_o;
180 12 unneback
input wbs_clk, wbs_rst;
181
 
182
output [31:0] wbm_dat_o;
183
output reg [31:2] wbm_adr_o;
184
output [3:0]  wbm_sel_o;
185
output reg [1:0]  wbm_bte_o;
186
output reg [2:0]  wbm_cti_o;
187 14 unneback
output reg wbm_we_o;
188
output wbm_cyc_o;
189 12 unneback
output wbm_stb_o;
190
input [31:0]  wbm_dat_i;
191
input wbm_ack_i;
192
input wbm_clk, wbm_rst;
193
 
194
// bte
195
parameter linear       = 2'b00;
196
parameter wrap4        = 2'b01;
197
parameter wrap8        = 2'b10;
198
parameter wrap16       = 2'b11;
199
// cti
200
parameter classic      = 3'b000;
201
parameter incburst     = 3'b010;
202
parameter endofburst   = 3'b111;
203
 
204 94 unneback
localparam wbs_adr  = 1'b0;
205
localparam wbs_data = 1'b1;
206 12 unneback
 
207 94 unneback
localparam wbm_adr0      = 2'b00;
208
localparam wbm_adr1      = 2'b01;
209
localparam wbm_data      = 2'b10;
210
localparam wbm_data_wait = 2'b11;
211 12 unneback
 
212
reg [1:0] wbs_bte_reg;
213
reg wbs;
214
wire wbs_eoc_alert, wbm_eoc_alert;
215
reg wbs_eoc, wbm_eoc;
216
reg [1:0] wbm;
217
 
218 14 unneback
wire [1:16] wbs_count, wbm_count;
219 12 unneback
 
220
wire [35:0] a_d, a_q, b_d, b_q;
221
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
222
reg a_rd_reg;
223
wire b_rd_adr, b_rd_data;
224 14 unneback
wire b_rd_data_reg;
225
wire [35:0] temp;
226 12 unneback
 
227
`define WE 5
228
`define BTE 4:3
229
`define CTI 2:0
230
 
231
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
232
always @ (posedge wbs_clk or posedge wbs_rst)
233
if (wbs_rst)
234
        wbs_eoc <= 1'b0;
235
else
236
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
237 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
238 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
239
                wbs_eoc <= 1'b1;
240
 
241 40 unneback
`define MODULE cnt_shreg_ce_clear
242
`BASE`MODULE # ( .length(16))
243
`undef MODULE
244 12 unneback
    cnt0 (
245
        .cke(wbs_ack_o),
246
        .clear(wbs_eoc),
247
        .q(wbs_count),
248
        .rst(wbs_rst),
249
        .clk(wbs_clk));
250
 
251
always @ (posedge wbs_clk or posedge wbs_rst)
252
if (wbs_rst)
253
        wbs <= wbs_adr;
254
else
255 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
256 12 unneback
                wbs <= wbs_data;
257
        else if (wbs_eoc & wbs_ack_o)
258
                wbs <= wbs_adr;
259
 
260
// wbs FIFO
261 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
262
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
263 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
264
              1'b0;
265
assign a_rd = !a_fifo_empty;
266
always @ (posedge wbs_clk or posedge wbs_rst)
267
if (wbs_rst)
268
        a_rd_reg <= 1'b0;
269
else
270
        a_rd_reg <= a_rd;
271
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
272
 
273
assign wbs_dat_o = a_q[35:4];
274
 
275
always @ (posedge wbs_clk or posedge wbs_rst)
276
if (wbs_rst)
277 13 unneback
        wbs_bte_reg <= 2'b00;
278 12 unneback
else
279 13 unneback
        wbs_bte_reg <= wbs_bte_i;
280 12 unneback
 
281
// wbm FIFO
282
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
283
always @ (posedge wbm_clk or posedge wbm_rst)
284
if (wbm_rst)
285
        wbm_eoc <= 1'b0;
286
else
287
        if (wbm==wbm_adr0 & !b_fifo_empty)
288
                wbm_eoc <= b_q[`BTE] == linear;
289
        else if (wbm_eoc_alert & wbm_ack_i)
290
                wbm_eoc <= 1'b1;
291
 
292
always @ (posedge wbm_clk or posedge wbm_rst)
293
if (wbm_rst)
294
        wbm <= wbm_adr0;
295
else
296 33 unneback
/*
297 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
298
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
299
        (wbm==wbm_adr1 & !wbm_we_o) |
300
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
301
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
302 33 unneback
*/
303
    case (wbm)
304
    wbm_adr0:
305
        if (!b_fifo_empty)
306
            wbm <= wbm_adr1;
307
    wbm_adr1:
308
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
309
            wbm <= wbm_data;
310
    wbm_data:
311
        if (wbm_ack_i & wbm_eoc)
312
            wbm <= wbm_adr0;
313
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
314
            wbm <= wbm_data_wait;
315
    wbm_data_wait:
316
        if (!b_fifo_empty)
317
            wbm <= wbm_data;
318
    endcase
319 12 unneback
 
320
assign b_d = {wbm_dat_i,4'b1111};
321
assign b_wr = !wbm_we_o & wbm_ack_i;
322
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
323
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
324
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
325 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
326 12 unneback
                   1'b0;
327
assign b_rd = b_rd_adr | b_rd_data;
328
 
329 40 unneback
`define MODULE dff
330
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
331
`undef MODULE
332
`define MODULE dff_ce
333
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
334
`undef MODULE
335 12 unneback
 
336
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
337
 
338 40 unneback
`define MODULE cnt_shreg_ce_clear
339 42 unneback
`BASE`MODULE # ( .length(16))
340 40 unneback
`undef MODULE
341 12 unneback
    cnt1 (
342
        .cke(wbm_ack_i),
343
        .clear(wbm_eoc),
344
        .q(wbm_count),
345
        .rst(wbm_rst),
346
        .clk(wbm_clk));
347
 
348 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
349
assign wbm_stb_o = (wbm==wbm_data);
350 12 unneback
 
351
always @ (posedge wbm_clk or posedge wbm_rst)
352
if (wbm_rst)
353
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
354
else begin
355
        if (wbm==wbm_adr0 & !b_fifo_empty)
356
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
357
        else if (wbm_eoc_alert & wbm_ack_i)
358
                wbm_cti_o <= endofburst;
359
end
360
 
361
//async_fifo_dw_simplex_top
362 40 unneback
`define MODULE fifo_2r2w_async_simplex
363
`BASE`MODULE
364
`undef MODULE
365 12 unneback
# ( .data_width(36), .addr_width(addr_width))
366
fifo (
367
    // a side
368
    .a_d(a_d),
369
    .a_wr(a_wr),
370
    .a_fifo_full(a_fifo_full),
371
    .a_q(a_q),
372
    .a_rd(a_rd),
373
    .a_fifo_empty(a_fifo_empty),
374
    .a_clk(wbs_clk),
375
    .a_rst(wbs_rst),
376
    // b side
377
    .b_d(b_d),
378
    .b_wr(b_wr),
379
    .b_fifo_full(b_fifo_full),
380
    .b_q(b_q),
381
    .b_rd(b_rd),
382
    .b_fifo_empty(b_fifo_empty),
383
    .b_clk(wbm_clk),
384
    .b_rst(wbm_rst)
385
    );
386
 
387
endmodule
388 40 unneback
`undef WE
389
`undef BTE
390
`undef CTI
391
`endif
392 17 unneback
 
393 75 unneback
`ifdef WB3AVALON_BRIDGE
394
`define MODULE wb3avalon_bridge
395
module `BASE`MODULE (
396
`undef MODULE
397
        // wishbone slave side
398
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
399 77 unneback
        // avalon master side
400 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
401
 
402 84 unneback
parameter linewrapburst = 1'b0;
403
 
404 75 unneback
input [31:0] wbs_dat_i;
405
input [31:2] wbs_adr_i;
406
input [3:0]  wbs_sel_i;
407
input [1:0]  wbs_bte_i;
408
input [2:0]  wbs_cti_i;
409 83 unneback
input wbs_we_i;
410
input wbs_cyc_i;
411
input wbs_stb_i;
412 75 unneback
output [31:0] wbs_dat_o;
413
output wbs_ack_o;
414
input wbs_clk, wbs_rst;
415
 
416
input [31:0] readdata;
417
output [31:0] writedata;
418
output [31:2] address;
419
output [3:0]  be;
420
output write;
421 81 unneback
output read;
422 75 unneback
output beginbursttransfer;
423
output [3:0] burstcount;
424
input readdatavalid;
425
input waitrequest;
426
input clk;
427
input rst;
428
 
429
wire [1:0] wbm_bte_o;
430
wire [2:0] wbm_cti_o;
431
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
432
reg last_cyc;
433 79 unneback
reg [3:0] counter;
434 82 unneback
reg read_busy;
435 75 unneback
 
436
always @ (posedge clk or posedge rst)
437
if (rst)
438
    last_cyc <= 1'b0;
439
else
440
    last_cyc <= wbm_cyc_o;
441
 
442 79 unneback
always @ (posedge clk or posedge rst)
443
if (rst)
444 82 unneback
    read_busy <= 1'b0;
445 79 unneback
else
446 82 unneback
    if (read & !waitrequest)
447
        read_busy <= 1'b1;
448
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
449
        read_busy <= 1'b0;
450
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
451 81 unneback
 
452 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
453
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
454
                    (wbm_bte_o==2'b10) ? 4'd8 :
455 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
456
                    4'd1;
457 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
458 75 unneback
 
459 79 unneback
always @ (posedge clk or posedge rst)
460
if (rst) begin
461
    counter <= 4'd0;
462
end else
463 80 unneback
    if (wbm_we_o) begin
464
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
465 84 unneback
            counter <= burstcount -4'd1;
466 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
467
            counter <= burstcount;
468
        end else if (!waitrequest & wbm_stb_o) begin
469
            counter <= counter - 4'd1;
470
        end
471 82 unneback
    end
472 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
473 79 unneback
 
474 75 unneback
`define MODULE wb3wb3_bridge
475 77 unneback
`BASE`MODULE wbwb3inst (
476 75 unneback
`undef MODULE
477
    // wishbone slave side
478
    .wbs_dat_i(wbs_dat_i),
479
    .wbs_adr_i(wbs_adr_i),
480
    .wbs_sel_i(wbs_sel_i),
481
    .wbs_bte_i(wbs_bte_i),
482
    .wbs_cti_i(wbs_cti_i),
483
    .wbs_we_i(wbs_we_i),
484
    .wbs_cyc_i(wbs_cyc_i),
485
    .wbs_stb_i(wbs_stb_i),
486
    .wbs_dat_o(wbs_dat_o),
487
    .wbs_ack_o(wbs_ack_o),
488
    .wbs_clk(wbs_clk),
489
    .wbs_rst(wbs_rst),
490
    // wishbone master side
491
    .wbm_dat_o(writedata),
492 78 unneback
    .wbm_adr_o(address),
493 75 unneback
    .wbm_sel_o(be),
494
    .wbm_bte_o(wbm_bte_o),
495
    .wbm_cti_o(wbm_cti_o),
496
    .wbm_we_o(wbm_we_o),
497
    .wbm_cyc_o(wbm_cyc_o),
498
    .wbm_stb_o(wbm_stb_o),
499
    .wbm_dat_i(readdata),
500
    .wbm_ack_i(wbm_ack_i),
501
    .wbm_clk(clk),
502
    .wbm_rst(rst));
503
 
504
 
505
endmodule
506
`endif
507
 
508 40 unneback
`ifdef WB3_ARBITER_TYPE1
509
`define MODULE wb3_arbiter_type1
510 42 unneback
module `BASE`MODULE (
511 40 unneback
`undef MODULE
512 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
513
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
514
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
515
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
516
    wb_clk, wb_rst
517
);
518
 
519
parameter nr_of_ports = 3;
520
parameter adr_size = 26;
521
parameter adr_lo   = 2;
522
parameter dat_size = 32;
523
parameter sel_size = dat_size/8;
524
 
525
localparam aw = (adr_size - adr_lo) * nr_of_ports;
526
localparam dw = dat_size * nr_of_ports;
527
localparam sw = sel_size * nr_of_ports;
528
localparam cw = 3 * nr_of_ports;
529
localparam bw = 2 * nr_of_ports;
530
 
531
input  [dw-1:0] wbm_dat_o;
532
input  [aw-1:0] wbm_adr_o;
533
input  [sw-1:0] wbm_sel_o;
534
input  [cw-1:0] wbm_cti_o;
535
input  [bw-1:0] wbm_bte_o;
536
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
537
output [dw-1:0] wbm_dat_i;
538
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
539
 
540
output [dat_size-1:0] wbs_dat_i;
541
output [adr_size-1:adr_lo] wbs_adr_i;
542
output [sel_size-1:0] wbs_sel_i;
543
output [2:0] wbs_cti_i;
544
output [1:0] wbs_bte_i;
545
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
546
input  [dat_size-1:0] wbs_dat_o;
547
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
548
 
549
input wb_clk, wb_rst;
550
 
551 44 unneback
reg  [nr_of_ports-1:0] select;
552 39 unneback
wire [nr_of_ports-1:0] state;
553
wire [nr_of_ports-1:0] eoc; // end-of-cycle
554
wire [nr_of_ports-1:0] sel;
555
wire idle;
556
 
557
genvar i;
558
 
559
assign idle = !(|state);
560
 
561
generate
562
if (nr_of_ports == 2) begin
563
 
564
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
565
 
566
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
567
 
568 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
569
 
570
    always @ (idle or wbm_cyc_o)
571
    if (idle)
572
        casex (wbm_cyc_o)
573
        2'b1x : select = 2'b10;
574
        2'b01 : select = 2'b01;
575
        default : select = {nr_of_ports{1'b0}};
576
        endcase
577
    else
578
        select = {nr_of_ports{1'b0}};
579
 
580 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
581
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
582
 
583
end
584
endgenerate
585
 
586
generate
587
if (nr_of_ports == 3) begin
588
 
589
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
590
 
591
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
592
 
593 44 unneback
    always @ (idle or wbm_cyc_o)
594
    if (idle)
595
        casex (wbm_cyc_o)
596
        3'b1xx : select = 3'b100;
597
        3'b01x : select = 3'b010;
598
        3'b001 : select = 3'b001;
599
        default : select = {nr_of_ports{1'b0}};
600
        endcase
601
    else
602
        select = {nr_of_ports{1'b0}};
603
 
604
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
605 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
606
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
607
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
608
 
609
end
610
endgenerate
611
 
612
generate
613 44 unneback
if (nr_of_ports == 4) begin
614
 
615
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
616
 
617
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
618
 
619
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
620
 
621
    always @ (idle or wbm_cyc_o)
622
    if (idle)
623
        casex (wbm_cyc_o)
624
        4'b1xxx : select = 4'b1000;
625
        4'b01xx : select = 4'b0100;
626
        4'b001x : select = 4'b0010;
627
        4'b0001 : select = 4'b0001;
628
        default : select = {nr_of_ports{1'b0}};
629
        endcase
630
    else
631
        select = {nr_of_ports{1'b0}};
632
 
633
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
634
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
635
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
636
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
637
 
638
end
639
endgenerate
640
 
641
generate
642
if (nr_of_ports == 5) begin
643
 
644
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
645
 
646
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
647
 
648
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
649
 
650
    always @ (idle or wbm_cyc_o)
651
    if (idle)
652
        casex (wbm_cyc_o)
653
        5'b1xxxx : select = 5'b10000;
654
        5'b01xxx : select = 5'b01000;
655
        5'b001xx : select = 5'b00100;
656
        5'b0001x : select = 5'b00010;
657
        5'b00001 : select = 5'b00001;
658
        default : select = {nr_of_ports{1'b0}};
659
        endcase
660
    else
661
        select = {nr_of_ports{1'b0}};
662
 
663
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
664
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
665
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
666
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
667
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
668
 
669
end
670
endgenerate
671
 
672
generate
673 67 unneback
if (nr_of_ports == 6) begin
674
 
675
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
676
 
677
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
678
 
679
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
680
 
681
    always @ (idle or wbm_cyc_o)
682
    if (idle)
683
        casex (wbm_cyc_o)
684
        6'b1xxxxx : select = 6'b100000;
685
        6'b01xxxx : select = 6'b010000;
686
        6'b001xxx : select = 6'b001000;
687
        6'b0001xx : select = 6'b000100;
688
        6'b00001x : select = 6'b000010;
689
        6'b000001 : select = 6'b000001;
690
        default : select = {nr_of_ports{1'b0}};
691
        endcase
692
    else
693
        select = {nr_of_ports{1'b0}};
694
 
695
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
696
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
697
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
698
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
699
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
700
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
701
 
702
end
703
endgenerate
704
 
705
generate
706
if (nr_of_ports == 7) begin
707
 
708
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
709
 
710
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
711
 
712
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
713
 
714
    always @ (idle or wbm_cyc_o)
715
    if (idle)
716
        casex (wbm_cyc_o)
717
        7'b1xxxxxx : select = 7'b1000000;
718
        7'b01xxxxx : select = 7'b0100000;
719
        7'b001xxxx : select = 7'b0010000;
720
        7'b0001xxx : select = 7'b0001000;
721
        7'b00001xx : select = 7'b0000100;
722
        7'b000001x : select = 7'b0000010;
723
        7'b0000001 : select = 7'b0000001;
724
        default : select = {nr_of_ports{1'b0}};
725
        endcase
726
    else
727
        select = {nr_of_ports{1'b0}};
728
 
729
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
730
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
731
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
732
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
733
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
734
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
735
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
736
 
737
end
738
endgenerate
739
 
740
generate
741
if (nr_of_ports == 8) begin
742
 
743
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
744
 
745
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
746
 
747
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
748
 
749
    always @ (idle or wbm_cyc_o)
750
    if (idle)
751
        casex (wbm_cyc_o)
752
        8'b1xxxxxxx : select = 8'b10000000;
753
        8'b01xxxxxx : select = 8'b01000000;
754
        8'b001xxxxx : select = 8'b00100000;
755
        8'b0001xxxx : select = 8'b00010000;
756
        8'b00001xxx : select = 8'b00001000;
757
        8'b000001xx : select = 8'b00000100;
758
        8'b0000001x : select = 8'b00000010;
759
        8'b00000001 : select = 8'b00000001;
760
        default : select = {nr_of_ports{1'b0}};
761
        endcase
762
    else
763
        select = {nr_of_ports{1'b0}};
764
 
765
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
766
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
767
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
768
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
769
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
770
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
771
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
772
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
773
 
774
end
775
endgenerate
776
 
777
generate
778 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
779 42 unneback
`define MODULE spr
780
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
781
`undef MODULE
782 39 unneback
end
783
endgenerate
784
 
785
    assign sel = select | state;
786
 
787 40 unneback
`define MODULE mux_andor
788
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
789
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
790
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
791
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
792
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
793
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
794
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
795
`undef MODULE
796 39 unneback
    assign wbs_cyc_i = |sel;
797
 
798
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
799
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
800
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
801
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
802
 
803
endmodule
804 40 unneback
`endif
805 39 unneback
 
806 101 unneback
`ifdef WB_RAM
807 49 unneback
// WB RAM with byte enable
808 101 unneback
`define MODULE wb_ram
809 59 unneback
module `BASE`MODULE (
810
`undef MODULE
811 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
812 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
813 59 unneback
 
814 101 unneback
parameter adr_width = 16;
815
parameter mem_size = 1<<adr_width;
816
parameter dat_width = 32;
817
parameter max_burst_width = 4; // only used for B3
818
parameter mode = "B3"; // valid options: B3, B4
819 60 unneback
parameter memory_init = 1;
820
parameter memory_file = "vl_ram.vmem";
821 59 unneback
 
822 101 unneback
input [dat_width-1:0] wbs_dat_i;
823
input [adr_width-1:0] wbs_adr_i;
824
input [2:0] wbs_cti_i;
825
input [1:0] wbs_bte_i;
826
input [dat_width/8-1:0] wbs_sel_i;
827 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
828 101 unneback
output [dat_width-1:0] wbs_dat_o;
829 70 unneback
output wbs_ack_o;
830 101 unneback
output wbs_stall_o;
831 71 unneback
input wb_clk, wb_rst;
832 59 unneback
 
833 101 unneback
wire [adr_width-1:0] adr;
834
wire we;
835 59 unneback
 
836 101 unneback
generate
837
if (mode=="B3") begin : B3_inst
838 83 unneback
`define MODULE wb_adr_inc
839 101 unneback
`BASE`MODULE # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
840 83 unneback
    .cyc_i(wbs_cyc_i),
841
    .stb_i(wbs_stb_i),
842
    .cti_i(wbs_cti_i),
843
    .bte_i(wbs_bte_i),
844
    .adr_i(wbs_adr_i),
845 84 unneback
    .we_i(wbs_we_i),
846 83 unneback
    .ack_o(wbs_ack_o),
847
    .adr_o(adr),
848
    .clk(wb_clk),
849
    .rst(wb_rst));
850
`undef MODULE
851 101 unneback
assign we = wbs_we_i & wbs_ack_o;
852
end else if (mode=="B4") begin : B4_inst
853
reg wbs_ack_o_reg;
854
always @ (posedge wb_clk or posedge wb_rst)
855
    if (wb_rst)
856
        wbs_ack_o_reg <= 1'b0;
857
    else
858
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
859
assign wbs_ack_o = wbs_ack_o_reg;
860
assign wbs_stall_o = 1'b0;
861
assign adr = wbs_adr_i;
862
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
863
end
864
endgenerate
865 60 unneback
 
866 100 unneback
`define MODULE ram_be
867
`BASE`MODULE # (
868
    .data_width(dat_width),
869
    .addr_width(adr_width),
870
    .mem_size(mem_size),
871
    .memory_init(memory_init),
872
    .memory_file(memory_file))
873
ram0(
874
`undef MODULE
875 101 unneback
    .d(wbs_dat_i),
876
    .adr(adr),
877
    .be(wbs_sel_i),
878
    .we(we),
879
    .q(wbs_dat_o),
880 100 unneback
    .clk(wb_clk)
881
);
882 49 unneback
 
883
endmodule
884
`endif
885
 
886 103 unneback
`ifdef WB_SHADOW_RAM
887
// A wishbone compliant RAM module that can be placed in front of other memory controllers
888
`define MODULE wb_shadow_ram
889
module `BASE`MODULE (
890
`undef MODULE
891
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
892
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
893
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
894
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
895
    wb_clk, wb_rst);
896
 
897
parameter dat_width = 32;
898
parameter mode = "B4";
899
parameter max_burst_width = 4; // only used for B3
900
 
901
parameter shadow_mem_adr_width = 10;
902
parameter shadow_mem_size = 1024;
903
parameter shadow_mem_init = 2;
904
parameter shadow_mem_file = "vl_ram.v";
905
 
906
parameter main_mem_adr_width = 24;
907
 
908
input [dat_width-1:0] wbs_dat_i;
909
input [main_mem_adr_width-1:0] wbs_adr_i;
910
input [2:0] wbs_cti_i;
911
input [1:0] wbs_bte_i;
912
input [dat_width/8-1:0] wbs_sel_i;
913
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
914
output [dat_width-1:0] wbs_dat_o;
915
output wbs_ack_o;
916
output wbs_stall_o;
917
 
918
output [dat_width-1:0] wbm_dat_o;
919
output [main_mem_adr_width-1:0] wbm_adr_o;
920
output [2:0] wbm_cti_o;
921
output [1:0] wbm_bte_o;
922
output [dat_width/8-1:0] wbm_sel_o;
923
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
924
input [dat_width-1:0] wbm_dat_i;
925
input wbm_ack_i, wbm_stall_i;
926
 
927
input wb_clk, wb_rst;
928
 
929
generate
930
if (shadow_mem_size>0) begin : shadow_ram_inst
931
 
932
wire cyc;
933
wire [dat_width-1:0] dat;
934
wire stall, ack;
935
 
936
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
937
`define MODULE wb_ram
938
`BASE`MODULE # (
939
    .dat_width(dat_width),
940
    .adr_width(shadow_mem_adr_width),
941
    .mem_size(shadow_mem_size),
942
    .memory_init(shadow_mem_init),
943
    .mode(mode))
944
shadow_mem0 (
945
    .wbs_dat_i(wbs_dat_i),
946
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
947
    .wbs_sel_i(wbs_sel_i),
948
    .wbs_we_i (wbs_we_i),
949
    .wbs_bte_i(wbs_bte_i),
950
    .wbs_cti_i(wbs_cti_i),
951
    .wbs_stb_i(wbs_stb_i),
952
    .wbs_cyc_i(cyc),
953
    .wbs_dat_o(dat),
954
    .wbs_stall_o(stall),
955
    .wbs_ack_o(ack),
956
    .wb_clk(wb_clk),
957
    .wb_rst(wb_rst));
958
`undef MODULE
959
 
960
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
961
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
962
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
963
 
964
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
965
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
966
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
967
 
968
end else begin : no_shadow_ram_inst
969
 
970
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
971
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
972
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
973
 
974
end
975
endgenerate
976
 
977
endmodule
978
`endif
979
 
980 48 unneback
`ifdef WB_B4_ROM
981
// WB ROM
982
`define MODULE wb_b4_rom
983
module `BASE`MODULE (
984
`undef MODULE
985
    wb_adr_i, wb_stb_i, wb_cyc_i,
986
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
987
 
988
    parameter dat_width = 32;
989
    parameter dat_default = 32'h15000000;
990
    parameter adr_width = 32;
991
 
992
/*
993
//E2_ifndef ROM
994
//E2_define ROM "rom.v"
995
//E2_endif
996
*/
997
    input [adr_width-1:2]   wb_adr_i;
998
    input                   wb_stb_i;
999
    input                   wb_cyc_i;
1000
    output [dat_width-1:0]  wb_dat_o;
1001
    reg [dat_width-1:0]     wb_dat_o;
1002
    output                  wb_ack_o;
1003
    reg                     wb_ack_o;
1004
    output                  stall_o;
1005
    input                   wb_clk;
1006
    input                   wb_rst;
1007
 
1008
always @ (posedge wb_clk or posedge wb_rst)
1009
    if (wb_rst)
1010
        wb_dat_o <= {dat_width{1'b0}};
1011
    else
1012
         case (wb_adr_i[adr_width-1:2])
1013
//E2_ifdef ROM
1014
//E2_include `ROM
1015
//E2_endif
1016
           default:
1017
             wb_dat_o <= dat_default;
1018
 
1019
         endcase // case (wb_adr_i)
1020
 
1021
 
1022
always @ (posedge wb_clk or posedge wb_rst)
1023
    if (wb_rst)
1024
        wb_ack_o <= 1'b0;
1025
    else
1026
        wb_ack_o <= wb_stb_i & wb_cyc_i;
1027
 
1028
assign stall_o = 1'b0;
1029
 
1030
endmodule
1031
`endif
1032
 
1033
 
1034 40 unneback
`ifdef WB_BOOT_ROM
1035 17 unneback
// WB ROM
1036 40 unneback
`define MODULE wb_boot_rom
1037
module `BASE`MODULE (
1038
`undef MODULE
1039 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
1040 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
1041 17 unneback
 
1042 18 unneback
    parameter adr_hi = 31;
1043
    parameter adr_lo = 28;
1044
    parameter adr_sel = 4'hf;
1045
    parameter addr_width = 5;
1046 33 unneback
/*
1047 17 unneback
//E2_ifndef BOOT_ROM
1048
//E2_define BOOT_ROM "boot_rom.v"
1049
//E2_endif
1050 33 unneback
*/
1051 18 unneback
    input [adr_hi:2]    wb_adr_i;
1052
    input               wb_stb_i;
1053
    input               wb_cyc_i;
1054
    output [31:0]        wb_dat_o;
1055
    output              wb_ack_o;
1056
    output              hit_o;
1057
    input               wb_clk;
1058
    input               wb_rst;
1059
 
1060
    wire hit;
1061
    reg [31:0] wb_dat;
1062
    reg wb_ack;
1063
 
1064
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1065 17 unneback
 
1066
always @ (posedge wb_clk or posedge wb_rst)
1067
    if (wb_rst)
1068 18 unneback
        wb_dat <= 32'h15000000;
1069 17 unneback
    else
1070 18 unneback
         case (wb_adr_i[addr_width-1:2])
1071 33 unneback
//E2_ifdef BOOT_ROM
1072 17 unneback
//E2_include `BOOT_ROM
1073 33 unneback
//E2_endif
1074 17 unneback
           /*
1075
            // Zero r0 and jump to 0x00000100
1076 18 unneback
 
1077
            1 : wb_dat <= 32'hA8200000;
1078
            2 : wb_dat <= 32'hA8C00100;
1079
            3 : wb_dat <= 32'h44003000;
1080
            4 : wb_dat <= 32'h15000000;
1081 17 unneback
            */
1082
           default:
1083 18 unneback
             wb_dat <= 32'h00000000;
1084 17 unneback
 
1085
         endcase // case (wb_adr_i)
1086
 
1087
 
1088
always @ (posedge wb_clk or posedge wb_rst)
1089
    if (wb_rst)
1090 18 unneback
        wb_ack <= 1'b0;
1091 17 unneback
    else
1092 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1093 17 unneback
 
1094 18 unneback
assign hit_o = hit;
1095
assign wb_dat_o = wb_dat & {32{wb_ack}};
1096
assign wb_ack_o = wb_ack;
1097
 
1098 17 unneback
endmodule
1099 40 unneback
`endif
1100 32 unneback
 
1101 92 unneback
`ifdef WB_B3_DPRAM
1102
`define MODULE wb_b3_dpram
1103 40 unneback
module `BASE`MODULE (
1104
`undef MODULE
1105 32 unneback
        // wishbone slave side a
1106 92 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1107 32 unneback
        wbsa_clk, wbsa_rst,
1108 92 unneback
        // wishbone slave side b
1109
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1110 32 unneback
        wbsb_clk, wbsb_rst);
1111
 
1112 92 unneback
parameter data_width_a = 32;
1113
parameter data_width_b = data_width_a;
1114
parameter addr_width_a = 8;
1115
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
1116 101 unneback
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
1117 92 unneback
parameter max_burst_width_a = 4;
1118
parameter max_burst_width_b = max_burst_width_a;
1119 101 unneback
parameter mode = "B3";
1120 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
1121
input [addr_width_a-1:0] wbsa_adr_i;
1122
input [data_width_a/8-1:0] wbsa_sel_i;
1123
input [2:0] wbsa_cti_i;
1124
input [1:0] wbsa_bte_i;
1125 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1126 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
1127 32 unneback
output wbsa_ack_o;
1128
input wbsa_clk, wbsa_rst;
1129
 
1130 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
1131
input [addr_width_b-1:0] wbsb_adr_i;
1132
input [data_width_b/8-1:0] wbsb_sel_i;
1133
input [2:0] wbsb_cti_i;
1134
input [1:0] wbsb_bte_i;
1135 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1136 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
1137 32 unneback
output wbsb_ack_o;
1138
input wbsb_clk, wbsb_rst;
1139
 
1140 92 unneback
wire [addr_width_a-1:0] adr_a;
1141
wire [addr_width_b-1:0] adr_b;
1142 101 unneback
wire we_a, we_b;
1143
generate
1144
if (mode=="B3") begin : b3_inst
1145 92 unneback
`define MODULE wb_adr_inc
1146
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
1147
    .cyc_i(wbsa_cyc_i),
1148
    .stb_i(wbsa_stb_i),
1149
    .cti_i(wbsa_cti_i),
1150
    .bte_i(wbsa_bte_i),
1151
    .adr_i(wbsa_adr_i),
1152
    .we_i(wbsa_we_i),
1153
    .ack_o(wbsa_ack_o),
1154
    .adr_o(adr_a),
1155
    .clk(wbsa_clk),
1156
    .rst(wbsa_rst));
1157 101 unneback
assign we_a = wbsa_we_i & wbsa_ack_o;
1158 92 unneback
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
1159
    .cyc_i(wbsb_cyc_i),
1160
    .stb_i(wbsb_stb_i),
1161
    .cti_i(wbsb_cti_i),
1162
    .bte_i(wbsb_bte_i),
1163
    .adr_i(wbsb_adr_i),
1164
    .we_i(wbsb_we_i),
1165
    .ack_o(wbsb_ack_o),
1166
    .adr_o(adr_b),
1167
    .clk(wbsb_clk),
1168
    .rst(wbsb_rst));
1169 40 unneback
`undef MODULE
1170 101 unneback
assign we_b = wbsb_we_i & wbsb_ack_o;
1171
end else if (mode=="B4") begin : b4_inst
1172
always @ (posedge wbsa_clk or posedge wbsa_rst)
1173
    if (wbsa_rst)
1174
        wbsa_ack_o <= 1'b0;
1175
    else
1176
        wbsa_ack_o <= wbsa_stb_i & wbsa_cyc_i;
1177
assign wbsa_stall_o = 1'b0;
1178
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
1179
always @ (posedge wbsb_clk or posedge wbsb_rst)
1180
    if (wbsb_rst)
1181
        wbsb_ack_o <= 1'b0;
1182
    else
1183
        wbsb_ack_o <= wbsb_stb_i & wbsb_cyc_i;
1184
assign wbsb_stall_o = 1'b0;
1185
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
1186
end
1187
endgenerate
1188 92 unneback
 
1189
`define MODULE dpram_be_2r2w
1190
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
1191
`undef MODULE
1192
ram_i (
1193 32 unneback
    .d_a(wbsa_dat_i),
1194 92 unneback
    .q_a(wbsa_dat_o),
1195
    .adr_a(adr_a),
1196
    .be_a(wbsa_sel_i),
1197 101 unneback
    .we_a(we_a),
1198 32 unneback
    .clk_a(wbsa_clk),
1199
    .d_b(wbsb_dat_i),
1200 92 unneback
    .q_b(wbsb_dat_o),
1201
    .adr_b(adr_b),
1202
    .be_b(wbsb_sel_i),
1203 101 unneback
    .we_b(we_b),
1204 32 unneback
    .clk_b(wbsb_clk) );
1205
 
1206
endmodule
1207 40 unneback
`endif
1208 94 unneback
 
1209 101 unneback
`ifdef WB_CACHE
1210
`define MODULE wb_cache
1211 96 unneback
module `BASE`MODULE (
1212 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
1213 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
1214 96 unneback
);
1215
`undef MODULE
1216
 
1217
parameter dw_s = 32;
1218
parameter aw_s = 24;
1219
parameter dw_m = dw_s;
1220 100 unneback
localparam aw_m = dw_s * aw_s / dw_m;
1221
parameter wbs_max_burst_width = 4;
1222 103 unneback
parameter wbs_mode = "B3";
1223 96 unneback
 
1224 97 unneback
parameter async = 1; // wbs_clk != wbm_clk
1225
 
1226 96 unneback
parameter nr_of_ways = 1;
1227 97 unneback
parameter aw_offset = 4; // 4 => 16 words per cache line
1228
parameter aw_slot = 10;
1229 100 unneback
 
1230
parameter valid_mem = 0;
1231
parameter debug = 0;
1232
 
1233
localparam aw_b_offset = aw_offset * dw_s / dw_m;
1234 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
1235 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
1236 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
1237 97 unneback
`define SIZE2WIDTH wbm_burst_size
1238
localparam wbm_burst_width `SIZE2WIDTH_EXPR
1239
`undef SIZE2WIDTH
1240
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
1241
`define SIZE2WIDTH nr_of_wbm_burst
1242
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
1243
`undef SIZE2WIDTH
1244 100 unneback
 
1245 96 unneback
input [dw_s-1:0] wbs_dat_i;
1246
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
1247 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
1248 96 unneback
input [2:0] wbs_cti_i;
1249
input [1:0] wbs_bte_i;
1250 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
1251 96 unneback
output [dw_s-1:0] wbs_dat_o;
1252
output wbs_ack_o;
1253 103 unneback
output wbs_stall_o;
1254 96 unneback
input wbs_clk, wbs_rst;
1255
 
1256
output [dw_m-1:0] wbm_dat_o;
1257
output [aw_m-1:0] wbm_adr_o;
1258
output [dw_m/8-1:0] wbm_sel_o;
1259
output [2:0] wbm_cti_o;
1260
output [1:0] wbm_bte_o;
1261 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
1262 96 unneback
input [dw_m-1:0] wbm_dat_i;
1263
input wbm_ack_i;
1264
input wbm_stall_i;
1265
input wbm_clk, wbm_rst;
1266
 
1267 100 unneback
wire valid, dirty, hit;
1268 97 unneback
wire [aw_tag-1:0] tag;
1269
wire tag_mem_we;
1270
wire [aw_tag-1:0] wbs_adr_tag;
1271
wire [aw_slot-1:0] wbs_adr_slot;
1272 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
1273
wire [aw_s-1:0] wbs_adr;
1274 96 unneback
 
1275 97 unneback
reg [1:0] state;
1276
localparam idle = 2'h0;
1277
localparam rdwr = 2'h1;
1278
localparam push = 2'h2;
1279
localparam pull = 2'h3;
1280
wire eoc;
1281 103 unneback
wire we;
1282 97 unneback
 
1283
// cdc
1284
wire done, mem_alert, mem_done;
1285
 
1286 98 unneback
// wbm side
1287
reg [aw_m-1:0] wbm_radr;
1288
reg [aw_m-1:0] wbm_wadr;
1289 100 unneback
wire [aw_slot-1:0] wbm_adr;
1290 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
1291
 
1292 100 unneback
reg [2:0] phase;
1293
// phase = {we,stb,cyc}
1294
localparam wbm_wait     = 3'b000;
1295
localparam wbm_wr       = 3'b111;
1296
localparam wbm_wr_drain = 3'b101;
1297
localparam wbm_rd       = 3'b011;
1298
localparam wbm_rd_drain = 3'b001;
1299 98 unneback
 
1300 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
1301
 
1302 100 unneback
generate
1303
if (valid_mem==0) begin : no_valid_mem
1304
assign valid = 1'b1;
1305
end else begin : valid_mem_inst
1306
`define MODULE dpram_1r1w
1307 97 unneback
`BASE`MODULE
1308 100 unneback
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
1309
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
1310
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
1311 97 unneback
`undef MODULE
1312 100 unneback
end
1313
endgenerate
1314 97 unneback
 
1315 100 unneback
`define MODULE dpram_1r1w
1316
`BASE`MODULE
1317
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
1318
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
1319
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
1320
assign hit = wbs_adr_tag == tag;
1321
`undef MODULE
1322
 
1323
`define MODULE dpram_1r2w
1324
`BASE`MODULE
1325
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
1326
    dirty_mem (
1327
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
1328
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
1329
`undef MODULE
1330
 
1331 103 unneback
generate
1332
if (wbs_mode=="B3") begin : inst_b3
1333 96 unneback
`define MODULE wb_adr_inc
1334 100 unneback
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
1335
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
1336
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
1337 96 unneback
    .cti_i(wbs_cti_i),
1338
    .bte_i(wbs_bte_i),
1339
    .adr_i(wbs_adr_i),
1340 97 unneback
    .we_i (wbs_we_i),
1341 96 unneback
    .ack_o(wbs_ack_o),
1342 97 unneback
    .adr_o(wbs_adr),
1343 100 unneback
    .clk(wbs_clk),
1344
    .rst(wbs_rst));
1345 96 unneback
`undef MODULE
1346 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
1347
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
1348
end else if (wbs_mode=="B4") begin : inst_b4
1349
end
1350 96 unneback
 
1351 103 unneback
endgenerate
1352
 
1353 97 unneback
`define MODULE dpram_be_2r2w
1354
`BASE`MODULE
1355 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
1356 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
1357 100 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
1358 97 unneback
`undef MODULE
1359
 
1360
always @ (posedge wbs_clk or posedge wbs_rst)
1361
if (wbs_rst)
1362 98 unneback
    state <= idle;
1363 97 unneback
else
1364
    case (state)
1365
    idle:
1366
        if (wbs_cyc_i)
1367
            state <= rdwr;
1368
    rdwr:
1369 100 unneback
        casex ({valid, hit, dirty, eoc})
1370
        4'b0xxx: state <= pull;
1371
        4'b11x1: state <= idle;
1372
        4'b101x: state <= push;
1373
        4'b100x: state <= pull;
1374
        endcase
1375 97 unneback
    push:
1376
        if (done)
1377
            state <= rdwr;
1378
    pull:
1379
        if (done)
1380
            state <= rdwr;
1381
    default: state <= idle;
1382
    endcase
1383
 
1384
// cdc
1385
generate
1386
if (async==1) begin : cdc0
1387
`define MODULE cdc
1388 100 unneback
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
1389 97 unneback
`undef MODULE
1390
end
1391
else begin : nocdc
1392 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
1393 97 unneback
    assign done = mem_done;
1394
end
1395
endgenerate
1396
 
1397
// FSM generating a number of burts 4 cycles
1398
// actual number depends on data width ratio
1399
// nr_of_wbm_burst
1400 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
1401 97 unneback
 
1402
always @ (posedge wbm_clk or posedge wbm_rst)
1403
if (wbm_rst)
1404 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
1405 97 unneback
else
1406 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
1407
        cnt_rw <= cnt_rw + 1;
1408 97 unneback
 
1409 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1410
if (wbm_rst)
1411 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
1412 98 unneback
else
1413 100 unneback
    if (wbm_ack_i)
1414
        cnt_ack <= cnt_ack + 1;
1415 97 unneback
 
1416 100 unneback
generate
1417 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
1418 100 unneback
 
1419 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1420
if (wbm_rst)
1421
    phase <= wbm_wait;
1422
else
1423
    case (phase)
1424
    wbm_wait:
1425
        if (mem_alert)
1426 100 unneback
            if (state==push)
1427
                phase <= wbm_wr;
1428
            else
1429
                phase <= wbm_rd;
1430 98 unneback
    wbm_wr:
1431 100 unneback
        if (&cnt_rw)
1432
            phase <= wbm_wr_drain;
1433
    wbm_wr_drain:
1434
        if (&cnt_ack)
1435 98 unneback
            phase <= wbm_rd;
1436
    wbm_rd:
1437 100 unneback
        if (&cnt_rw)
1438
            phase <= wbm_rd_drain;
1439
    wbm_rd_drain:
1440
        if (&cnt_ack)
1441
            phase <= wbm_wait;
1442 98 unneback
    default: phase <= wbm_wait;
1443
    endcase
1444
 
1445 100 unneback
end else begin : multiple_burst
1446
 
1447 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1448
if (wbm_rst)
1449
    phase <= wbm_wait;
1450
else
1451
    case (phase)
1452
    wbm_wait:
1453
        if (mem_alert)
1454
            if (state==push)
1455
                phase <= wbm_wr;
1456
            else
1457
                phase <= wbm_rd;
1458
    wbm_wr:
1459
        if (&cnt_rw[wbm_burst_width-1:0])
1460
            phase <= wbm_wr_drain;
1461
    wbm_wr_drain:
1462
        if (&cnt_ack)
1463
            phase <= wbm_rd;
1464
        else if (&cnt_ack[wbm_burst_width-1:0])
1465
            phase <= wbm_wr;
1466
    wbm_rd:
1467
        if (&cnt_rw[wbm_burst_width-1:0])
1468
            phase <= wbm_rd_drain;
1469
    wbm_rd_drain:
1470
        if (&cnt_ack)
1471
            phase <= wbm_wait;
1472
        else if (&cnt_ack[wbm_burst_width-1:0])
1473
            phase <= wbm_rd;
1474
    default: phase <= wbm_wait;
1475
    endcase
1476 100 unneback
 
1477 101 unneback
 
1478 100 unneback
end
1479
endgenerate
1480
 
1481 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
1482 100 unneback
 
1483
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
1484
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
1485
assign wbm_sel_o = {dw_m/8{1'b1}};
1486
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
1487 98 unneback
assign wbm_bte_o = bte;
1488 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
1489 98 unneback
 
1490 96 unneback
endmodule
1491
`endif
1492 103 unneback
 
1493
`ifdef WB_AVALON_BRIDGE
1494
// Wishbone to avalon bridge supporting one type of burst transfer only
1495
// intended use is together with cache above
1496
// WB B4 -> pipelined avalon
1497
`define MODULE wb_avalon_bridge
1498
module `BASE`MODULE (
1499
`undef MODULE
1500
        // wishbone slave side
1501
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
1502
        // avalon master side
1503
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
1504
        // common
1505
        clk, rst);
1506
 
1507
parameter adr_width = 30;
1508
parameter dat_width = 32;
1509
parameter burst_size = 4;
1510
 
1511
input [dat_width-1:0] wbs_dat_i;
1512
input [adr_width-1:0] wbs_adr_i;
1513
input [dat_width/8-1:0]  wbs_sel_i;
1514
input [1:0]  wbs_bte_i;
1515
input [2:0]  wbs_cti_i;
1516
input wbs_we_i;
1517
input wbs_cyc_i;
1518
input wbs_stb_i;
1519
output [dat_width:0] wbs_dat_o;
1520
output wbs_ack_o;
1521
output wbs_stall_o;
1522
 
1523
input [dat_width-1:0] readdata;
1524
input readdatavalid;
1525
output [dat_width-1:0] writedata;
1526
output [adr_width-1:0] address;
1527
output [dat_width/8-1:0]  be;
1528
output write;
1529
output read;
1530
output beginbursttransfer;
1531
output [3:0] burstcount;
1532
input waitrequest;
1533
input clk, rst;
1534
 
1535
reg last_cyc_idle_or_eoc;
1536
 
1537
reg [3:0] cnt;
1538
always @ (posedge clk or posedge rst)
1539
if (rst)
1540
    cnt <= 4'h0;
1541
else
1542
    if (beginbursttransfer & waitrequest)
1543
        cnt <= burst_size - 1;
1544
    else if (beginbursttransfer & !waitrequest)
1545
        cnt <= burst_size - 2;
1546
    else if (wbs_ack_o)
1547
        cnt <= cnt - 1;
1548
 
1549
reg wr_ack;
1550
always @ (posedge clk or posedge rst)
1551
if (rst)
1552
    wr_ack <= 1'b0;
1553
else
1554
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
1555
 
1556
// to avalon
1557
assign writedata = wbs_dat_i;
1558
assign address = wbs_adr_i;
1559
assign be = wbs_sel_i;
1560
assign write = cnt==(burst_size-1) & wbs_cyc_i &  wbs_we_i;
1561
assign read  = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
1562
assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
1563
assign burstcount = burst_size;
1564
 
1565
// to wishbone
1566
assign wbs_dat_o = readdata;
1567
assign wbs_ack_o = wr_ack | readdatavalid;
1568
assign wbs_stall_o = waitrequest;
1569
 
1570
endmodule
1571
`endif
1572
 
1573
`ifdef WB_AVALON_MEM_CACHE
1574
`define MODULE wb_avalon_mem_cache
1575
module `BASE`MODULE (
1576
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
1577
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
1578
);
1579
`undef MODULE
1580
 
1581
// wishbone
1582
parameter wb_dat_width = 32;
1583
parameter wb_adr_width = 22;
1584
parameter wb_max_burst_width = 4;
1585
parameter wb_mode = "B4";
1586
// avalon
1587
parameter avalon_dat_width = 32;
1588
localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
1589
parameter avalon_burst_size = 4;
1590
// cache
1591
parameter async = 1;
1592
parameter nr_of_ways = 1;
1593
parameter aw_offset = 4;
1594
parameter aw_slot = 10;
1595
parameter valid_mem = 1;
1596
// shadow RAM
1597
parameter shadow_ram = 0;
1598
parameter shadow_ram_adr_width = 10;
1599
parameter shadow_ram_size = 1024;
1600
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
1601
parameter shadow_ram_file = "vl_ram.v";
1602
 
1603
input [wb_dat_width-1:0] wbs_dat_i;
1604
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
1605
input [wb_dat_width/8-1:0] wbs_sel_i;
1606
input [2:0] wbs_cti_i;
1607
input [1:0] wbs_bte_i;
1608
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
1609
output [wb_dat_width-1:0] wbs_dat_o;
1610
output wbs_ack_o;
1611
output wbs_stall_o;
1612
input wbs_clk, wbs_rst;
1613
 
1614
input [avalon_dat_width-1:0] readdata;
1615
input readdatavalid;
1616
output [avalon_dat_width-1:0] writedata;
1617
output [avalon_adr_width-1:0] address;
1618
output [avalon_dat_width/8-1:0]  be;
1619
output write;
1620
output read;
1621
output beginbursttransfer;
1622
output [3:0] burstcount;
1623
input waitrequest;
1624
input clk, rst;
1625
 
1626
`define DAT_WIDTH wb_dat_width
1627
`define ADR_WIDTH wb_adr_width
1628
`define WB wb1
1629
`include "wb_wires.v"
1630
`define WB wb2
1631
`include "wb_wires.v"
1632
`undef DAT_WIDTH
1633
`undef ADR_WIDTH
1634
 
1635
`define MODULE wb_shadow_ram
1636
`BASE`MODULE # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
1637
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_adr_width), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
1638
                 .main_mem_adr_width(wb_adr_width))
1639
shadow_ram0 (
1640
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
1641
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
1642
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
1643
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
1644
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
1645
`undef MODULE
1646
 
1647
`define MODULE wb_cache
1648
`BASE`MODULE
1649
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
1650
cache0 (
1651
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
1652
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
1653
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
1654
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
1655
`undef MODULE
1656
 
1657
`define MODULE wb_avalon_bridge
1658
`BASE`MODULE # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
1659
bridge0 (
1660
        // wishbone slave side
1661
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
1662
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
1663
        // avalon master side
1664
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
1665
        // common
1666
        .clk(clk), .rst(rst));
1667
`undef MODULE
1668
 
1669
endmodule
1670
`endif

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