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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// async wb3 - wb3 bridge
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`timescale 1ns/1ns
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module wb3wb3_bridge (
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        // wishbone slave side
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        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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        // wishbone master side
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        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
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input [31:0] wbs_dat_i;
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input [31:2] wbs_adr_i;
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input [3:0]  wbs_sel_i;
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input [1:0]  wbs_bte_i;
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input [2:0]  wbs_cti_i;
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input wbs_we_i, wbs_cyc_i, wbs_stb_i;
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output [31:0] wbs_dat_o;
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output reg wbs_ack_o;
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input wbs_clk, wbs_rst;
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output [31:0] wbm_dat_o;
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output reg [31:2] wbm_adr_o;
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output [3:0]  wbm_sel_o;
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output reg [1:0]  wbm_bte_o;
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output reg [2:0]  wbm_cti_o;
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output reg wbm_we_o, wbm_cyc_o;
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output wbm_stb_o;
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input [31:0]  wbm_dat_i;
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input wbm_ack_i;
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input wbm_clk, wbm_rst;
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parameter addr_width = 4;
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// bte
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parameter linear       = 2'b00;
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parameter wrap4        = 2'b01;
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parameter wrap8        = 2'b10;
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parameter wrap16       = 2'b11;
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// cti
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parameter classic      = 3'b000;
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parameter incburst     = 3'b010;
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parameter endofburst   = 3'b111;
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parameter wbs_adr  = 1'b0;
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parameter wbs_data = 1'b1;
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parameter wbm_adr0 = 2'b00;
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parameter wbm_adr1 = 2'b01;
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parameter wbm_data = 2'b10;
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reg wbs_we_reg;
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reg [1:0] wbs_bte_reg;
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reg wbs;
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wire wbs_eoc_alert, wbm_eoc_alert;
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reg wbs_eoc, wbm_eoc;
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reg [1:0] wbm;
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reg [1:16] wbs_count, wbm_count;
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reg wbs_ack_o_rd;
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wire wbs_ack_o_wr;
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wire [35:0] a_d, a_q, b_d, b_q;
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wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
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reg a_rd_reg;
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wire b_rd_adr, b_rd_data;
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reg b_rd_data_reg;
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reg [35:0] temp;
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`define WE 5
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`define BTE 4:3
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`define CTI 2:0
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assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
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always @ (posedge wbs_clk or posedge wbs_rst)
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if (wbs_rst)
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        wbs_eoc <= 1'b0;
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else
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        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
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                wbs_eoc <= wbs_bte_i==linear;
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        else if (wbs_eoc_alert & (a_rd | a_wr))
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                wbs_eoc <= 1'b1;
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cnt_shreg_ce_clear # ( .length(16))
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    cnt0 (
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        .cke(wbs_ack_o),
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        .clear(wbs_eoc),
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        .q(wbs_count),
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        .rst(wbs_rst),
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        .clk(wbs_clk));
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always @ (posedge wbs_clk or posedge wbs_rst)
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if (wbs_rst)
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        wbs <= wbs_adr;
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else
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        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
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                wbs <= wbs_data;
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        else if (wbs_eoc & wbs_ack_o)
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                wbs <= wbs_adr;
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// wbs FIFO
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assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
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assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
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              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
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              1'b0;
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assign a_rd = !a_fifo_empty;
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always @ (posedge wbs_clk or posedge wbs_rst)
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if (wbs_rst)
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        a_rd_reg <= 1'b0;
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else
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        a_rd_reg <= a_rd;
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assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
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assign wbs_dat_o = a_q[35:4];
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always @ (posedge wbs_clk or posedge wbs_rst)
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if (wbs_rst)
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        {wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00};
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else
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        {wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i};
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// wbm FIFO
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assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
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always @ (posedge wbm_clk or posedge wbm_rst)
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if (wbm_rst)
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        wbm_eoc <= 1'b0;
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else
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        if (wbm==wbm_adr0 & !b_fifo_empty)
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                wbm_eoc <= b_q[`BTE] == linear;
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        else if (wbm_eoc_alert & wbm_ack_i)
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                wbm_eoc <= 1'b1;
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always @ (posedge wbm_clk or posedge wbm_rst)
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if (wbm_rst)
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        wbm <= wbm_adr0;
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else
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    if ((wbm==wbm_adr0 & !b_fifo_empty) |
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        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
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        (wbm==wbm_adr1 & !wbm_we_o) |
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        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
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        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
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assign b_d = {wbm_dat_i,4'b1111};
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assign b_wr = !wbm_we_o & wbm_ack_i;
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assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
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assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
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                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
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                   1'b0;
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assign b_rd = b_rd_adr | b_rd_data;
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dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
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dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
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assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
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cnt_shreg_ce_clear # ( .length(16))
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    cnt1 (
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        .cke(wbm_ack_i),
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        .clear(wbm_eoc),
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        .q(wbm_count),
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        .rst(wbm_rst),
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        .clk(wbm_clk));
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assign wbm_cyc_o = wbm==wbm_data;
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assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
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                   (wbm==wbm_data) ? 1'b1 :
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                   1'b0;
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always @ (posedge wbm_clk or posedge wbm_rst)
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if (wbm_rst)
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        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
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else begin
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        if (wbm==wbm_adr0 & !b_fifo_empty)
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                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
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        else if (wbm_eoc_alert & wbm_ack_i)
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                wbm_cti_o <= endofburst;
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end
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//async_fifo_dw_simplex_top
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vl_fifo_2r2w_async_simplex
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# ( .data_width(36), .addr_width(addr_width))
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fifo (
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    // a side
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    .a_d(a_d),
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    .a_wr(a_wr),
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    .a_fifo_full(a_fifo_full),
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    .a_q(a_q),
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    .a_rd(a_rd),
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    .a_fifo_empty(a_fifo_empty),
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    .a_clk(wbs_clk),
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    .a_rst(wbs_rst),
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    // b side
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    .b_d(b_d),
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    .b_wr(b_wr),
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    .b_fifo_full(b_fifo_full),
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    .b_q(b_q),
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    .b_rd(b_rd),
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    .b_fifo_empty(b_fifo_empty),
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    .b_clk(wbm_clk),
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    .b_rst(wbm_rst)
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    );
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endmodule

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