OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Blame information for rev 33

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, wishbone stuff                           ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Wishbone compliant modules                                  ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   -                                                          ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// async wb3 - wb3 bridge
44
`timescale 1ns/1ns
45 18 unneback
module vl_wb3wb3_bridge (
46 12 unneback
        // wishbone slave side
47
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
48
        // wishbone master side
49
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
50
 
51
input [31:0] wbs_dat_i;
52
input [31:2] wbs_adr_i;
53
input [3:0]  wbs_sel_i;
54
input [1:0]  wbs_bte_i;
55
input [2:0]  wbs_cti_i;
56
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
57
output [31:0] wbs_dat_o;
58 14 unneback
output wbs_ack_o;
59 12 unneback
input wbs_clk, wbs_rst;
60
 
61
output [31:0] wbm_dat_o;
62
output reg [31:2] wbm_adr_o;
63
output [3:0]  wbm_sel_o;
64
output reg [1:0]  wbm_bte_o;
65
output reg [2:0]  wbm_cti_o;
66 14 unneback
output reg wbm_we_o;
67
output wbm_cyc_o;
68 12 unneback
output wbm_stb_o;
69
input [31:0]  wbm_dat_i;
70
input wbm_ack_i;
71
input wbm_clk, wbm_rst;
72
 
73
parameter addr_width = 4;
74
 
75
// bte
76
parameter linear       = 2'b00;
77
parameter wrap4        = 2'b01;
78
parameter wrap8        = 2'b10;
79
parameter wrap16       = 2'b11;
80
// cti
81
parameter classic      = 3'b000;
82
parameter incburst     = 3'b010;
83
parameter endofburst   = 3'b111;
84
 
85
parameter wbs_adr  = 1'b0;
86
parameter wbs_data = 1'b1;
87
 
88 33 unneback
parameter wbm_adr0      = 2'b00;
89
parameter wbm_adr1      = 2'b01;
90
parameter wbm_data      = 2'b10;
91
parameter wbm_data_wait = 2'b11;
92 12 unneback
 
93
reg [1:0] wbs_bte_reg;
94
reg wbs;
95
wire wbs_eoc_alert, wbm_eoc_alert;
96
reg wbs_eoc, wbm_eoc;
97
reg [1:0] wbm;
98
 
99 14 unneback
wire [1:16] wbs_count, wbm_count;
100 12 unneback
 
101
wire [35:0] a_d, a_q, b_d, b_q;
102
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
103
reg a_rd_reg;
104
wire b_rd_adr, b_rd_data;
105 14 unneback
wire b_rd_data_reg;
106
wire [35:0] temp;
107 12 unneback
 
108
`define WE 5
109
`define BTE 4:3
110
`define CTI 2:0
111
 
112
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
113
always @ (posedge wbs_clk or posedge wbs_rst)
114
if (wbs_rst)
115
        wbs_eoc <= 1'b0;
116
else
117
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
118
                wbs_eoc <= wbs_bte_i==linear;
119
        else if (wbs_eoc_alert & (a_rd | a_wr))
120
                wbs_eoc <= 1'b1;
121
 
122 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
123 12 unneback
    cnt0 (
124
        .cke(wbs_ack_o),
125
        .clear(wbs_eoc),
126
        .q(wbs_count),
127
        .rst(wbs_rst),
128
        .clk(wbs_clk));
129
 
130
always @ (posedge wbs_clk or posedge wbs_rst)
131
if (wbs_rst)
132
        wbs <= wbs_adr;
133
else
134
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
135
                wbs <= wbs_data;
136
        else if (wbs_eoc & wbs_ack_o)
137
                wbs <= wbs_adr;
138
 
139
// wbs FIFO
140
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
141
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
142
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
143
              1'b0;
144
assign a_rd = !a_fifo_empty;
145
always @ (posedge wbs_clk or posedge wbs_rst)
146
if (wbs_rst)
147
        a_rd_reg <= 1'b0;
148
else
149
        a_rd_reg <= a_rd;
150
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
151
 
152
assign wbs_dat_o = a_q[35:4];
153
 
154
always @ (posedge wbs_clk or posedge wbs_rst)
155
if (wbs_rst)
156 13 unneback
        wbs_bte_reg <= 2'b00;
157 12 unneback
else
158 13 unneback
        wbs_bte_reg <= wbs_bte_i;
159 12 unneback
 
160
// wbm FIFO
161
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
162
always @ (posedge wbm_clk or posedge wbm_rst)
163
if (wbm_rst)
164
        wbm_eoc <= 1'b0;
165
else
166
        if (wbm==wbm_adr0 & !b_fifo_empty)
167
                wbm_eoc <= b_q[`BTE] == linear;
168
        else if (wbm_eoc_alert & wbm_ack_i)
169
                wbm_eoc <= 1'b1;
170
 
171
always @ (posedge wbm_clk or posedge wbm_rst)
172
if (wbm_rst)
173
        wbm <= wbm_adr0;
174
else
175 33 unneback
/*
176 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
177
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
178
        (wbm==wbm_adr1 & !wbm_we_o) |
179
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
180
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
181 33 unneback
*/
182
    case (wbm)
183
    wbm_adr0:
184
        if (!b_fifo_empty)
185
            wbm <= wbm_adr1;
186
    wbm_adr1:
187
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
188
            wbm <= wbm_data;
189
    wbm_data:
190
        if (wbm_ack_i & wbm_eoc)
191
            wbm <= wbm_adr0;
192
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
193
            wbm <= wbm_data_wait;
194
    wbm_data_wait:
195
        if (!b_fifo_empty)
196
            wbm <= wbm_data;
197
    endcase
198 12 unneback
 
199
assign b_d = {wbm_dat_i,4'b1111};
200
assign b_wr = !wbm_we_o & wbm_ack_i;
201
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
202
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
203
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
204 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
205 12 unneback
                   1'b0;
206
assign b_rd = b_rd_adr | b_rd_data;
207
 
208 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
209
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
210 12 unneback
 
211
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
212
 
213 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
214 12 unneback
    cnt1 (
215
        .cke(wbm_ack_i),
216
        .clear(wbm_eoc),
217
        .q(wbm_count),
218
        .rst(wbm_rst),
219
        .clk(wbm_clk));
220
 
221 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
222
assign wbm_stb_o = (wbm==wbm_data);
223 12 unneback
 
224
always @ (posedge wbm_clk or posedge wbm_rst)
225
if (wbm_rst)
226
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
227
else begin
228
        if (wbm==wbm_adr0 & !b_fifo_empty)
229
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
230
        else if (wbm_eoc_alert & wbm_ack_i)
231
                wbm_cti_o <= endofburst;
232
end
233
 
234
//async_fifo_dw_simplex_top
235
vl_fifo_2r2w_async_simplex
236
# ( .data_width(36), .addr_width(addr_width))
237
fifo (
238
    // a side
239
    .a_d(a_d),
240
    .a_wr(a_wr),
241
    .a_fifo_full(a_fifo_full),
242
    .a_q(a_q),
243
    .a_rd(a_rd),
244
    .a_fifo_empty(a_fifo_empty),
245
    .a_clk(wbs_clk),
246
    .a_rst(wbs_rst),
247
    // b side
248
    .b_d(b_d),
249
    .b_wr(b_wr),
250
    .b_fifo_full(b_fifo_full),
251
    .b_q(b_q),
252
    .b_rd(b_rd),
253
    .b_fifo_empty(b_fifo_empty),
254
    .b_clk(wbm_clk),
255
    .b_rst(wbm_rst)
256
    );
257
 
258
endmodule
259 17 unneback
 
260
// WB ROM
261 18 unneback
module vl_wb_boot_rom (
262 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
263 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
264 17 unneback
 
265 18 unneback
    parameter adr_hi = 31;
266
    parameter adr_lo = 28;
267
    parameter adr_sel = 4'hf;
268
    parameter addr_width = 5;
269 33 unneback
/*
270 17 unneback
//E2_ifndef BOOT_ROM
271
//E2_define BOOT_ROM "boot_rom.v"
272
//E2_endif
273 33 unneback
*/
274 18 unneback
    input [adr_hi:2]    wb_adr_i;
275
    input               wb_stb_i;
276
    input               wb_cyc_i;
277
    output [31:0]        wb_dat_o;
278
    output              wb_ack_o;
279
    output              hit_o;
280
    input               wb_clk;
281
    input               wb_rst;
282
 
283
    wire hit;
284
    reg [31:0] wb_dat;
285
    reg wb_ack;
286
 
287
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
288 17 unneback
 
289
always @ (posedge wb_clk or posedge wb_rst)
290
    if (wb_rst)
291 18 unneback
        wb_dat <= 32'h15000000;
292 17 unneback
    else
293 18 unneback
         case (wb_adr_i[addr_width-1:2])
294 33 unneback
//E2_ifdef BOOT_ROM
295 17 unneback
//E2_include `BOOT_ROM
296 33 unneback
//E2_endif
297 17 unneback
           /*
298
            // Zero r0 and jump to 0x00000100
299 18 unneback
 
300
            1 : wb_dat <= 32'hA8200000;
301
            2 : wb_dat <= 32'hA8C00100;
302
            3 : wb_dat <= 32'h44003000;
303
            4 : wb_dat <= 32'h15000000;
304 17 unneback
            */
305
           default:
306 18 unneback
             wb_dat <= 32'h00000000;
307 17 unneback
 
308
         endcase // case (wb_adr_i)
309
 
310
 
311
always @ (posedge wb_clk or posedge wb_rst)
312
    if (wb_rst)
313 18 unneback
        wb_ack <= 1'b0;
314 17 unneback
    else
315 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
316 17 unneback
 
317 18 unneback
assign hit_o = hit;
318
assign wb_dat_o = wb_dat & {32{wb_ack}};
319
assign wb_ack_o = wb_ack;
320
 
321 17 unneback
endmodule
322 32 unneback
 
323
module vl_wb_dpram (
324
        // wishbone slave side a
325
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
326
        wbsa_clk, wbsa_rst,
327
        // wishbone slave side a
328
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
329
        wbsb_clk, wbsb_rst);
330
 
331
parameter data_width = 32;
332
parameter addr_width = 8;
333
 
334
parameter dat_o_mask_a = 1;
335
parameter dat_o_mask_b = 1;
336
 
337
input [31:0] wbsa_dat_i;
338
input [addr_width-1:2] wbsa_adr_i;
339
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
340
output [31:0] wbsa_dat_o;
341
output wbsa_ack_o;
342
input wbsa_clk, wbsa_rst;
343
 
344
input [31:0] wbsb_dat_i;
345
input [addr_width-1:2] wbsb_adr_i;
346
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
347
output [31:0] wbsb_dat_o;
348
output wbsb_ack_o;
349
input wbsb_clk, wbsb_rst;
350
 
351
wire wbsa_dat_tmp, wbsb_dat_tmp;
352
 
353
vl_dpram_2r2w # (
354 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
355 32 unneback
dpram0(
356
    .d_a(wbsa_dat_i),
357
    .q_a(wbsa_dat_tmp),
358
    .adr_a(wbsa_adr_i),
359
    .we_a(wbsa_we_i),
360
    .clk_a(wbsa_clk),
361
    .d_b(wbsb_dat_i),
362
    .q_b(wbsb_dat_tmp),
363
    .adr_b(wbsb_adr_i),
364
    .we_b(wbsb_we_i),
365
    .clk_b(wbsb_clk) );
366
 
367 33 unneback
generate if (dat_o_mask_a==1)
368 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
369
endgenerate
370 33 unneback
generate if (dat_o_mask_a==0)
371 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
372
endgenerate
373
 
374 33 unneback
generate if (dat_o_mask_b==1)
375 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
376
endgenerate
377 33 unneback
generate if (dat_o_mask_b==0)
378 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
379
endgenerate
380
 
381
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
382
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
383
 
384
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.