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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef WB3WB3_BRIDGE
44 12 unneback
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46 40 unneback
`define MODULE wb3wb3_bridge
47
module `BASE`MODULE (
48
`undef MODULE
49 12 unneback
        // wishbone slave side
50
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
51
        // wishbone master side
52
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
53
 
54
input [31:0] wbs_dat_i;
55
input [31:2] wbs_adr_i;
56
input [3:0]  wbs_sel_i;
57
input [1:0]  wbs_bte_i;
58
input [2:0]  wbs_cti_i;
59
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
60
output [31:0] wbs_dat_o;
61 14 unneback
output wbs_ack_o;
62 12 unneback
input wbs_clk, wbs_rst;
63
 
64
output [31:0] wbm_dat_o;
65
output reg [31:2] wbm_adr_o;
66
output [3:0]  wbm_sel_o;
67
output reg [1:0]  wbm_bte_o;
68
output reg [2:0]  wbm_cti_o;
69 14 unneback
output reg wbm_we_o;
70
output wbm_cyc_o;
71 12 unneback
output wbm_stb_o;
72
input [31:0]  wbm_dat_i;
73
input wbm_ack_i;
74
input wbm_clk, wbm_rst;
75
 
76
parameter addr_width = 4;
77
 
78
// bte
79
parameter linear       = 2'b00;
80
parameter wrap4        = 2'b01;
81
parameter wrap8        = 2'b10;
82
parameter wrap16       = 2'b11;
83
// cti
84
parameter classic      = 3'b000;
85
parameter incburst     = 3'b010;
86
parameter endofburst   = 3'b111;
87
 
88
parameter wbs_adr  = 1'b0;
89
parameter wbs_data = 1'b1;
90
 
91 33 unneback
parameter wbm_adr0      = 2'b00;
92
parameter wbm_adr1      = 2'b01;
93
parameter wbm_data      = 2'b10;
94
parameter wbm_data_wait = 2'b11;
95 12 unneback
 
96
reg [1:0] wbs_bte_reg;
97
reg wbs;
98
wire wbs_eoc_alert, wbm_eoc_alert;
99
reg wbs_eoc, wbm_eoc;
100
reg [1:0] wbm;
101
 
102 14 unneback
wire [1:16] wbs_count, wbm_count;
103 12 unneback
 
104
wire [35:0] a_d, a_q, b_d, b_q;
105
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
106
reg a_rd_reg;
107
wire b_rd_adr, b_rd_data;
108 14 unneback
wire b_rd_data_reg;
109
wire [35:0] temp;
110 12 unneback
 
111
`define WE 5
112
`define BTE 4:3
113
`define CTI 2:0
114
 
115
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
116
always @ (posedge wbs_clk or posedge wbs_rst)
117
if (wbs_rst)
118
        wbs_eoc <= 1'b0;
119
else
120
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
121
                wbs_eoc <= wbs_bte_i==linear;
122
        else if (wbs_eoc_alert & (a_rd | a_wr))
123
                wbs_eoc <= 1'b1;
124
 
125 40 unneback
`define MODULE cnt_shreg_ce_clear
126
`BASE`MODULE # ( .length(16))
127
`undef MODULE
128 12 unneback
    cnt0 (
129
        .cke(wbs_ack_o),
130
        .clear(wbs_eoc),
131
        .q(wbs_count),
132
        .rst(wbs_rst),
133
        .clk(wbs_clk));
134
 
135
always @ (posedge wbs_clk or posedge wbs_rst)
136
if (wbs_rst)
137
        wbs <= wbs_adr;
138
else
139
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
140
                wbs <= wbs_data;
141
        else if (wbs_eoc & wbs_ack_o)
142
                wbs <= wbs_adr;
143
 
144
// wbs FIFO
145
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
146
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
147
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
148
              1'b0;
149
assign a_rd = !a_fifo_empty;
150
always @ (posedge wbs_clk or posedge wbs_rst)
151
if (wbs_rst)
152
        a_rd_reg <= 1'b0;
153
else
154
        a_rd_reg <= a_rd;
155
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
156
 
157
assign wbs_dat_o = a_q[35:4];
158
 
159
always @ (posedge wbs_clk or posedge wbs_rst)
160
if (wbs_rst)
161 13 unneback
        wbs_bte_reg <= 2'b00;
162 12 unneback
else
163 13 unneback
        wbs_bte_reg <= wbs_bte_i;
164 12 unneback
 
165
// wbm FIFO
166
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
167
always @ (posedge wbm_clk or posedge wbm_rst)
168
if (wbm_rst)
169
        wbm_eoc <= 1'b0;
170
else
171
        if (wbm==wbm_adr0 & !b_fifo_empty)
172
                wbm_eoc <= b_q[`BTE] == linear;
173
        else if (wbm_eoc_alert & wbm_ack_i)
174
                wbm_eoc <= 1'b1;
175
 
176
always @ (posedge wbm_clk or posedge wbm_rst)
177
if (wbm_rst)
178
        wbm <= wbm_adr0;
179
else
180 33 unneback
/*
181 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
182
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
183
        (wbm==wbm_adr1 & !wbm_we_o) |
184
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
185
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
186 33 unneback
*/
187
    case (wbm)
188
    wbm_adr0:
189
        if (!b_fifo_empty)
190
            wbm <= wbm_adr1;
191
    wbm_adr1:
192
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
193
            wbm <= wbm_data;
194
    wbm_data:
195
        if (wbm_ack_i & wbm_eoc)
196
            wbm <= wbm_adr0;
197
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
198
            wbm <= wbm_data_wait;
199
    wbm_data_wait:
200
        if (!b_fifo_empty)
201
            wbm <= wbm_data;
202
    endcase
203 12 unneback
 
204
assign b_d = {wbm_dat_i,4'b1111};
205
assign b_wr = !wbm_we_o & wbm_ack_i;
206
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
207
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
208
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
209 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
210 12 unneback
                   1'b0;
211
assign b_rd = b_rd_adr | b_rd_data;
212
 
213 40 unneback
`define MODULE dff
214
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
215
`undef MODULE
216
`define MODULE dff_ce
217
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
218
`undef MODULE
219 12 unneback
 
220
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
221
 
222 40 unneback
`define MODULE cnt_shreg_ce_clear
223 42 unneback
`BASE`MODULE # ( .length(16))
224 40 unneback
`undef MODULE
225 12 unneback
    cnt1 (
226
        .cke(wbm_ack_i),
227
        .clear(wbm_eoc),
228
        .q(wbm_count),
229
        .rst(wbm_rst),
230
        .clk(wbm_clk));
231
 
232 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
233
assign wbm_stb_o = (wbm==wbm_data);
234 12 unneback
 
235
always @ (posedge wbm_clk or posedge wbm_rst)
236
if (wbm_rst)
237
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
238
else begin
239
        if (wbm==wbm_adr0 & !b_fifo_empty)
240
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
241
        else if (wbm_eoc_alert & wbm_ack_i)
242
                wbm_cti_o <= endofburst;
243
end
244
 
245
//async_fifo_dw_simplex_top
246 40 unneback
`define MODULE fifo_2r2w_async_simplex
247
`BASE`MODULE
248
`undef MODULE
249 12 unneback
# ( .data_width(36), .addr_width(addr_width))
250
fifo (
251
    // a side
252
    .a_d(a_d),
253
    .a_wr(a_wr),
254
    .a_fifo_full(a_fifo_full),
255
    .a_q(a_q),
256
    .a_rd(a_rd),
257
    .a_fifo_empty(a_fifo_empty),
258
    .a_clk(wbs_clk),
259
    .a_rst(wbs_rst),
260
    // b side
261
    .b_d(b_d),
262
    .b_wr(b_wr),
263
    .b_fifo_full(b_fifo_full),
264
    .b_q(b_q),
265
    .b_rd(b_rd),
266
    .b_fifo_empty(b_fifo_empty),
267
    .b_clk(wbm_clk),
268
    .b_rst(wbm_rst)
269
    );
270
 
271
endmodule
272 40 unneback
`undef WE
273
`undef BTE
274
`undef CTI
275
`endif
276 17 unneback
 
277 40 unneback
`ifdef WB3_ARBITER_TYPE1
278
`define MODULE wb3_arbiter_type1
279 42 unneback
module `BASE`MODULE (
280 40 unneback
`undef MODULE
281 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
282
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
283
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
284
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
285
    wb_clk, wb_rst
286
);
287
 
288
parameter nr_of_ports = 3;
289
parameter adr_size = 26;
290
parameter adr_lo   = 2;
291
parameter dat_size = 32;
292
parameter sel_size = dat_size/8;
293
 
294
localparam aw = (adr_size - adr_lo) * nr_of_ports;
295
localparam dw = dat_size * nr_of_ports;
296
localparam sw = sel_size * nr_of_ports;
297
localparam cw = 3 * nr_of_ports;
298
localparam bw = 2 * nr_of_ports;
299
 
300
input  [dw-1:0] wbm_dat_o;
301
input  [aw-1:0] wbm_adr_o;
302
input  [sw-1:0] wbm_sel_o;
303
input  [cw-1:0] wbm_cti_o;
304
input  [bw-1:0] wbm_bte_o;
305
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
306
output [dw-1:0] wbm_dat_i;
307
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
308
 
309
output [dat_size-1:0] wbs_dat_i;
310
output [adr_size-1:adr_lo] wbs_adr_i;
311
output [sel_size-1:0] wbs_sel_i;
312
output [2:0] wbs_cti_i;
313
output [1:0] wbs_bte_i;
314
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
315
input  [dat_size-1:0] wbs_dat_o;
316
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
317
 
318
input wb_clk, wb_rst;
319
 
320 44 unneback
reg  [nr_of_ports-1:0] select;
321 39 unneback
wire [nr_of_ports-1:0] state;
322
wire [nr_of_ports-1:0] eoc; // end-of-cycle
323
wire [nr_of_ports-1:0] sel;
324
wire idle;
325
 
326
genvar i;
327
 
328
assign idle = !(|state);
329
 
330
generate
331
if (nr_of_ports == 2) begin
332
 
333
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
334
 
335
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
336
 
337 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
338
 
339
    always @ (idle or wbm_cyc_o)
340
    if (idle)
341
        casex (wbm_cyc_o)
342
        2'b1x : select = 2'b10;
343
        2'b01 : select = 2'b01;
344
        default : select = {nr_of_ports{1'b0}};
345
        endcase
346
    else
347
        select = {nr_of_ports{1'b0}};
348
 
349 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
350
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
351
 
352
end
353
endgenerate
354
 
355
generate
356
if (nr_of_ports == 3) begin
357
 
358
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
359
 
360
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
361
 
362 44 unneback
    always @ (idle or wbm_cyc_o)
363
    if (idle)
364
        casex (wbm_cyc_o)
365
        3'b1xx : select = 3'b100;
366
        3'b01x : select = 3'b010;
367
        3'b001 : select = 3'b001;
368
        default : select = {nr_of_ports{1'b0}};
369
        endcase
370
    else
371
        select = {nr_of_ports{1'b0}};
372
 
373
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
374 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
375
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
376
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
377
 
378
end
379
endgenerate
380
 
381
generate
382 44 unneback
if (nr_of_ports == 4) begin
383
 
384
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
385
 
386
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
387
 
388
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
389
 
390
    always @ (idle or wbm_cyc_o)
391
    if (idle)
392
        casex (wbm_cyc_o)
393
        4'b1xxx : select = 4'b1000;
394
        4'b01xx : select = 4'b0100;
395
        4'b001x : select = 4'b0010;
396
        4'b0001 : select = 4'b0001;
397
        default : select = {nr_of_ports{1'b0}};
398
        endcase
399
    else
400
        select = {nr_of_ports{1'b0}};
401
 
402
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
403
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
404
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
405
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
406
 
407
end
408
endgenerate
409
 
410
generate
411
if (nr_of_ports == 5) begin
412
 
413
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
414
 
415
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
416
 
417
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
418
 
419
    always @ (idle or wbm_cyc_o)
420
    if (idle)
421
        casex (wbm_cyc_o)
422
        5'b1xxxx : select = 5'b10000;
423
        5'b01xxx : select = 5'b01000;
424
        5'b001xx : select = 5'b00100;
425
        5'b0001x : select = 5'b00010;
426
        5'b00001 : select = 5'b00001;
427
        default : select = {nr_of_ports{1'b0}};
428
        endcase
429
    else
430
        select = {nr_of_ports{1'b0}};
431
 
432
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
433
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
434
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
435
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
436
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
437
 
438
end
439
endgenerate
440
 
441
generate
442 39 unneback
for (i=0;i<nr_of_ports;i=i+1) begin
443 42 unneback
`define MODULE spr
444
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
445
`undef MODULE
446 39 unneback
end
447
endgenerate
448
 
449
    assign sel = select | state;
450
 
451 40 unneback
`define MODULE mux_andor
452
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
453
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
454
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
455
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
456
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
457
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
458
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
459
`undef MODULE
460 39 unneback
    assign wbs_cyc_i = |sel;
461
 
462
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
463
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
464
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
465
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
466
 
467
endmodule
468 40 unneback
`endif
469 39 unneback
 
470 49 unneback
`ifdef WB_B4_RAM_BE
471
// WB RAM with byte enable
472
`define MODULE wb_b4_ram_be
473
module `BASE`MODULE (
474
`undef MODULE
475
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
476 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
477 49 unneback
 
478
    parameter dat_width = 32;
479
    parameter adr_width = 8;
480
 
481
input [dat_width-1:0] wb_dat_i;
482
input [adr_width-1:0] wb_adr_i;
483
input [dat_width/8-1:0] wb_sel_i;
484
input wb_we_i, wb_stb_i, wb_cyc_i;
485
output [dat_width-1:0] wb_dat_o;
486 51 unneback
reg [dat_width-1:0] wb_dat_o;
487 52 unneback
output wb_stall_o;
488 49 unneback
output wb_ack_o;
489
reg wb_ack_o;
490
input wb_clk, wb_rst;
491
 
492
generate
493
if (dat_width==32) begin
494 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
495
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
496
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
497
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
498 49 unneback
    always @ (posedge wb_clk)
499
    begin
500 50 unneback
        if (wb_sel_i[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
501
        if (wb_sel_i[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
502
        if (wb_sel_i[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
503
        if (wb_sel_i[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
504 51 unneback
        wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
505 49 unneback
    end
506
end
507
endgenerate
508
 
509 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
510 55 unneback
if (wb_rst)
511 52 unneback
    wb_ack_o <= 1'b0;
512
else
513 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
514 52 unneback
 
515
assign wb_stall_o = 1'b0;
516
 
517 49 unneback
endmodule
518
`endif
519
 
520 48 unneback
`ifdef WB_B4_ROM
521
// WB ROM
522
`define MODULE wb_b4_rom
523
module `BASE`MODULE (
524
`undef MODULE
525
    wb_adr_i, wb_stb_i, wb_cyc_i,
526
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
527
 
528
    parameter dat_width = 32;
529
    parameter dat_default = 32'h15000000;
530
    parameter adr_width = 32;
531
 
532
/*
533
//E2_ifndef ROM
534
//E2_define ROM "rom.v"
535
//E2_endif
536
*/
537
    input [adr_width-1:2]   wb_adr_i;
538
    input                   wb_stb_i;
539
    input                   wb_cyc_i;
540
    output [dat_width-1:0]  wb_dat_o;
541
    reg [dat_width-1:0]     wb_dat_o;
542
    output                  wb_ack_o;
543
    reg                     wb_ack_o;
544
    output                  stall_o;
545
    input                   wb_clk;
546
    input                   wb_rst;
547
 
548
always @ (posedge wb_clk or posedge wb_rst)
549
    if (wb_rst)
550
        wb_dat_o <= {dat_width{1'b0}};
551
    else
552
         case (wb_adr_i[adr_width-1:2])
553
//E2_ifdef ROM
554
//E2_include `ROM
555
//E2_endif
556
           default:
557
             wb_dat_o <= dat_default;
558
 
559
         endcase // case (wb_adr_i)
560
 
561
 
562
always @ (posedge wb_clk or posedge wb_rst)
563
    if (wb_rst)
564
        wb_ack_o <= 1'b0;
565
    else
566
        wb_ack_o <= wb_stb_i & wb_cyc_i;
567
 
568
assign stall_o = 1'b0;
569
 
570
endmodule
571
`endif
572
 
573
 
574 40 unneback
`ifdef WB_BOOT_ROM
575 17 unneback
// WB ROM
576 40 unneback
`define MODULE wb_boot_rom
577
module `BASE`MODULE (
578
`undef MODULE
579 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
580 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
581 17 unneback
 
582 18 unneback
    parameter adr_hi = 31;
583
    parameter adr_lo = 28;
584
    parameter adr_sel = 4'hf;
585
    parameter addr_width = 5;
586 33 unneback
/*
587 17 unneback
//E2_ifndef BOOT_ROM
588
//E2_define BOOT_ROM "boot_rom.v"
589
//E2_endif
590 33 unneback
*/
591 18 unneback
    input [adr_hi:2]    wb_adr_i;
592
    input               wb_stb_i;
593
    input               wb_cyc_i;
594
    output [31:0]        wb_dat_o;
595
    output              wb_ack_o;
596
    output              hit_o;
597
    input               wb_clk;
598
    input               wb_rst;
599
 
600
    wire hit;
601
    reg [31:0] wb_dat;
602
    reg wb_ack;
603
 
604
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
605 17 unneback
 
606
always @ (posedge wb_clk or posedge wb_rst)
607
    if (wb_rst)
608 18 unneback
        wb_dat <= 32'h15000000;
609 17 unneback
    else
610 18 unneback
         case (wb_adr_i[addr_width-1:2])
611 33 unneback
//E2_ifdef BOOT_ROM
612 17 unneback
//E2_include `BOOT_ROM
613 33 unneback
//E2_endif
614 17 unneback
           /*
615
            // Zero r0 and jump to 0x00000100
616 18 unneback
 
617
            1 : wb_dat <= 32'hA8200000;
618
            2 : wb_dat <= 32'hA8C00100;
619
            3 : wb_dat <= 32'h44003000;
620
            4 : wb_dat <= 32'h15000000;
621 17 unneback
            */
622
           default:
623 18 unneback
             wb_dat <= 32'h00000000;
624 17 unneback
 
625
         endcase // case (wb_adr_i)
626
 
627
 
628
always @ (posedge wb_clk or posedge wb_rst)
629
    if (wb_rst)
630 18 unneback
        wb_ack <= 1'b0;
631 17 unneback
    else
632 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
633 17 unneback
 
634 18 unneback
assign hit_o = hit;
635
assign wb_dat_o = wb_dat & {32{wb_ack}};
636
assign wb_ack_o = wb_ack;
637
 
638 17 unneback
endmodule
639 40 unneback
`endif
640 32 unneback
 
641 40 unneback
`ifdef WB_DPRAM
642
`define MODULE wb_dpram
643
module `BASE`MODULE (
644
`undef MODULE
645 32 unneback
        // wishbone slave side a
646
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
647
        wbsa_clk, wbsa_rst,
648
        // wishbone slave side a
649
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
650
        wbsb_clk, wbsb_rst);
651
 
652
parameter data_width = 32;
653
parameter addr_width = 8;
654
 
655
parameter dat_o_mask_a = 1;
656
parameter dat_o_mask_b = 1;
657
 
658
input [31:0] wbsa_dat_i;
659
input [addr_width-1:2] wbsa_adr_i;
660
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
661
output [31:0] wbsa_dat_o;
662
output wbsa_ack_o;
663
input wbsa_clk, wbsa_rst;
664
 
665
input [31:0] wbsb_dat_i;
666
input [addr_width-1:2] wbsb_adr_i;
667
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
668
output [31:0] wbsb_dat_o;
669
output wbsb_ack_o;
670
input wbsb_clk, wbsb_rst;
671
 
672
wire wbsa_dat_tmp, wbsb_dat_tmp;
673
 
674 40 unneback
`define MODULE dpram_2r2w
675
`BASE`MODULE # (
676
`undef MODULE
677 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
678 32 unneback
dpram0(
679
    .d_a(wbsa_dat_i),
680
    .q_a(wbsa_dat_tmp),
681
    .adr_a(wbsa_adr_i),
682
    .we_a(wbsa_we_i),
683
    .clk_a(wbsa_clk),
684
    .d_b(wbsb_dat_i),
685
    .q_b(wbsb_dat_tmp),
686
    .adr_b(wbsb_adr_i),
687
    .we_b(wbsb_we_i),
688
    .clk_b(wbsb_clk) );
689
 
690 33 unneback
generate if (dat_o_mask_a==1)
691 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
692
endgenerate
693 33 unneback
generate if (dat_o_mask_a==0)
694 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
695
endgenerate
696
 
697 33 unneback
generate if (dat_o_mask_b==1)
698 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
699
endgenerate
700 33 unneback
generate if (dat_o_mask_b==0)
701 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
702
endgenerate
703
 
704 40 unneback
`define MODULE spr
705
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
706
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
707
`undef MODULE
708 32 unneback
 
709
endmodule
710 40 unneback
`endif

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