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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef WB3WB3_BRIDGE
44 12 unneback
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46 40 unneback
`define MODULE wb3wb3_bridge
47
module `BASE`MODULE (
48
`undef MODULE
49 12 unneback
        // wishbone slave side
50
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
51
        // wishbone master side
52
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
53
 
54
input [31:0] wbs_dat_i;
55
input [31:2] wbs_adr_i;
56
input [3:0]  wbs_sel_i;
57
input [1:0]  wbs_bte_i;
58
input [2:0]  wbs_cti_i;
59
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
60
output [31:0] wbs_dat_o;
61 14 unneback
output wbs_ack_o;
62 12 unneback
input wbs_clk, wbs_rst;
63
 
64
output [31:0] wbm_dat_o;
65
output reg [31:2] wbm_adr_o;
66
output [3:0]  wbm_sel_o;
67
output reg [1:0]  wbm_bte_o;
68
output reg [2:0]  wbm_cti_o;
69 14 unneback
output reg wbm_we_o;
70
output wbm_cyc_o;
71 12 unneback
output wbm_stb_o;
72
input [31:0]  wbm_dat_i;
73
input wbm_ack_i;
74
input wbm_clk, wbm_rst;
75
 
76
parameter addr_width = 4;
77
 
78
// bte
79
parameter linear       = 2'b00;
80
parameter wrap4        = 2'b01;
81
parameter wrap8        = 2'b10;
82
parameter wrap16       = 2'b11;
83
// cti
84
parameter classic      = 3'b000;
85
parameter incburst     = 3'b010;
86
parameter endofburst   = 3'b111;
87
 
88
parameter wbs_adr  = 1'b0;
89
parameter wbs_data = 1'b1;
90
 
91 33 unneback
parameter wbm_adr0      = 2'b00;
92
parameter wbm_adr1      = 2'b01;
93
parameter wbm_data      = 2'b10;
94
parameter wbm_data_wait = 2'b11;
95 12 unneback
 
96
reg [1:0] wbs_bte_reg;
97
reg wbs;
98
wire wbs_eoc_alert, wbm_eoc_alert;
99
reg wbs_eoc, wbm_eoc;
100
reg [1:0] wbm;
101
 
102 14 unneback
wire [1:16] wbs_count, wbm_count;
103 12 unneback
 
104
wire [35:0] a_d, a_q, b_d, b_q;
105
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
106
reg a_rd_reg;
107
wire b_rd_adr, b_rd_data;
108 14 unneback
wire b_rd_data_reg;
109
wire [35:0] temp;
110 12 unneback
 
111
`define WE 5
112
`define BTE 4:3
113
`define CTI 2:0
114
 
115
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
116
always @ (posedge wbs_clk or posedge wbs_rst)
117
if (wbs_rst)
118
        wbs_eoc <= 1'b0;
119
else
120
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
121
                wbs_eoc <= wbs_bte_i==linear;
122
        else if (wbs_eoc_alert & (a_rd | a_wr))
123
                wbs_eoc <= 1'b1;
124
 
125 40 unneback
`define MODULE cnt_shreg_ce_clear
126
`BASE`MODULE # ( .length(16))
127
`undef MODULE
128 12 unneback
    cnt0 (
129
        .cke(wbs_ack_o),
130
        .clear(wbs_eoc),
131
        .q(wbs_count),
132
        .rst(wbs_rst),
133
        .clk(wbs_clk));
134
 
135
always @ (posedge wbs_clk or posedge wbs_rst)
136
if (wbs_rst)
137
        wbs <= wbs_adr;
138
else
139
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
140
                wbs <= wbs_data;
141
        else if (wbs_eoc & wbs_ack_o)
142
                wbs <= wbs_adr;
143
 
144
// wbs FIFO
145
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
146
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
147
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
148
              1'b0;
149
assign a_rd = !a_fifo_empty;
150
always @ (posedge wbs_clk or posedge wbs_rst)
151
if (wbs_rst)
152
        a_rd_reg <= 1'b0;
153
else
154
        a_rd_reg <= a_rd;
155
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
156
 
157
assign wbs_dat_o = a_q[35:4];
158
 
159
always @ (posedge wbs_clk or posedge wbs_rst)
160
if (wbs_rst)
161 13 unneback
        wbs_bte_reg <= 2'b00;
162 12 unneback
else
163 13 unneback
        wbs_bte_reg <= wbs_bte_i;
164 12 unneback
 
165
// wbm FIFO
166
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
167
always @ (posedge wbm_clk or posedge wbm_rst)
168
if (wbm_rst)
169
        wbm_eoc <= 1'b0;
170
else
171
        if (wbm==wbm_adr0 & !b_fifo_empty)
172
                wbm_eoc <= b_q[`BTE] == linear;
173
        else if (wbm_eoc_alert & wbm_ack_i)
174
                wbm_eoc <= 1'b1;
175
 
176
always @ (posedge wbm_clk or posedge wbm_rst)
177
if (wbm_rst)
178
        wbm <= wbm_adr0;
179
else
180 33 unneback
/*
181 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
182
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
183
        (wbm==wbm_adr1 & !wbm_we_o) |
184
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
185
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
186 33 unneback
*/
187
    case (wbm)
188
    wbm_adr0:
189
        if (!b_fifo_empty)
190
            wbm <= wbm_adr1;
191
    wbm_adr1:
192
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
193
            wbm <= wbm_data;
194
    wbm_data:
195
        if (wbm_ack_i & wbm_eoc)
196
            wbm <= wbm_adr0;
197
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
198
            wbm <= wbm_data_wait;
199
    wbm_data_wait:
200
        if (!b_fifo_empty)
201
            wbm <= wbm_data;
202
    endcase
203 12 unneback
 
204
assign b_d = {wbm_dat_i,4'b1111};
205
assign b_wr = !wbm_we_o & wbm_ack_i;
206
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
207
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
208
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
209 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
210 12 unneback
                   1'b0;
211
assign b_rd = b_rd_adr | b_rd_data;
212
 
213 40 unneback
`define MODULE dff
214
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
215
`undef MODULE
216
`define MODULE dff_ce
217
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
218
`undef MODULE
219 12 unneback
 
220
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
221
 
222 40 unneback
`define MODULE cnt_shreg_ce_clear
223 42 unneback
`BASE`MODULE # ( .length(16))
224 40 unneback
`undef MODULE
225 12 unneback
    cnt1 (
226
        .cke(wbm_ack_i),
227
        .clear(wbm_eoc),
228
        .q(wbm_count),
229
        .rst(wbm_rst),
230
        .clk(wbm_clk));
231
 
232 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
233
assign wbm_stb_o = (wbm==wbm_data);
234 12 unneback
 
235
always @ (posedge wbm_clk or posedge wbm_rst)
236
if (wbm_rst)
237
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
238
else begin
239
        if (wbm==wbm_adr0 & !b_fifo_empty)
240
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
241
        else if (wbm_eoc_alert & wbm_ack_i)
242
                wbm_cti_o <= endofburst;
243
end
244
 
245
//async_fifo_dw_simplex_top
246 40 unneback
`define MODULE fifo_2r2w_async_simplex
247
`BASE`MODULE
248
`undef MODULE
249 12 unneback
# ( .data_width(36), .addr_width(addr_width))
250
fifo (
251
    // a side
252
    .a_d(a_d),
253
    .a_wr(a_wr),
254
    .a_fifo_full(a_fifo_full),
255
    .a_q(a_q),
256
    .a_rd(a_rd),
257
    .a_fifo_empty(a_fifo_empty),
258
    .a_clk(wbs_clk),
259
    .a_rst(wbs_rst),
260
    // b side
261
    .b_d(b_d),
262
    .b_wr(b_wr),
263
    .b_fifo_full(b_fifo_full),
264
    .b_q(b_q),
265
    .b_rd(b_rd),
266
    .b_fifo_empty(b_fifo_empty),
267
    .b_clk(wbm_clk),
268
    .b_rst(wbm_rst)
269
    );
270
 
271
endmodule
272 40 unneback
`undef WE
273
`undef BTE
274
`undef CTI
275
`endif
276 17 unneback
 
277 40 unneback
`ifdef WB3_ARBITER_TYPE1
278
`define MODULE wb3_arbiter_type1
279 42 unneback
module `BASE`MODULE (
280 40 unneback
`undef MODULE
281 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
282
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
283
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
284
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
285
    wb_clk, wb_rst
286
);
287
 
288
parameter nr_of_ports = 3;
289
parameter adr_size = 26;
290
parameter adr_lo   = 2;
291
parameter dat_size = 32;
292
parameter sel_size = dat_size/8;
293
 
294
localparam aw = (adr_size - adr_lo) * nr_of_ports;
295
localparam dw = dat_size * nr_of_ports;
296
localparam sw = sel_size * nr_of_ports;
297
localparam cw = 3 * nr_of_ports;
298
localparam bw = 2 * nr_of_ports;
299
 
300
input  [dw-1:0] wbm_dat_o;
301
input  [aw-1:0] wbm_adr_o;
302
input  [sw-1:0] wbm_sel_o;
303
input  [cw-1:0] wbm_cti_o;
304
input  [bw-1:0] wbm_bte_o;
305
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
306
output [dw-1:0] wbm_dat_i;
307
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
308
 
309
output [dat_size-1:0] wbs_dat_i;
310
output [adr_size-1:adr_lo] wbs_adr_i;
311
output [sel_size-1:0] wbs_sel_i;
312
output [2:0] wbs_cti_i;
313
output [1:0] wbs_bte_i;
314
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
315
input  [dat_size-1:0] wbs_dat_o;
316
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
317
 
318
input wb_clk, wb_rst;
319
 
320 44 unneback
reg  [nr_of_ports-1:0] select;
321 39 unneback
wire [nr_of_ports-1:0] state;
322
wire [nr_of_ports-1:0] eoc; // end-of-cycle
323
wire [nr_of_ports-1:0] sel;
324
wire idle;
325
 
326
genvar i;
327
 
328
assign idle = !(|state);
329
 
330
generate
331
if (nr_of_ports == 2) begin
332
 
333
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
334
 
335
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
336
 
337 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
338
 
339
    always @ (idle or wbm_cyc_o)
340
    if (idle)
341
        casex (wbm_cyc_o)
342
        2'b1x : select = 2'b10;
343
        2'b01 : select = 2'b01;
344
        default : select = {nr_of_ports{1'b0}};
345
        endcase
346
    else
347
        select = {nr_of_ports{1'b0}};
348
 
349 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
350
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
351
 
352
end
353
endgenerate
354
 
355
generate
356
if (nr_of_ports == 3) begin
357
 
358
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
359
 
360
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
361
 
362 44 unneback
    always @ (idle or wbm_cyc_o)
363
    if (idle)
364
        casex (wbm_cyc_o)
365
        3'b1xx : select = 3'b100;
366
        3'b01x : select = 3'b010;
367
        3'b001 : select = 3'b001;
368
        default : select = {nr_of_ports{1'b0}};
369
        endcase
370
    else
371
        select = {nr_of_ports{1'b0}};
372
 
373
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
374 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
375
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
376
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
377
 
378
end
379
endgenerate
380
 
381
generate
382 44 unneback
if (nr_of_ports == 4) begin
383
 
384
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
385
 
386
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
387
 
388
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
389
 
390
    always @ (idle or wbm_cyc_o)
391
    if (idle)
392
        casex (wbm_cyc_o)
393
        4'b1xxx : select = 4'b1000;
394
        4'b01xx : select = 4'b0100;
395
        4'b001x : select = 4'b0010;
396
        4'b0001 : select = 4'b0001;
397
        default : select = {nr_of_ports{1'b0}};
398
        endcase
399
    else
400
        select = {nr_of_ports{1'b0}};
401
 
402
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
403
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
404
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
405
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
406
 
407
end
408
endgenerate
409
 
410
generate
411
if (nr_of_ports == 5) begin
412
 
413
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
414
 
415
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
416
 
417
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
418
 
419
    always @ (idle or wbm_cyc_o)
420
    if (idle)
421
        casex (wbm_cyc_o)
422
        5'b1xxxx : select = 5'b10000;
423
        5'b01xxx : select = 5'b01000;
424
        5'b001xx : select = 5'b00100;
425
        5'b0001x : select = 5'b00010;
426
        5'b00001 : select = 5'b00001;
427
        default : select = {nr_of_ports{1'b0}};
428
        endcase
429
    else
430
        select = {nr_of_ports{1'b0}};
431
 
432
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
433
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
434
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
435
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
436
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
437
 
438
end
439
endgenerate
440
 
441
generate
442 67 unneback
if (nr_of_ports == 6) begin
443
 
444
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
445
 
446
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
447
 
448
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
449
 
450
    always @ (idle or wbm_cyc_o)
451
    if (idle)
452
        casex (wbm_cyc_o)
453
        6'b1xxxxx : select = 6'b100000;
454
        6'b01xxxx : select = 6'b010000;
455
        6'b001xxx : select = 6'b001000;
456
        6'b0001xx : select = 6'b000100;
457
        6'b00001x : select = 6'b000010;
458
        6'b000001 : select = 6'b000001;
459
        default : select = {nr_of_ports{1'b0}};
460
        endcase
461
    else
462
        select = {nr_of_ports{1'b0}};
463
 
464
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
465
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
466
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
467
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
468
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
469
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
470
 
471
end
472
endgenerate
473
 
474
generate
475
if (nr_of_ports == 7) begin
476
 
477
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
478
 
479
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
480
 
481
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
482
 
483
    always @ (idle or wbm_cyc_o)
484
    if (idle)
485
        casex (wbm_cyc_o)
486
        7'b1xxxxxx : select = 7'b1000000;
487
        7'b01xxxxx : select = 7'b0100000;
488
        7'b001xxxx : select = 7'b0010000;
489
        7'b0001xxx : select = 7'b0001000;
490
        7'b00001xx : select = 7'b0000100;
491
        7'b000001x : select = 7'b0000010;
492
        7'b0000001 : select = 7'b0000001;
493
        default : select = {nr_of_ports{1'b0}};
494
        endcase
495
    else
496
        select = {nr_of_ports{1'b0}};
497
 
498
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
499
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
500
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
501
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
502
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
503
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
504
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
505
 
506
end
507
endgenerate
508
 
509
generate
510
if (nr_of_ports == 8) begin
511
 
512
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
513
 
514
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
515
 
516
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
517
 
518
    always @ (idle or wbm_cyc_o)
519
    if (idle)
520
        casex (wbm_cyc_o)
521
        8'b1xxxxxxx : select = 8'b10000000;
522
        8'b01xxxxxx : select = 8'b01000000;
523
        8'b001xxxxx : select = 8'b00100000;
524
        8'b0001xxxx : select = 8'b00010000;
525
        8'b00001xxx : select = 8'b00001000;
526
        8'b000001xx : select = 8'b00000100;
527
        8'b0000001x : select = 8'b00000010;
528
        8'b00000001 : select = 8'b00000001;
529
        default : select = {nr_of_ports{1'b0}};
530
        endcase
531
    else
532
        select = {nr_of_ports{1'b0}};
533
 
534
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
535
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
536
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
537
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
538
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
539
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
540
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
541
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
542
 
543
end
544
endgenerate
545
 
546
generate
547 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
548 42 unneback
`define MODULE spr
549
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
550
`undef MODULE
551 39 unneback
end
552
endgenerate
553
 
554
    assign sel = select | state;
555
 
556 40 unneback
`define MODULE mux_andor
557
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
558
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
559
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
560
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
561
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
562
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
563
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
564
`undef MODULE
565 39 unneback
    assign wbs_cyc_i = |sel;
566
 
567
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
568
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
569
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
570
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
571
 
572
endmodule
573 40 unneback
`endif
574 39 unneback
 
575 60 unneback
`ifdef WB_B3_RAM_BE
576 49 unneback
// WB RAM with byte enable
577 59 unneback
`define MODULE wb_b3_ram_be
578
module `BASE`MODULE (
579
`undef MODULE
580 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
581
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
582 59 unneback
 
583 68 unneback
parameter adr_size = 16;
584 60 unneback
parameter adr_lo   = 2;
585 68 unneback
parameter mem_size = 1<<16;
586 60 unneback
parameter dat_size = 32;
587
parameter memory_init = 1;
588
parameter memory_file = "vl_ram.vmem";
589 59 unneback
 
590 69 unneback
localparam aw = (adr_size - adr_lo);
591
localparam dw = dat_size;
592
localparam sw = dat_size/8;
593
localparam cw = 3;
594
localparam bw = 2;
595 60 unneback
 
596 70 unneback
input [dw-1:0] wbs_dat_i;
597
input [aw-1:0] wbs_adr_i;
598
input [cw-1:0] wbs_cti_i;
599
input [bw-1:0] wbs_bte_i;
600
input [sw-1:0] wbs_sel_i;
601
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
602
output [dw-1:0] wbs_dat_o;
603
output wbs_ack_o;
604
input wbs_clk, wbs_rst;
605 59 unneback
 
606 60 unneback
wire [sw-1:0] cke;
607 59 unneback
 
608 60 unneback
reg wbs_ack_o;
609
 
610
`define MODULE ram_be
611
`BASE`MODULE # (
612
    .data_width(dat_size),
613
    .addr_width(adr_size),
614 69 unneback
    .mem_size(mem_size),
615 68 unneback
    .memory_init(memory_init),
616
    .memory_file(memory_file))
617 60 unneback
ram0(
618
`undef MODULE
619
    .d(wbs_dat_i),
620
    .adr(wbs_adr_i[adr_size-1:2]),
621
    .be(wbs_sel_i),
622
    .we(wbs_we_i),
623
    .q(wbs_dat_o),
624
    .clk(wb_clk)
625
);
626
 
627 59 unneback
always @ (posedge wb_clk or posedge wb_rst)
628
if (wb_rst)
629 60 unneback
    wbs_ack_o <= 1'b0;
630 59 unneback
else
631 60 unneback
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
632
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
633 59 unneback
    else
634 60 unneback
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
635
 
636 59 unneback
endmodule
637
`endif
638
 
639
`ifdef WB_B4_RAM_BE
640
// WB RAM with byte enable
641 49 unneback
`define MODULE wb_b4_ram_be
642
module `BASE`MODULE (
643
`undef MODULE
644
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
645 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
646 49 unneback
 
647
    parameter dat_width = 32;
648
    parameter adr_width = 8;
649
 
650
input [dat_width-1:0] wb_dat_i;
651
input [adr_width-1:0] wb_adr_i;
652
input [dat_width/8-1:0] wb_sel_i;
653
input wb_we_i, wb_stb_i, wb_cyc_i;
654
output [dat_width-1:0] wb_dat_o;
655 51 unneback
reg [dat_width-1:0] wb_dat_o;
656 52 unneback
output wb_stall_o;
657 49 unneback
output wb_ack_o;
658
reg wb_ack_o;
659
input wb_clk, wb_rst;
660
 
661 56 unneback
wire [dat_width/8-1:0] cke;
662
 
663 49 unneback
generate
664
if (dat_width==32) begin
665 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
666
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
667
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
668
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
669 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
670 49 unneback
    always @ (posedge wb_clk)
671
    begin
672 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
673
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
674
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
675
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
676 49 unneback
    end
677 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
678
    begin
679
        if (wb_rst)
680
            wb_dat_o <= 32'h0;
681
        else
682
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
683
    end
684 49 unneback
end
685
endgenerate
686
 
687 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
688 55 unneback
if (wb_rst)
689 52 unneback
    wb_ack_o <= 1'b0;
690
else
691 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
692 52 unneback
 
693
assign wb_stall_o = 1'b0;
694
 
695 49 unneback
endmodule
696
`endif
697
 
698 48 unneback
`ifdef WB_B4_ROM
699
// WB ROM
700
`define MODULE wb_b4_rom
701
module `BASE`MODULE (
702
`undef MODULE
703
    wb_adr_i, wb_stb_i, wb_cyc_i,
704
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
705
 
706
    parameter dat_width = 32;
707
    parameter dat_default = 32'h15000000;
708
    parameter adr_width = 32;
709
 
710
/*
711
//E2_ifndef ROM
712
//E2_define ROM "rom.v"
713
//E2_endif
714
*/
715
    input [adr_width-1:2]   wb_adr_i;
716
    input                   wb_stb_i;
717
    input                   wb_cyc_i;
718
    output [dat_width-1:0]  wb_dat_o;
719
    reg [dat_width-1:0]     wb_dat_o;
720
    output                  wb_ack_o;
721
    reg                     wb_ack_o;
722
    output                  stall_o;
723
    input                   wb_clk;
724
    input                   wb_rst;
725
 
726
always @ (posedge wb_clk or posedge wb_rst)
727
    if (wb_rst)
728
        wb_dat_o <= {dat_width{1'b0}};
729
    else
730
         case (wb_adr_i[adr_width-1:2])
731
//E2_ifdef ROM
732
//E2_include `ROM
733
//E2_endif
734
           default:
735
             wb_dat_o <= dat_default;
736
 
737
         endcase // case (wb_adr_i)
738
 
739
 
740
always @ (posedge wb_clk or posedge wb_rst)
741
    if (wb_rst)
742
        wb_ack_o <= 1'b0;
743
    else
744
        wb_ack_o <= wb_stb_i & wb_cyc_i;
745
 
746
assign stall_o = 1'b0;
747
 
748
endmodule
749
`endif
750
 
751
 
752 40 unneback
`ifdef WB_BOOT_ROM
753 17 unneback
// WB ROM
754 40 unneback
`define MODULE wb_boot_rom
755
module `BASE`MODULE (
756
`undef MODULE
757 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
758 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
759 17 unneback
 
760 18 unneback
    parameter adr_hi = 31;
761
    parameter adr_lo = 28;
762
    parameter adr_sel = 4'hf;
763
    parameter addr_width = 5;
764 33 unneback
/*
765 17 unneback
//E2_ifndef BOOT_ROM
766
//E2_define BOOT_ROM "boot_rom.v"
767
//E2_endif
768 33 unneback
*/
769 18 unneback
    input [adr_hi:2]    wb_adr_i;
770
    input               wb_stb_i;
771
    input               wb_cyc_i;
772
    output [31:0]        wb_dat_o;
773
    output              wb_ack_o;
774
    output              hit_o;
775
    input               wb_clk;
776
    input               wb_rst;
777
 
778
    wire hit;
779
    reg [31:0] wb_dat;
780
    reg wb_ack;
781
 
782
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
783 17 unneback
 
784
always @ (posedge wb_clk or posedge wb_rst)
785
    if (wb_rst)
786 18 unneback
        wb_dat <= 32'h15000000;
787 17 unneback
    else
788 18 unneback
         case (wb_adr_i[addr_width-1:2])
789 33 unneback
//E2_ifdef BOOT_ROM
790 17 unneback
//E2_include `BOOT_ROM
791 33 unneback
//E2_endif
792 17 unneback
           /*
793
            // Zero r0 and jump to 0x00000100
794 18 unneback
 
795
            1 : wb_dat <= 32'hA8200000;
796
            2 : wb_dat <= 32'hA8C00100;
797
            3 : wb_dat <= 32'h44003000;
798
            4 : wb_dat <= 32'h15000000;
799 17 unneback
            */
800
           default:
801 18 unneback
             wb_dat <= 32'h00000000;
802 17 unneback
 
803
         endcase // case (wb_adr_i)
804
 
805
 
806
always @ (posedge wb_clk or posedge wb_rst)
807
    if (wb_rst)
808 18 unneback
        wb_ack <= 1'b0;
809 17 unneback
    else
810 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
811 17 unneback
 
812 18 unneback
assign hit_o = hit;
813
assign wb_dat_o = wb_dat & {32{wb_ack}};
814
assign wb_ack_o = wb_ack;
815
 
816 17 unneback
endmodule
817 40 unneback
`endif
818 32 unneback
 
819 40 unneback
`ifdef WB_DPRAM
820
`define MODULE wb_dpram
821
module `BASE`MODULE (
822
`undef MODULE
823 32 unneback
        // wishbone slave side a
824
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
825
        wbsa_clk, wbsa_rst,
826
        // wishbone slave side a
827
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
828
        wbsb_clk, wbsb_rst);
829
 
830
parameter data_width = 32;
831
parameter addr_width = 8;
832
 
833
parameter dat_o_mask_a = 1;
834
parameter dat_o_mask_b = 1;
835
 
836
input [31:0] wbsa_dat_i;
837
input [addr_width-1:2] wbsa_adr_i;
838
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
839
output [31:0] wbsa_dat_o;
840
output wbsa_ack_o;
841
input wbsa_clk, wbsa_rst;
842
 
843
input [31:0] wbsb_dat_i;
844
input [addr_width-1:2] wbsb_adr_i;
845
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
846
output [31:0] wbsb_dat_o;
847
output wbsb_ack_o;
848
input wbsb_clk, wbsb_rst;
849
 
850
wire wbsa_dat_tmp, wbsb_dat_tmp;
851
 
852 40 unneback
`define MODULE dpram_2r2w
853
`BASE`MODULE # (
854
`undef MODULE
855 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
856 32 unneback
dpram0(
857
    .d_a(wbsa_dat_i),
858
    .q_a(wbsa_dat_tmp),
859
    .adr_a(wbsa_adr_i),
860
    .we_a(wbsa_we_i),
861
    .clk_a(wbsa_clk),
862
    .d_b(wbsb_dat_i),
863
    .q_b(wbsb_dat_tmp),
864
    .adr_b(wbsb_adr_i),
865
    .we_b(wbsb_we_i),
866
    .clk_b(wbsb_clk) );
867
 
868 33 unneback
generate if (dat_o_mask_a==1)
869 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
870
endgenerate
871 33 unneback
generate if (dat_o_mask_a==0)
872 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
873
endgenerate
874
 
875 33 unneback
generate if (dat_o_mask_b==1)
876 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
877
endgenerate
878 33 unneback
generate if (dat_o_mask_b==0)
879 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
880
endgenerate
881
 
882 40 unneback
`define MODULE spr
883
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
884
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
885
`undef MODULE
886 32 unneback
 
887
endmodule
888 40 unneback
`endif

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