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1 12 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46
`define MODULE wb_adr_inc
47 84 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
48 75 unneback
`undef MODULE
49 83 unneback
parameter adr_width = 10;
50
parameter max_burst_width = 4;
51 84 unneback
input cyc_i, stb_i, we_i;
52 83 unneback
input [2:0] cti_i;
53
input [1:0] bte_i;
54
input [adr_width-1:0] adr_i;
55
output [adr_width-1:0] adr_o;
56
output ack_o;
57
input clk, rst;
58 75 unneback
 
59 83 unneback
reg [adr_width-1:0] adr;
60 90 unneback
wire [max_burst_width-1:0] to_adr;
61
 
62 83 unneback
generate
63
if (max_burst_width==0) begin : inst_0
64
    reg ack_o;
65
    assign adr_o = adr_i;
66 75 unneback
    always @ (posedge clk or posedge rst)
67 83 unneback
    if (rst)
68
        ack_o <= 1'b0;
69
    else
70
        ack_o <= cyc_i & stb_i & !ack_o;
71
end else begin
72
 
73
    reg [1:0] last_cycle;
74
    localparam idle = 2'b00;
75
    localparam cyc  = 2'b01;
76
    localparam ws   = 2'b10;
77
    localparam eoc  = 2'b11;
78
    always @ (posedge clk or posedge rst)
79
    if (rst)
80
        last_cycle <= idle;
81
    else
82
        last_cycle <= (!cyc_i) ? idle :
83
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
84
                      (cyc_i & !stb_i) ? ws :
85
                      cyc;
86
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
87 84 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
88
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
89
                                        adr[max_burst_width-1:0];
90 90 unneback
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
91 83 unneback
end
92
endgenerate
93
 
94
generate
95
if (max_burst_width==2) begin : inst_2
96
    always @ (posedge clk or posedge rst)
97
    if (rst)
98
        adr <= 2'h0;
99
    else
100
        if (cyc_i & stb_i)
101
            adr[1:0] <= to_adr[1:0] + 2'd1;
102 75 unneback
        else
103 83 unneback
            adr <= to_adr[1:0];
104
end
105
endgenerate
106
 
107
generate
108
if (max_burst_width==3) begin : inst_3
109
    always @ (posedge clk or posedge rst)
110
    if (rst)
111
        adr <= 3'h0;
112
    else
113
        if (cyc_i & stb_i)
114
            case (bte_i)
115
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
116
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
117 75 unneback
            endcase
118 83 unneback
        else
119
            adr <= to_adr[2:0];
120
end
121
endgenerate
122
 
123
generate
124
if (max_burst_width==4) begin : inst_4
125
    always @ (posedge clk or posedge rst)
126
    if (rst)
127
        adr <= 4'h0;
128
    else
129
        if (cyc_i & stb_i)
130
            case (bte_i)
131
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
132
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
133
            default: adr[3:0] <= to_adr + 4'd1;
134
            endcase
135
        else
136
            adr <= to_adr[3:0];
137
end
138
endgenerate
139
 
140
generate
141
if (adr_width > max_burst_width) begin : pass_through
142
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
143
end
144
endgenerate
145
 
146
endmodule
147 75 unneback
`endif
148
 
149 40 unneback
`ifdef WB3WB3_BRIDGE
150 12 unneback
// async wb3 - wb3 bridge
151
`timescale 1ns/1ns
152 40 unneback
`define MODULE wb3wb3_bridge
153
module `BASE`MODULE (
154
`undef MODULE
155 12 unneback
        // wishbone slave side
156
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
157
        // wishbone master side
158
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
159
 
160
input [31:0] wbs_dat_i;
161
input [31:2] wbs_adr_i;
162
input [3:0]  wbs_sel_i;
163
input [1:0]  wbs_bte_i;
164
input [2:0]  wbs_cti_i;
165
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
166
output [31:0] wbs_dat_o;
167 14 unneback
output wbs_ack_o;
168 12 unneback
input wbs_clk, wbs_rst;
169
 
170
output [31:0] wbm_dat_o;
171
output reg [31:2] wbm_adr_o;
172
output [3:0]  wbm_sel_o;
173
output reg [1:0]  wbm_bte_o;
174
output reg [2:0]  wbm_cti_o;
175 14 unneback
output reg wbm_we_o;
176
output wbm_cyc_o;
177 12 unneback
output wbm_stb_o;
178
input [31:0]  wbm_dat_i;
179
input wbm_ack_i;
180
input wbm_clk, wbm_rst;
181
 
182
parameter addr_width = 4;
183
 
184
// bte
185
parameter linear       = 2'b00;
186
parameter wrap4        = 2'b01;
187
parameter wrap8        = 2'b10;
188
parameter wrap16       = 2'b11;
189
// cti
190
parameter classic      = 3'b000;
191
parameter incburst     = 3'b010;
192
parameter endofburst   = 3'b111;
193
 
194
parameter wbs_adr  = 1'b0;
195
parameter wbs_data = 1'b1;
196
 
197 33 unneback
parameter wbm_adr0      = 2'b00;
198
parameter wbm_adr1      = 2'b01;
199
parameter wbm_data      = 2'b10;
200
parameter wbm_data_wait = 2'b11;
201 12 unneback
 
202
reg [1:0] wbs_bte_reg;
203
reg wbs;
204
wire wbs_eoc_alert, wbm_eoc_alert;
205
reg wbs_eoc, wbm_eoc;
206
reg [1:0] wbm;
207
 
208 14 unneback
wire [1:16] wbs_count, wbm_count;
209 12 unneback
 
210
wire [35:0] a_d, a_q, b_d, b_q;
211
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
212
reg a_rd_reg;
213
wire b_rd_adr, b_rd_data;
214 14 unneback
wire b_rd_data_reg;
215
wire [35:0] temp;
216 12 unneback
 
217
`define WE 5
218
`define BTE 4:3
219
`define CTI 2:0
220
 
221
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
222
always @ (posedge wbs_clk or posedge wbs_rst)
223
if (wbs_rst)
224
        wbs_eoc <= 1'b0;
225
else
226
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
227 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
228 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
229
                wbs_eoc <= 1'b1;
230
 
231 40 unneback
`define MODULE cnt_shreg_ce_clear
232
`BASE`MODULE # ( .length(16))
233
`undef MODULE
234 12 unneback
    cnt0 (
235
        .cke(wbs_ack_o),
236
        .clear(wbs_eoc),
237
        .q(wbs_count),
238
        .rst(wbs_rst),
239
        .clk(wbs_clk));
240
 
241
always @ (posedge wbs_clk or posedge wbs_rst)
242
if (wbs_rst)
243
        wbs <= wbs_adr;
244
else
245 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
246 12 unneback
                wbs <= wbs_data;
247
        else if (wbs_eoc & wbs_ack_o)
248
                wbs <= wbs_adr;
249
 
250
// wbs FIFO
251 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
252
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
253 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
254
              1'b0;
255
assign a_rd = !a_fifo_empty;
256
always @ (posedge wbs_clk or posedge wbs_rst)
257
if (wbs_rst)
258
        a_rd_reg <= 1'b0;
259
else
260
        a_rd_reg <= a_rd;
261
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
262
 
263
assign wbs_dat_o = a_q[35:4];
264
 
265
always @ (posedge wbs_clk or posedge wbs_rst)
266
if (wbs_rst)
267 13 unneback
        wbs_bte_reg <= 2'b00;
268 12 unneback
else
269 13 unneback
        wbs_bte_reg <= wbs_bte_i;
270 12 unneback
 
271
// wbm FIFO
272
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
273
always @ (posedge wbm_clk or posedge wbm_rst)
274
if (wbm_rst)
275
        wbm_eoc <= 1'b0;
276
else
277
        if (wbm==wbm_adr0 & !b_fifo_empty)
278
                wbm_eoc <= b_q[`BTE] == linear;
279
        else if (wbm_eoc_alert & wbm_ack_i)
280
                wbm_eoc <= 1'b1;
281
 
282
always @ (posedge wbm_clk or posedge wbm_rst)
283
if (wbm_rst)
284
        wbm <= wbm_adr0;
285
else
286 33 unneback
/*
287 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
288
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
289
        (wbm==wbm_adr1 & !wbm_we_o) |
290
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
291
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
292 33 unneback
*/
293
    case (wbm)
294
    wbm_adr0:
295
        if (!b_fifo_empty)
296
            wbm <= wbm_adr1;
297
    wbm_adr1:
298
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
299
            wbm <= wbm_data;
300
    wbm_data:
301
        if (wbm_ack_i & wbm_eoc)
302
            wbm <= wbm_adr0;
303
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
304
            wbm <= wbm_data_wait;
305
    wbm_data_wait:
306
        if (!b_fifo_empty)
307
            wbm <= wbm_data;
308
    endcase
309 12 unneback
 
310
assign b_d = {wbm_dat_i,4'b1111};
311
assign b_wr = !wbm_we_o & wbm_ack_i;
312
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
313
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
314
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
315 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
316 12 unneback
                   1'b0;
317
assign b_rd = b_rd_adr | b_rd_data;
318
 
319 40 unneback
`define MODULE dff
320
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
321
`undef MODULE
322
`define MODULE dff_ce
323
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
324
`undef MODULE
325 12 unneback
 
326
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
327
 
328 40 unneback
`define MODULE cnt_shreg_ce_clear
329 42 unneback
`BASE`MODULE # ( .length(16))
330 40 unneback
`undef MODULE
331 12 unneback
    cnt1 (
332
        .cke(wbm_ack_i),
333
        .clear(wbm_eoc),
334
        .q(wbm_count),
335
        .rst(wbm_rst),
336
        .clk(wbm_clk));
337
 
338 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
339
assign wbm_stb_o = (wbm==wbm_data);
340 12 unneback
 
341
always @ (posedge wbm_clk or posedge wbm_rst)
342
if (wbm_rst)
343
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
344
else begin
345
        if (wbm==wbm_adr0 & !b_fifo_empty)
346
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
347
        else if (wbm_eoc_alert & wbm_ack_i)
348
                wbm_cti_o <= endofburst;
349
end
350
 
351
//async_fifo_dw_simplex_top
352 40 unneback
`define MODULE fifo_2r2w_async_simplex
353
`BASE`MODULE
354
`undef MODULE
355 12 unneback
# ( .data_width(36), .addr_width(addr_width))
356
fifo (
357
    // a side
358
    .a_d(a_d),
359
    .a_wr(a_wr),
360
    .a_fifo_full(a_fifo_full),
361
    .a_q(a_q),
362
    .a_rd(a_rd),
363
    .a_fifo_empty(a_fifo_empty),
364
    .a_clk(wbs_clk),
365
    .a_rst(wbs_rst),
366
    // b side
367
    .b_d(b_d),
368
    .b_wr(b_wr),
369
    .b_fifo_full(b_fifo_full),
370
    .b_q(b_q),
371
    .b_rd(b_rd),
372
    .b_fifo_empty(b_fifo_empty),
373
    .b_clk(wbm_clk),
374
    .b_rst(wbm_rst)
375
    );
376
 
377
endmodule
378 40 unneback
`undef WE
379
`undef BTE
380
`undef CTI
381
`endif
382 17 unneback
 
383 75 unneback
`ifdef WB3AVALON_BRIDGE
384
`define MODULE wb3avalon_bridge
385
module `BASE`MODULE (
386
`undef MODULE
387
        // wishbone slave side
388
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
389 77 unneback
        // avalon master side
390 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
391
 
392 84 unneback
parameter linewrapburst = 1'b0;
393
 
394 75 unneback
input [31:0] wbs_dat_i;
395
input [31:2] wbs_adr_i;
396
input [3:0]  wbs_sel_i;
397
input [1:0]  wbs_bte_i;
398
input [2:0]  wbs_cti_i;
399 83 unneback
input wbs_we_i;
400
input wbs_cyc_i;
401
input wbs_stb_i;
402 75 unneback
output [31:0] wbs_dat_o;
403
output wbs_ack_o;
404
input wbs_clk, wbs_rst;
405
 
406
input [31:0] readdata;
407
output [31:0] writedata;
408
output [31:2] address;
409
output [3:0]  be;
410
output write;
411 81 unneback
output read;
412 75 unneback
output beginbursttransfer;
413
output [3:0] burstcount;
414
input readdatavalid;
415
input waitrequest;
416
input clk;
417
input rst;
418
 
419
wire [1:0] wbm_bte_o;
420
wire [2:0] wbm_cti_o;
421
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
422
reg last_cyc;
423 79 unneback
reg [3:0] counter;
424 82 unneback
reg read_busy;
425 75 unneback
 
426
always @ (posedge clk or posedge rst)
427
if (rst)
428
    last_cyc <= 1'b0;
429
else
430
    last_cyc <= wbm_cyc_o;
431
 
432 79 unneback
always @ (posedge clk or posedge rst)
433
if (rst)
434 82 unneback
    read_busy <= 1'b0;
435 79 unneback
else
436 82 unneback
    if (read & !waitrequest)
437
        read_busy <= 1'b1;
438
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
439
        read_busy <= 1'b0;
440
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
441 81 unneback
 
442 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
443
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
444
                    (wbm_bte_o==2'b10) ? 4'd8 :
445 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
446
                    4'd1;
447 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
448 75 unneback
 
449 79 unneback
always @ (posedge clk or posedge rst)
450
if (rst) begin
451
    counter <= 4'd0;
452
end else
453 80 unneback
    if (wbm_we_o) begin
454
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
455 84 unneback
            counter <= burstcount -4'd1;
456 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
457
            counter <= burstcount;
458
        end else if (!waitrequest & wbm_stb_o) begin
459
            counter <= counter - 4'd1;
460
        end
461 82 unneback
    end
462 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
463 79 unneback
 
464 75 unneback
`define MODULE wb3wb3_bridge
465 77 unneback
`BASE`MODULE wbwb3inst (
466 75 unneback
`undef MODULE
467
    // wishbone slave side
468
    .wbs_dat_i(wbs_dat_i),
469
    .wbs_adr_i(wbs_adr_i),
470
    .wbs_sel_i(wbs_sel_i),
471
    .wbs_bte_i(wbs_bte_i),
472
    .wbs_cti_i(wbs_cti_i),
473
    .wbs_we_i(wbs_we_i),
474
    .wbs_cyc_i(wbs_cyc_i),
475
    .wbs_stb_i(wbs_stb_i),
476
    .wbs_dat_o(wbs_dat_o),
477
    .wbs_ack_o(wbs_ack_o),
478
    .wbs_clk(wbs_clk),
479
    .wbs_rst(wbs_rst),
480
    // wishbone master side
481
    .wbm_dat_o(writedata),
482 78 unneback
    .wbm_adr_o(address),
483 75 unneback
    .wbm_sel_o(be),
484
    .wbm_bte_o(wbm_bte_o),
485
    .wbm_cti_o(wbm_cti_o),
486
    .wbm_we_o(wbm_we_o),
487
    .wbm_cyc_o(wbm_cyc_o),
488
    .wbm_stb_o(wbm_stb_o),
489
    .wbm_dat_i(readdata),
490
    .wbm_ack_i(wbm_ack_i),
491
    .wbm_clk(clk),
492
    .wbm_rst(rst));
493
 
494
 
495
endmodule
496
`endif
497
 
498 40 unneback
`ifdef WB3_ARBITER_TYPE1
499
`define MODULE wb3_arbiter_type1
500 42 unneback
module `BASE`MODULE (
501 40 unneback
`undef MODULE
502 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
503
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
504
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
505
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
506
    wb_clk, wb_rst
507
);
508
 
509
parameter nr_of_ports = 3;
510
parameter adr_size = 26;
511
parameter adr_lo   = 2;
512
parameter dat_size = 32;
513
parameter sel_size = dat_size/8;
514
 
515
localparam aw = (adr_size - adr_lo) * nr_of_ports;
516
localparam dw = dat_size * nr_of_ports;
517
localparam sw = sel_size * nr_of_ports;
518
localparam cw = 3 * nr_of_ports;
519
localparam bw = 2 * nr_of_ports;
520
 
521
input  [dw-1:0] wbm_dat_o;
522
input  [aw-1:0] wbm_adr_o;
523
input  [sw-1:0] wbm_sel_o;
524
input  [cw-1:0] wbm_cti_o;
525
input  [bw-1:0] wbm_bte_o;
526
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
527
output [dw-1:0] wbm_dat_i;
528
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
529
 
530
output [dat_size-1:0] wbs_dat_i;
531
output [adr_size-1:adr_lo] wbs_adr_i;
532
output [sel_size-1:0] wbs_sel_i;
533
output [2:0] wbs_cti_i;
534
output [1:0] wbs_bte_i;
535
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
536
input  [dat_size-1:0] wbs_dat_o;
537
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
538
 
539
input wb_clk, wb_rst;
540
 
541 44 unneback
reg  [nr_of_ports-1:0] select;
542 39 unneback
wire [nr_of_ports-1:0] state;
543
wire [nr_of_ports-1:0] eoc; // end-of-cycle
544
wire [nr_of_ports-1:0] sel;
545
wire idle;
546
 
547
genvar i;
548
 
549
assign idle = !(|state);
550
 
551
generate
552
if (nr_of_ports == 2) begin
553
 
554
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
555
 
556
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
557
 
558 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
559
 
560
    always @ (idle or wbm_cyc_o)
561
    if (idle)
562
        casex (wbm_cyc_o)
563
        2'b1x : select = 2'b10;
564
        2'b01 : select = 2'b01;
565
        default : select = {nr_of_ports{1'b0}};
566
        endcase
567
    else
568
        select = {nr_of_ports{1'b0}};
569
 
570 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
571
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
572
 
573
end
574
endgenerate
575
 
576
generate
577
if (nr_of_ports == 3) begin
578
 
579
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
580
 
581
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
582
 
583 44 unneback
    always @ (idle or wbm_cyc_o)
584
    if (idle)
585
        casex (wbm_cyc_o)
586
        3'b1xx : select = 3'b100;
587
        3'b01x : select = 3'b010;
588
        3'b001 : select = 3'b001;
589
        default : select = {nr_of_ports{1'b0}};
590
        endcase
591
    else
592
        select = {nr_of_ports{1'b0}};
593
 
594
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
595 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
596
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
597
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
598
 
599
end
600
endgenerate
601
 
602
generate
603 44 unneback
if (nr_of_ports == 4) begin
604
 
605
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
606
 
607
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
608
 
609
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
610
 
611
    always @ (idle or wbm_cyc_o)
612
    if (idle)
613
        casex (wbm_cyc_o)
614
        4'b1xxx : select = 4'b1000;
615
        4'b01xx : select = 4'b0100;
616
        4'b001x : select = 4'b0010;
617
        4'b0001 : select = 4'b0001;
618
        default : select = {nr_of_ports{1'b0}};
619
        endcase
620
    else
621
        select = {nr_of_ports{1'b0}};
622
 
623
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
624
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
625
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
626
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
627
 
628
end
629
endgenerate
630
 
631
generate
632
if (nr_of_ports == 5) begin
633
 
634
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
635
 
636
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
637
 
638
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
639
 
640
    always @ (idle or wbm_cyc_o)
641
    if (idle)
642
        casex (wbm_cyc_o)
643
        5'b1xxxx : select = 5'b10000;
644
        5'b01xxx : select = 5'b01000;
645
        5'b001xx : select = 5'b00100;
646
        5'b0001x : select = 5'b00010;
647
        5'b00001 : select = 5'b00001;
648
        default : select = {nr_of_ports{1'b0}};
649
        endcase
650
    else
651
        select = {nr_of_ports{1'b0}};
652
 
653
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
654
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
655
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
656
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
657
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
658
 
659
end
660
endgenerate
661
 
662
generate
663 67 unneback
if (nr_of_ports == 6) begin
664
 
665
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
666
 
667
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
668
 
669
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
670
 
671
    always @ (idle or wbm_cyc_o)
672
    if (idle)
673
        casex (wbm_cyc_o)
674
        6'b1xxxxx : select = 6'b100000;
675
        6'b01xxxx : select = 6'b010000;
676
        6'b001xxx : select = 6'b001000;
677
        6'b0001xx : select = 6'b000100;
678
        6'b00001x : select = 6'b000010;
679
        6'b000001 : select = 6'b000001;
680
        default : select = {nr_of_ports{1'b0}};
681
        endcase
682
    else
683
        select = {nr_of_ports{1'b0}};
684
 
685
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
686
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
687
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
688
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
689
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
690
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
691
 
692
end
693
endgenerate
694
 
695
generate
696
if (nr_of_ports == 7) begin
697
 
698
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
699
 
700
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
701
 
702
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
703
 
704
    always @ (idle or wbm_cyc_o)
705
    if (idle)
706
        casex (wbm_cyc_o)
707
        7'b1xxxxxx : select = 7'b1000000;
708
        7'b01xxxxx : select = 7'b0100000;
709
        7'b001xxxx : select = 7'b0010000;
710
        7'b0001xxx : select = 7'b0001000;
711
        7'b00001xx : select = 7'b0000100;
712
        7'b000001x : select = 7'b0000010;
713
        7'b0000001 : select = 7'b0000001;
714
        default : select = {nr_of_ports{1'b0}};
715
        endcase
716
    else
717
        select = {nr_of_ports{1'b0}};
718
 
719
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
720
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
721
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
722
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
723
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
724
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
725
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
726
 
727
end
728
endgenerate
729
 
730
generate
731
if (nr_of_ports == 8) begin
732
 
733
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
734
 
735
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
736
 
737
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
738
 
739
    always @ (idle or wbm_cyc_o)
740
    if (idle)
741
        casex (wbm_cyc_o)
742
        8'b1xxxxxxx : select = 8'b10000000;
743
        8'b01xxxxxx : select = 8'b01000000;
744
        8'b001xxxxx : select = 8'b00100000;
745
        8'b0001xxxx : select = 8'b00010000;
746
        8'b00001xxx : select = 8'b00001000;
747
        8'b000001xx : select = 8'b00000100;
748
        8'b0000001x : select = 8'b00000010;
749
        8'b00000001 : select = 8'b00000001;
750
        default : select = {nr_of_ports{1'b0}};
751
        endcase
752
    else
753
        select = {nr_of_ports{1'b0}};
754
 
755
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
756
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
757
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
758
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
759
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
760
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
761
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
762
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
763
 
764
end
765
endgenerate
766
 
767
generate
768 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
769 42 unneback
`define MODULE spr
770
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
771
`undef MODULE
772 39 unneback
end
773
endgenerate
774
 
775
    assign sel = select | state;
776
 
777 40 unneback
`define MODULE mux_andor
778
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
779
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
780
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
781
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
782
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
783
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
784
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
785
`undef MODULE
786 39 unneback
    assign wbs_cyc_i = |sel;
787
 
788
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
789
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
790
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
791
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
792
 
793
endmodule
794 40 unneback
`endif
795 39 unneback
 
796 60 unneback
`ifdef WB_B3_RAM_BE
797 49 unneback
// WB RAM with byte enable
798 59 unneback
`define MODULE wb_b3_ram_be
799
module `BASE`MODULE (
800
`undef MODULE
801 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
802
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
803 59 unneback
 
804 68 unneback
parameter adr_size = 16;
805 84 unneback
parameter mem_size = 1<<adr_size;
806 60 unneback
parameter dat_size = 32;
807 83 unneback
parameter max_burst_width = 4;
808 60 unneback
parameter memory_init = 1;
809
parameter memory_file = "vl_ram.vmem";
810 59 unneback
 
811 84 unneback
localparam aw = (adr_size);
812 69 unneback
localparam dw = dat_size;
813
localparam sw = dat_size/8;
814
localparam cw = 3;
815
localparam bw = 2;
816 60 unneback
 
817 70 unneback
input [dw-1:0] wbs_dat_i;
818
input [aw-1:0] wbs_adr_i;
819
input [cw-1:0] wbs_cti_i;
820
input [bw-1:0] wbs_bte_i;
821
input [sw-1:0] wbs_sel_i;
822
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
823
output [dw-1:0] wbs_dat_o;
824
output wbs_ack_o;
825 71 unneback
input wb_clk, wb_rst;
826 59 unneback
 
827 83 unneback
wire [aw-1:0] adr;
828 59 unneback
 
829 60 unneback
`define MODULE ram_be
830
`BASE`MODULE # (
831
    .data_width(dat_size),
832 83 unneback
    .addr_width(aw),
833 69 unneback
    .mem_size(mem_size),
834 68 unneback
    .memory_init(memory_init),
835
    .memory_file(memory_file))
836 60 unneback
ram0(
837
`undef MODULE
838
    .d(wbs_dat_i),
839 83 unneback
    .adr(adr),
840 60 unneback
    .be(wbs_sel_i),
841 90 unneback
    .re(wbs_stb_i),
842 86 unneback
    .we(wbs_we_i & wbs_ack_o),
843 60 unneback
    .q(wbs_dat_o),
844
    .clk(wb_clk)
845
);
846
 
847 83 unneback
`define MODULE wb_adr_inc
848
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
849
    .cyc_i(wbs_cyc_i),
850
    .stb_i(wbs_stb_i),
851
    .cti_i(wbs_cti_i),
852
    .bte_i(wbs_bte_i),
853
    .adr_i(wbs_adr_i),
854 84 unneback
    .we_i(wbs_we_i),
855 83 unneback
    .ack_o(wbs_ack_o),
856
    .adr_o(adr),
857
    .clk(wb_clk),
858
    .rst(wb_rst));
859
`undef MODULE
860 60 unneback
 
861 59 unneback
endmodule
862
`endif
863
 
864
`ifdef WB_B4_RAM_BE
865
// WB RAM with byte enable
866 49 unneback
`define MODULE wb_b4_ram_be
867
module `BASE`MODULE (
868
`undef MODULE
869
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
870 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
871 49 unneback
 
872
    parameter dat_width = 32;
873
    parameter adr_width = 8;
874
 
875
input [dat_width-1:0] wb_dat_i;
876
input [adr_width-1:0] wb_adr_i;
877
input [dat_width/8-1:0] wb_sel_i;
878
input wb_we_i, wb_stb_i, wb_cyc_i;
879
output [dat_width-1:0] wb_dat_o;
880 51 unneback
reg [dat_width-1:0] wb_dat_o;
881 52 unneback
output wb_stall_o;
882 49 unneback
output wb_ack_o;
883
reg wb_ack_o;
884
input wb_clk, wb_rst;
885
 
886 56 unneback
wire [dat_width/8-1:0] cke;
887
 
888 49 unneback
generate
889
if (dat_width==32) begin
890 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
891
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
892
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
893
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
894 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
895 49 unneback
    always @ (posedge wb_clk)
896
    begin
897 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
898
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
899
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
900
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
901 49 unneback
    end
902 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
903
    begin
904
        if (wb_rst)
905
            wb_dat_o <= 32'h0;
906
        else
907
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
908
    end
909 49 unneback
end
910
endgenerate
911
 
912 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
913 55 unneback
if (wb_rst)
914 52 unneback
    wb_ack_o <= 1'b0;
915
else
916 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
917 52 unneback
 
918
assign wb_stall_o = 1'b0;
919
 
920 49 unneback
endmodule
921
`endif
922
 
923 48 unneback
`ifdef WB_B4_ROM
924
// WB ROM
925
`define MODULE wb_b4_rom
926
module `BASE`MODULE (
927
`undef MODULE
928
    wb_adr_i, wb_stb_i, wb_cyc_i,
929
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
930
 
931
    parameter dat_width = 32;
932
    parameter dat_default = 32'h15000000;
933
    parameter adr_width = 32;
934
 
935
/*
936
//E2_ifndef ROM
937
//E2_define ROM "rom.v"
938
//E2_endif
939
*/
940
    input [adr_width-1:2]   wb_adr_i;
941
    input                   wb_stb_i;
942
    input                   wb_cyc_i;
943
    output [dat_width-1:0]  wb_dat_o;
944
    reg [dat_width-1:0]     wb_dat_o;
945
    output                  wb_ack_o;
946
    reg                     wb_ack_o;
947
    output                  stall_o;
948
    input                   wb_clk;
949
    input                   wb_rst;
950
 
951
always @ (posedge wb_clk or posedge wb_rst)
952
    if (wb_rst)
953
        wb_dat_o <= {dat_width{1'b0}};
954
    else
955
         case (wb_adr_i[adr_width-1:2])
956
//E2_ifdef ROM
957
//E2_include `ROM
958
//E2_endif
959
           default:
960
             wb_dat_o <= dat_default;
961
 
962
         endcase // case (wb_adr_i)
963
 
964
 
965
always @ (posedge wb_clk or posedge wb_rst)
966
    if (wb_rst)
967
        wb_ack_o <= 1'b0;
968
    else
969
        wb_ack_o <= wb_stb_i & wb_cyc_i;
970
 
971
assign stall_o = 1'b0;
972
 
973
endmodule
974
`endif
975
 
976
 
977 40 unneback
`ifdef WB_BOOT_ROM
978 17 unneback
// WB ROM
979 40 unneback
`define MODULE wb_boot_rom
980
module `BASE`MODULE (
981
`undef MODULE
982 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
983 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
984 17 unneback
 
985 18 unneback
    parameter adr_hi = 31;
986
    parameter adr_lo = 28;
987
    parameter adr_sel = 4'hf;
988
    parameter addr_width = 5;
989 33 unneback
/*
990 17 unneback
//E2_ifndef BOOT_ROM
991
//E2_define BOOT_ROM "boot_rom.v"
992
//E2_endif
993 33 unneback
*/
994 18 unneback
    input [adr_hi:2]    wb_adr_i;
995
    input               wb_stb_i;
996
    input               wb_cyc_i;
997
    output [31:0]        wb_dat_o;
998
    output              wb_ack_o;
999
    output              hit_o;
1000
    input               wb_clk;
1001
    input               wb_rst;
1002
 
1003
    wire hit;
1004
    reg [31:0] wb_dat;
1005
    reg wb_ack;
1006
 
1007
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1008 17 unneback
 
1009
always @ (posedge wb_clk or posedge wb_rst)
1010
    if (wb_rst)
1011 18 unneback
        wb_dat <= 32'h15000000;
1012 17 unneback
    else
1013 18 unneback
         case (wb_adr_i[addr_width-1:2])
1014 33 unneback
//E2_ifdef BOOT_ROM
1015 17 unneback
//E2_include `BOOT_ROM
1016 33 unneback
//E2_endif
1017 17 unneback
           /*
1018
            // Zero r0 and jump to 0x00000100
1019 18 unneback
 
1020
            1 : wb_dat <= 32'hA8200000;
1021
            2 : wb_dat <= 32'hA8C00100;
1022
            3 : wb_dat <= 32'h44003000;
1023
            4 : wb_dat <= 32'h15000000;
1024 17 unneback
            */
1025
           default:
1026 18 unneback
             wb_dat <= 32'h00000000;
1027 17 unneback
 
1028
         endcase // case (wb_adr_i)
1029
 
1030
 
1031
always @ (posedge wb_clk or posedge wb_rst)
1032
    if (wb_rst)
1033 18 unneback
        wb_ack <= 1'b0;
1034 17 unneback
    else
1035 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1036 17 unneback
 
1037 18 unneback
assign hit_o = hit;
1038
assign wb_dat_o = wb_dat & {32{wb_ack}};
1039
assign wb_ack_o = wb_ack;
1040
 
1041 17 unneback
endmodule
1042 40 unneback
`endif
1043 32 unneback
 
1044 40 unneback
`ifdef WB_DPRAM
1045
`define MODULE wb_dpram
1046
module `BASE`MODULE (
1047
`undef MODULE
1048 32 unneback
        // wishbone slave side a
1049
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1050
        wbsa_clk, wbsa_rst,
1051
        // wishbone slave side a
1052
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1053
        wbsb_clk, wbsb_rst);
1054
 
1055
parameter data_width = 32;
1056
parameter addr_width = 8;
1057
 
1058
parameter dat_o_mask_a = 1;
1059
parameter dat_o_mask_b = 1;
1060
 
1061
input [31:0] wbsa_dat_i;
1062
input [addr_width-1:2] wbsa_adr_i;
1063
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1064
output [31:0] wbsa_dat_o;
1065
output wbsa_ack_o;
1066
input wbsa_clk, wbsa_rst;
1067
 
1068
input [31:0] wbsb_dat_i;
1069
input [addr_width-1:2] wbsb_adr_i;
1070
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1071
output [31:0] wbsb_dat_o;
1072
output wbsb_ack_o;
1073
input wbsb_clk, wbsb_rst;
1074
 
1075
wire wbsa_dat_tmp, wbsb_dat_tmp;
1076
 
1077 40 unneback
`define MODULE dpram_2r2w
1078
`BASE`MODULE # (
1079
`undef MODULE
1080 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
1081 32 unneback
dpram0(
1082
    .d_a(wbsa_dat_i),
1083
    .q_a(wbsa_dat_tmp),
1084
    .adr_a(wbsa_adr_i),
1085
    .we_a(wbsa_we_i),
1086
    .clk_a(wbsa_clk),
1087
    .d_b(wbsb_dat_i),
1088
    .q_b(wbsb_dat_tmp),
1089
    .adr_b(wbsb_adr_i),
1090
    .we_b(wbsb_we_i),
1091
    .clk_b(wbsb_clk) );
1092
 
1093 33 unneback
generate if (dat_o_mask_a==1)
1094 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
1095
endgenerate
1096 33 unneback
generate if (dat_o_mask_a==0)
1097 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
1098
endgenerate
1099
 
1100 33 unneback
generate if (dat_o_mask_b==1)
1101 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
1102
endgenerate
1103 33 unneback
generate if (dat_o_mask_b==0)
1104 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
1105
endgenerate
1106
 
1107 40 unneback
`define MODULE spr
1108
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
1109
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
1110
`undef MODULE
1111 32 unneback
 
1112
endmodule
1113 40 unneback
`endif

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