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1 12 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46
`define MODULE wb_adr_inc
47 84 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
48 75 unneback
`undef MODULE
49 83 unneback
parameter adr_width = 10;
50
parameter max_burst_width = 4;
51 84 unneback
input cyc_i, stb_i, we_i;
52 83 unneback
input [2:0] cti_i;
53
input [1:0] bte_i;
54
input [adr_width-1:0] adr_i;
55
output [adr_width-1:0] adr_o;
56
output ack_o;
57
input clk, rst;
58 75 unneback
 
59 83 unneback
reg [adr_width-1:0] adr;
60 90 unneback
wire [max_burst_width-1:0] to_adr;
61 91 unneback
reg [max_burst_width-1:0] last_adr;
62
reg [1:0] last_cycle;
63
localparam idle = 2'b00;
64
localparam cyc  = 2'b01;
65
localparam ws   = 2'b10;
66
localparam eoc  = 2'b11;
67 90 unneback
 
68 91 unneback
always @ (posedge clk or posedge rst)
69
if (rst)
70
    last_adr <= {max_burst_width{1'b0}};
71
else
72
    if (stb_i)
73
        last_adr <=adr_o;
74
 
75 83 unneback
generate
76
if (max_burst_width==0) begin : inst_0
77
    reg ack_o;
78
    assign adr_o = adr_i;
79 75 unneback
    always @ (posedge clk or posedge rst)
80 83 unneback
    if (rst)
81
        ack_o <= 1'b0;
82
    else
83
        ack_o <= cyc_i & stb_i & !ack_o;
84
end else begin
85
 
86
    always @ (posedge clk or posedge rst)
87
    if (rst)
88
        last_cycle <= idle;
89
    else
90
        last_cycle <= (!cyc_i) ? idle :
91
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
92
                      (cyc_i & !stb_i) ? ws :
93
                      cyc;
94
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
95 84 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
96 91 unneback
                                        (!stb_i) ? last_adr :
97 84 unneback
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
98
                                        adr[max_burst_width-1:0];
99 90 unneback
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
100 83 unneback
end
101
endgenerate
102
 
103
generate
104
if (max_burst_width==2) begin : inst_2
105
    always @ (posedge clk or posedge rst)
106
    if (rst)
107
        adr <= 2'h0;
108
    else
109
        if (cyc_i & stb_i)
110
            adr[1:0] <= to_adr[1:0] + 2'd1;
111 75 unneback
        else
112 83 unneback
            adr <= to_adr[1:0];
113
end
114
endgenerate
115
 
116
generate
117
if (max_burst_width==3) begin : inst_3
118
    always @ (posedge clk or posedge rst)
119
    if (rst)
120
        adr <= 3'h0;
121
    else
122
        if (cyc_i & stb_i)
123
            case (bte_i)
124
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
125
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
126 75 unneback
            endcase
127 83 unneback
        else
128
            adr <= to_adr[2:0];
129
end
130
endgenerate
131
 
132
generate
133
if (max_burst_width==4) begin : inst_4
134
    always @ (posedge clk or posedge rst)
135
    if (rst)
136
        adr <= 4'h0;
137
    else
138 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
139 83 unneback
            case (bte_i)
140
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
141
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
142
            default: adr[3:0] <= to_adr + 4'd1;
143
            endcase
144
        else
145
            adr <= to_adr[3:0];
146
end
147
endgenerate
148
 
149
generate
150
if (adr_width > max_burst_width) begin : pass_through
151
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
152
end
153
endgenerate
154
 
155
endmodule
156 75 unneback
`endif
157
 
158 40 unneback
`ifdef WB3WB3_BRIDGE
159 12 unneback
// async wb3 - wb3 bridge
160
`timescale 1ns/1ns
161 40 unneback
`define MODULE wb3wb3_bridge
162
module `BASE`MODULE (
163
`undef MODULE
164 12 unneback
        // wishbone slave side
165
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
166
        // wishbone master side
167
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
168
 
169
input [31:0] wbs_dat_i;
170
input [31:2] wbs_adr_i;
171
input [3:0]  wbs_sel_i;
172
input [1:0]  wbs_bte_i;
173
input [2:0]  wbs_cti_i;
174
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
175
output [31:0] wbs_dat_o;
176 14 unneback
output wbs_ack_o;
177 12 unneback
input wbs_clk, wbs_rst;
178
 
179
output [31:0] wbm_dat_o;
180
output reg [31:2] wbm_adr_o;
181
output [3:0]  wbm_sel_o;
182
output reg [1:0]  wbm_bte_o;
183
output reg [2:0]  wbm_cti_o;
184 14 unneback
output reg wbm_we_o;
185
output wbm_cyc_o;
186 12 unneback
output wbm_stb_o;
187
input [31:0]  wbm_dat_i;
188
input wbm_ack_i;
189
input wbm_clk, wbm_rst;
190
 
191
parameter addr_width = 4;
192
 
193
// bte
194
parameter linear       = 2'b00;
195
parameter wrap4        = 2'b01;
196
parameter wrap8        = 2'b10;
197
parameter wrap16       = 2'b11;
198
// cti
199
parameter classic      = 3'b000;
200
parameter incburst     = 3'b010;
201
parameter endofburst   = 3'b111;
202
 
203
parameter wbs_adr  = 1'b0;
204
parameter wbs_data = 1'b1;
205
 
206 33 unneback
parameter wbm_adr0      = 2'b00;
207
parameter wbm_adr1      = 2'b01;
208
parameter wbm_data      = 2'b10;
209
parameter wbm_data_wait = 2'b11;
210 12 unneback
 
211
reg [1:0] wbs_bte_reg;
212
reg wbs;
213
wire wbs_eoc_alert, wbm_eoc_alert;
214
reg wbs_eoc, wbm_eoc;
215
reg [1:0] wbm;
216
 
217 14 unneback
wire [1:16] wbs_count, wbm_count;
218 12 unneback
 
219
wire [35:0] a_d, a_q, b_d, b_q;
220
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
221
reg a_rd_reg;
222
wire b_rd_adr, b_rd_data;
223 14 unneback
wire b_rd_data_reg;
224
wire [35:0] temp;
225 12 unneback
 
226
`define WE 5
227
`define BTE 4:3
228
`define CTI 2:0
229
 
230
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
231
always @ (posedge wbs_clk or posedge wbs_rst)
232
if (wbs_rst)
233
        wbs_eoc <= 1'b0;
234
else
235
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
236 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
237 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
238
                wbs_eoc <= 1'b1;
239
 
240 40 unneback
`define MODULE cnt_shreg_ce_clear
241
`BASE`MODULE # ( .length(16))
242
`undef MODULE
243 12 unneback
    cnt0 (
244
        .cke(wbs_ack_o),
245
        .clear(wbs_eoc),
246
        .q(wbs_count),
247
        .rst(wbs_rst),
248
        .clk(wbs_clk));
249
 
250
always @ (posedge wbs_clk or posedge wbs_rst)
251
if (wbs_rst)
252
        wbs <= wbs_adr;
253
else
254 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
255 12 unneback
                wbs <= wbs_data;
256
        else if (wbs_eoc & wbs_ack_o)
257
                wbs <= wbs_adr;
258
 
259
// wbs FIFO
260 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
261
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
262 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
263
              1'b0;
264
assign a_rd = !a_fifo_empty;
265
always @ (posedge wbs_clk or posedge wbs_rst)
266
if (wbs_rst)
267
        a_rd_reg <= 1'b0;
268
else
269
        a_rd_reg <= a_rd;
270
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
271
 
272
assign wbs_dat_o = a_q[35:4];
273
 
274
always @ (posedge wbs_clk or posedge wbs_rst)
275
if (wbs_rst)
276 13 unneback
        wbs_bte_reg <= 2'b00;
277 12 unneback
else
278 13 unneback
        wbs_bte_reg <= wbs_bte_i;
279 12 unneback
 
280
// wbm FIFO
281
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
282
always @ (posedge wbm_clk or posedge wbm_rst)
283
if (wbm_rst)
284
        wbm_eoc <= 1'b0;
285
else
286
        if (wbm==wbm_adr0 & !b_fifo_empty)
287
                wbm_eoc <= b_q[`BTE] == linear;
288
        else if (wbm_eoc_alert & wbm_ack_i)
289
                wbm_eoc <= 1'b1;
290
 
291
always @ (posedge wbm_clk or posedge wbm_rst)
292
if (wbm_rst)
293
        wbm <= wbm_adr0;
294
else
295 33 unneback
/*
296 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
297
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
298
        (wbm==wbm_adr1 & !wbm_we_o) |
299
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
300
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
301 33 unneback
*/
302
    case (wbm)
303
    wbm_adr0:
304
        if (!b_fifo_empty)
305
            wbm <= wbm_adr1;
306
    wbm_adr1:
307
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
308
            wbm <= wbm_data;
309
    wbm_data:
310
        if (wbm_ack_i & wbm_eoc)
311
            wbm <= wbm_adr0;
312
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
313
            wbm <= wbm_data_wait;
314
    wbm_data_wait:
315
        if (!b_fifo_empty)
316
            wbm <= wbm_data;
317
    endcase
318 12 unneback
 
319
assign b_d = {wbm_dat_i,4'b1111};
320
assign b_wr = !wbm_we_o & wbm_ack_i;
321
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
322
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
323
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
324 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
325 12 unneback
                   1'b0;
326
assign b_rd = b_rd_adr | b_rd_data;
327
 
328 40 unneback
`define MODULE dff
329
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
330
`undef MODULE
331
`define MODULE dff_ce
332
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
333
`undef MODULE
334 12 unneback
 
335
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
336
 
337 40 unneback
`define MODULE cnt_shreg_ce_clear
338 42 unneback
`BASE`MODULE # ( .length(16))
339 40 unneback
`undef MODULE
340 12 unneback
    cnt1 (
341
        .cke(wbm_ack_i),
342
        .clear(wbm_eoc),
343
        .q(wbm_count),
344
        .rst(wbm_rst),
345
        .clk(wbm_clk));
346
 
347 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
348
assign wbm_stb_o = (wbm==wbm_data);
349 12 unneback
 
350
always @ (posedge wbm_clk or posedge wbm_rst)
351
if (wbm_rst)
352
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
353
else begin
354
        if (wbm==wbm_adr0 & !b_fifo_empty)
355
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
356
        else if (wbm_eoc_alert & wbm_ack_i)
357
                wbm_cti_o <= endofburst;
358
end
359
 
360
//async_fifo_dw_simplex_top
361 40 unneback
`define MODULE fifo_2r2w_async_simplex
362
`BASE`MODULE
363
`undef MODULE
364 12 unneback
# ( .data_width(36), .addr_width(addr_width))
365
fifo (
366
    // a side
367
    .a_d(a_d),
368
    .a_wr(a_wr),
369
    .a_fifo_full(a_fifo_full),
370
    .a_q(a_q),
371
    .a_rd(a_rd),
372
    .a_fifo_empty(a_fifo_empty),
373
    .a_clk(wbs_clk),
374
    .a_rst(wbs_rst),
375
    // b side
376
    .b_d(b_d),
377
    .b_wr(b_wr),
378
    .b_fifo_full(b_fifo_full),
379
    .b_q(b_q),
380
    .b_rd(b_rd),
381
    .b_fifo_empty(b_fifo_empty),
382
    .b_clk(wbm_clk),
383
    .b_rst(wbm_rst)
384
    );
385
 
386
endmodule
387 40 unneback
`undef WE
388
`undef BTE
389
`undef CTI
390
`endif
391 17 unneback
 
392 75 unneback
`ifdef WB3AVALON_BRIDGE
393
`define MODULE wb3avalon_bridge
394
module `BASE`MODULE (
395
`undef MODULE
396
        // wishbone slave side
397
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
398 77 unneback
        // avalon master side
399 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
400
 
401 84 unneback
parameter linewrapburst = 1'b0;
402
 
403 75 unneback
input [31:0] wbs_dat_i;
404
input [31:2] wbs_adr_i;
405
input [3:0]  wbs_sel_i;
406
input [1:0]  wbs_bte_i;
407
input [2:0]  wbs_cti_i;
408 83 unneback
input wbs_we_i;
409
input wbs_cyc_i;
410
input wbs_stb_i;
411 75 unneback
output [31:0] wbs_dat_o;
412
output wbs_ack_o;
413
input wbs_clk, wbs_rst;
414
 
415
input [31:0] readdata;
416
output [31:0] writedata;
417
output [31:2] address;
418
output [3:0]  be;
419
output write;
420 81 unneback
output read;
421 75 unneback
output beginbursttransfer;
422
output [3:0] burstcount;
423
input readdatavalid;
424
input waitrequest;
425
input clk;
426
input rst;
427
 
428
wire [1:0] wbm_bte_o;
429
wire [2:0] wbm_cti_o;
430
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
431
reg last_cyc;
432 79 unneback
reg [3:0] counter;
433 82 unneback
reg read_busy;
434 75 unneback
 
435
always @ (posedge clk or posedge rst)
436
if (rst)
437
    last_cyc <= 1'b0;
438
else
439
    last_cyc <= wbm_cyc_o;
440
 
441 79 unneback
always @ (posedge clk or posedge rst)
442
if (rst)
443 82 unneback
    read_busy <= 1'b0;
444 79 unneback
else
445 82 unneback
    if (read & !waitrequest)
446
        read_busy <= 1'b1;
447
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
448
        read_busy <= 1'b0;
449
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
450 81 unneback
 
451 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
452
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
453
                    (wbm_bte_o==2'b10) ? 4'd8 :
454 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
455
                    4'd1;
456 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
457 75 unneback
 
458 79 unneback
always @ (posedge clk or posedge rst)
459
if (rst) begin
460
    counter <= 4'd0;
461
end else
462 80 unneback
    if (wbm_we_o) begin
463
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
464 84 unneback
            counter <= burstcount -4'd1;
465 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
466
            counter <= burstcount;
467
        end else if (!waitrequest & wbm_stb_o) begin
468
            counter <= counter - 4'd1;
469
        end
470 82 unneback
    end
471 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
472 79 unneback
 
473 75 unneback
`define MODULE wb3wb3_bridge
474 77 unneback
`BASE`MODULE wbwb3inst (
475 75 unneback
`undef MODULE
476
    // wishbone slave side
477
    .wbs_dat_i(wbs_dat_i),
478
    .wbs_adr_i(wbs_adr_i),
479
    .wbs_sel_i(wbs_sel_i),
480
    .wbs_bte_i(wbs_bte_i),
481
    .wbs_cti_i(wbs_cti_i),
482
    .wbs_we_i(wbs_we_i),
483
    .wbs_cyc_i(wbs_cyc_i),
484
    .wbs_stb_i(wbs_stb_i),
485
    .wbs_dat_o(wbs_dat_o),
486
    .wbs_ack_o(wbs_ack_o),
487
    .wbs_clk(wbs_clk),
488
    .wbs_rst(wbs_rst),
489
    // wishbone master side
490
    .wbm_dat_o(writedata),
491 78 unneback
    .wbm_adr_o(address),
492 75 unneback
    .wbm_sel_o(be),
493
    .wbm_bte_o(wbm_bte_o),
494
    .wbm_cti_o(wbm_cti_o),
495
    .wbm_we_o(wbm_we_o),
496
    .wbm_cyc_o(wbm_cyc_o),
497
    .wbm_stb_o(wbm_stb_o),
498
    .wbm_dat_i(readdata),
499
    .wbm_ack_i(wbm_ack_i),
500
    .wbm_clk(clk),
501
    .wbm_rst(rst));
502
 
503
 
504
endmodule
505
`endif
506
 
507 40 unneback
`ifdef WB3_ARBITER_TYPE1
508
`define MODULE wb3_arbiter_type1
509 42 unneback
module `BASE`MODULE (
510 40 unneback
`undef MODULE
511 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
512
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
513
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
514
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
515
    wb_clk, wb_rst
516
);
517
 
518
parameter nr_of_ports = 3;
519
parameter adr_size = 26;
520
parameter adr_lo   = 2;
521
parameter dat_size = 32;
522
parameter sel_size = dat_size/8;
523
 
524
localparam aw = (adr_size - adr_lo) * nr_of_ports;
525
localparam dw = dat_size * nr_of_ports;
526
localparam sw = sel_size * nr_of_ports;
527
localparam cw = 3 * nr_of_ports;
528
localparam bw = 2 * nr_of_ports;
529
 
530
input  [dw-1:0] wbm_dat_o;
531
input  [aw-1:0] wbm_adr_o;
532
input  [sw-1:0] wbm_sel_o;
533
input  [cw-1:0] wbm_cti_o;
534
input  [bw-1:0] wbm_bte_o;
535
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
536
output [dw-1:0] wbm_dat_i;
537
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
538
 
539
output [dat_size-1:0] wbs_dat_i;
540
output [adr_size-1:adr_lo] wbs_adr_i;
541
output [sel_size-1:0] wbs_sel_i;
542
output [2:0] wbs_cti_i;
543
output [1:0] wbs_bte_i;
544
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
545
input  [dat_size-1:0] wbs_dat_o;
546
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
547
 
548
input wb_clk, wb_rst;
549
 
550 44 unneback
reg  [nr_of_ports-1:0] select;
551 39 unneback
wire [nr_of_ports-1:0] state;
552
wire [nr_of_ports-1:0] eoc; // end-of-cycle
553
wire [nr_of_ports-1:0] sel;
554
wire idle;
555
 
556
genvar i;
557
 
558
assign idle = !(|state);
559
 
560
generate
561
if (nr_of_ports == 2) begin
562
 
563
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
564
 
565
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
566
 
567 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
568
 
569
    always @ (idle or wbm_cyc_o)
570
    if (idle)
571
        casex (wbm_cyc_o)
572
        2'b1x : select = 2'b10;
573
        2'b01 : select = 2'b01;
574
        default : select = {nr_of_ports{1'b0}};
575
        endcase
576
    else
577
        select = {nr_of_ports{1'b0}};
578
 
579 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
580
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
581
 
582
end
583
endgenerate
584
 
585
generate
586
if (nr_of_ports == 3) begin
587
 
588
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
589
 
590
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
591
 
592 44 unneback
    always @ (idle or wbm_cyc_o)
593
    if (idle)
594
        casex (wbm_cyc_o)
595
        3'b1xx : select = 3'b100;
596
        3'b01x : select = 3'b010;
597
        3'b001 : select = 3'b001;
598
        default : select = {nr_of_ports{1'b0}};
599
        endcase
600
    else
601
        select = {nr_of_ports{1'b0}};
602
 
603
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
604 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
605
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
606
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
607
 
608
end
609
endgenerate
610
 
611
generate
612 44 unneback
if (nr_of_ports == 4) begin
613
 
614
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
615
 
616
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
617
 
618
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
619
 
620
    always @ (idle or wbm_cyc_o)
621
    if (idle)
622
        casex (wbm_cyc_o)
623
        4'b1xxx : select = 4'b1000;
624
        4'b01xx : select = 4'b0100;
625
        4'b001x : select = 4'b0010;
626
        4'b0001 : select = 4'b0001;
627
        default : select = {nr_of_ports{1'b0}};
628
        endcase
629
    else
630
        select = {nr_of_ports{1'b0}};
631
 
632
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
633
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
634
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
635
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
636
 
637
end
638
endgenerate
639
 
640
generate
641
if (nr_of_ports == 5) begin
642
 
643
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
644
 
645
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
646
 
647
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
648
 
649
    always @ (idle or wbm_cyc_o)
650
    if (idle)
651
        casex (wbm_cyc_o)
652
        5'b1xxxx : select = 5'b10000;
653
        5'b01xxx : select = 5'b01000;
654
        5'b001xx : select = 5'b00100;
655
        5'b0001x : select = 5'b00010;
656
        5'b00001 : select = 5'b00001;
657
        default : select = {nr_of_ports{1'b0}};
658
        endcase
659
    else
660
        select = {nr_of_ports{1'b0}};
661
 
662
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
663
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
664
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
665
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
666
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
667
 
668
end
669
endgenerate
670
 
671
generate
672 67 unneback
if (nr_of_ports == 6) begin
673
 
674
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
675
 
676
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
677
 
678
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
679
 
680
    always @ (idle or wbm_cyc_o)
681
    if (idle)
682
        casex (wbm_cyc_o)
683
        6'b1xxxxx : select = 6'b100000;
684
        6'b01xxxx : select = 6'b010000;
685
        6'b001xxx : select = 6'b001000;
686
        6'b0001xx : select = 6'b000100;
687
        6'b00001x : select = 6'b000010;
688
        6'b000001 : select = 6'b000001;
689
        default : select = {nr_of_ports{1'b0}};
690
        endcase
691
    else
692
        select = {nr_of_ports{1'b0}};
693
 
694
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
695
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
696
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
697
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
698
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
699
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
700
 
701
end
702
endgenerate
703
 
704
generate
705
if (nr_of_ports == 7) begin
706
 
707
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
708
 
709
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
710
 
711
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
712
 
713
    always @ (idle or wbm_cyc_o)
714
    if (idle)
715
        casex (wbm_cyc_o)
716
        7'b1xxxxxx : select = 7'b1000000;
717
        7'b01xxxxx : select = 7'b0100000;
718
        7'b001xxxx : select = 7'b0010000;
719
        7'b0001xxx : select = 7'b0001000;
720
        7'b00001xx : select = 7'b0000100;
721
        7'b000001x : select = 7'b0000010;
722
        7'b0000001 : select = 7'b0000001;
723
        default : select = {nr_of_ports{1'b0}};
724
        endcase
725
    else
726
        select = {nr_of_ports{1'b0}};
727
 
728
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
729
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
730
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
731
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
732
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
733
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
734
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
735
 
736
end
737
endgenerate
738
 
739
generate
740
if (nr_of_ports == 8) begin
741
 
742
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
743
 
744
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
745
 
746
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
747
 
748
    always @ (idle or wbm_cyc_o)
749
    if (idle)
750
        casex (wbm_cyc_o)
751
        8'b1xxxxxxx : select = 8'b10000000;
752
        8'b01xxxxxx : select = 8'b01000000;
753
        8'b001xxxxx : select = 8'b00100000;
754
        8'b0001xxxx : select = 8'b00010000;
755
        8'b00001xxx : select = 8'b00001000;
756
        8'b000001xx : select = 8'b00000100;
757
        8'b0000001x : select = 8'b00000010;
758
        8'b00000001 : select = 8'b00000001;
759
        default : select = {nr_of_ports{1'b0}};
760
        endcase
761
    else
762
        select = {nr_of_ports{1'b0}};
763
 
764
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
765
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
766
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
767
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
768
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
769
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
770
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
771
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
772
 
773
end
774
endgenerate
775
 
776
generate
777 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
778 42 unneback
`define MODULE spr
779
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
780
`undef MODULE
781 39 unneback
end
782
endgenerate
783
 
784
    assign sel = select | state;
785
 
786 40 unneback
`define MODULE mux_andor
787
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
788
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
789
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
790
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
791
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
792
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
793
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
794
`undef MODULE
795 39 unneback
    assign wbs_cyc_i = |sel;
796
 
797
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
798
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
799
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
800
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
801
 
802
endmodule
803 40 unneback
`endif
804 39 unneback
 
805 60 unneback
`ifdef WB_B3_RAM_BE
806 49 unneback
// WB RAM with byte enable
807 59 unneback
`define MODULE wb_b3_ram_be
808
module `BASE`MODULE (
809
`undef MODULE
810 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
811
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
812 59 unneback
 
813 68 unneback
parameter adr_size = 16;
814 84 unneback
parameter mem_size = 1<<adr_size;
815 60 unneback
parameter dat_size = 32;
816 83 unneback
parameter max_burst_width = 4;
817 60 unneback
parameter memory_init = 1;
818
parameter memory_file = "vl_ram.vmem";
819 59 unneback
 
820 84 unneback
localparam aw = (adr_size);
821 69 unneback
localparam dw = dat_size;
822
localparam sw = dat_size/8;
823
localparam cw = 3;
824
localparam bw = 2;
825 60 unneback
 
826 70 unneback
input [dw-1:0] wbs_dat_i;
827
input [aw-1:0] wbs_adr_i;
828
input [cw-1:0] wbs_cti_i;
829
input [bw-1:0] wbs_bte_i;
830
input [sw-1:0] wbs_sel_i;
831
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
832
output [dw-1:0] wbs_dat_o;
833
output wbs_ack_o;
834 71 unneback
input wb_clk, wb_rst;
835 59 unneback
 
836 83 unneback
wire [aw-1:0] adr;
837 59 unneback
 
838 60 unneback
`define MODULE ram_be
839
`BASE`MODULE # (
840
    .data_width(dat_size),
841 83 unneback
    .addr_width(aw),
842 69 unneback
    .mem_size(mem_size),
843 68 unneback
    .memory_init(memory_init),
844
    .memory_file(memory_file))
845 60 unneback
ram0(
846
`undef MODULE
847
    .d(wbs_dat_i),
848 83 unneback
    .adr(adr),
849 60 unneback
    .be(wbs_sel_i),
850 86 unneback
    .we(wbs_we_i & wbs_ack_o),
851 60 unneback
    .q(wbs_dat_o),
852
    .clk(wb_clk)
853
);
854
 
855 83 unneback
`define MODULE wb_adr_inc
856
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
857
    .cyc_i(wbs_cyc_i),
858
    .stb_i(wbs_stb_i),
859
    .cti_i(wbs_cti_i),
860
    .bte_i(wbs_bte_i),
861
    .adr_i(wbs_adr_i),
862 84 unneback
    .we_i(wbs_we_i),
863 83 unneback
    .ack_o(wbs_ack_o),
864
    .adr_o(adr),
865
    .clk(wb_clk),
866
    .rst(wb_rst));
867
`undef MODULE
868 60 unneback
 
869 59 unneback
endmodule
870
`endif
871
 
872
`ifdef WB_B4_RAM_BE
873
// WB RAM with byte enable
874 49 unneback
`define MODULE wb_b4_ram_be
875
module `BASE`MODULE (
876
`undef MODULE
877
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
878 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
879 49 unneback
 
880
    parameter dat_width = 32;
881
    parameter adr_width = 8;
882
 
883
input [dat_width-1:0] wb_dat_i;
884
input [adr_width-1:0] wb_adr_i;
885
input [dat_width/8-1:0] wb_sel_i;
886
input wb_we_i, wb_stb_i, wb_cyc_i;
887
output [dat_width-1:0] wb_dat_o;
888 51 unneback
reg [dat_width-1:0] wb_dat_o;
889 52 unneback
output wb_stall_o;
890 49 unneback
output wb_ack_o;
891
reg wb_ack_o;
892
input wb_clk, wb_rst;
893
 
894 56 unneback
wire [dat_width/8-1:0] cke;
895
 
896 49 unneback
generate
897
if (dat_width==32) begin
898 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
899
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
900
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
901
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
902 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
903 49 unneback
    always @ (posedge wb_clk)
904
    begin
905 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
906
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
907
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
908
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
909 49 unneback
    end
910 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
911
    begin
912
        if (wb_rst)
913
            wb_dat_o <= 32'h0;
914
        else
915
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
916
    end
917 49 unneback
end
918
endgenerate
919
 
920 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
921 55 unneback
if (wb_rst)
922 52 unneback
    wb_ack_o <= 1'b0;
923
else
924 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
925 52 unneback
 
926
assign wb_stall_o = 1'b0;
927
 
928 49 unneback
endmodule
929
`endif
930
 
931 48 unneback
`ifdef WB_B4_ROM
932
// WB ROM
933
`define MODULE wb_b4_rom
934
module `BASE`MODULE (
935
`undef MODULE
936
    wb_adr_i, wb_stb_i, wb_cyc_i,
937
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
938
 
939
    parameter dat_width = 32;
940
    parameter dat_default = 32'h15000000;
941
    parameter adr_width = 32;
942
 
943
/*
944
//E2_ifndef ROM
945
//E2_define ROM "rom.v"
946
//E2_endif
947
*/
948
    input [adr_width-1:2]   wb_adr_i;
949
    input                   wb_stb_i;
950
    input                   wb_cyc_i;
951
    output [dat_width-1:0]  wb_dat_o;
952
    reg [dat_width-1:0]     wb_dat_o;
953
    output                  wb_ack_o;
954
    reg                     wb_ack_o;
955
    output                  stall_o;
956
    input                   wb_clk;
957
    input                   wb_rst;
958
 
959
always @ (posedge wb_clk or posedge wb_rst)
960
    if (wb_rst)
961
        wb_dat_o <= {dat_width{1'b0}};
962
    else
963
         case (wb_adr_i[adr_width-1:2])
964
//E2_ifdef ROM
965
//E2_include `ROM
966
//E2_endif
967
           default:
968
             wb_dat_o <= dat_default;
969
 
970
         endcase // case (wb_adr_i)
971
 
972
 
973
always @ (posedge wb_clk or posedge wb_rst)
974
    if (wb_rst)
975
        wb_ack_o <= 1'b0;
976
    else
977
        wb_ack_o <= wb_stb_i & wb_cyc_i;
978
 
979
assign stall_o = 1'b0;
980
 
981
endmodule
982
`endif
983
 
984
 
985 40 unneback
`ifdef WB_BOOT_ROM
986 17 unneback
// WB ROM
987 40 unneback
`define MODULE wb_boot_rom
988
module `BASE`MODULE (
989
`undef MODULE
990 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
991 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
992 17 unneback
 
993 18 unneback
    parameter adr_hi = 31;
994
    parameter adr_lo = 28;
995
    parameter adr_sel = 4'hf;
996
    parameter addr_width = 5;
997 33 unneback
/*
998 17 unneback
//E2_ifndef BOOT_ROM
999
//E2_define BOOT_ROM "boot_rom.v"
1000
//E2_endif
1001 33 unneback
*/
1002 18 unneback
    input [adr_hi:2]    wb_adr_i;
1003
    input               wb_stb_i;
1004
    input               wb_cyc_i;
1005
    output [31:0]        wb_dat_o;
1006
    output              wb_ack_o;
1007
    output              hit_o;
1008
    input               wb_clk;
1009
    input               wb_rst;
1010
 
1011
    wire hit;
1012
    reg [31:0] wb_dat;
1013
    reg wb_ack;
1014
 
1015
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1016 17 unneback
 
1017
always @ (posedge wb_clk or posedge wb_rst)
1018
    if (wb_rst)
1019 18 unneback
        wb_dat <= 32'h15000000;
1020 17 unneback
    else
1021 18 unneback
         case (wb_adr_i[addr_width-1:2])
1022 33 unneback
//E2_ifdef BOOT_ROM
1023 17 unneback
//E2_include `BOOT_ROM
1024 33 unneback
//E2_endif
1025 17 unneback
           /*
1026
            // Zero r0 and jump to 0x00000100
1027 18 unneback
 
1028
            1 : wb_dat <= 32'hA8200000;
1029
            2 : wb_dat <= 32'hA8C00100;
1030
            3 : wb_dat <= 32'h44003000;
1031
            4 : wb_dat <= 32'h15000000;
1032 17 unneback
            */
1033
           default:
1034 18 unneback
             wb_dat <= 32'h00000000;
1035 17 unneback
 
1036
         endcase // case (wb_adr_i)
1037
 
1038
 
1039
always @ (posedge wb_clk or posedge wb_rst)
1040
    if (wb_rst)
1041 18 unneback
        wb_ack <= 1'b0;
1042 17 unneback
    else
1043 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1044 17 unneback
 
1045 18 unneback
assign hit_o = hit;
1046
assign wb_dat_o = wb_dat & {32{wb_ack}};
1047
assign wb_ack_o = wb_ack;
1048
 
1049 17 unneback
endmodule
1050 40 unneback
`endif
1051 32 unneback
 
1052 40 unneback
`ifdef WB_DPRAM
1053
`define MODULE wb_dpram
1054
module `BASE`MODULE (
1055
`undef MODULE
1056 32 unneback
        // wishbone slave side a
1057
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1058
        wbsa_clk, wbsa_rst,
1059
        // wishbone slave side a
1060
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1061
        wbsb_clk, wbsb_rst);
1062
 
1063
parameter data_width = 32;
1064
parameter addr_width = 8;
1065
 
1066
parameter dat_o_mask_a = 1;
1067
parameter dat_o_mask_b = 1;
1068
 
1069
input [31:0] wbsa_dat_i;
1070
input [addr_width-1:2] wbsa_adr_i;
1071
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1072
output [31:0] wbsa_dat_o;
1073
output wbsa_ack_o;
1074
input wbsa_clk, wbsa_rst;
1075
 
1076
input [31:0] wbsb_dat_i;
1077
input [addr_width-1:2] wbsb_adr_i;
1078
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1079
output [31:0] wbsb_dat_o;
1080
output wbsb_ack_o;
1081
input wbsb_clk, wbsb_rst;
1082
 
1083
wire wbsa_dat_tmp, wbsb_dat_tmp;
1084
 
1085 40 unneback
`define MODULE dpram_2r2w
1086
`BASE`MODULE # (
1087
`undef MODULE
1088 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
1089 32 unneback
dpram0(
1090
    .d_a(wbsa_dat_i),
1091
    .q_a(wbsa_dat_tmp),
1092
    .adr_a(wbsa_adr_i),
1093
    .we_a(wbsa_we_i),
1094
    .clk_a(wbsa_clk),
1095
    .d_b(wbsb_dat_i),
1096
    .q_b(wbsb_dat_tmp),
1097
    .adr_b(wbsb_adr_i),
1098
    .we_b(wbsb_we_i),
1099
    .clk_b(wbsb_clk) );
1100
 
1101 33 unneback
generate if (dat_o_mask_a==1)
1102 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
1103
endgenerate
1104 33 unneback
generate if (dat_o_mask_a==0)
1105 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
1106
endgenerate
1107
 
1108 33 unneback
generate if (dat_o_mask_b==1)
1109 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
1110
endgenerate
1111 33 unneback
generate if (dat_o_mask_b==0)
1112 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
1113
endgenerate
1114
 
1115 40 unneback
`define MODULE spr
1116
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
1117
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
1118
`undef MODULE
1119 32 unneback
 
1120
endmodule
1121 40 unneback
`endif

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