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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46
`define MODULE wb_adr_inc
47 84 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
48 75 unneback
`undef MODULE
49 83 unneback
parameter adr_width = 10;
50
parameter max_burst_width = 4;
51 84 unneback
input cyc_i, stb_i, we_i;
52 83 unneback
input [2:0] cti_i;
53
input [1:0] bte_i;
54
input [adr_width-1:0] adr_i;
55
output [adr_width-1:0] adr_o;
56
output ack_o;
57
input clk, rst;
58 75 unneback
 
59 83 unneback
reg [adr_width-1:0] adr;
60 90 unneback
wire [max_burst_width-1:0] to_adr;
61 91 unneback
reg [max_burst_width-1:0] last_adr;
62 92 unneback
reg last_cycle;
63
localparam idle_or_eoc = 1'b0;
64
localparam cyc_or_ws   = 1'b1;
65 90 unneback
 
66 91 unneback
always @ (posedge clk or posedge rst)
67
if (rst)
68
    last_adr <= {max_burst_width{1'b0}};
69
else
70
    if (stb_i)
71 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
72 91 unneback
 
73 83 unneback
generate
74
if (max_burst_width==0) begin : inst_0
75
    reg ack_o;
76
    assign adr_o = adr_i;
77 75 unneback
    always @ (posedge clk or posedge rst)
78 83 unneback
    if (rst)
79
        ack_o <= 1'b0;
80
    else
81
        ack_o <= cyc_i & stb_i & !ack_o;
82
end else begin
83
 
84
    always @ (posedge clk or posedge rst)
85
    if (rst)
86 92 unneback
        last_cycle <= idle_or_eoc;
87 83 unneback
    else
88 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
89
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
90
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
91
                      cyc_or_ws; // cyc
92
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
93 84 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
94 91 unneback
                                        (!stb_i) ? last_adr :
95 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
96 84 unneback
                                        adr[max_burst_width-1:0];
97 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
98 83 unneback
end
99
endgenerate
100
 
101
generate
102
if (max_burst_width==2) begin : inst_2
103
    always @ (posedge clk or posedge rst)
104
    if (rst)
105
        adr <= 2'h0;
106
    else
107
        if (cyc_i & stb_i)
108
            adr[1:0] <= to_adr[1:0] + 2'd1;
109 75 unneback
        else
110 83 unneback
            adr <= to_adr[1:0];
111
end
112
endgenerate
113
 
114
generate
115
if (max_burst_width==3) begin : inst_3
116
    always @ (posedge clk or posedge rst)
117
    if (rst)
118
        adr <= 3'h0;
119
    else
120
        if (cyc_i & stb_i)
121
            case (bte_i)
122
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
123
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
124 75 unneback
            endcase
125 83 unneback
        else
126
            adr <= to_adr[2:0];
127
end
128
endgenerate
129
 
130
generate
131
if (max_burst_width==4) begin : inst_4
132
    always @ (posedge clk or posedge rst)
133
    if (rst)
134
        adr <= 4'h0;
135
    else
136 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
137 83 unneback
            case (bte_i)
138
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
139
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
140
            default: adr[3:0] <= to_adr + 4'd1;
141
            endcase
142
        else
143
            adr <= to_adr[3:0];
144
end
145
endgenerate
146
 
147
generate
148
if (adr_width > max_burst_width) begin : pass_through
149
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
150
end
151
endgenerate
152
 
153
endmodule
154 75 unneback
`endif
155
 
156 40 unneback
`ifdef WB3WB3_BRIDGE
157 12 unneback
// async wb3 - wb3 bridge
158
`timescale 1ns/1ns
159 40 unneback
`define MODULE wb3wb3_bridge
160
module `BASE`MODULE (
161
`undef MODULE
162 12 unneback
        // wishbone slave side
163
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
164
        // wishbone master side
165
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
166
 
167
input [31:0] wbs_dat_i;
168
input [31:2] wbs_adr_i;
169
input [3:0]  wbs_sel_i;
170
input [1:0]  wbs_bte_i;
171
input [2:0]  wbs_cti_i;
172
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
173
output [31:0] wbs_dat_o;
174 14 unneback
output wbs_ack_o;
175 12 unneback
input wbs_clk, wbs_rst;
176
 
177
output [31:0] wbm_dat_o;
178
output reg [31:2] wbm_adr_o;
179
output [3:0]  wbm_sel_o;
180
output reg [1:0]  wbm_bte_o;
181
output reg [2:0]  wbm_cti_o;
182 14 unneback
output reg wbm_we_o;
183
output wbm_cyc_o;
184 12 unneback
output wbm_stb_o;
185
input [31:0]  wbm_dat_i;
186
input wbm_ack_i;
187
input wbm_clk, wbm_rst;
188
 
189
parameter addr_width = 4;
190
 
191
// bte
192
parameter linear       = 2'b00;
193
parameter wrap4        = 2'b01;
194
parameter wrap8        = 2'b10;
195
parameter wrap16       = 2'b11;
196
// cti
197
parameter classic      = 3'b000;
198
parameter incburst     = 3'b010;
199
parameter endofburst   = 3'b111;
200
 
201
parameter wbs_adr  = 1'b0;
202
parameter wbs_data = 1'b1;
203
 
204 33 unneback
parameter wbm_adr0      = 2'b00;
205
parameter wbm_adr1      = 2'b01;
206
parameter wbm_data      = 2'b10;
207
parameter wbm_data_wait = 2'b11;
208 12 unneback
 
209
reg [1:0] wbs_bte_reg;
210
reg wbs;
211
wire wbs_eoc_alert, wbm_eoc_alert;
212
reg wbs_eoc, wbm_eoc;
213
reg [1:0] wbm;
214
 
215 14 unneback
wire [1:16] wbs_count, wbm_count;
216 12 unneback
 
217
wire [35:0] a_d, a_q, b_d, b_q;
218
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
219
reg a_rd_reg;
220
wire b_rd_adr, b_rd_data;
221 14 unneback
wire b_rd_data_reg;
222
wire [35:0] temp;
223 12 unneback
 
224
`define WE 5
225
`define BTE 4:3
226
`define CTI 2:0
227
 
228
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
229
always @ (posedge wbs_clk or posedge wbs_rst)
230
if (wbs_rst)
231
        wbs_eoc <= 1'b0;
232
else
233
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
234 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
235 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
236
                wbs_eoc <= 1'b1;
237
 
238 40 unneback
`define MODULE cnt_shreg_ce_clear
239
`BASE`MODULE # ( .length(16))
240
`undef MODULE
241 12 unneback
    cnt0 (
242
        .cke(wbs_ack_o),
243
        .clear(wbs_eoc),
244
        .q(wbs_count),
245
        .rst(wbs_rst),
246
        .clk(wbs_clk));
247
 
248
always @ (posedge wbs_clk or posedge wbs_rst)
249
if (wbs_rst)
250
        wbs <= wbs_adr;
251
else
252 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
253 12 unneback
                wbs <= wbs_data;
254
        else if (wbs_eoc & wbs_ack_o)
255
                wbs <= wbs_adr;
256
 
257
// wbs FIFO
258 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
259
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
260 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
261
              1'b0;
262
assign a_rd = !a_fifo_empty;
263
always @ (posedge wbs_clk or posedge wbs_rst)
264
if (wbs_rst)
265
        a_rd_reg <= 1'b0;
266
else
267
        a_rd_reg <= a_rd;
268
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
269
 
270
assign wbs_dat_o = a_q[35:4];
271
 
272
always @ (posedge wbs_clk or posedge wbs_rst)
273
if (wbs_rst)
274 13 unneback
        wbs_bte_reg <= 2'b00;
275 12 unneback
else
276 13 unneback
        wbs_bte_reg <= wbs_bte_i;
277 12 unneback
 
278
// wbm FIFO
279
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
280
always @ (posedge wbm_clk or posedge wbm_rst)
281
if (wbm_rst)
282
        wbm_eoc <= 1'b0;
283
else
284
        if (wbm==wbm_adr0 & !b_fifo_empty)
285
                wbm_eoc <= b_q[`BTE] == linear;
286
        else if (wbm_eoc_alert & wbm_ack_i)
287
                wbm_eoc <= 1'b1;
288
 
289
always @ (posedge wbm_clk or posedge wbm_rst)
290
if (wbm_rst)
291
        wbm <= wbm_adr0;
292
else
293 33 unneback
/*
294 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
295
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
296
        (wbm==wbm_adr1 & !wbm_we_o) |
297
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
298
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
299 33 unneback
*/
300
    case (wbm)
301
    wbm_adr0:
302
        if (!b_fifo_empty)
303
            wbm <= wbm_adr1;
304
    wbm_adr1:
305
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
306
            wbm <= wbm_data;
307
    wbm_data:
308
        if (wbm_ack_i & wbm_eoc)
309
            wbm <= wbm_adr0;
310
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
311
            wbm <= wbm_data_wait;
312
    wbm_data_wait:
313
        if (!b_fifo_empty)
314
            wbm <= wbm_data;
315
    endcase
316 12 unneback
 
317
assign b_d = {wbm_dat_i,4'b1111};
318
assign b_wr = !wbm_we_o & wbm_ack_i;
319
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
320
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
321
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
322 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
323 12 unneback
                   1'b0;
324
assign b_rd = b_rd_adr | b_rd_data;
325
 
326 40 unneback
`define MODULE dff
327
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
328
`undef MODULE
329
`define MODULE dff_ce
330
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
331
`undef MODULE
332 12 unneback
 
333
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
334
 
335 40 unneback
`define MODULE cnt_shreg_ce_clear
336 42 unneback
`BASE`MODULE # ( .length(16))
337 40 unneback
`undef MODULE
338 12 unneback
    cnt1 (
339
        .cke(wbm_ack_i),
340
        .clear(wbm_eoc),
341
        .q(wbm_count),
342
        .rst(wbm_rst),
343
        .clk(wbm_clk));
344
 
345 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
346
assign wbm_stb_o = (wbm==wbm_data);
347 12 unneback
 
348
always @ (posedge wbm_clk or posedge wbm_rst)
349
if (wbm_rst)
350
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
351
else begin
352
        if (wbm==wbm_adr0 & !b_fifo_empty)
353
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
354
        else if (wbm_eoc_alert & wbm_ack_i)
355
                wbm_cti_o <= endofburst;
356
end
357
 
358
//async_fifo_dw_simplex_top
359 40 unneback
`define MODULE fifo_2r2w_async_simplex
360
`BASE`MODULE
361
`undef MODULE
362 12 unneback
# ( .data_width(36), .addr_width(addr_width))
363
fifo (
364
    // a side
365
    .a_d(a_d),
366
    .a_wr(a_wr),
367
    .a_fifo_full(a_fifo_full),
368
    .a_q(a_q),
369
    .a_rd(a_rd),
370
    .a_fifo_empty(a_fifo_empty),
371
    .a_clk(wbs_clk),
372
    .a_rst(wbs_rst),
373
    // b side
374
    .b_d(b_d),
375
    .b_wr(b_wr),
376
    .b_fifo_full(b_fifo_full),
377
    .b_q(b_q),
378
    .b_rd(b_rd),
379
    .b_fifo_empty(b_fifo_empty),
380
    .b_clk(wbm_clk),
381
    .b_rst(wbm_rst)
382
    );
383
 
384
endmodule
385 40 unneback
`undef WE
386
`undef BTE
387
`undef CTI
388
`endif
389 17 unneback
 
390 75 unneback
`ifdef WB3AVALON_BRIDGE
391
`define MODULE wb3avalon_bridge
392
module `BASE`MODULE (
393
`undef MODULE
394
        // wishbone slave side
395
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
396 77 unneback
        // avalon master side
397 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
398
 
399 84 unneback
parameter linewrapburst = 1'b0;
400
 
401 75 unneback
input [31:0] wbs_dat_i;
402
input [31:2] wbs_adr_i;
403
input [3:0]  wbs_sel_i;
404
input [1:0]  wbs_bte_i;
405
input [2:0]  wbs_cti_i;
406 83 unneback
input wbs_we_i;
407
input wbs_cyc_i;
408
input wbs_stb_i;
409 75 unneback
output [31:0] wbs_dat_o;
410
output wbs_ack_o;
411
input wbs_clk, wbs_rst;
412
 
413
input [31:0] readdata;
414
output [31:0] writedata;
415
output [31:2] address;
416
output [3:0]  be;
417
output write;
418 81 unneback
output read;
419 75 unneback
output beginbursttransfer;
420
output [3:0] burstcount;
421
input readdatavalid;
422
input waitrequest;
423
input clk;
424
input rst;
425
 
426
wire [1:0] wbm_bte_o;
427
wire [2:0] wbm_cti_o;
428
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
429
reg last_cyc;
430 79 unneback
reg [3:0] counter;
431 82 unneback
reg read_busy;
432 75 unneback
 
433
always @ (posedge clk or posedge rst)
434
if (rst)
435
    last_cyc <= 1'b0;
436
else
437
    last_cyc <= wbm_cyc_o;
438
 
439 79 unneback
always @ (posedge clk or posedge rst)
440
if (rst)
441 82 unneback
    read_busy <= 1'b0;
442 79 unneback
else
443 82 unneback
    if (read & !waitrequest)
444
        read_busy <= 1'b1;
445
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
446
        read_busy <= 1'b0;
447
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
448 81 unneback
 
449 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
450
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
451
                    (wbm_bte_o==2'b10) ? 4'd8 :
452 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
453
                    4'd1;
454 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
455 75 unneback
 
456 79 unneback
always @ (posedge clk or posedge rst)
457
if (rst) begin
458
    counter <= 4'd0;
459
end else
460 80 unneback
    if (wbm_we_o) begin
461
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
462 84 unneback
            counter <= burstcount -4'd1;
463 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
464
            counter <= burstcount;
465
        end else if (!waitrequest & wbm_stb_o) begin
466
            counter <= counter - 4'd1;
467
        end
468 82 unneback
    end
469 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
470 79 unneback
 
471 75 unneback
`define MODULE wb3wb3_bridge
472 77 unneback
`BASE`MODULE wbwb3inst (
473 75 unneback
`undef MODULE
474
    // wishbone slave side
475
    .wbs_dat_i(wbs_dat_i),
476
    .wbs_adr_i(wbs_adr_i),
477
    .wbs_sel_i(wbs_sel_i),
478
    .wbs_bte_i(wbs_bte_i),
479
    .wbs_cti_i(wbs_cti_i),
480
    .wbs_we_i(wbs_we_i),
481
    .wbs_cyc_i(wbs_cyc_i),
482
    .wbs_stb_i(wbs_stb_i),
483
    .wbs_dat_o(wbs_dat_o),
484
    .wbs_ack_o(wbs_ack_o),
485
    .wbs_clk(wbs_clk),
486
    .wbs_rst(wbs_rst),
487
    // wishbone master side
488
    .wbm_dat_o(writedata),
489 78 unneback
    .wbm_adr_o(address),
490 75 unneback
    .wbm_sel_o(be),
491
    .wbm_bte_o(wbm_bte_o),
492
    .wbm_cti_o(wbm_cti_o),
493
    .wbm_we_o(wbm_we_o),
494
    .wbm_cyc_o(wbm_cyc_o),
495
    .wbm_stb_o(wbm_stb_o),
496
    .wbm_dat_i(readdata),
497
    .wbm_ack_i(wbm_ack_i),
498
    .wbm_clk(clk),
499
    .wbm_rst(rst));
500
 
501
 
502
endmodule
503
`endif
504
 
505 40 unneback
`ifdef WB3_ARBITER_TYPE1
506
`define MODULE wb3_arbiter_type1
507 42 unneback
module `BASE`MODULE (
508 40 unneback
`undef MODULE
509 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
510
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
511
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
512
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
513
    wb_clk, wb_rst
514
);
515
 
516
parameter nr_of_ports = 3;
517
parameter adr_size = 26;
518
parameter adr_lo   = 2;
519
parameter dat_size = 32;
520
parameter sel_size = dat_size/8;
521
 
522
localparam aw = (adr_size - adr_lo) * nr_of_ports;
523
localparam dw = dat_size * nr_of_ports;
524
localparam sw = sel_size * nr_of_ports;
525
localparam cw = 3 * nr_of_ports;
526
localparam bw = 2 * nr_of_ports;
527
 
528
input  [dw-1:0] wbm_dat_o;
529
input  [aw-1:0] wbm_adr_o;
530
input  [sw-1:0] wbm_sel_o;
531
input  [cw-1:0] wbm_cti_o;
532
input  [bw-1:0] wbm_bte_o;
533
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
534
output [dw-1:0] wbm_dat_i;
535
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
536
 
537
output [dat_size-1:0] wbs_dat_i;
538
output [adr_size-1:adr_lo] wbs_adr_i;
539
output [sel_size-1:0] wbs_sel_i;
540
output [2:0] wbs_cti_i;
541
output [1:0] wbs_bte_i;
542
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
543
input  [dat_size-1:0] wbs_dat_o;
544
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
545
 
546
input wb_clk, wb_rst;
547
 
548 44 unneback
reg  [nr_of_ports-1:0] select;
549 39 unneback
wire [nr_of_ports-1:0] state;
550
wire [nr_of_ports-1:0] eoc; // end-of-cycle
551
wire [nr_of_ports-1:0] sel;
552
wire idle;
553
 
554
genvar i;
555
 
556
assign idle = !(|state);
557
 
558
generate
559
if (nr_of_ports == 2) begin
560
 
561
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
562
 
563
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
564
 
565 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
566
 
567
    always @ (idle or wbm_cyc_o)
568
    if (idle)
569
        casex (wbm_cyc_o)
570
        2'b1x : select = 2'b10;
571
        2'b01 : select = 2'b01;
572
        default : select = {nr_of_ports{1'b0}};
573
        endcase
574
    else
575
        select = {nr_of_ports{1'b0}};
576
 
577 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
578
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
579
 
580
end
581
endgenerate
582
 
583
generate
584
if (nr_of_ports == 3) begin
585
 
586
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
587
 
588
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
589
 
590 44 unneback
    always @ (idle or wbm_cyc_o)
591
    if (idle)
592
        casex (wbm_cyc_o)
593
        3'b1xx : select = 3'b100;
594
        3'b01x : select = 3'b010;
595
        3'b001 : select = 3'b001;
596
        default : select = {nr_of_ports{1'b0}};
597
        endcase
598
    else
599
        select = {nr_of_ports{1'b0}};
600
 
601
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
602 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
603
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
604
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
605
 
606
end
607
endgenerate
608
 
609
generate
610 44 unneback
if (nr_of_ports == 4) begin
611
 
612
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
613
 
614
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
615
 
616
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
617
 
618
    always @ (idle or wbm_cyc_o)
619
    if (idle)
620
        casex (wbm_cyc_o)
621
        4'b1xxx : select = 4'b1000;
622
        4'b01xx : select = 4'b0100;
623
        4'b001x : select = 4'b0010;
624
        4'b0001 : select = 4'b0001;
625
        default : select = {nr_of_ports{1'b0}};
626
        endcase
627
    else
628
        select = {nr_of_ports{1'b0}};
629
 
630
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
631
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
632
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
633
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
634
 
635
end
636
endgenerate
637
 
638
generate
639
if (nr_of_ports == 5) begin
640
 
641
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
642
 
643
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
644
 
645
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
646
 
647
    always @ (idle or wbm_cyc_o)
648
    if (idle)
649
        casex (wbm_cyc_o)
650
        5'b1xxxx : select = 5'b10000;
651
        5'b01xxx : select = 5'b01000;
652
        5'b001xx : select = 5'b00100;
653
        5'b0001x : select = 5'b00010;
654
        5'b00001 : select = 5'b00001;
655
        default : select = {nr_of_ports{1'b0}};
656
        endcase
657
    else
658
        select = {nr_of_ports{1'b0}};
659
 
660
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
661
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
662
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
663
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
664
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
665
 
666
end
667
endgenerate
668
 
669
generate
670 67 unneback
if (nr_of_ports == 6) begin
671
 
672
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
673
 
674
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
675
 
676
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
677
 
678
    always @ (idle or wbm_cyc_o)
679
    if (idle)
680
        casex (wbm_cyc_o)
681
        6'b1xxxxx : select = 6'b100000;
682
        6'b01xxxx : select = 6'b010000;
683
        6'b001xxx : select = 6'b001000;
684
        6'b0001xx : select = 6'b000100;
685
        6'b00001x : select = 6'b000010;
686
        6'b000001 : select = 6'b000001;
687
        default : select = {nr_of_ports{1'b0}};
688
        endcase
689
    else
690
        select = {nr_of_ports{1'b0}};
691
 
692
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
693
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
694
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
695
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
696
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
697
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
698
 
699
end
700
endgenerate
701
 
702
generate
703
if (nr_of_ports == 7) begin
704
 
705
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
706
 
707
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
708
 
709
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
710
 
711
    always @ (idle or wbm_cyc_o)
712
    if (idle)
713
        casex (wbm_cyc_o)
714
        7'b1xxxxxx : select = 7'b1000000;
715
        7'b01xxxxx : select = 7'b0100000;
716
        7'b001xxxx : select = 7'b0010000;
717
        7'b0001xxx : select = 7'b0001000;
718
        7'b00001xx : select = 7'b0000100;
719
        7'b000001x : select = 7'b0000010;
720
        7'b0000001 : select = 7'b0000001;
721
        default : select = {nr_of_ports{1'b0}};
722
        endcase
723
    else
724
        select = {nr_of_ports{1'b0}};
725
 
726
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
727
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
728
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
729
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
730
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
731
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
732
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
733
 
734
end
735
endgenerate
736
 
737
generate
738
if (nr_of_ports == 8) begin
739
 
740
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
741
 
742
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
743
 
744
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
745
 
746
    always @ (idle or wbm_cyc_o)
747
    if (idle)
748
        casex (wbm_cyc_o)
749
        8'b1xxxxxxx : select = 8'b10000000;
750
        8'b01xxxxxx : select = 8'b01000000;
751
        8'b001xxxxx : select = 8'b00100000;
752
        8'b0001xxxx : select = 8'b00010000;
753
        8'b00001xxx : select = 8'b00001000;
754
        8'b000001xx : select = 8'b00000100;
755
        8'b0000001x : select = 8'b00000010;
756
        8'b00000001 : select = 8'b00000001;
757
        default : select = {nr_of_ports{1'b0}};
758
        endcase
759
    else
760
        select = {nr_of_ports{1'b0}};
761
 
762
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
763
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
764
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
765
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
766
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
767
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
768
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
769
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
770
 
771
end
772
endgenerate
773
 
774
generate
775 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
776 42 unneback
`define MODULE spr
777
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
778
`undef MODULE
779 39 unneback
end
780
endgenerate
781
 
782
    assign sel = select | state;
783
 
784 40 unneback
`define MODULE mux_andor
785
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
786
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
787
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
788
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
789
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
790
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
791
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
792
`undef MODULE
793 39 unneback
    assign wbs_cyc_i = |sel;
794
 
795
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
796
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
797
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
798
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
799
 
800
endmodule
801 40 unneback
`endif
802 39 unneback
 
803 60 unneback
`ifdef WB_B3_RAM_BE
804 49 unneback
// WB RAM with byte enable
805 59 unneback
`define MODULE wb_b3_ram_be
806
module `BASE`MODULE (
807
`undef MODULE
808 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
809
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
810 59 unneback
 
811 68 unneback
parameter adr_size = 16;
812 84 unneback
parameter mem_size = 1<<adr_size;
813 60 unneback
parameter dat_size = 32;
814 83 unneback
parameter max_burst_width = 4;
815 60 unneback
parameter memory_init = 1;
816
parameter memory_file = "vl_ram.vmem";
817 59 unneback
 
818 84 unneback
localparam aw = (adr_size);
819 69 unneback
localparam dw = dat_size;
820
localparam sw = dat_size/8;
821
localparam cw = 3;
822
localparam bw = 2;
823 60 unneback
 
824 70 unneback
input [dw-1:0] wbs_dat_i;
825
input [aw-1:0] wbs_adr_i;
826
input [cw-1:0] wbs_cti_i;
827
input [bw-1:0] wbs_bte_i;
828
input [sw-1:0] wbs_sel_i;
829
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
830
output [dw-1:0] wbs_dat_o;
831
output wbs_ack_o;
832 71 unneback
input wb_clk, wb_rst;
833 59 unneback
 
834 83 unneback
wire [aw-1:0] adr;
835 59 unneback
 
836 60 unneback
`define MODULE ram_be
837
`BASE`MODULE # (
838
    .data_width(dat_size),
839 83 unneback
    .addr_width(aw),
840 69 unneback
    .mem_size(mem_size),
841 68 unneback
    .memory_init(memory_init),
842
    .memory_file(memory_file))
843 60 unneback
ram0(
844
`undef MODULE
845
    .d(wbs_dat_i),
846 83 unneback
    .adr(adr),
847 60 unneback
    .be(wbs_sel_i),
848 86 unneback
    .we(wbs_we_i & wbs_ack_o),
849 60 unneback
    .q(wbs_dat_o),
850
    .clk(wb_clk)
851
);
852
 
853 83 unneback
`define MODULE wb_adr_inc
854
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
855
    .cyc_i(wbs_cyc_i),
856
    .stb_i(wbs_stb_i),
857
    .cti_i(wbs_cti_i),
858
    .bte_i(wbs_bte_i),
859
    .adr_i(wbs_adr_i),
860 84 unneback
    .we_i(wbs_we_i),
861 83 unneback
    .ack_o(wbs_ack_o),
862
    .adr_o(adr),
863
    .clk(wb_clk),
864
    .rst(wb_rst));
865
`undef MODULE
866 60 unneback
 
867 59 unneback
endmodule
868
`endif
869
 
870
`ifdef WB_B4_RAM_BE
871
// WB RAM with byte enable
872 49 unneback
`define MODULE wb_b4_ram_be
873
module `BASE`MODULE (
874
`undef MODULE
875
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
876 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
877 49 unneback
 
878
    parameter dat_width = 32;
879
    parameter adr_width = 8;
880
 
881
input [dat_width-1:0] wb_dat_i;
882
input [adr_width-1:0] wb_adr_i;
883
input [dat_width/8-1:0] wb_sel_i;
884
input wb_we_i, wb_stb_i, wb_cyc_i;
885
output [dat_width-1:0] wb_dat_o;
886 51 unneback
reg [dat_width-1:0] wb_dat_o;
887 52 unneback
output wb_stall_o;
888 49 unneback
output wb_ack_o;
889
reg wb_ack_o;
890
input wb_clk, wb_rst;
891
 
892 56 unneback
wire [dat_width/8-1:0] cke;
893
 
894 49 unneback
generate
895
if (dat_width==32) begin
896 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
897
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
898
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
899
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
900 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
901 49 unneback
    always @ (posedge wb_clk)
902
    begin
903 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
904
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
905
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
906
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
907 49 unneback
    end
908 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
909
    begin
910
        if (wb_rst)
911
            wb_dat_o <= 32'h0;
912
        else
913
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
914
    end
915 49 unneback
end
916
endgenerate
917
 
918 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
919 55 unneback
if (wb_rst)
920 52 unneback
    wb_ack_o <= 1'b0;
921
else
922 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
923 52 unneback
 
924
assign wb_stall_o = 1'b0;
925
 
926 49 unneback
endmodule
927
`endif
928
 
929 48 unneback
`ifdef WB_B4_ROM
930
// WB ROM
931
`define MODULE wb_b4_rom
932
module `BASE`MODULE (
933
`undef MODULE
934
    wb_adr_i, wb_stb_i, wb_cyc_i,
935
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
936
 
937
    parameter dat_width = 32;
938
    parameter dat_default = 32'h15000000;
939
    parameter adr_width = 32;
940
 
941
/*
942
//E2_ifndef ROM
943
//E2_define ROM "rom.v"
944
//E2_endif
945
*/
946
    input [adr_width-1:2]   wb_adr_i;
947
    input                   wb_stb_i;
948
    input                   wb_cyc_i;
949
    output [dat_width-1:0]  wb_dat_o;
950
    reg [dat_width-1:0]     wb_dat_o;
951
    output                  wb_ack_o;
952
    reg                     wb_ack_o;
953
    output                  stall_o;
954
    input                   wb_clk;
955
    input                   wb_rst;
956
 
957
always @ (posedge wb_clk or posedge wb_rst)
958
    if (wb_rst)
959
        wb_dat_o <= {dat_width{1'b0}};
960
    else
961
         case (wb_adr_i[adr_width-1:2])
962
//E2_ifdef ROM
963
//E2_include `ROM
964
//E2_endif
965
           default:
966
             wb_dat_o <= dat_default;
967
 
968
         endcase // case (wb_adr_i)
969
 
970
 
971
always @ (posedge wb_clk or posedge wb_rst)
972
    if (wb_rst)
973
        wb_ack_o <= 1'b0;
974
    else
975
        wb_ack_o <= wb_stb_i & wb_cyc_i;
976
 
977
assign stall_o = 1'b0;
978
 
979
endmodule
980
`endif
981
 
982
 
983 40 unneback
`ifdef WB_BOOT_ROM
984 17 unneback
// WB ROM
985 40 unneback
`define MODULE wb_boot_rom
986
module `BASE`MODULE (
987
`undef MODULE
988 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
989 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
990 17 unneback
 
991 18 unneback
    parameter adr_hi = 31;
992
    parameter adr_lo = 28;
993
    parameter adr_sel = 4'hf;
994
    parameter addr_width = 5;
995 33 unneback
/*
996 17 unneback
//E2_ifndef BOOT_ROM
997
//E2_define BOOT_ROM "boot_rom.v"
998
//E2_endif
999 33 unneback
*/
1000 18 unneback
    input [adr_hi:2]    wb_adr_i;
1001
    input               wb_stb_i;
1002
    input               wb_cyc_i;
1003
    output [31:0]        wb_dat_o;
1004
    output              wb_ack_o;
1005
    output              hit_o;
1006
    input               wb_clk;
1007
    input               wb_rst;
1008
 
1009
    wire hit;
1010
    reg [31:0] wb_dat;
1011
    reg wb_ack;
1012
 
1013
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1014 17 unneback
 
1015
always @ (posedge wb_clk or posedge wb_rst)
1016
    if (wb_rst)
1017 18 unneback
        wb_dat <= 32'h15000000;
1018 17 unneback
    else
1019 18 unneback
         case (wb_adr_i[addr_width-1:2])
1020 33 unneback
//E2_ifdef BOOT_ROM
1021 17 unneback
//E2_include `BOOT_ROM
1022 33 unneback
//E2_endif
1023 17 unneback
           /*
1024
            // Zero r0 and jump to 0x00000100
1025 18 unneback
 
1026
            1 : wb_dat <= 32'hA8200000;
1027
            2 : wb_dat <= 32'hA8C00100;
1028
            3 : wb_dat <= 32'h44003000;
1029
            4 : wb_dat <= 32'h15000000;
1030 17 unneback
            */
1031
           default:
1032 18 unneback
             wb_dat <= 32'h00000000;
1033 17 unneback
 
1034
         endcase // case (wb_adr_i)
1035
 
1036
 
1037
always @ (posedge wb_clk or posedge wb_rst)
1038
    if (wb_rst)
1039 18 unneback
        wb_ack <= 1'b0;
1040 17 unneback
    else
1041 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1042 17 unneback
 
1043 18 unneback
assign hit_o = hit;
1044
assign wb_dat_o = wb_dat & {32{wb_ack}};
1045
assign wb_ack_o = wb_ack;
1046
 
1047 17 unneback
endmodule
1048 40 unneback
`endif
1049 32 unneback
 
1050 92 unneback
`ifdef WB_B3_DPRAM
1051
`define MODULE wb_b3_dpram
1052 40 unneback
module `BASE`MODULE (
1053
`undef MODULE
1054 32 unneback
        // wishbone slave side a
1055 92 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1056 32 unneback
        wbsa_clk, wbsa_rst,
1057 92 unneback
        // wishbone slave side b
1058
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1059 32 unneback
        wbsb_clk, wbsb_rst);
1060
 
1061 92 unneback
parameter data_width_a = 32;
1062
parameter data_width_b = data_width_a;
1063
parameter addr_width_a = 8;
1064
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
1065
   parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
1066
parameter max_burst_width_a = 4;
1067
parameter max_burst_width_b = max_burst_width_a;
1068 32 unneback
 
1069 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
1070
input [addr_width_a-1:0] wbsa_adr_i;
1071
input [data_width_a/8-1:0] wbsa_sel_i;
1072
input [2:0] wbsa_cti_i;
1073
input [1:0] wbsa_bte_i;
1074 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1075 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
1076 32 unneback
output wbsa_ack_o;
1077
input wbsa_clk, wbsa_rst;
1078
 
1079 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
1080
input [addr_width_b-1:0] wbsb_adr_i;
1081
input [data_width_b/8-1:0] wbsb_sel_i;
1082
input [2:0] wbsb_cti_i;
1083
input [1:0] wbsb_bte_i;
1084 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1085 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
1086 32 unneback
output wbsb_ack_o;
1087
input wbsb_clk, wbsb_rst;
1088
 
1089 92 unneback
wire [addr_width_a-1:0] adr_a;
1090
wire [addr_width_b-1:0] adr_b;
1091 32 unneback
 
1092 92 unneback
`define MODULE wb_adr_inc
1093
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
1094
    .cyc_i(wbsa_cyc_i),
1095
    .stb_i(wbsa_stb_i),
1096
    .cti_i(wbsa_cti_i),
1097
    .bte_i(wbsa_bte_i),
1098
    .adr_i(wbsa_adr_i),
1099
    .we_i(wbsa_we_i),
1100
    .ack_o(wbsa_ack_o),
1101
    .adr_o(adr_a),
1102
    .clk(wbsa_clk),
1103
    .rst(wbsa_rst));
1104
 
1105
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
1106
    .cyc_i(wbsb_cyc_i),
1107
    .stb_i(wbsb_stb_i),
1108
    .cti_i(wbsb_cti_i),
1109
    .bte_i(wbsb_bte_i),
1110
    .adr_i(wbsb_adr_i),
1111
    .we_i(wbsb_we_i),
1112
    .ack_o(wbsb_ack_o),
1113
    .adr_o(adr_b),
1114
    .clk(wbsb_clk),
1115
    .rst(wbsb_rst));
1116 40 unneback
`undef MODULE
1117 92 unneback
 
1118
`define MODULE dpram_be_2r2w
1119
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
1120
`undef MODULE
1121
ram_i (
1122 32 unneback
    .d_a(wbsa_dat_i),
1123 92 unneback
    .q_a(wbsa_dat_o),
1124
    .adr_a(adr_a),
1125
    .be_a(wbsa_sel_i),
1126
    .we_a(wbsa_we_i & wbsa_ack_o),
1127 32 unneback
    .clk_a(wbsa_clk),
1128
    .d_b(wbsb_dat_i),
1129 92 unneback
    .q_b(wbsb_dat_o),
1130
    .adr_b(adr_b),
1131
    .be_b(wbsb_sel_i),
1132
    .we_b(wbsb_we_i & wbsb_ack_o),
1133 32 unneback
    .clk_b(wbsb_clk) );
1134
 
1135
endmodule
1136 40 unneback
`endif

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