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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile library, wishbone stuff                           ////

////                                                              ////

////  Description                                                 ////

////  Wishbone compliant modules                                  ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////   -                                                          ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

`ifdef WB_ADR_INC

// async wb3 - wb3 bridge

`timescale 1ns/1ns

`define MODULE wb_adr_inc

module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);

`undef MODULE

parameter adr_width = 10;

parameter max_burst_width = 4;

input cyc_i, stb_i, we_i;

input [2:0] cti_i;

input [1:0] bte_i;

input [adr_width-1:0] adr_i;

output [adr_width-1:0] adr_o;

output ack_o;

input clk, rst;

reg [adr_width-1:0] adr;

wire [max_burst_width-1:0] to_adr;

reg [max_burst_width-1:0] last_adr;

reg last_cycle;

localparam idle_or_eoc = 1'b0;

localparam cyc_or_ws   = 1'b1;

always @ (posedge clk or posedge rst)

if (rst)

    last_adr <= {max_burst_width{1'b0}};

else

    if (stb_i)

        last_adr <=adr_o[max_burst_width-1:0];

generate

if (max_burst_width==0) begin : inst_0

    reg ack_o;

    assign adr_o = adr_i;

    always @ (posedge clk or posedge rst)

    if (rst)

        ack_o <= 1'b0;

    else

        ack_o <= cyc_i & stb_i & !ack_o;

end else begin

    always @ (posedge clk or posedge rst)

    if (rst)

        last_cycle <= idle_or_eoc;

    else

        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle

                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc

                      (cyc_i & !stb_i) ? cyc_or_ws : //ws

                      cyc_or_ws; // cyc

    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];

    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :

                                        (!stb_i) ? last_adr :

                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :

                                        adr[max_burst_width-1:0];

    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;

end

endgenerate

generate

if (max_burst_width==2) begin : inst_2

    always @ (posedge clk or posedge rst)

    if (rst)

        adr <= 2'h0;

    else

        if (cyc_i & stb_i)

            adr[1:0] <= to_adr[1:0] + 2'd1;

        else

            adr <= to_adr[1:0];

end

endgenerate

generate

if (max_burst_width==3) begin : inst_3

    always @ (posedge clk or posedge rst)

    if (rst)

        adr <= 3'h0;

    else

        if (cyc_i & stb_i)

            case (bte_i)

            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};

            default: adr[3:0] <= to_adr[2:0] + 3'd1;

            endcase

        else

            adr <= to_adr[2:0];

end

endgenerate

generate

if (max_burst_width==4) begin : inst_4

    always @ (posedge clk or posedge rst)

    if (rst)

        adr <= 4'h0;

    else

        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once

            case (bte_i)

            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};

            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};

            default: adr[3:0] <= to_adr + 4'd1;

            endcase

        else

            adr <= to_adr[3:0];

end

endgenerate

generate

if (adr_width > max_burst_width) begin : pass_through

    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];

end

endgenerate

endmodule

`endif

`ifdef WB3WB3_BRIDGE

// async wb3 - wb3 bridge

`timescale 1ns/1ns

`define MODULE wb3wb3_bridge

module `BASE`MODULE (

`undef MODULE

        // wishbone slave side

        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,

        // wishbone master side

        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);

input [31:0] wbs_dat_i;

input [31:2] wbs_adr_i;

input [3:0]  wbs_sel_i;

input [1:0]  wbs_bte_i;

input [2:0]  wbs_cti_i;

input wbs_we_i, wbs_cyc_i, wbs_stb_i;

output [31:0] wbs_dat_o;

output wbs_ack_o;

input wbs_clk, wbs_rst;

output [31:0] wbm_dat_o;

output reg [31:2] wbm_adr_o;

output [3:0]  wbm_sel_o;

output reg [1:0]  wbm_bte_o;

output reg [2:0]  wbm_cti_o;

output reg wbm_we_o;

output wbm_cyc_o;

output wbm_stb_o;

input [31:0]  wbm_dat_i;

input wbm_ack_i;

input wbm_clk, wbm_rst;

parameter addr_width = 4;

// bte

parameter linear       = 2'b00;

parameter wrap4        = 2'b01;

parameter wrap8        = 2'b10;

parameter wrap16       = 2'b11;

// cti

parameter classic      = 3'b000;

parameter incburst     = 3'b010;

parameter endofburst   = 3'b111;

parameter wbs_adr  = 1'b0;

parameter wbs_data = 1'b1;

parameter wbm_adr0      = 2'b00;

parameter wbm_adr1      = 2'b01;

parameter wbm_data      = 2'b10;

parameter wbm_data_wait = 2'b11;

reg [1:0] wbs_bte_reg;

reg wbs;

wire wbs_eoc_alert, wbm_eoc_alert;

reg wbs_eoc, wbm_eoc;

reg [1:0] wbm;

wire [1:16] wbs_count, wbm_count;

wire [35:0] a_d, a_q, b_d, b_q;

wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;

reg a_rd_reg;

wire b_rd_adr, b_rd_data;

wire b_rd_data_reg;

wire [35:0] temp;

`define WE 5

`define BTE 4:3

`define CTI 2:0

assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);

always @ (posedge wbs_clk or posedge wbs_rst)

if (wbs_rst)

        wbs_eoc <= 1'b0;

else

        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)

                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);

        else if (wbs_eoc_alert & (a_rd | a_wr))

                wbs_eoc <= 1'b1;

`define MODULE cnt_shreg_ce_clear

`BASE`MODULE # ( .length(16))

`undef MODULE

    cnt0 (

        .cke(wbs_ack_o),

        .clear(wbs_eoc),

        .q(wbs_count),

        .rst(wbs_rst),

        .clk(wbs_clk));

always @ (posedge wbs_clk or posedge wbs_rst)

if (wbs_rst)

        wbs <= wbs_adr;

else

        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)

                wbs <= wbs_data;

        else if (wbs_eoc & wbs_ack_o)

                wbs <= wbs_adr;

// wbs FIFO

assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};

assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :

              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :

              1'b0;

assign a_rd = !a_fifo_empty;

always @ (posedge wbs_clk or posedge wbs_rst)

if (wbs_rst)

        a_rd_reg <= 1'b0;

else

        a_rd_reg <= a_rd;

assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);

assign wbs_dat_o = a_q[35:4];

always @ (posedge wbs_clk or posedge wbs_rst)

if (wbs_rst)

        wbs_bte_reg <= 2'b00;

else

        wbs_bte_reg <= wbs_bte_i;

// wbm FIFO

assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);

always @ (posedge wbm_clk or posedge wbm_rst)

if (wbm_rst)

        wbm_eoc <= 1'b0;

else

        if (wbm==wbm_adr0 & !b_fifo_empty)

                wbm_eoc <= b_q[`BTE] == linear;

        else if (wbm_eoc_alert & wbm_ack_i)

                wbm_eoc <= 1'b1;

always @ (posedge wbm_clk or posedge wbm_rst)

if (wbm_rst)

        wbm <= wbm_adr0;

else

/*

    if ((wbm==wbm_adr0 & !b_fifo_empty) |

        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |

        (wbm==wbm_adr1 & !wbm_we_o) |

        (wbm==wbm_data & wbm_ack_i & wbm_eoc))

        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10

*/

    case (wbm)

    wbm_adr0:

        if (!b_fifo_empty)

            wbm <= wbm_adr1;

    wbm_adr1:

        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))

            wbm <= wbm_data;

    wbm_data:

        if (wbm_ack_i & wbm_eoc)

            wbm <= wbm_adr0;

        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)

            wbm <= wbm_data_wait;

    wbm_data_wait:

        if (!b_fifo_empty)

            wbm <= wbm_data;

    endcase

assign b_d = {wbm_dat_i,4'b1111};

assign b_wr = !wbm_we_o & wbm_ack_i;

assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);

assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]

                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :

                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :

                   1'b0;

assign b_rd = b_rd_adr | b_rd_data;

`define MODULE dff

`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));

`undef MODULE

`define MODULE dff_ce

`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));

`undef MODULE

assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;

`define MODULE cnt_shreg_ce_clear

`BASE`MODULE # ( .length(16))

`undef MODULE

    cnt1 (

        .cke(wbm_ack_i),

        .clear(wbm_eoc),

        .q(wbm_count),

        .rst(wbm_rst),

        .clk(wbm_clk));

assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);

assign wbm_stb_o = (wbm==wbm_data);

always @ (posedge wbm_clk or posedge wbm_rst)

if (wbm_rst)

        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};

else begin

        if (wbm==wbm_adr0 & !b_fifo_empty)

                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;

        else if (wbm_eoc_alert & wbm_ack_i)

                wbm_cti_o <= endofburst;

end

//async_fifo_dw_simplex_top

`define MODULE fifo_2r2w_async_simplex

`BASE`MODULE

`undef MODULE

# ( .data_width(36), .addr_width(addr_width))

fifo (

    // a side

    .a_d(a_d),

    .a_wr(a_wr),

    .a_fifo_full(a_fifo_full),

    .a_q(a_q),

    .a_rd(a_rd),

    .a_fifo_empty(a_fifo_empty),

    .a_clk(wbs_clk),

    .a_rst(wbs_rst),

    // b side

    .b_d(b_d),

    .b_wr(b_wr),

    .b_fifo_full(b_fifo_full),

    .b_q(b_q),

    .b_rd(b_rd),

    .b_fifo_empty(b_fifo_empty),

    .b_clk(wbm_clk),

    .b_rst(wbm_rst)

    );

endmodule

`undef WE

`undef BTE

`undef CTI

`endif

`ifdef WB3AVALON_BRIDGE

`define MODULE wb3avalon_bridge

module `BASE`MODULE (

`undef MODULE

        // wishbone slave side

        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,

        // avalon master side

        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);

parameter linewrapburst = 1'b0;

input [31:0] wbs_dat_i;

input [31:2] wbs_adr_i;

input [3:0]  wbs_sel_i;

input [1:0]  wbs_bte_i;

input [2:0]  wbs_cti_i;

input wbs_we_i;

input wbs_cyc_i;

input wbs_stb_i;

output [31:0] wbs_dat_o;

output wbs_ack_o;

input wbs_clk, wbs_rst;

input [31:0] readdata;

output [31:0] writedata;

output [31:2] address;

output [3:0]  be;

output write;

output read;

output beginbursttransfer;

output [3:0] burstcount;

input readdatavalid;

input waitrequest;

input clk;

input rst;

wire [1:0] wbm_bte_o;

wire [2:0] wbm_cti_o;

wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;

reg last_cyc;

reg [3:0] counter;

reg read_busy;

always @ (posedge clk or posedge rst)

if (rst)

    last_cyc <= 1'b0;

else

    last_cyc <= wbm_cyc_o;

always @ (posedge clk or posedge rst)

if (rst)

    read_busy <= 1'b0;

else

    if (read & !waitrequest)

        read_busy <= 1'b1;

    else if (wbm_ack_i & wbm_cti_o!=3'b010)

        read_busy <= 1'b0;

assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;

assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;

assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :

                    (wbm_bte_o==2'b10) ? 4'd8 :

                    (wbm_bte_o==2'b11) ? 4'd16:

                    4'd1;

assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);

always @ (posedge clk or posedge rst)

if (rst) begin

    counter <= 4'd0;

end else

    if (wbm_we_o) begin

        if (!waitrequest & !last_cyc & wbm_cyc_o) begin

            counter <= burstcount -4'd1;

        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin

            counter <= burstcount;

        end else if (!waitrequest & wbm_stb_o) begin

            counter <= counter - 4'd1;

        end

    end

assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;

`define MODULE wb3wb3_bridge

`BASE`MODULE wbwb3inst (

`undef MODULE

    // wishbone slave side

    .wbs_dat_i(wbs_dat_i),

    .wbs_adr_i(wbs_adr_i),

    .wbs_sel_i(wbs_sel_i),

    .wbs_bte_i(wbs_bte_i),

    .wbs_cti_i(wbs_cti_i),

    .wbs_we_i(wbs_we_i),

    .wbs_cyc_i(wbs_cyc_i),

    .wbs_stb_i(wbs_stb_i),

    .wbs_dat_o(wbs_dat_o),

    .wbs_ack_o(wbs_ack_o),

    .wbs_clk(wbs_clk),

    .wbs_rst(wbs_rst),

    // wishbone master side

    .wbm_dat_o(writedata),

    .wbm_adr_o(address),

    .wbm_sel_o(be),

    .wbm_bte_o(wbm_bte_o),

    .wbm_cti_o(wbm_cti_o),

    .wbm_we_o(wbm_we_o),

    .wbm_cyc_o(wbm_cyc_o),

    .wbm_stb_o(wbm_stb_o),

    .wbm_dat_i(readdata),

    .wbm_ack_i(wbm_ack_i),

    .wbm_clk(clk),

    .wbm_rst(rst));

endmodule

`endif

`ifdef WB3_ARBITER_TYPE1

`define MODULE wb3_arbiter_type1

module `BASE`MODULE (

`undef MODULE

    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,

    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,

    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,

    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,

    wb_clk, wb_rst

);

parameter nr_of_ports = 3;

parameter adr_size = 26;

parameter adr_lo   = 2;

parameter dat_size = 32;

parameter sel_size = dat_size/8;

localparam aw = (adr_size - adr_lo) * nr_of_ports;

localparam dw = dat_size * nr_of_ports;

localparam sw = sel_size * nr_of_ports;

localparam cw = 3 * nr_of_ports;

localparam bw = 2 * nr_of_ports;

input  [dw-1:0] wbm_dat_o;

input  [aw-1:0] wbm_adr_o;

input  [sw-1:0] wbm_sel_o;

input  [cw-1:0] wbm_cti_o;

input  [bw-1:0] wbm_bte_o;

input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;

output [dw-1:0] wbm_dat_i;

output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;

output [dat_size-1:0] wbs_dat_i;

output [adr_size-1:adr_lo] wbs_adr_i;

output [sel_size-1:0] wbs_sel_i;

output [2:0] wbs_cti_i;

output [1:0] wbs_bte_i;

output wbs_we_i, wbs_stb_i, wbs_cyc_i;

input  [dat_size-1:0] wbs_dat_o;

input  wbs_ack_o, wbs_err_o, wbs_rty_o;

input wb_clk, wb_rst;

reg  [nr_of_ports-1:0] select;

wire [nr_of_ports-1:0] state;

wire [nr_of_ports-1:0] eoc; // end-of-cycle

wire [nr_of_ports-1:0] sel;

wire idle;

genvar i;

assign idle = !(|state);

generate

if (nr_of_ports == 2) begin

    wire [2:0] wbm1_cti_o, wbm0_cti_o;

    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;

    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};

    always @ (idle or wbm_cyc_o)

    if (idle)

        casex (wbm_cyc_o)

        2'b1x : select = 2'b10;

        2'b01 : select = 2'b01;

        default : select = {nr_of_ports{1'b0}};

        endcase

    else

        select = {nr_of_ports{1'b0}};

    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];

    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];

end

endgenerate

generate

if (nr_of_ports == 3) begin

    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;

    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;