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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46
`define MODULE wb_adr_inc
47 84 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
48 75 unneback
`undef MODULE
49 83 unneback
parameter adr_width = 10;
50
parameter max_burst_width = 4;
51 84 unneback
input cyc_i, stb_i, we_i;
52 83 unneback
input [2:0] cti_i;
53
input [1:0] bte_i;
54
input [adr_width-1:0] adr_i;
55
output [adr_width-1:0] adr_o;
56
output ack_o;
57
input clk, rst;
58 75 unneback
 
59 83 unneback
reg [adr_width-1:0] adr;
60 90 unneback
wire [max_burst_width-1:0] to_adr;
61 91 unneback
reg [max_burst_width-1:0] last_adr;
62 92 unneback
reg last_cycle;
63
localparam idle_or_eoc = 1'b0;
64
localparam cyc_or_ws   = 1'b1;
65 90 unneback
 
66 91 unneback
always @ (posedge clk or posedge rst)
67
if (rst)
68
    last_adr <= {max_burst_width{1'b0}};
69
else
70
    if (stb_i)
71 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
72 91 unneback
 
73 83 unneback
generate
74
if (max_burst_width==0) begin : inst_0
75
    reg ack_o;
76
    assign adr_o = adr_i;
77 75 unneback
    always @ (posedge clk or posedge rst)
78 83 unneback
    if (rst)
79
        ack_o <= 1'b0;
80
    else
81
        ack_o <= cyc_i & stb_i & !ack_o;
82
end else begin
83
 
84
    always @ (posedge clk or posedge rst)
85
    if (rst)
86 92 unneback
        last_cycle <= idle_or_eoc;
87 83 unneback
    else
88 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
89
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
90
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
91
                      cyc_or_ws; // cyc
92
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
93 84 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
94 91 unneback
                                        (!stb_i) ? last_adr :
95 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
96 84 unneback
                                        adr[max_burst_width-1:0];
97 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
98 83 unneback
end
99
endgenerate
100
 
101
generate
102
if (max_burst_width==2) begin : inst_2
103
    always @ (posedge clk or posedge rst)
104
    if (rst)
105
        adr <= 2'h0;
106
    else
107
        if (cyc_i & stb_i)
108
            adr[1:0] <= to_adr[1:0] + 2'd1;
109 75 unneback
        else
110 83 unneback
            adr <= to_adr[1:0];
111
end
112
endgenerate
113
 
114
generate
115
if (max_burst_width==3) begin : inst_3
116
    always @ (posedge clk or posedge rst)
117
    if (rst)
118
        adr <= 3'h0;
119
    else
120
        if (cyc_i & stb_i)
121
            case (bte_i)
122
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
123
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
124 75 unneback
            endcase
125 83 unneback
        else
126
            adr <= to_adr[2:0];
127
end
128
endgenerate
129
 
130
generate
131
if (max_burst_width==4) begin : inst_4
132
    always @ (posedge clk or posedge rst)
133
    if (rst)
134
        adr <= 4'h0;
135
    else
136 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
137 83 unneback
            case (bte_i)
138
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
139
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
140
            default: adr[3:0] <= to_adr + 4'd1;
141
            endcase
142
        else
143
            adr <= to_adr[3:0];
144
end
145
endgenerate
146
 
147
generate
148
if (adr_width > max_burst_width) begin : pass_through
149
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
150
end
151
endgenerate
152
 
153
endmodule
154 75 unneback
`endif
155
 
156 40 unneback
`ifdef WB3WB3_BRIDGE
157 12 unneback
// async wb3 - wb3 bridge
158
`timescale 1ns/1ns
159 40 unneback
`define MODULE wb3wb3_bridge
160
module `BASE`MODULE (
161
`undef MODULE
162 12 unneback
        // wishbone slave side
163
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
164
        // wishbone master side
165
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
166
 
167 94 unneback
parameter style = "FIFO"; // valid: simple, FIFO
168
parameter addr_width = 4;
169
 
170 12 unneback
input [31:0] wbs_dat_i;
171
input [31:2] wbs_adr_i;
172
input [3:0]  wbs_sel_i;
173
input [1:0]  wbs_bte_i;
174
input [2:0]  wbs_cti_i;
175
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
176
output [31:0] wbs_dat_o;
177 14 unneback
output wbs_ack_o;
178 12 unneback
input wbs_clk, wbs_rst;
179
 
180
output [31:0] wbm_dat_o;
181
output reg [31:2] wbm_adr_o;
182
output [3:0]  wbm_sel_o;
183
output reg [1:0]  wbm_bte_o;
184
output reg [2:0]  wbm_cti_o;
185 14 unneback
output reg wbm_we_o;
186
output wbm_cyc_o;
187 12 unneback
output wbm_stb_o;
188
input [31:0]  wbm_dat_i;
189
input wbm_ack_i;
190
input wbm_clk, wbm_rst;
191
 
192
// bte
193
parameter linear       = 2'b00;
194
parameter wrap4        = 2'b01;
195
parameter wrap8        = 2'b10;
196
parameter wrap16       = 2'b11;
197
// cti
198
parameter classic      = 3'b000;
199
parameter incburst     = 3'b010;
200
parameter endofburst   = 3'b111;
201
 
202 94 unneback
localparam wbs_adr  = 1'b0;
203
localparam wbs_data = 1'b1;
204 12 unneback
 
205 94 unneback
localparam wbm_adr0      = 2'b00;
206
localparam wbm_adr1      = 2'b01;
207
localparam wbm_data      = 2'b10;
208
localparam wbm_data_wait = 2'b11;
209 12 unneback
 
210
reg [1:0] wbs_bte_reg;
211
reg wbs;
212
wire wbs_eoc_alert, wbm_eoc_alert;
213
reg wbs_eoc, wbm_eoc;
214
reg [1:0] wbm;
215
 
216 14 unneback
wire [1:16] wbs_count, wbm_count;
217 12 unneback
 
218
wire [35:0] a_d, a_q, b_d, b_q;
219
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
220
reg a_rd_reg;
221
wire b_rd_adr, b_rd_data;
222 14 unneback
wire b_rd_data_reg;
223
wire [35:0] temp;
224 12 unneback
 
225
`define WE 5
226
`define BTE 4:3
227
`define CTI 2:0
228
 
229
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
230
always @ (posedge wbs_clk or posedge wbs_rst)
231
if (wbs_rst)
232
        wbs_eoc <= 1'b0;
233
else
234
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
235 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
236 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
237
                wbs_eoc <= 1'b1;
238
 
239 40 unneback
`define MODULE cnt_shreg_ce_clear
240
`BASE`MODULE # ( .length(16))
241
`undef MODULE
242 12 unneback
    cnt0 (
243
        .cke(wbs_ack_o),
244
        .clear(wbs_eoc),
245
        .q(wbs_count),
246
        .rst(wbs_rst),
247
        .clk(wbs_clk));
248
 
249
always @ (posedge wbs_clk or posedge wbs_rst)
250
if (wbs_rst)
251
        wbs <= wbs_adr;
252
else
253 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
254 12 unneback
                wbs <= wbs_data;
255
        else if (wbs_eoc & wbs_ack_o)
256
                wbs <= wbs_adr;
257
 
258
// wbs FIFO
259 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
260
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
261 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
262
              1'b0;
263
assign a_rd = !a_fifo_empty;
264
always @ (posedge wbs_clk or posedge wbs_rst)
265
if (wbs_rst)
266
        a_rd_reg <= 1'b0;
267
else
268
        a_rd_reg <= a_rd;
269
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
270
 
271
assign wbs_dat_o = a_q[35:4];
272
 
273
always @ (posedge wbs_clk or posedge wbs_rst)
274
if (wbs_rst)
275 13 unneback
        wbs_bte_reg <= 2'b00;
276 12 unneback
else
277 13 unneback
        wbs_bte_reg <= wbs_bte_i;
278 12 unneback
 
279
// wbm FIFO
280
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
281
always @ (posedge wbm_clk or posedge wbm_rst)
282
if (wbm_rst)
283
        wbm_eoc <= 1'b0;
284
else
285
        if (wbm==wbm_adr0 & !b_fifo_empty)
286
                wbm_eoc <= b_q[`BTE] == linear;
287
        else if (wbm_eoc_alert & wbm_ack_i)
288
                wbm_eoc <= 1'b1;
289
 
290
always @ (posedge wbm_clk or posedge wbm_rst)
291
if (wbm_rst)
292
        wbm <= wbm_adr0;
293
else
294 33 unneback
/*
295 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
296
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
297
        (wbm==wbm_adr1 & !wbm_we_o) |
298
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
299
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
300 33 unneback
*/
301
    case (wbm)
302
    wbm_adr0:
303
        if (!b_fifo_empty)
304
            wbm <= wbm_adr1;
305
    wbm_adr1:
306
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
307
            wbm <= wbm_data;
308
    wbm_data:
309
        if (wbm_ack_i & wbm_eoc)
310
            wbm <= wbm_adr0;
311
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
312
            wbm <= wbm_data_wait;
313
    wbm_data_wait:
314
        if (!b_fifo_empty)
315
            wbm <= wbm_data;
316
    endcase
317 12 unneback
 
318
assign b_d = {wbm_dat_i,4'b1111};
319
assign b_wr = !wbm_we_o & wbm_ack_i;
320
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
321
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
322
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
323 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
324 12 unneback
                   1'b0;
325
assign b_rd = b_rd_adr | b_rd_data;
326
 
327 40 unneback
`define MODULE dff
328
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
329
`undef MODULE
330
`define MODULE dff_ce
331
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
332
`undef MODULE
333 12 unneback
 
334
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
335
 
336 40 unneback
`define MODULE cnt_shreg_ce_clear
337 42 unneback
`BASE`MODULE # ( .length(16))
338 40 unneback
`undef MODULE
339 12 unneback
    cnt1 (
340
        .cke(wbm_ack_i),
341
        .clear(wbm_eoc),
342
        .q(wbm_count),
343
        .rst(wbm_rst),
344
        .clk(wbm_clk));
345
 
346 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
347
assign wbm_stb_o = (wbm==wbm_data);
348 12 unneback
 
349
always @ (posedge wbm_clk or posedge wbm_rst)
350
if (wbm_rst)
351
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
352
else begin
353
        if (wbm==wbm_adr0 & !b_fifo_empty)
354
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
355
        else if (wbm_eoc_alert & wbm_ack_i)
356
                wbm_cti_o <= endofburst;
357
end
358
 
359
//async_fifo_dw_simplex_top
360 40 unneback
`define MODULE fifo_2r2w_async_simplex
361
`BASE`MODULE
362
`undef MODULE
363 12 unneback
# ( .data_width(36), .addr_width(addr_width))
364
fifo (
365
    // a side
366
    .a_d(a_d),
367
    .a_wr(a_wr),
368
    .a_fifo_full(a_fifo_full),
369
    .a_q(a_q),
370
    .a_rd(a_rd),
371
    .a_fifo_empty(a_fifo_empty),
372
    .a_clk(wbs_clk),
373
    .a_rst(wbs_rst),
374
    // b side
375
    .b_d(b_d),
376
    .b_wr(b_wr),
377
    .b_fifo_full(b_fifo_full),
378
    .b_q(b_q),
379
    .b_rd(b_rd),
380
    .b_fifo_empty(b_fifo_empty),
381
    .b_clk(wbm_clk),
382
    .b_rst(wbm_rst)
383
    );
384
 
385
endmodule
386 40 unneback
`undef WE
387
`undef BTE
388
`undef CTI
389
`endif
390 17 unneback
 
391 75 unneback
`ifdef WB3AVALON_BRIDGE
392
`define MODULE wb3avalon_bridge
393
module `BASE`MODULE (
394
`undef MODULE
395
        // wishbone slave side
396
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
397 77 unneback
        // avalon master side
398 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
399
 
400 84 unneback
parameter linewrapburst = 1'b0;
401
 
402 75 unneback
input [31:0] wbs_dat_i;
403
input [31:2] wbs_adr_i;
404
input [3:0]  wbs_sel_i;
405
input [1:0]  wbs_bte_i;
406
input [2:0]  wbs_cti_i;
407 83 unneback
input wbs_we_i;
408
input wbs_cyc_i;
409
input wbs_stb_i;
410 75 unneback
output [31:0] wbs_dat_o;
411
output wbs_ack_o;
412
input wbs_clk, wbs_rst;
413
 
414
input [31:0] readdata;
415
output [31:0] writedata;
416
output [31:2] address;
417
output [3:0]  be;
418
output write;
419 81 unneback
output read;
420 75 unneback
output beginbursttransfer;
421
output [3:0] burstcount;
422
input readdatavalid;
423
input waitrequest;
424
input clk;
425
input rst;
426
 
427
wire [1:0] wbm_bte_o;
428
wire [2:0] wbm_cti_o;
429
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
430
reg last_cyc;
431 79 unneback
reg [3:0] counter;
432 82 unneback
reg read_busy;
433 75 unneback
 
434
always @ (posedge clk or posedge rst)
435
if (rst)
436
    last_cyc <= 1'b0;
437
else
438
    last_cyc <= wbm_cyc_o;
439
 
440 79 unneback
always @ (posedge clk or posedge rst)
441
if (rst)
442 82 unneback
    read_busy <= 1'b0;
443 79 unneback
else
444 82 unneback
    if (read & !waitrequest)
445
        read_busy <= 1'b1;
446
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
447
        read_busy <= 1'b0;
448
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
449 81 unneback
 
450 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
451
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
452
                    (wbm_bte_o==2'b10) ? 4'd8 :
453 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
454
                    4'd1;
455 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
456 75 unneback
 
457 79 unneback
always @ (posedge clk or posedge rst)
458
if (rst) begin
459
    counter <= 4'd0;
460
end else
461 80 unneback
    if (wbm_we_o) begin
462
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
463 84 unneback
            counter <= burstcount -4'd1;
464 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
465
            counter <= burstcount;
466
        end else if (!waitrequest & wbm_stb_o) begin
467
            counter <= counter - 4'd1;
468
        end
469 82 unneback
    end
470 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
471 79 unneback
 
472 75 unneback
`define MODULE wb3wb3_bridge
473 77 unneback
`BASE`MODULE wbwb3inst (
474 75 unneback
`undef MODULE
475
    // wishbone slave side
476
    .wbs_dat_i(wbs_dat_i),
477
    .wbs_adr_i(wbs_adr_i),
478
    .wbs_sel_i(wbs_sel_i),
479
    .wbs_bte_i(wbs_bte_i),
480
    .wbs_cti_i(wbs_cti_i),
481
    .wbs_we_i(wbs_we_i),
482
    .wbs_cyc_i(wbs_cyc_i),
483
    .wbs_stb_i(wbs_stb_i),
484
    .wbs_dat_o(wbs_dat_o),
485
    .wbs_ack_o(wbs_ack_o),
486
    .wbs_clk(wbs_clk),
487
    .wbs_rst(wbs_rst),
488
    // wishbone master side
489
    .wbm_dat_o(writedata),
490 78 unneback
    .wbm_adr_o(address),
491 75 unneback
    .wbm_sel_o(be),
492
    .wbm_bte_o(wbm_bte_o),
493
    .wbm_cti_o(wbm_cti_o),
494
    .wbm_we_o(wbm_we_o),
495
    .wbm_cyc_o(wbm_cyc_o),
496
    .wbm_stb_o(wbm_stb_o),
497
    .wbm_dat_i(readdata),
498
    .wbm_ack_i(wbm_ack_i),
499
    .wbm_clk(clk),
500
    .wbm_rst(rst));
501
 
502
 
503
endmodule
504
`endif
505
 
506 40 unneback
`ifdef WB3_ARBITER_TYPE1
507
`define MODULE wb3_arbiter_type1
508 42 unneback
module `BASE`MODULE (
509 40 unneback
`undef MODULE
510 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
511
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
512
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
513
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
514
    wb_clk, wb_rst
515
);
516
 
517
parameter nr_of_ports = 3;
518
parameter adr_size = 26;
519
parameter adr_lo   = 2;
520
parameter dat_size = 32;
521
parameter sel_size = dat_size/8;
522
 
523
localparam aw = (adr_size - adr_lo) * nr_of_ports;
524
localparam dw = dat_size * nr_of_ports;
525
localparam sw = sel_size * nr_of_ports;
526
localparam cw = 3 * nr_of_ports;
527
localparam bw = 2 * nr_of_ports;
528
 
529
input  [dw-1:0] wbm_dat_o;
530
input  [aw-1:0] wbm_adr_o;
531
input  [sw-1:0] wbm_sel_o;
532
input  [cw-1:0] wbm_cti_o;
533
input  [bw-1:0] wbm_bte_o;
534
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
535
output [dw-1:0] wbm_dat_i;
536
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
537
 
538
output [dat_size-1:0] wbs_dat_i;
539
output [adr_size-1:adr_lo] wbs_adr_i;
540
output [sel_size-1:0] wbs_sel_i;
541
output [2:0] wbs_cti_i;
542
output [1:0] wbs_bte_i;
543
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
544
input  [dat_size-1:0] wbs_dat_o;
545
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
546
 
547
input wb_clk, wb_rst;
548
 
549 44 unneback
reg  [nr_of_ports-1:0] select;
550 39 unneback
wire [nr_of_ports-1:0] state;
551
wire [nr_of_ports-1:0] eoc; // end-of-cycle
552
wire [nr_of_ports-1:0] sel;
553
wire idle;
554
 
555
genvar i;
556
 
557
assign idle = !(|state);
558
 
559
generate
560
if (nr_of_ports == 2) begin
561
 
562
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
563
 
564
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
565
 
566 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
567
 
568
    always @ (idle or wbm_cyc_o)
569
    if (idle)
570
        casex (wbm_cyc_o)
571
        2'b1x : select = 2'b10;
572
        2'b01 : select = 2'b01;
573
        default : select = {nr_of_ports{1'b0}};
574
        endcase
575
    else
576
        select = {nr_of_ports{1'b0}};
577
 
578 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
579
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
580
 
581
end
582
endgenerate
583
 
584
generate
585
if (nr_of_ports == 3) begin
586
 
587
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
588
 
589
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
590
 
591 44 unneback
    always @ (idle or wbm_cyc_o)
592
    if (idle)
593
        casex (wbm_cyc_o)
594
        3'b1xx : select = 3'b100;
595
        3'b01x : select = 3'b010;
596
        3'b001 : select = 3'b001;
597
        default : select = {nr_of_ports{1'b0}};
598
        endcase
599
    else
600
        select = {nr_of_ports{1'b0}};
601
 
602
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
603 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
604
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
605
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
606
 
607
end
608
endgenerate
609
 
610
generate
611 44 unneback
if (nr_of_ports == 4) begin
612
 
613
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
614
 
615
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
616
 
617
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
618
 
619
    always @ (idle or wbm_cyc_o)
620
    if (idle)
621
        casex (wbm_cyc_o)
622
        4'b1xxx : select = 4'b1000;
623
        4'b01xx : select = 4'b0100;
624
        4'b001x : select = 4'b0010;
625
        4'b0001 : select = 4'b0001;
626
        default : select = {nr_of_ports{1'b0}};
627
        endcase
628
    else
629
        select = {nr_of_ports{1'b0}};
630
 
631
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
632
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
633
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
634
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
635
 
636
end
637
endgenerate
638
 
639
generate
640
if (nr_of_ports == 5) begin
641
 
642
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
643
 
644
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
645
 
646
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
647
 
648
    always @ (idle or wbm_cyc_o)
649
    if (idle)
650
        casex (wbm_cyc_o)
651
        5'b1xxxx : select = 5'b10000;
652
        5'b01xxx : select = 5'b01000;
653
        5'b001xx : select = 5'b00100;
654
        5'b0001x : select = 5'b00010;
655
        5'b00001 : select = 5'b00001;
656
        default : select = {nr_of_ports{1'b0}};
657
        endcase
658
    else
659
        select = {nr_of_ports{1'b0}};
660
 
661
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
662
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
663
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
664
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
665
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
666
 
667
end
668
endgenerate
669
 
670
generate
671 67 unneback
if (nr_of_ports == 6) begin
672
 
673
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
674
 
675
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
676
 
677
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
678
 
679
    always @ (idle or wbm_cyc_o)
680
    if (idle)
681
        casex (wbm_cyc_o)
682
        6'b1xxxxx : select = 6'b100000;
683
        6'b01xxxx : select = 6'b010000;
684
        6'b001xxx : select = 6'b001000;
685
        6'b0001xx : select = 6'b000100;
686
        6'b00001x : select = 6'b000010;
687
        6'b000001 : select = 6'b000001;
688
        default : select = {nr_of_ports{1'b0}};
689
        endcase
690
    else
691
        select = {nr_of_ports{1'b0}};
692
 
693
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
694
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
695
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
696
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
697
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
698
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
699
 
700
end
701
endgenerate
702
 
703
generate
704
if (nr_of_ports == 7) begin
705
 
706
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
707
 
708
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
709
 
710
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
711
 
712
    always @ (idle or wbm_cyc_o)
713
    if (idle)
714
        casex (wbm_cyc_o)
715
        7'b1xxxxxx : select = 7'b1000000;
716
        7'b01xxxxx : select = 7'b0100000;
717
        7'b001xxxx : select = 7'b0010000;
718
        7'b0001xxx : select = 7'b0001000;
719
        7'b00001xx : select = 7'b0000100;
720
        7'b000001x : select = 7'b0000010;
721
        7'b0000001 : select = 7'b0000001;
722
        default : select = {nr_of_ports{1'b0}};
723
        endcase
724
    else
725
        select = {nr_of_ports{1'b0}};
726
 
727
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
728
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
729
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
730
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
731
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
732
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
733
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
734
 
735
end
736
endgenerate
737
 
738
generate
739
if (nr_of_ports == 8) begin
740
 
741
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
742
 
743
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
744
 
745
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
746
 
747
    always @ (idle or wbm_cyc_o)
748
    if (idle)
749
        casex (wbm_cyc_o)
750
        8'b1xxxxxxx : select = 8'b10000000;
751
        8'b01xxxxxx : select = 8'b01000000;
752
        8'b001xxxxx : select = 8'b00100000;
753
        8'b0001xxxx : select = 8'b00010000;
754
        8'b00001xxx : select = 8'b00001000;
755
        8'b000001xx : select = 8'b00000100;
756
        8'b0000001x : select = 8'b00000010;
757
        8'b00000001 : select = 8'b00000001;
758
        default : select = {nr_of_ports{1'b0}};
759
        endcase
760
    else
761
        select = {nr_of_ports{1'b0}};
762
 
763
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
764
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
765
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
766
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
767
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
768
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
769
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
770
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
771
 
772
end
773
endgenerate
774
 
775
generate
776 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
777 42 unneback
`define MODULE spr
778
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
779
`undef MODULE
780 39 unneback
end
781
endgenerate
782
 
783
    assign sel = select | state;
784
 
785 40 unneback
`define MODULE mux_andor
786
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
787
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
788
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
789
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
790
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
791
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
792
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
793
`undef MODULE
794 39 unneback
    assign wbs_cyc_i = |sel;
795
 
796
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
797
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
798
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
799
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
800
 
801
endmodule
802 40 unneback
`endif
803 39 unneback
 
804 60 unneback
`ifdef WB_B3_RAM_BE
805 49 unneback
// WB RAM with byte enable
806 59 unneback
`define MODULE wb_b3_ram_be
807
module `BASE`MODULE (
808
`undef MODULE
809 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
810
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
811 59 unneback
 
812 68 unneback
parameter adr_size = 16;
813 84 unneback
parameter mem_size = 1<<adr_size;
814 60 unneback
parameter dat_size = 32;
815 83 unneback
parameter max_burst_width = 4;
816 60 unneback
parameter memory_init = 1;
817
parameter memory_file = "vl_ram.vmem";
818 59 unneback
 
819 84 unneback
localparam aw = (adr_size);
820 69 unneback
localparam dw = dat_size;
821
localparam sw = dat_size/8;
822
localparam cw = 3;
823
localparam bw = 2;
824 60 unneback
 
825 70 unneback
input [dw-1:0] wbs_dat_i;
826
input [aw-1:0] wbs_adr_i;
827
input [cw-1:0] wbs_cti_i;
828
input [bw-1:0] wbs_bte_i;
829
input [sw-1:0] wbs_sel_i;
830
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
831
output [dw-1:0] wbs_dat_o;
832
output wbs_ack_o;
833 71 unneback
input wb_clk, wb_rst;
834 59 unneback
 
835 83 unneback
wire [aw-1:0] adr;
836 59 unneback
 
837 60 unneback
`define MODULE ram_be
838
`BASE`MODULE # (
839
    .data_width(dat_size),
840 83 unneback
    .addr_width(aw),
841 69 unneback
    .mem_size(mem_size),
842 68 unneback
    .memory_init(memory_init),
843
    .memory_file(memory_file))
844 60 unneback
ram0(
845
`undef MODULE
846
    .d(wbs_dat_i),
847 83 unneback
    .adr(adr),
848 60 unneback
    .be(wbs_sel_i),
849 86 unneback
    .we(wbs_we_i & wbs_ack_o),
850 60 unneback
    .q(wbs_dat_o),
851
    .clk(wb_clk)
852
);
853
 
854 83 unneback
`define MODULE wb_adr_inc
855
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
856
    .cyc_i(wbs_cyc_i),
857
    .stb_i(wbs_stb_i),
858
    .cti_i(wbs_cti_i),
859
    .bte_i(wbs_bte_i),
860
    .adr_i(wbs_adr_i),
861 84 unneback
    .we_i(wbs_we_i),
862 83 unneback
    .ack_o(wbs_ack_o),
863
    .adr_o(adr),
864
    .clk(wb_clk),
865
    .rst(wb_rst));
866
`undef MODULE
867 60 unneback
 
868 59 unneback
endmodule
869
`endif
870
 
871
`ifdef WB_B4_RAM_BE
872
// WB RAM with byte enable
873 49 unneback
`define MODULE wb_b4_ram_be
874
module `BASE`MODULE (
875
`undef MODULE
876
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
877 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
878 49 unneback
 
879
    parameter dat_width = 32;
880
    parameter adr_width = 8;
881
 
882
input [dat_width-1:0] wb_dat_i;
883
input [adr_width-1:0] wb_adr_i;
884
input [dat_width/8-1:0] wb_sel_i;
885
input wb_we_i, wb_stb_i, wb_cyc_i;
886
output [dat_width-1:0] wb_dat_o;
887 51 unneback
reg [dat_width-1:0] wb_dat_o;
888 52 unneback
output wb_stall_o;
889 49 unneback
output wb_ack_o;
890
reg wb_ack_o;
891
input wb_clk, wb_rst;
892
 
893 56 unneback
wire [dat_width/8-1:0] cke;
894
 
895 49 unneback
generate
896
if (dat_width==32) begin
897 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
898
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
899
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
900
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
901 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
902 49 unneback
    always @ (posedge wb_clk)
903
    begin
904 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
905
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
906
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
907
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
908 49 unneback
    end
909 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
910
    begin
911
        if (wb_rst)
912
            wb_dat_o <= 32'h0;
913
        else
914
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
915
    end
916 49 unneback
end
917
endgenerate
918
 
919 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
920 55 unneback
if (wb_rst)
921 52 unneback
    wb_ack_o <= 1'b0;
922
else
923 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
924 52 unneback
 
925
assign wb_stall_o = 1'b0;
926
 
927 49 unneback
endmodule
928
`endif
929
 
930 48 unneback
`ifdef WB_B4_ROM
931
// WB ROM
932
`define MODULE wb_b4_rom
933
module `BASE`MODULE (
934
`undef MODULE
935
    wb_adr_i, wb_stb_i, wb_cyc_i,
936
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
937
 
938
    parameter dat_width = 32;
939
    parameter dat_default = 32'h15000000;
940
    parameter adr_width = 32;
941
 
942
/*
943
//E2_ifndef ROM
944
//E2_define ROM "rom.v"
945
//E2_endif
946
*/
947
    input [adr_width-1:2]   wb_adr_i;
948
    input                   wb_stb_i;
949
    input                   wb_cyc_i;
950
    output [dat_width-1:0]  wb_dat_o;
951
    reg [dat_width-1:0]     wb_dat_o;
952
    output                  wb_ack_o;
953
    reg                     wb_ack_o;
954
    output                  stall_o;
955
    input                   wb_clk;
956
    input                   wb_rst;
957
 
958
always @ (posedge wb_clk or posedge wb_rst)
959
    if (wb_rst)
960
        wb_dat_o <= {dat_width{1'b0}};
961
    else
962
         case (wb_adr_i[adr_width-1:2])
963
//E2_ifdef ROM
964
//E2_include `ROM
965
//E2_endif
966
           default:
967
             wb_dat_o <= dat_default;
968
 
969
         endcase // case (wb_adr_i)
970
 
971
 
972
always @ (posedge wb_clk or posedge wb_rst)
973
    if (wb_rst)
974
        wb_ack_o <= 1'b0;
975
    else
976
        wb_ack_o <= wb_stb_i & wb_cyc_i;
977
 
978
assign stall_o = 1'b0;
979
 
980
endmodule
981
`endif
982
 
983
 
984 40 unneback
`ifdef WB_BOOT_ROM
985 17 unneback
// WB ROM
986 40 unneback
`define MODULE wb_boot_rom
987
module `BASE`MODULE (
988
`undef MODULE
989 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
990 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
991 17 unneback
 
992 18 unneback
    parameter adr_hi = 31;
993
    parameter adr_lo = 28;
994
    parameter adr_sel = 4'hf;
995
    parameter addr_width = 5;
996 33 unneback
/*
997 17 unneback
//E2_ifndef BOOT_ROM
998
//E2_define BOOT_ROM "boot_rom.v"
999
//E2_endif
1000 33 unneback
*/
1001 18 unneback
    input [adr_hi:2]    wb_adr_i;
1002
    input               wb_stb_i;
1003
    input               wb_cyc_i;
1004
    output [31:0]        wb_dat_o;
1005
    output              wb_ack_o;
1006
    output              hit_o;
1007
    input               wb_clk;
1008
    input               wb_rst;
1009
 
1010
    wire hit;
1011
    reg [31:0] wb_dat;
1012
    reg wb_ack;
1013
 
1014
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1015 17 unneback
 
1016
always @ (posedge wb_clk or posedge wb_rst)
1017
    if (wb_rst)
1018 18 unneback
        wb_dat <= 32'h15000000;
1019 17 unneback
    else
1020 18 unneback
         case (wb_adr_i[addr_width-1:2])
1021 33 unneback
//E2_ifdef BOOT_ROM
1022 17 unneback
//E2_include `BOOT_ROM
1023 33 unneback
//E2_endif
1024 17 unneback
           /*
1025
            // Zero r0 and jump to 0x00000100
1026 18 unneback
 
1027
            1 : wb_dat <= 32'hA8200000;
1028
            2 : wb_dat <= 32'hA8C00100;
1029
            3 : wb_dat <= 32'h44003000;
1030
            4 : wb_dat <= 32'h15000000;
1031 17 unneback
            */
1032
           default:
1033 18 unneback
             wb_dat <= 32'h00000000;
1034 17 unneback
 
1035
         endcase // case (wb_adr_i)
1036
 
1037
 
1038
always @ (posedge wb_clk or posedge wb_rst)
1039
    if (wb_rst)
1040 18 unneback
        wb_ack <= 1'b0;
1041 17 unneback
    else
1042 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1043 17 unneback
 
1044 18 unneback
assign hit_o = hit;
1045
assign wb_dat_o = wb_dat & {32{wb_ack}};
1046
assign wb_ack_o = wb_ack;
1047
 
1048 17 unneback
endmodule
1049 40 unneback
`endif
1050 32 unneback
 
1051 92 unneback
`ifdef WB_B3_DPRAM
1052
`define MODULE wb_b3_dpram
1053 40 unneback
module `BASE`MODULE (
1054
`undef MODULE
1055 32 unneback
        // wishbone slave side a
1056 92 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1057 32 unneback
        wbsa_clk, wbsa_rst,
1058 92 unneback
        // wishbone slave side b
1059
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1060 32 unneback
        wbsb_clk, wbsb_rst);
1061
 
1062 92 unneback
parameter data_width_a = 32;
1063
parameter data_width_b = data_width_a;
1064
parameter addr_width_a = 8;
1065
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
1066
   parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
1067
parameter max_burst_width_a = 4;
1068
parameter max_burst_width_b = max_burst_width_a;
1069 32 unneback
 
1070 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
1071
input [addr_width_a-1:0] wbsa_adr_i;
1072
input [data_width_a/8-1:0] wbsa_sel_i;
1073
input [2:0] wbsa_cti_i;
1074
input [1:0] wbsa_bte_i;
1075 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1076 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
1077 32 unneback
output wbsa_ack_o;
1078
input wbsa_clk, wbsa_rst;
1079
 
1080 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
1081
input [addr_width_b-1:0] wbsb_adr_i;
1082
input [data_width_b/8-1:0] wbsb_sel_i;
1083
input [2:0] wbsb_cti_i;
1084
input [1:0] wbsb_bte_i;
1085 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1086 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
1087 32 unneback
output wbsb_ack_o;
1088
input wbsb_clk, wbsb_rst;
1089
 
1090 92 unneback
wire [addr_width_a-1:0] adr_a;
1091
wire [addr_width_b-1:0] adr_b;
1092 32 unneback
 
1093 92 unneback
`define MODULE wb_adr_inc
1094
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
1095
    .cyc_i(wbsa_cyc_i),
1096
    .stb_i(wbsa_stb_i),
1097
    .cti_i(wbsa_cti_i),
1098
    .bte_i(wbsa_bte_i),
1099
    .adr_i(wbsa_adr_i),
1100
    .we_i(wbsa_we_i),
1101
    .ack_o(wbsa_ack_o),
1102
    .adr_o(adr_a),
1103
    .clk(wbsa_clk),
1104
    .rst(wbsa_rst));
1105
 
1106
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
1107
    .cyc_i(wbsb_cyc_i),
1108
    .stb_i(wbsb_stb_i),
1109
    .cti_i(wbsb_cti_i),
1110
    .bte_i(wbsb_bte_i),
1111
    .adr_i(wbsb_adr_i),
1112
    .we_i(wbsb_we_i),
1113
    .ack_o(wbsb_ack_o),
1114
    .adr_o(adr_b),
1115
    .clk(wbsb_clk),
1116
    .rst(wbsb_rst));
1117 40 unneback
`undef MODULE
1118 92 unneback
 
1119
`define MODULE dpram_be_2r2w
1120
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
1121
`undef MODULE
1122
ram_i (
1123 32 unneback
    .d_a(wbsa_dat_i),
1124 92 unneback
    .q_a(wbsa_dat_o),
1125
    .adr_a(adr_a),
1126
    .be_a(wbsa_sel_i),
1127
    .we_a(wbsa_we_i & wbsa_ack_o),
1128 32 unneback
    .clk_a(wbsa_clk),
1129
    .d_b(wbsb_dat_i),
1130 92 unneback
    .q_b(wbsb_dat_o),
1131
    .adr_b(adr_b),
1132
    .be_b(wbsb_sel_i),
1133
    .we_b(wbsb_we_i & wbsb_ack_o),
1134 32 unneback
    .clk_b(wbsb_clk) );
1135
 
1136
endmodule
1137 40 unneback
`endif
1138 94 unneback
 

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