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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46
`define MODULE wb_adr_inc
47 84 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
48 75 unneback
`undef MODULE
49 83 unneback
parameter adr_width = 10;
50
parameter max_burst_width = 4;
51 84 unneback
input cyc_i, stb_i, we_i;
52 83 unneback
input [2:0] cti_i;
53
input [1:0] bte_i;
54
input [adr_width-1:0] adr_i;
55
output [adr_width-1:0] adr_o;
56
output ack_o;
57
input clk, rst;
58 75 unneback
 
59 83 unneback
reg [adr_width-1:0] adr;
60 90 unneback
wire [max_burst_width-1:0] to_adr;
61 91 unneback
reg [max_burst_width-1:0] last_adr;
62 92 unneback
reg last_cycle;
63
localparam idle_or_eoc = 1'b0;
64
localparam cyc_or_ws   = 1'b1;
65 90 unneback
 
66 91 unneback
always @ (posedge clk or posedge rst)
67
if (rst)
68
    last_adr <= {max_burst_width{1'b0}};
69
else
70
    if (stb_i)
71 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
72 91 unneback
 
73 83 unneback
generate
74
if (max_burst_width==0) begin : inst_0
75 96 unneback
 
76
        reg ack_o;
77
        assign adr_o = adr_i;
78
        always @ (posedge clk or posedge rst)
79
        if (rst)
80
            ack_o <= 1'b0;
81
        else
82
            ack_o <= cyc_i & stb_i & !ack_o;
83
 
84 83 unneback
end else begin
85
 
86
    always @ (posedge clk or posedge rst)
87
    if (rst)
88 92 unneback
        last_cycle <= idle_or_eoc;
89 83 unneback
    else
90 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
91
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
92
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
93
                      cyc_or_ws; // cyc
94
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
95 84 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
96 91 unneback
                                        (!stb_i) ? last_adr :
97 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
98 84 unneback
                                        adr[max_burst_width-1:0];
99 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
100 96 unneback
 
101 83 unneback
end
102
endgenerate
103
 
104
generate
105
if (max_burst_width==2) begin : inst_2
106
    always @ (posedge clk or posedge rst)
107
    if (rst)
108
        adr <= 2'h0;
109
    else
110
        if (cyc_i & stb_i)
111
            adr[1:0] <= to_adr[1:0] + 2'd1;
112 75 unneback
        else
113 83 unneback
            adr <= to_adr[1:0];
114
end
115
endgenerate
116
 
117
generate
118
if (max_burst_width==3) begin : inst_3
119
    always @ (posedge clk or posedge rst)
120
    if (rst)
121
        adr <= 3'h0;
122
    else
123
        if (cyc_i & stb_i)
124
            case (bte_i)
125
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
126
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
127 75 unneback
            endcase
128 83 unneback
        else
129
            adr <= to_adr[2:0];
130
end
131
endgenerate
132
 
133
generate
134
if (max_burst_width==4) begin : inst_4
135
    always @ (posedge clk or posedge rst)
136
    if (rst)
137
        adr <= 4'h0;
138
    else
139 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
140 83 unneback
            case (bte_i)
141
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
142
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
143
            default: adr[3:0] <= to_adr + 4'd1;
144
            endcase
145
        else
146
            adr <= to_adr[3:0];
147
end
148
endgenerate
149
 
150
generate
151
if (adr_width > max_burst_width) begin : pass_through
152
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
153
end
154
endgenerate
155
 
156
endmodule
157 75 unneback
`endif
158
 
159 40 unneback
`ifdef WB3WB3_BRIDGE
160 12 unneback
// async wb3 - wb3 bridge
161
`timescale 1ns/1ns
162 40 unneback
`define MODULE wb3wb3_bridge
163
module `BASE`MODULE (
164
`undef MODULE
165 12 unneback
        // wishbone slave side
166
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
167
        // wishbone master side
168
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
169
 
170 94 unneback
parameter style = "FIFO"; // valid: simple, FIFO
171
parameter addr_width = 4;
172
 
173 12 unneback
input [31:0] wbs_dat_i;
174
input [31:2] wbs_adr_i;
175
input [3:0]  wbs_sel_i;
176
input [1:0]  wbs_bte_i;
177
input [2:0]  wbs_cti_i;
178
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
179
output [31:0] wbs_dat_o;
180 14 unneback
output wbs_ack_o;
181 12 unneback
input wbs_clk, wbs_rst;
182
 
183
output [31:0] wbm_dat_o;
184
output reg [31:2] wbm_adr_o;
185
output [3:0]  wbm_sel_o;
186
output reg [1:0]  wbm_bte_o;
187
output reg [2:0]  wbm_cti_o;
188 14 unneback
output reg wbm_we_o;
189
output wbm_cyc_o;
190 12 unneback
output wbm_stb_o;
191
input [31:0]  wbm_dat_i;
192
input wbm_ack_i;
193
input wbm_clk, wbm_rst;
194
 
195
// bte
196
parameter linear       = 2'b00;
197
parameter wrap4        = 2'b01;
198
parameter wrap8        = 2'b10;
199
parameter wrap16       = 2'b11;
200
// cti
201
parameter classic      = 3'b000;
202
parameter incburst     = 3'b010;
203
parameter endofburst   = 3'b111;
204
 
205 94 unneback
localparam wbs_adr  = 1'b0;
206
localparam wbs_data = 1'b1;
207 12 unneback
 
208 94 unneback
localparam wbm_adr0      = 2'b00;
209
localparam wbm_adr1      = 2'b01;
210
localparam wbm_data      = 2'b10;
211
localparam wbm_data_wait = 2'b11;
212 12 unneback
 
213
reg [1:0] wbs_bte_reg;
214
reg wbs;
215
wire wbs_eoc_alert, wbm_eoc_alert;
216
reg wbs_eoc, wbm_eoc;
217
reg [1:0] wbm;
218
 
219 14 unneback
wire [1:16] wbs_count, wbm_count;
220 12 unneback
 
221
wire [35:0] a_d, a_q, b_d, b_q;
222
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
223
reg a_rd_reg;
224
wire b_rd_adr, b_rd_data;
225 14 unneback
wire b_rd_data_reg;
226
wire [35:0] temp;
227 12 unneback
 
228
`define WE 5
229
`define BTE 4:3
230
`define CTI 2:0
231
 
232
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
233
always @ (posedge wbs_clk or posedge wbs_rst)
234
if (wbs_rst)
235
        wbs_eoc <= 1'b0;
236
else
237
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
238 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
239 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
240
                wbs_eoc <= 1'b1;
241
 
242 40 unneback
`define MODULE cnt_shreg_ce_clear
243
`BASE`MODULE # ( .length(16))
244
`undef MODULE
245 12 unneback
    cnt0 (
246
        .cke(wbs_ack_o),
247
        .clear(wbs_eoc),
248
        .q(wbs_count),
249
        .rst(wbs_rst),
250
        .clk(wbs_clk));
251
 
252
always @ (posedge wbs_clk or posedge wbs_rst)
253
if (wbs_rst)
254
        wbs <= wbs_adr;
255
else
256 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
257 12 unneback
                wbs <= wbs_data;
258
        else if (wbs_eoc & wbs_ack_o)
259
                wbs <= wbs_adr;
260
 
261
// wbs FIFO
262 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
263
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
264 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
265
              1'b0;
266
assign a_rd = !a_fifo_empty;
267
always @ (posedge wbs_clk or posedge wbs_rst)
268
if (wbs_rst)
269
        a_rd_reg <= 1'b0;
270
else
271
        a_rd_reg <= a_rd;
272
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
273
 
274
assign wbs_dat_o = a_q[35:4];
275
 
276
always @ (posedge wbs_clk or posedge wbs_rst)
277
if (wbs_rst)
278 13 unneback
        wbs_bte_reg <= 2'b00;
279 12 unneback
else
280 13 unneback
        wbs_bte_reg <= wbs_bte_i;
281 12 unneback
 
282
// wbm FIFO
283
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
284
always @ (posedge wbm_clk or posedge wbm_rst)
285
if (wbm_rst)
286
        wbm_eoc <= 1'b0;
287
else
288
        if (wbm==wbm_adr0 & !b_fifo_empty)
289
                wbm_eoc <= b_q[`BTE] == linear;
290
        else if (wbm_eoc_alert & wbm_ack_i)
291
                wbm_eoc <= 1'b1;
292
 
293
always @ (posedge wbm_clk or posedge wbm_rst)
294
if (wbm_rst)
295
        wbm <= wbm_adr0;
296
else
297 33 unneback
/*
298 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
299
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
300
        (wbm==wbm_adr1 & !wbm_we_o) |
301
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
302
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
303 33 unneback
*/
304
    case (wbm)
305
    wbm_adr0:
306
        if (!b_fifo_empty)
307
            wbm <= wbm_adr1;
308
    wbm_adr1:
309
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
310
            wbm <= wbm_data;
311
    wbm_data:
312
        if (wbm_ack_i & wbm_eoc)
313
            wbm <= wbm_adr0;
314
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
315
            wbm <= wbm_data_wait;
316
    wbm_data_wait:
317
        if (!b_fifo_empty)
318
            wbm <= wbm_data;
319
    endcase
320 12 unneback
 
321
assign b_d = {wbm_dat_i,4'b1111};
322
assign b_wr = !wbm_we_o & wbm_ack_i;
323
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
324
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
325
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
326 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
327 12 unneback
                   1'b0;
328
assign b_rd = b_rd_adr | b_rd_data;
329
 
330 40 unneback
`define MODULE dff
331
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
332
`undef MODULE
333
`define MODULE dff_ce
334
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
335
`undef MODULE
336 12 unneback
 
337
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
338
 
339 40 unneback
`define MODULE cnt_shreg_ce_clear
340 42 unneback
`BASE`MODULE # ( .length(16))
341 40 unneback
`undef MODULE
342 12 unneback
    cnt1 (
343
        .cke(wbm_ack_i),
344
        .clear(wbm_eoc),
345
        .q(wbm_count),
346
        .rst(wbm_rst),
347
        .clk(wbm_clk));
348
 
349 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
350
assign wbm_stb_o = (wbm==wbm_data);
351 12 unneback
 
352
always @ (posedge wbm_clk or posedge wbm_rst)
353
if (wbm_rst)
354
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
355
else begin
356
        if (wbm==wbm_adr0 & !b_fifo_empty)
357
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
358
        else if (wbm_eoc_alert & wbm_ack_i)
359
                wbm_cti_o <= endofburst;
360
end
361
 
362
//async_fifo_dw_simplex_top
363 40 unneback
`define MODULE fifo_2r2w_async_simplex
364
`BASE`MODULE
365
`undef MODULE
366 12 unneback
# ( .data_width(36), .addr_width(addr_width))
367
fifo (
368
    // a side
369
    .a_d(a_d),
370
    .a_wr(a_wr),
371
    .a_fifo_full(a_fifo_full),
372
    .a_q(a_q),
373
    .a_rd(a_rd),
374
    .a_fifo_empty(a_fifo_empty),
375
    .a_clk(wbs_clk),
376
    .a_rst(wbs_rst),
377
    // b side
378
    .b_d(b_d),
379
    .b_wr(b_wr),
380
    .b_fifo_full(b_fifo_full),
381
    .b_q(b_q),
382
    .b_rd(b_rd),
383
    .b_fifo_empty(b_fifo_empty),
384
    .b_clk(wbm_clk),
385
    .b_rst(wbm_rst)
386
    );
387
 
388
endmodule
389 40 unneback
`undef WE
390
`undef BTE
391
`undef CTI
392
`endif
393 17 unneback
 
394 75 unneback
`ifdef WB3AVALON_BRIDGE
395
`define MODULE wb3avalon_bridge
396
module `BASE`MODULE (
397
`undef MODULE
398
        // wishbone slave side
399
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
400 77 unneback
        // avalon master side
401 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
402
 
403 84 unneback
parameter linewrapburst = 1'b0;
404
 
405 75 unneback
input [31:0] wbs_dat_i;
406
input [31:2] wbs_adr_i;
407
input [3:0]  wbs_sel_i;
408
input [1:0]  wbs_bte_i;
409
input [2:0]  wbs_cti_i;
410 83 unneback
input wbs_we_i;
411
input wbs_cyc_i;
412
input wbs_stb_i;
413 75 unneback
output [31:0] wbs_dat_o;
414
output wbs_ack_o;
415
input wbs_clk, wbs_rst;
416
 
417
input [31:0] readdata;
418
output [31:0] writedata;
419
output [31:2] address;
420
output [3:0]  be;
421
output write;
422 81 unneback
output read;
423 75 unneback
output beginbursttransfer;
424
output [3:0] burstcount;
425
input readdatavalid;
426
input waitrequest;
427
input clk;
428
input rst;
429
 
430
wire [1:0] wbm_bte_o;
431
wire [2:0] wbm_cti_o;
432
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
433
reg last_cyc;
434 79 unneback
reg [3:0] counter;
435 82 unneback
reg read_busy;
436 75 unneback
 
437
always @ (posedge clk or posedge rst)
438
if (rst)
439
    last_cyc <= 1'b0;
440
else
441
    last_cyc <= wbm_cyc_o;
442
 
443 79 unneback
always @ (posedge clk or posedge rst)
444
if (rst)
445 82 unneback
    read_busy <= 1'b0;
446 79 unneback
else
447 82 unneback
    if (read & !waitrequest)
448
        read_busy <= 1'b1;
449
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
450
        read_busy <= 1'b0;
451
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
452 81 unneback
 
453 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
454
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
455
                    (wbm_bte_o==2'b10) ? 4'd8 :
456 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
457
                    4'd1;
458 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
459 75 unneback
 
460 79 unneback
always @ (posedge clk or posedge rst)
461
if (rst) begin
462
    counter <= 4'd0;
463
end else
464 80 unneback
    if (wbm_we_o) begin
465
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
466 84 unneback
            counter <= burstcount -4'd1;
467 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
468
            counter <= burstcount;
469
        end else if (!waitrequest & wbm_stb_o) begin
470
            counter <= counter - 4'd1;
471
        end
472 82 unneback
    end
473 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
474 79 unneback
 
475 75 unneback
`define MODULE wb3wb3_bridge
476 77 unneback
`BASE`MODULE wbwb3inst (
477 75 unneback
`undef MODULE
478
    // wishbone slave side
479
    .wbs_dat_i(wbs_dat_i),
480
    .wbs_adr_i(wbs_adr_i),
481
    .wbs_sel_i(wbs_sel_i),
482
    .wbs_bte_i(wbs_bte_i),
483
    .wbs_cti_i(wbs_cti_i),
484
    .wbs_we_i(wbs_we_i),
485
    .wbs_cyc_i(wbs_cyc_i),
486
    .wbs_stb_i(wbs_stb_i),
487
    .wbs_dat_o(wbs_dat_o),
488
    .wbs_ack_o(wbs_ack_o),
489
    .wbs_clk(wbs_clk),
490
    .wbs_rst(wbs_rst),
491
    // wishbone master side
492
    .wbm_dat_o(writedata),
493 78 unneback
    .wbm_adr_o(address),
494 75 unneback
    .wbm_sel_o(be),
495
    .wbm_bte_o(wbm_bte_o),
496
    .wbm_cti_o(wbm_cti_o),
497
    .wbm_we_o(wbm_we_o),
498
    .wbm_cyc_o(wbm_cyc_o),
499
    .wbm_stb_o(wbm_stb_o),
500
    .wbm_dat_i(readdata),
501
    .wbm_ack_i(wbm_ack_i),
502
    .wbm_clk(clk),
503
    .wbm_rst(rst));
504
 
505
 
506
endmodule
507
`endif
508
 
509 40 unneback
`ifdef WB3_ARBITER_TYPE1
510
`define MODULE wb3_arbiter_type1
511 42 unneback
module `BASE`MODULE (
512 40 unneback
`undef MODULE
513 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
514
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
515
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
516
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
517
    wb_clk, wb_rst
518
);
519
 
520
parameter nr_of_ports = 3;
521
parameter adr_size = 26;
522
parameter adr_lo   = 2;
523
parameter dat_size = 32;
524
parameter sel_size = dat_size/8;
525
 
526
localparam aw = (adr_size - adr_lo) * nr_of_ports;
527
localparam dw = dat_size * nr_of_ports;
528
localparam sw = sel_size * nr_of_ports;
529
localparam cw = 3 * nr_of_ports;
530
localparam bw = 2 * nr_of_ports;
531
 
532
input  [dw-1:0] wbm_dat_o;
533
input  [aw-1:0] wbm_adr_o;
534
input  [sw-1:0] wbm_sel_o;
535
input  [cw-1:0] wbm_cti_o;
536
input  [bw-1:0] wbm_bte_o;
537
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
538
output [dw-1:0] wbm_dat_i;
539
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
540
 
541
output [dat_size-1:0] wbs_dat_i;
542
output [adr_size-1:adr_lo] wbs_adr_i;
543
output [sel_size-1:0] wbs_sel_i;
544
output [2:0] wbs_cti_i;
545
output [1:0] wbs_bte_i;
546
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
547
input  [dat_size-1:0] wbs_dat_o;
548
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
549
 
550
input wb_clk, wb_rst;
551
 
552 44 unneback
reg  [nr_of_ports-1:0] select;
553 39 unneback
wire [nr_of_ports-1:0] state;
554
wire [nr_of_ports-1:0] eoc; // end-of-cycle
555
wire [nr_of_ports-1:0] sel;
556
wire idle;
557
 
558
genvar i;
559
 
560
assign idle = !(|state);
561
 
562
generate
563
if (nr_of_ports == 2) begin
564
 
565
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
566
 
567
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
568
 
569 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
570
 
571
    always @ (idle or wbm_cyc_o)
572
    if (idle)
573
        casex (wbm_cyc_o)
574
        2'b1x : select = 2'b10;
575
        2'b01 : select = 2'b01;
576
        default : select = {nr_of_ports{1'b0}};
577
        endcase
578
    else
579
        select = {nr_of_ports{1'b0}};
580
 
581 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
582
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
583
 
584
end
585
endgenerate
586
 
587
generate
588
if (nr_of_ports == 3) begin
589
 
590
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
591
 
592
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
593
 
594 44 unneback
    always @ (idle or wbm_cyc_o)
595
    if (idle)
596
        casex (wbm_cyc_o)
597
        3'b1xx : select = 3'b100;
598
        3'b01x : select = 3'b010;
599
        3'b001 : select = 3'b001;
600
        default : select = {nr_of_ports{1'b0}};
601
        endcase
602
    else
603
        select = {nr_of_ports{1'b0}};
604
 
605
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
606 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
607
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
608
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
609
 
610
end
611
endgenerate
612
 
613
generate
614 44 unneback
if (nr_of_ports == 4) begin
615
 
616
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
617
 
618
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
619
 
620
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
621
 
622
    always @ (idle or wbm_cyc_o)
623
    if (idle)
624
        casex (wbm_cyc_o)
625
        4'b1xxx : select = 4'b1000;
626
        4'b01xx : select = 4'b0100;
627
        4'b001x : select = 4'b0010;
628
        4'b0001 : select = 4'b0001;
629
        default : select = {nr_of_ports{1'b0}};
630
        endcase
631
    else
632
        select = {nr_of_ports{1'b0}};
633
 
634
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
635
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
636
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
637
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
638
 
639
end
640
endgenerate
641
 
642
generate
643
if (nr_of_ports == 5) begin
644
 
645
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
646
 
647
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
648
 
649
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
650
 
651
    always @ (idle or wbm_cyc_o)
652
    if (idle)
653
        casex (wbm_cyc_o)
654
        5'b1xxxx : select = 5'b10000;
655
        5'b01xxx : select = 5'b01000;
656
        5'b001xx : select = 5'b00100;
657
        5'b0001x : select = 5'b00010;
658
        5'b00001 : select = 5'b00001;
659
        default : select = {nr_of_ports{1'b0}};
660
        endcase
661
    else
662
        select = {nr_of_ports{1'b0}};
663
 
664
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
665
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
666
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
667
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
668
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
669
 
670
end
671
endgenerate
672
 
673
generate
674 67 unneback
if (nr_of_ports == 6) begin
675
 
676
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
677
 
678
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
679
 
680
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
681
 
682
    always @ (idle or wbm_cyc_o)
683
    if (idle)
684
        casex (wbm_cyc_o)
685
        6'b1xxxxx : select = 6'b100000;
686
        6'b01xxxx : select = 6'b010000;
687
        6'b001xxx : select = 6'b001000;
688
        6'b0001xx : select = 6'b000100;
689
        6'b00001x : select = 6'b000010;
690
        6'b000001 : select = 6'b000001;
691
        default : select = {nr_of_ports{1'b0}};
692
        endcase
693
    else
694
        select = {nr_of_ports{1'b0}};
695
 
696
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
697
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
698
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
699
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
700
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
701
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
702
 
703
end
704
endgenerate
705
 
706
generate
707
if (nr_of_ports == 7) begin
708
 
709
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
710
 
711
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
712
 
713
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
714
 
715
    always @ (idle or wbm_cyc_o)
716
    if (idle)
717
        casex (wbm_cyc_o)
718
        7'b1xxxxxx : select = 7'b1000000;
719
        7'b01xxxxx : select = 7'b0100000;
720
        7'b001xxxx : select = 7'b0010000;
721
        7'b0001xxx : select = 7'b0001000;
722
        7'b00001xx : select = 7'b0000100;
723
        7'b000001x : select = 7'b0000010;
724
        7'b0000001 : select = 7'b0000001;
725
        default : select = {nr_of_ports{1'b0}};
726
        endcase
727
    else
728
        select = {nr_of_ports{1'b0}};
729
 
730
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
731
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
732
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
733
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
734
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
735
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
736
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
737
 
738
end
739
endgenerate
740
 
741
generate
742
if (nr_of_ports == 8) begin
743
 
744
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
745
 
746
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
747
 
748
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
749
 
750
    always @ (idle or wbm_cyc_o)
751
    if (idle)
752
        casex (wbm_cyc_o)
753
        8'b1xxxxxxx : select = 8'b10000000;
754
        8'b01xxxxxx : select = 8'b01000000;
755
        8'b001xxxxx : select = 8'b00100000;
756
        8'b0001xxxx : select = 8'b00010000;
757
        8'b00001xxx : select = 8'b00001000;
758
        8'b000001xx : select = 8'b00000100;
759
        8'b0000001x : select = 8'b00000010;
760
        8'b00000001 : select = 8'b00000001;
761
        default : select = {nr_of_ports{1'b0}};
762
        endcase
763
    else
764
        select = {nr_of_ports{1'b0}};
765
 
766
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
767
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
768
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
769
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
770
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
771
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
772
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
773
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
774
 
775
end
776
endgenerate
777
 
778
generate
779 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
780 42 unneback
`define MODULE spr
781
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
782
`undef MODULE
783 39 unneback
end
784
endgenerate
785
 
786
    assign sel = select | state;
787
 
788 40 unneback
`define MODULE mux_andor
789
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
790
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
791
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
792
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
793
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
794
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
795
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
796
`undef MODULE
797 39 unneback
    assign wbs_cyc_i = |sel;
798
 
799
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
800
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
801
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
802
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
803
 
804
endmodule
805 40 unneback
`endif
806 39 unneback
 
807 60 unneback
`ifdef WB_B3_RAM_BE
808 49 unneback
// WB RAM with byte enable
809 59 unneback
`define MODULE wb_b3_ram_be
810
module `BASE`MODULE (
811
`undef MODULE
812 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
813
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
814 59 unneback
 
815 68 unneback
parameter adr_size = 16;
816 84 unneback
parameter mem_size = 1<<adr_size;
817 60 unneback
parameter dat_size = 32;
818 83 unneback
parameter max_burst_width = 4;
819 60 unneback
parameter memory_init = 1;
820
parameter memory_file = "vl_ram.vmem";
821 59 unneback
 
822 84 unneback
localparam aw = (adr_size);
823 69 unneback
localparam dw = dat_size;
824
localparam sw = dat_size/8;
825
localparam cw = 3;
826
localparam bw = 2;
827 60 unneback
 
828 70 unneback
input [dw-1:0] wbs_dat_i;
829
input [aw-1:0] wbs_adr_i;
830
input [cw-1:0] wbs_cti_i;
831
input [bw-1:0] wbs_bte_i;
832
input [sw-1:0] wbs_sel_i;
833
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
834
output [dw-1:0] wbs_dat_o;
835
output wbs_ack_o;
836 71 unneback
input wb_clk, wb_rst;
837 59 unneback
 
838 83 unneback
wire [aw-1:0] adr;
839 59 unneback
 
840 60 unneback
`define MODULE ram_be
841
`BASE`MODULE # (
842
    .data_width(dat_size),
843 83 unneback
    .addr_width(aw),
844 69 unneback
    .mem_size(mem_size),
845 68 unneback
    .memory_init(memory_init),
846
    .memory_file(memory_file))
847 60 unneback
ram0(
848
`undef MODULE
849
    .d(wbs_dat_i),
850 83 unneback
    .adr(adr),
851 60 unneback
    .be(wbs_sel_i),
852 86 unneback
    .we(wbs_we_i & wbs_ack_o),
853 60 unneback
    .q(wbs_dat_o),
854
    .clk(wb_clk)
855
);
856
 
857 83 unneback
`define MODULE wb_adr_inc
858
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
859
    .cyc_i(wbs_cyc_i),
860
    .stb_i(wbs_stb_i),
861
    .cti_i(wbs_cti_i),
862
    .bte_i(wbs_bte_i),
863
    .adr_i(wbs_adr_i),
864 84 unneback
    .we_i(wbs_we_i),
865 83 unneback
    .ack_o(wbs_ack_o),
866
    .adr_o(adr),
867
    .clk(wb_clk),
868
    .rst(wb_rst));
869
`undef MODULE
870 60 unneback
 
871 59 unneback
endmodule
872
`endif
873
 
874
`ifdef WB_B4_RAM_BE
875
// WB RAM with byte enable
876 49 unneback
`define MODULE wb_b4_ram_be
877
module `BASE`MODULE (
878
`undef MODULE
879
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
880 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
881 49 unneback
 
882
    parameter dat_width = 32;
883
    parameter adr_width = 8;
884
 
885
input [dat_width-1:0] wb_dat_i;
886
input [adr_width-1:0] wb_adr_i;
887
input [dat_width/8-1:0] wb_sel_i;
888
input wb_we_i, wb_stb_i, wb_cyc_i;
889
output [dat_width-1:0] wb_dat_o;
890 51 unneback
reg [dat_width-1:0] wb_dat_o;
891 52 unneback
output wb_stall_o;
892 49 unneback
output wb_ack_o;
893
reg wb_ack_o;
894
input wb_clk, wb_rst;
895
 
896 56 unneback
wire [dat_width/8-1:0] cke;
897
 
898 49 unneback
generate
899
if (dat_width==32) begin
900 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
901
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
902
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
903
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
904 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
905 49 unneback
    always @ (posedge wb_clk)
906
    begin
907 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
908
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
909
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
910
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
911 49 unneback
    end
912 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
913
    begin
914
        if (wb_rst)
915
            wb_dat_o <= 32'h0;
916
        else
917
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
918
    end
919 49 unneback
end
920
endgenerate
921
 
922 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
923 55 unneback
if (wb_rst)
924 52 unneback
    wb_ack_o <= 1'b0;
925
else
926 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
927 52 unneback
 
928
assign wb_stall_o = 1'b0;
929
 
930 49 unneback
endmodule
931
`endif
932
 
933 48 unneback
`ifdef WB_B4_ROM
934
// WB ROM
935
`define MODULE wb_b4_rom
936
module `BASE`MODULE (
937
`undef MODULE
938
    wb_adr_i, wb_stb_i, wb_cyc_i,
939
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
940
 
941
    parameter dat_width = 32;
942
    parameter dat_default = 32'h15000000;
943
    parameter adr_width = 32;
944
 
945
/*
946
//E2_ifndef ROM
947
//E2_define ROM "rom.v"
948
//E2_endif
949
*/
950
    input [adr_width-1:2]   wb_adr_i;
951
    input                   wb_stb_i;
952
    input                   wb_cyc_i;
953
    output [dat_width-1:0]  wb_dat_o;
954
    reg [dat_width-1:0]     wb_dat_o;
955
    output                  wb_ack_o;
956
    reg                     wb_ack_o;
957
    output                  stall_o;
958
    input                   wb_clk;
959
    input                   wb_rst;
960
 
961
always @ (posedge wb_clk or posedge wb_rst)
962
    if (wb_rst)
963
        wb_dat_o <= {dat_width{1'b0}};
964
    else
965
         case (wb_adr_i[adr_width-1:2])
966
//E2_ifdef ROM
967
//E2_include `ROM
968
//E2_endif
969
           default:
970
             wb_dat_o <= dat_default;
971
 
972
         endcase // case (wb_adr_i)
973
 
974
 
975
always @ (posedge wb_clk or posedge wb_rst)
976
    if (wb_rst)
977
        wb_ack_o <= 1'b0;
978
    else
979
        wb_ack_o <= wb_stb_i & wb_cyc_i;
980
 
981
assign stall_o = 1'b0;
982
 
983
endmodule
984
`endif
985
 
986
 
987 40 unneback
`ifdef WB_BOOT_ROM
988 17 unneback
// WB ROM
989 40 unneback
`define MODULE wb_boot_rom
990
module `BASE`MODULE (
991
`undef MODULE
992 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
993 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
994 17 unneback
 
995 18 unneback
    parameter adr_hi = 31;
996
    parameter adr_lo = 28;
997
    parameter adr_sel = 4'hf;
998
    parameter addr_width = 5;
999 33 unneback
/*
1000 17 unneback
//E2_ifndef BOOT_ROM
1001
//E2_define BOOT_ROM "boot_rom.v"
1002
//E2_endif
1003 33 unneback
*/
1004 18 unneback
    input [adr_hi:2]    wb_adr_i;
1005
    input               wb_stb_i;
1006
    input               wb_cyc_i;
1007
    output [31:0]        wb_dat_o;
1008
    output              wb_ack_o;
1009
    output              hit_o;
1010
    input               wb_clk;
1011
    input               wb_rst;
1012
 
1013
    wire hit;
1014
    reg [31:0] wb_dat;
1015
    reg wb_ack;
1016
 
1017
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1018 17 unneback
 
1019
always @ (posedge wb_clk or posedge wb_rst)
1020
    if (wb_rst)
1021 18 unneback
        wb_dat <= 32'h15000000;
1022 17 unneback
    else
1023 18 unneback
         case (wb_adr_i[addr_width-1:2])
1024 33 unneback
//E2_ifdef BOOT_ROM
1025 17 unneback
//E2_include `BOOT_ROM
1026 33 unneback
//E2_endif
1027 17 unneback
           /*
1028
            // Zero r0 and jump to 0x00000100
1029 18 unneback
 
1030
            1 : wb_dat <= 32'hA8200000;
1031
            2 : wb_dat <= 32'hA8C00100;
1032
            3 : wb_dat <= 32'h44003000;
1033
            4 : wb_dat <= 32'h15000000;
1034 17 unneback
            */
1035
           default:
1036 18 unneback
             wb_dat <= 32'h00000000;
1037 17 unneback
 
1038
         endcase // case (wb_adr_i)
1039
 
1040
 
1041
always @ (posedge wb_clk or posedge wb_rst)
1042
    if (wb_rst)
1043 18 unneback
        wb_ack <= 1'b0;
1044 17 unneback
    else
1045 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1046 17 unneback
 
1047 18 unneback
assign hit_o = hit;
1048
assign wb_dat_o = wb_dat & {32{wb_ack}};
1049
assign wb_ack_o = wb_ack;
1050
 
1051 17 unneback
endmodule
1052 40 unneback
`endif
1053 32 unneback
 
1054 92 unneback
`ifdef WB_B3_DPRAM
1055
`define MODULE wb_b3_dpram
1056 40 unneback
module `BASE`MODULE (
1057
`undef MODULE
1058 32 unneback
        // wishbone slave side a
1059 92 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1060 32 unneback
        wbsa_clk, wbsa_rst,
1061 92 unneback
        // wishbone slave side b
1062
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1063 32 unneback
        wbsb_clk, wbsb_rst);
1064
 
1065 92 unneback
parameter data_width_a = 32;
1066
parameter data_width_b = data_width_a;
1067
parameter addr_width_a = 8;
1068
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
1069
   parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
1070
parameter max_burst_width_a = 4;
1071
parameter max_burst_width_b = max_burst_width_a;
1072 32 unneback
 
1073 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
1074
input [addr_width_a-1:0] wbsa_adr_i;
1075
input [data_width_a/8-1:0] wbsa_sel_i;
1076
input [2:0] wbsa_cti_i;
1077
input [1:0] wbsa_bte_i;
1078 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1079 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
1080 32 unneback
output wbsa_ack_o;
1081
input wbsa_clk, wbsa_rst;
1082
 
1083 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
1084
input [addr_width_b-1:0] wbsb_adr_i;
1085
input [data_width_b/8-1:0] wbsb_sel_i;
1086
input [2:0] wbsb_cti_i;
1087
input [1:0] wbsb_bte_i;
1088 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1089 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
1090 32 unneback
output wbsb_ack_o;
1091
input wbsb_clk, wbsb_rst;
1092
 
1093 92 unneback
wire [addr_width_a-1:0] adr_a;
1094
wire [addr_width_b-1:0] adr_b;
1095 32 unneback
 
1096 92 unneback
`define MODULE wb_adr_inc
1097
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
1098
    .cyc_i(wbsa_cyc_i),
1099
    .stb_i(wbsa_stb_i),
1100
    .cti_i(wbsa_cti_i),
1101
    .bte_i(wbsa_bte_i),
1102
    .adr_i(wbsa_adr_i),
1103
    .we_i(wbsa_we_i),
1104
    .ack_o(wbsa_ack_o),
1105
    .adr_o(adr_a),
1106
    .clk(wbsa_clk),
1107
    .rst(wbsa_rst));
1108
 
1109
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
1110
    .cyc_i(wbsb_cyc_i),
1111
    .stb_i(wbsb_stb_i),
1112
    .cti_i(wbsb_cti_i),
1113
    .bte_i(wbsb_bte_i),
1114
    .adr_i(wbsb_adr_i),
1115
    .we_i(wbsb_we_i),
1116
    .ack_o(wbsb_ack_o),
1117
    .adr_o(adr_b),
1118
    .clk(wbsb_clk),
1119
    .rst(wbsb_rst));
1120 40 unneback
`undef MODULE
1121 92 unneback
 
1122
`define MODULE dpram_be_2r2w
1123
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
1124
`undef MODULE
1125
ram_i (
1126 32 unneback
    .d_a(wbsa_dat_i),
1127 92 unneback
    .q_a(wbsa_dat_o),
1128
    .adr_a(adr_a),
1129
    .be_a(wbsa_sel_i),
1130
    .we_a(wbsa_we_i & wbsa_ack_o),
1131 32 unneback
    .clk_a(wbsa_clk),
1132
    .d_b(wbsb_dat_i),
1133 92 unneback
    .q_b(wbsb_dat_o),
1134
    .adr_b(adr_b),
1135
    .be_b(wbsb_sel_i),
1136
    .we_b(wbsb_we_i & wbsb_ack_o),
1137 32 unneback
    .clk_b(wbsb_clk) );
1138
 
1139
endmodule
1140 40 unneback
`endif
1141 94 unneback
 
1142 96 unneback
`ifdef WBB3_WBB4_CACHE
1143
`define MODULE wbb3_wbb4_cache
1144
module `BASE`MODULE (
1145 98 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1146
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
1147 96 unneback
);
1148
`undef MODULE
1149
 
1150
parameter dw_s = 32;
1151
parameter aw_s = 24;
1152
parameter dw_m = dw_s;
1153
parameter aw_m = dw_s * aw_s / dw_m;
1154 97 unneback
parameter max_burst_width = 4;
1155 96 unneback
 
1156 97 unneback
parameter async = 1; // wbs_clk != wbm_clk
1157
 
1158 96 unneback
parameter nr_of_ways = 1;
1159 97 unneback
parameter aw_offset = 4; // 4 => 16 words per cache line
1160
parameter aw_slot = 10;
1161 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
1162 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
1163 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
1164 97 unneback
`define SIZE2WIDTH wbm_burst_size
1165
localparam wbm_burst_width `SIZE2WIDTH_EXPR
1166
`undef SIZE2WIDTH
1167
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
1168
`define SIZE2WIDTH nr_of_wbm_burst
1169
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
1170
`undef SIZE2WIDTH
1171 96 unneback
input [dw_s-1:0] wbs_dat_i;
1172
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
1173 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
1174 96 unneback
input [2:0] wbs_cti_i;
1175
input [1:0] wbs_bte_i;
1176 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
1177 96 unneback
output [dw_s-1:0] wbs_dat_o;
1178
output wbs_ack_o;
1179
input wbs_clk, wbs_rst;
1180
 
1181
output [dw_m-1:0] wbm_dat_o;
1182
output [aw_m-1:0] wbm_adr_o;
1183
output [dw_m/8-1:0] wbm_sel_o;
1184
output [2:0] wbm_cti_o;
1185
output [1:0] wbm_bte_o;
1186 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
1187 96 unneback
input [dw_m-1:0] wbm_dat_i;
1188
input wbm_ack_i;
1189
input wbm_stall_i;
1190
input wbm_clk, wbm_rst;
1191
 
1192
wire dirty, valid;
1193 97 unneback
wire [aw_tag-1:0] tag;
1194
wire tag_mem_we;
1195
wire [aw_tag-1:0] wbs_adr_tag;
1196
wire [aw_slot-1:0] wbs_adr_slot;
1197 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
1198
wire [aw_s-1:0] wbs_adr;
1199 96 unneback
 
1200 97 unneback
reg [1:0] state;
1201
localparam idle = 2'h0;
1202
localparam rdwr = 2'h1;
1203
localparam push = 2'h2;
1204
localparam pull = 2'h3;
1205
wire eoc;
1206
 
1207
// cdc
1208
wire done, mem_alert, mem_done;
1209
 
1210 98 unneback
// wbm side
1211
reg [aw_m-1:0] wbm_radr;
1212
reg [aw_m-1:0] wbm_wadr;
1213
wire [aw_slot+-1:0] wbm_adr;
1214
wire wbm_radr_cke, wbm_wadr_cke;
1215
 
1216
reg [1:0] phase;
1217
localparam wbm_wait = 2'b00;
1218
localparam wbm_rd = 2'b10;
1219
localparam wbm_wr = 2'b11;
1220
 
1221 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
1222
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
1223
 
1224
`define MODULE ram
1225
`BASE`MODULE
1226 98 unneback
    # ( .data_width(aw_tag), .addr_width(aw_slot))
1227 97 unneback
    tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
1228
`undef MODULE
1229
assign valid = wbs_adr_tag == tag;
1230
 
1231 96 unneback
`define MODULE wb_adr_inc
1232 98 unneback
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(max_burst_width)) adr_inc0 (
1233 96 unneback
    .cyc_i(wbs_cyc_i),
1234 97 unneback
    .stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
1235 96 unneback
    .cti_i(wbs_cti_i),
1236
    .bte_i(wbs_bte_i),
1237
    .adr_i(wbs_adr_i),
1238 97 unneback
    .we_i (wbs_we_i),
1239 96 unneback
    .ack_o(wbs_ack_o),
1240 97 unneback
    .adr_o(wbs_adr),
1241
    .clk(wbsa_clk),
1242
    .rst(wbsa_rst));
1243 96 unneback
`undef MODULE
1244
 
1245 97 unneback
`define MODULE dpram_be_2r2w
1246
`BASE`MODULE
1247 98 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m) )
1248
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i &  wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
1249
                .d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
1250 97 unneback
`undef MODULE
1251
 
1252
always @ (posedge wbs_clk or posedge wbs_rst)
1253
if (wbs_rst)
1254 98 unneback
    state <= idle;
1255 97 unneback
else
1256
    case (state)
1257
    idle:
1258
        if (wbs_cyc_i)
1259
            state <= rdwr;
1260
    rdwr:
1261
        if (wbs_we_i & valid & eoc)
1262
            state <= idle;
1263
        else if (wbs_we_i & !valid)
1264
            state <= pull;
1265
        else if (!wbs_we_i & valid & eoc)
1266
            state <= idle;
1267
        else if (!wbs_we_i & !valid & !dirty)
1268
            state <= pull;
1269
        else if (!wbs_we_i & !valid & dirty)
1270
            state <= push;
1271
    push:
1272
        if (done)
1273
            state <= rdwr;
1274
    pull:
1275
        if (done)
1276
            state <= rdwr;
1277
    default: state <= idle;
1278
    endcase
1279
 
1280
 
1281
// cdc
1282
generate
1283
if (async==1) begin : cdc0
1284
`define MODULE cdc
1285
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & !valid), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
1286
`undef MODULE
1287
end
1288
else begin : nocdc
1289
    assign mem_alert = state==rdwr & !valid;
1290
    assign done = mem_done;
1291
end
1292
endgenerate
1293
 
1294
// FSM generating a number of burts 4 cycles
1295
// actual number depends on data width ratio
1296
// nr_of_wbm_burst
1297 98 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt0;
1298
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt1;
1299 97 unneback
 
1300
always @ (posedge wbm_clk or posedge wbm_rst)
1301
if (wbm_rst)
1302 98 unneback
    cnt0 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
1303 97 unneback
else
1304 98 unneback
    if (wbm_radr_cke)
1305
        cnt0 <= cnt0 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
1306
assign wbm_radr_cke = wbm_cyc_o & wbm_stb_o & !wbm_stall_i;
1307
assign wbm_radr = {wbs_adr_tag, tag, cnt0};
1308 97 unneback
 
1309 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1310
if (wbm_rst)
1311
    cnt1 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
1312
else
1313
    if (wbm_wadr_cke)
1314
        cnt1 <= cnt1 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
1315
assign wbm_wadr_cke = wbm_ack_i;
1316
assign wbm_wadr = {wbs_adr_tag, wbs_adr_slot, cnt1};
1317 97 unneback
 
1318 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1319
if (wbm_rst)
1320
    phase <= wbm_wait;
1321
else
1322
    case (phase)
1323
    wbm_wait:
1324
        if (mem_alert)
1325
            phase <= state;
1326
    wbm_wr:
1327
        if (&cnt1 & wbm_ack_i)
1328
            phase <= wbm_rd;
1329
    wbm_rd:
1330
        if (&cnt0 & wbm_ack_i)
1331
            phase <= idle;
1332
    default: phase <= wbm_wait;
1333
    endcase
1334
 
1335
assign wbm_adr_o = (phase==wbm_wr) ? {tag, wbs_adr_slot, cnt1} : {wbs_adr_tag, wbs_adr_slot, cnt1};
1336
assign wbm_adr   = (phase==wbm_wr) ? {wbs_adr_slot, cnt1} : {wbs_adr_slot, cnt1};
1337
assign wbm_cti_o = (&cnt0 | &cnt1) ? 3'b111 : 3'b010;
1338
assign wbm_bte_o = bte;
1339
assign wbm_we_o  = phase==wbm_wr;
1340
 
1341 96 unneback
endmodule
1342
`endif

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