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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb_wires.v] - Blame information for rev 103

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Line No. Rev Author Line
1 103 unneback
`define DAT_O _dat_o
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`define ADR_O _adr_o
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`define SEL_O _sel_o
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`define CTI_O _cti_o
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`define BTE_O _bte_o
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`define WE_O _we_o
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`define STB_O _stb_o
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`define CYC_O _cyc_o
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`define STALL_I _stall_i
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`define DAT_I _dat_i
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`define ACK_I _ack_i
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`ifndef DAT_WIDTH
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`define DAT_WIDTH 32
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`endif
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`ifndef ADR_WIDTH
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`define ADR_WIDTH 30
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`endif
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wire [`DAT_WIDTH-1:0] `WB`DAT_O;
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wire [`ADR_WIDTH-1:0] `WB`ADR_O;
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wire [`DAT_WIDTH/8-1:0] `WB`SEL_O;
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wire [2:0] `WB`CTI_O;
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wire [1:0] `WB`BTE_O;
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wire `WB`WE_O;
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wire `WB`STB_O;
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wire `WB`CYC_O;
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wire `WB`STALL_I;
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wire [`DAT_WIDTH-1:0] `WB`DAT_I;
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wire `WB`ACK_I;
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`undef WB
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`undef DAT_O
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`undef ADR_O
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`undef SEL_O
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`undef CTI_O
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`undef BTE_O
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`undef WE_O
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`undef STB_O
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`undef CYC_O
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`undef STALL_I
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`undef DAT_I
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`undef ACK_I

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