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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [sim/] [rtl_sim/] [run/] [Makefile] - Blame information for rev 102

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Line No. Rev Author Line
1 88 unneback
VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v
2
 
3 91 unneback
tb_wb_b3_ram_be:
4 88 unneback
        vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v
5 91 unneback
        vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/sim/rtl_sim/run/wb_b3_ram_be.v
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        vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/bench/wbm.v
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        vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/bench/tb_wb_b3_ram_be.v
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        vsim -do "run 10 us" -l log.txt -c work.vl_wb_b3_ram_be_tb
9 92 unneback
 
10
tb_wb_b3_dpram:
11
        vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_DPRAM $(VERILOG_FILES) > wb_b3_dpram.v
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        vlog -reportprogress 300 -work work ./wb_b3_dpram.v
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        vlog -reportprogress 300 -work work ./../../../bench/wbm.v
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        vlog -reportprogress 300 -work work ./../../../bench/tb_wb_b3_dpram.v
15 102 unneback
 
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tb_wb_cache:
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        vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_CACHE +define+WB_RAM +define+RAM_BE $(VERILOG_FILES) > wb_cache.v
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        vlog -reportprogress 300 -work work ./wb_cache.v
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        vlog -reportprogress 300 -work work ./../../../bench/wbm.v
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        vlog -reportprogress 300 -work work ./../../../bench/tb_wb_cache.v

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