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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [backend/] [ACTEL/] [TwoPortRAM_256x36/] [TwoPortRAM_256x36.gen] - Blame information for rev 8

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Line No. Rev Author Line
1 8 unneback 
Version:8.5.2.4
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ACTGENU_CALL:1
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BATCH:T
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FAM:ProASIC3
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OUTFORMAT:Verilog
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LPMTYPE:LPM_RAM
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LPM_HINT:TWO
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INSERT_PAD:NO
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INSERT_IOREG:NO
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GEN_BHV_VHDL_VAL:F
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GEN_BHV_VERILOG_VAL:F
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MGNTIMER:F
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MGNCMPL:T
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DESDIR:L:/work/ocsvn/versatile_mem_ctrl/syn/ACTEL/vmc/smartgen\TwoPortRAM_256x36
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GEN_BEHV_MODULE:T
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SMARTGEN_DIE:IS8X8M2
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SMARTGEN_PACKAGE:pq208
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AGENIII_IS_SUBPROJECT_LIBERO:T
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WWIDTH:36
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WDEPTH:256
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RWIDTH:36
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RDEPTH:256
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CLKS:2
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RESET_POLARITY:2
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INIT_RAM:F
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DEFAULT_WORD:0x000000000
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CASCADE:0
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WCLK_EDGE:RISE
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RCLK_EDGE:RISE
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WCLOCK_PN:WCLK
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RCLOCK_PN:RCLK
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PMODE2:0
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DATA_IN_PN:WD
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WADDRESS_PN:WADDR
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WE_PN:WEN
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DATA_OUT_PN:RD
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RADDRESS_PN:RADDR
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RE_PN:REN
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WE_POLARITY:1
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RE_POLARITY:1
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PTYPE:1

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