OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [versatile_mem_ctrl_defines.v] - Blame information for rev 112

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 111 unneback 
//=tab Main
2 
 
3 
// Number of WB groups
4 
//=select
5 
//`define WB_GRPS_1 // 1
6 
//`define WB_GRPS_2 // 2
7 
`define WB_GRPS_3 // 3
8 
//`define WB_GRPS_4 // 4
9 
//`define WB_GRPS_5 // 5
10 
//`define WB_GRPS_6 // 6
11 
//`define WB_GRPS_7 // 7
12 
//`define WB_GRPS_8 // 8
13 
//=end
14 
 
15 
`ifdef WB_GRPS_2
16 
    `define WB_GRPS_1
17 
    `define NR_OF_WB_GRPS 2
18 
    `define NR_OF_PORTS 2
19 
`endif
20 
`ifdef WB_GRPS_3
21 
    `define WB_GRPS_1
22 
    `define WB_GRPS_2
23 
    `define NR_OF_WB_GRPS 3
24 
    `define NR_OF_PORTS 3
25 
`endif
26 
`ifdef WB_GRPS_4
27 
    `define WB_GRPS_1
28 
    `define WB_GRPS_2
29 
    `define WB_GRPS_3
30 
    `define NR_OF_WB_GRPS 4
31 
    `define NR_OF_PORTS 4
32 
`endif
33 
`ifdef WB_GRPS_5
34 
    `define WB_GRPS_1
35 
    `define WB_GRPS_2
36 
    `define WB_GRPS_3
37 
    `define WB_GRPS_4
38 
    `define NR_OF_WB_GRPS 5
39 
    `define NR_OF_PORTS 5
40 
`endif
41 
`ifdef WB_GRPS_6
42 
    `define WB_GRPS_1
43 
    `define WB_GRPS_2
44 
    `define WB_GRPS_3
45 
    `define WB_GRPS_4
46 
    `define WB_GRPS_5
47 
    `define NR_OF_WB_GRPS 6
48 
    `define NR_OF_PORTS 6
49 
`endif
50 
`ifdef WB_GRPS_7
51 
    `define WB_GRPS_1
52 
    `define WB_GRPS_2
53 
    `define WB_GRPS_3
54 
    `define WB_GRPS_4
55 
    `define WB_GRPS_5
56 
    `define WB_GRPS_6
57 
    `define NR_OF_WB_GRPS 7
58 
    `define NR_OF_PORTS 7
59 
`endif
60 
`ifdef WB_GRPS_8
61 
    `define WB_GRPS_1
62 
    `define WB_GRPS_2
63 
    `define WB_GRPS_3
64 
    `define WB_GRPS_4
65 
    `define WB_GRPS_5
66 
    `define WB_GRPS_6
67 
    `define WB_GRPS_7
68 
    `define NR_OF_WB_GRPS 8
69 
    `define NR_OF_PORTS 8
70 
`endif
71 
 
72 
// Clock domain crossing WB1
73 
//=select
74 
//`define WB1_MEM_CLK // mem clk domain
75 
`define WB1_CLK // wb1 clk domain
76 
//=end
77 
// Clock domain crossing WB1
78 
//=select
79 
//`define WB2_MEM_CLK // mem clk domain
80 
`define WB2_CLK // wb2 clk domain
81 
//=end
82 
// Clock domain crossing WB1
83 
//=select
84 
`define WB3_MEM_CLK // mem clk domain
85 
//`define WB3_CLK // wb3 clk domain
86 
//=end
87 
// Clock domain crossing WB1
88 
//=select
89 
//`define WB4_MEM_CLK // mem clk domain
90 
`define WB4_CLK // wb4 clk domain
91 
//=end
92 
// Clock domain crossing WB1
93 
//=select
94 
//`define WB5_MEM_CLK // mem clk domain
95 
`define WB5_CLK // wb5 clk domain
96 
//=end
97 
// Clock domain crossing WB1
98 
//=select
99 
//`define WB6_MEM_CLK // mem clk domain
100 
`define WB6_CLK // wb6 clk domain
101 
//=end
102 
// Clock domain crossing WB1
103 
//=select
104 
//`define WB7_MEM_CLK // mem clk domain
105 
`define WB7_CLK // wb7 clk domain
106 
//=end
107 
// Clock domain crossing WB1
108 
//=select
109 
//`define WB8_MEM_CLK // mem clk domain
110 
`define WB8_CLK // wb8 clk domain
111 
//=end
112 
 
113 
// Module base name
114 
`define BASE versatile_mem_ctrl_
115 
 
116 
// Memory type
117 
//=select
118 
//`define RAM // RAM
119 112 unneback 
//`define SDR // SDR
120 111 unneback 
//`define DDR2 // DDR2
121 112 unneback 
`define DDR3 // DDR3
122 111 unneback 
//=end
123 
 
124 
// Shadow RAM
125 
`define SHADOW_RAM
126 
 
127 
//=tab RAM
128 
// Number of bits in address
129 
`define RAM_ADR_SIZE 16
130 
// Capacity in KBytes
131 
`define RAM_MEM_SIZE_KB 48
132 
`ifdef RAM_MEM_SIZE_KB
133 
`define RAM_MEM_SIZE `RAM_MEM_SIZE_KB*1024
134 
`endif
135 
 
136 
// Memory init
137 
`define RAM_MEM_INIT_DUMMY
138 
`ifndef RAM_MEM_INIT_DUMMY
139 
    `define RAM_MEM_INIT 0
140 
`else
141 
    `define RAM_MEM_INIT 1
142 
`endif
143 
 
144 
// Memory init file
145 
`define RAM_MEM_INIT_FILE "ram_init.v"
146 
 
147 
`ifdef RAM
148 
`define WB_ADR_SIZE `RAM_ADR_SIZE
149 
`endif
150 112 unneback 
`ifdef SHADOW_RAM
151 
`define WB_RAM_ADR_SIZE `RAM_ADR_SIZE
152 
`endif
153 111 unneback 
//=tab SDR SDRAM
154 
 
155 
// External data bus size
156 
`define SDR_EXT_DAT_SIZE 16
157 
 
158 
// Memory part
159 
//=select Memory part
160 
//`define MT48LC4M16 // Micron 4M16, 8MB
161 
`define MT48LC16M16 // Micron 16M16, 32MB
162 
//`define MT48LC32M16 // Micron 32M16, 64MB
163 
//=end
164 
 
165 
// SDRAM clock frequency
166 
// set refresh counter timeout
167 
// all rows should be refreshed every 64 ms
168 
// SDRAM CLK frequency
169 
//=select SDRAM CLK
170 
`define SDR_SDRAM_CLK_64 // SDRAM_CLK_64
171 
//`define SDR_SDRAM_CLK_75 // SDRAM_CLK_75
172 
//`define SDR_SDRAM_CLK_125 // SDRAM_CLK_125
173 
//`define SDR_SDRAM_CLK_133 // SDRAM_CLK_133
174 
//`define SDR_SDRAM_CLK_154 // SDRAM_CLK_154
175 
//=end
176 
 
177 
`ifdef MT48LC4M16
178 
// using 1 of MT48LC4M16
179 
// SDRAM data width is 16
180 
`define SDR_SDRAM_DATA_WIDTH 16
181 
`define SDR_SDRAM_DATA_WIDTH_16
182 
`define SDR_COL_SIZE 8
183 
`define SDR_ROW_SIZE 12
184 
`define SDR_ROW_SIZE_12
185 
`define SDR_BA_SIZE 2
186 
`endif //  `ifdef MT48LC4M16
187 
 
188 
`ifdef MT48LC16M16
189 
// using 1 of MT48LC16M16
190 
// SDRAM data width is 16
191 
`define SDR_SDRAM_DATA_WIDTH 16
192 
`define SDR_SDRAM_DATA_WIDTH_16
193 
`define SDR_COL_SIZE 9
194 
`define SDR_ROW_SIZE 13
195 
`define SDR_ROW_SIZE_13
196 
`define SDR_BA_SIZE 2
197 
`endif //  `ifdef MT48LC16M16
198 
 
199 
`ifdef MT48LC32M16
200 
// using 1 of MT48LC32M16
201 
// SDRAM data width is 16
202 
`define SDR_SDRAM_DATA_WIDTH 16
203 
`define SDR_SDRAM_DATA_WIDTH_16
204 
`define SDR_COL_SIZE 10
205 
`define SDR_ROW_SIZE 13
206 
`define SDR_ROW_SIZE_13
207 
`define SDR_BA_SIZE 2
208 
`endif //  `ifdef MT48LC16M16
209 
 
210 
// Refresh whole memory every 64 ms
211 
// Refresh each row every 64 ms
212 
// refresh timeout = 64 ms / Tperiod / number_of_rows
213 
 
214 
// 64 MHz, row_size=12
215 
// 64ms / (1/64MHz) / 2^12 = 1000
216 
// ./VersatileCounter.php 10 1000
217 
// 0101100100
218 
 
219 
`ifdef SDR_SDRAM_CLK_64
220 
    `ifdef SDR_ROW_SIZE_12
221 
        `define SDR_RFR_LENGTH 10
222 
        `define SDR_RFR_WRAP_VALUE 0101100100
223 
    `endif
224 
    `ifdef SDR_ROW_SIZE_13
225 
        `define SDR_RFR_LENGTH 9
226 
        `define SDR_RFR_WRAP_VALUE 001000011
227 
    `endif
228 
`endif
229 
`ifdef SDR_SDRAM_CLK_75
230 
    `ifdef SDR_ROW_SIZE_12
231 
        `define SDR_RFR_LENGTH 11
232 
        `define SDR_RFR_WRAP_VALUE 00110001101
233 
    `endif
234 
    `ifdef SDR_ROW_SIZE_13
235 
        `define SDR_RFR_LENGTH 10
236 
        `define SDR_RFR_WRAP_VALUE 0110111101
237 
    `endif
238 
`endif
239 
`ifdef SDR_SDRAM_CLK_125
240 
    `ifdef SDR_ROW_SIZE_12
241 
        `define SDR_RFR_LENGTH 11
242 
        `define SDR_RFR_WRAP_VALUE 10001000001
243 
    `endif
244 
    `ifdef SDR_ROW_SIZE_13
245 
        `define SDR_RFR_LENGTH 10
246 
        `define SDR_RFR_WRAP_VALUE 1010000111
247 
    `endif
248 
`endif
249 
`ifdef SDR_SDRAM_CLK_133
250 
    `ifdef SDR_ROW_SIZE_12
251 
        `define SDR_RFR_LENGTH 12
252 
        `define SDR_RFR_WRAP_VALUE 101100000111
253 
    `endif
254 
    `ifdef SDR_ROW_SIZE_13
255 
        `define SDR_RFR_LENGTH 11
256 
        `define SDR_RFR_WRAP_VALUE 11111111010
257 
    `endif
258 
`endif
259 
`ifdef SDR_SDRAM_CLK_154
260 
    `ifdef SDR_ROW_SIZE_12
261 
        `define SDR_RFR_LENGTH 12
262 
        `define SDR_RFR_WRAP_VALUE 000101011110
263 
    `endif
264 
    `ifdef SDR_ROW_SIZE_13
265 
        `define SDR_RFR_LENGTH 11
266 
        `define SDR_RFR_WRAP_VALUE 00111101010
267 
    `endif
268 
`endif
269 
 
270 
 
271 
// Disable burst
272 
//`define SDR_NO_BURST
273 
// Enable 4 beat wishbone busrt
274 
`define SDR_BEAT4
275 
// Enable 8 beat wishbone busrt
276 
`define SDR_BEAT8
277 
// Enable 16 beat wishbone busrt
278 
`define SDR_BEAT16
279 
 
280 
// tRFC
281 
`define SDR_TRFC 9
282 
// tRP
283 
`define SDR_TRP 2
284 
// tRCD
285 
`define SDR_TRCD 2
286 
// tMRD
287 
`define SDR_TMRD 2
288 
 
289 
// LMR
290 
// [12:10] reserved
291 
// [9]     WB, write burst; 0 - programmed burst length, 1 - single location
292 
// [8:7]   OP Mode, 2'b00
293 
// [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
294 
// [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
295 
// [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
296 
// LMR: Write burst
297 
`define SDR_INIT_WB 1'b0
298 
// LMR: CAS latency
299 
`define SDR_INIT_CL 3'b010
300 
// LMR: Burst type
301 
`define SDR_INIT_BT 1'b0
302 
// LMR: Burst length
303 
`define SDR_INIT_BL 3'b001
304 
 
305 
`ifdef SDR
306 
    `ifdef SDR_SDRAM_DATA_WIDTH_16
307 
        `define WB_ADR_SIZE `SDR_BA_SIZE+`SDR_COL_SIZE+`SDR_ROW_SIZE+1
308 
    `endif
309 
`endif
310 112 unneback 
 
311 111 unneback 
//=tab DDR2 SDRAM
312 
 
313 
// Use existing Avalon compatible IP
314 
`define DDR2_AVALON
315 
// IP module name
316 
`define DDR2_IP_NAME ALTERA_DDR2
317 112 unneback 
 
318 
`ifdef DDR2
319 
`define WB_ADR_SIZE 24
320 
`endif
321 
 
322 
//=tab DDR3 SDRAM
323 
 
324 
// Board
325 
//=select
326 
`define DDR3_BOARD_2AGX125N // ARRIAII BOARD 2AGX125N
327 
//=end
328 
`ifdef DDR3
329 
`ifdef DDR3_BOARD_2AGX125N
330 
`define WB_ADR_SIZE 30
331 
`endif
332 
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.