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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [versatile_mem_ctrl_top.v] - Blame information for rev 112

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1 111 unneback 
/*
2 
module `BASE`MODULE (
3 
`undef MODULE
4 
        // wishbone slave side
5 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
6 
        // wishbone master side
7 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
8 
 
9 
`ifdef WB3_ARBITER_TYPE1
10 
`define MODULE wb3_arbiter_type1
11 
module `BASE`MODULE (
12 
`undef MODULE
13 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
14 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
15 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
16 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
17 
    wb_clk, wb_rst
18 
);
19 
*/
20 
//`include "versatile_mem_ctrl_defines.v"
21 
`define MODULE top
22 
module `BASE`MODULE (
23 
`undef MODULE
24 
    input  [31:0] wbs_1_dat_i,
25 
    input  [`WB_ADR_SIZE-1:2] wbs_1_adr_i,
26 
    input   [3:0] wbs_1_sel_i,
27 
    input   [2:0] wbs_1_cti_i,
28 
    input   [1:0] wbs_1_bte_i,
29 
    input         wbs_1_we_i,
30 
    input         wbs_1_stb_i,
31 
    input         wbs_1_cyc_i,
32 
    output [31:0] wbs_1_dat_o,
33 
    output        wbs_1_ack_o,
34 
    input         wbs_1_clk_i,
35 
    input         wbs_1_rst_i,
36 
`ifdef WB_GRPS_2
37 
    input  [31:0] wbs_2_dat_i,
38 
    input  [`WB_ADR_SIZE-1:2] wbs_2_adr_i,
39 
    input   [3:0] wbs_2_sel_i,
40 
    input   [2:0] wbs_2_cti_i,
41 
    input   [1:0] wbs_2_bte_i,
42 
    input         wbs_2_we_i,
43 
    input         wbs_2_stb_i,
44 
    input         wbs_2_cyc_i,
45 
    output [31:0] wbs_2_dat_o,
46 
    output        wbs_2_ack_o,
47 
    input         wbs_2_clk_i,
48 
    input         wbs_2_rst_i,
49 
`endif
50 
`ifdef WB_GRPS_3
51 
    input  [31:0] wbs_3_dat_i,
52 
    input  [`WB_ADR_SIZE-1:2] wbs_3_adr_i,
53 
    input   [3:0] wbs_3_sel_i,
54 
    input   [2:0] wbs_3_cti_i,
55 
    input   [1:0] wbs_3_bte_i,
56 
    input         wbs_3_we_i,
57 
    input         wbs_3_stb_i,
58 
    input         wbs_3_cyc_i,
59 
    output [31:0] wbs_3_dat_o,
60 
    output        wbs_3_ack_o,
61 
    input         wbs_3_clk_i,
62 
    input         wbs_3_rst_i,
63 
`endif
64 
`ifdef WB_GRPS_4
65 
    input  [31:0] wbs_4_dat_i,
66 
    input  [`WB_ADR_SIZE-1:2] wbs_4_adr_i,
67 
    input   [3:0] wbs_4_sel_i,
68 
    input   [2:0] wbs_4_cti_i,
69 
    input   [1:0] wbs_4_bte_i,
70 
    input         wbs_4_we_i,
71 
    input         wbs_4_stb_i,
72 
    input         wbs_4_cyc_i,
73 
    output [31:0] wbs_4_dat_o,
74 
    output        wbs_4_ack_o,
75 
    input         wbs_4_clk_i,
76 
    input         wbs_4_rst_i,
77 
`endif
78 
`ifdef WB_GRPS_5
79 
    input  [31:0] wbs_5_dat_i,
80 
    input  [`WB_ADR_SIZE-1:2] wbs_5_adr_i,
81 
    input   [3:0] wbs_5_sel_i,
82 
    input   [2:0] wbs_5_cti_i,
83 
    input   [1:0] wbs_5_bte_i,
84 
    input         wbs_5_we_i,
85 
    input         wbs_5_stb_i,
86 
    input         wbs_5_cyc_i,
87 
    output [31:0] wbs_5_dat_o,
88 
    output        wbs_5_ack_o,
89 
    input         wbs_5_clk_i,
90 
    input         wbs_5_rst_i,
91 
`endif
92 
`ifdef WB_GRPS_6
93 
    input  [31:0] wbs_6_dat_i,
94 
    input  [`WB_ADR_SIZE-1:2] wbs_6_adr_i,
95 
    input   [3:0] wbs_6_sel_i,
96 
    input   [2:0] wbs_6_cti_i,
97 
    input   [1:0] wbs_6_bte_i,
98 
    input         wbs_6_we_i,
99 
    input         wbs_6_stb_i,
100 
    input         wbs_6_cyc_i,
101 
    output [31:0] wbs_6_dat_o,
102 
    output        wbs_6_ack_o,
103 
    input         wbs_6_clk_i,
104 
    input         wbs_6_rst_i,
105 
`endif
106 
`ifdef WB_GRPS_7
107 
    input  [31:0] wbs_7_dat_i,
108 
    input  [`WB_ADR_SIZE-1:2] wbs_7_adr_i,
109 
    input   [3:0] wbs_7_sel_i,
110 
    input   [2:0] wbs_7_cti_i,
111 
    input   [1:0] wbs_7_bte_i,
112 
    input         wbs_7_we_i,
113 
    input         wbs_7_stb_i,
114 
    input         wbs_7_cyc_i,
115 
    output [31:0] wbs_7_dat_o,
116 
    output        wbs_7_ack_o,
117 
    input         wbs_7_clk_i,
118 
    input         wbs_7_rst_i,
119 
`endif
120 
`ifdef WB_GRPS_8
121 
    input  [31:0] wbs_8_dat_i,
122 
    input  [`WB_ADR_SIZE-1:2] wbs_8_adr_i,
123 
    input   [3:0] wbs_8_sel_i,
124 
    input   [2:0] wbs_8_cti_i,
125 
    input   [1:0] wbs_8_bte_i,
126 
    input         wbs_8_we_i,
127 
    input         wbs_8_stb_i,
128 
    input         wbs_8_cyc_i,
129 
    output [31:0] wbs_8_dat_o,
130 
    output        wbs_8_ack_o,
131 
    input         wbs_8_clk_i,
132 
    input         wbs_8_rst_i,
133 
`endif
134 
`ifdef SDR
135 
    output  [1:0] ba,
136 
    output [12:0] a,
137 
    output  [2:0] cmd,
138 
    output       cke,
139 
    output       cs_n,
140 
    output [`SDR_SDRAM_DATA_WIDTH/8-1:0] dqm,
141 
    output [`SDR_SDRAM_DATA_WIDTH-1:0] dq_o,
142 
    input  [`SDR_SDRAM_DATA_WIDTH-1:0] dq_i,
143 
    output dq_oe,
144 
`endif
145 112 unneback 
`ifdef DDR3
146 
    output [12:0] mem_addr,
147 
    output [2:0] mem_ba,
148 
    output mem_cas_n,
149 
    output mem_cke,
150 
    inout mem_clk,
151 
    inout mem_clk_n,
152 
    output mem_cs_n,
153 
    output [1:0] mem_dm,
154 
    inout [15:0] mem_dq,
155 
    inout [1:0] mem_dqs,
156 
    inout [1:0] mem_dqsn,
157 
    output mem_odt,
158 
    output mem_ras_n,
159 
    input mem_reset_n,
160 
    output mem_we_n,
161 
    input mem_ref_clk, /* 100MHz */
162 
`endif
163 111 unneback 
    input mem_clk_i,
164 
    input mem_rst_i
165 
);
166 
 
167 
wire  [31:0] wbm_1_dat_o;
168 
wire  [`WB_ADR_SIZE-1:2] wbm_1_adr_o;
169 
wire   [3:0] wbm_1_sel_o;
170 
wire   [2:0] wbm_1_cti_o;
171 
wire   [1:0] wbm_1_bte_o;
172 
wire         wbm_1_we_o;
173 
wire         wbm_1_stb_o;
174 
wire         wbm_1_cyc_o;
175 
wire  [31:0] wbm_1_dat_i;
176 
wire         wbm_1_ack_i;
177 
`ifdef WB_GRPS_2
178 
wire  [31:0] wbm_2_dat_o;
179 
wire  [`WB_ADR_SIZE-1:2] wbm_2_adr_o;
180 
wire   [3:0] wbm_2_sel_o;
181 
wire   [2:0] wbm_2_cti_o;
182 
wire   [1:0] wbm_2_bte_o;
183 
wire         wbm_2_we_o;
184 
wire         wbm_2_stb_o;
185 
wire         wbm_2_cyc_o;
186 
wire  [31:0] wbm_2_dat_i;
187 
wire         wbm_2_ack_i;
188 
`endif
189 
`ifdef WB_GRPS_3
190 
wire  [31:0] wbm_3_dat_o;
191 
wire  [`WB_ADR_SIZE-1:2] wbm_3_adr_o;
192 
wire   [3:0] wbm_3_sel_o;
193 
wire   [2:0] wbm_3_cti_o;
194 
wire   [1:0] wbm_3_bte_o;
195 
wire         wbm_3_we_o;
196 
wire         wbm_3_stb_o;
197 
wire         wbm_3_cyc_o;
198 
wire  [31:0] wbm_3_dat_i;
199 
wire         wbm_3_ack_i;
200 
`endif
201 
`ifdef WB_GRPS_4
202 
wire  [31:0] wbm_4_dat_o;
203 
wire  [`WB_ADR_SIZE-1:2] wbm_4_adr_o;
204 
wire   [3:0] wbm_4_sel_o;
205 
wire   [2:0] wbm_4_cti_o;
206 
wire   [1:0] wbm_4_bte_o;
207 
wire         wbm_4_we_o;
208 
wire         wbm_4_stb_o;
209 
wire         wbm_4_cyc_o;
210 
wire  [31:0] wbm_4_dat_i;
211 
wire         wbm_4_ack_i;
212 
`endif
213 
`ifdef WB_GRPS_5
214 
wire  [31:0] wbm_5_dat_o;
215 
wire  [`WB_ADR_SIZE-1:2] wbm_5_adr_o;
216 
wire   [3:0] wbm_5_sel_o;
217 
wire   [2:0] wbm_5_cti_o;
218 
wire   [1:0] wbm_5_bte_o;
219 
wire         wbm_5_we_o;
220 
wire         wbm_5_stb_o;
221 
wire         wbm_5_cyc_o;
222 
wire  [31:0] wbm_5_dat_i;
223 
wire         wbm_5_ack_i;
224 
`endif
225 
`ifdef WB_GRPS_6
226 
wire  [31:0] wbm_6_dat_o;
227 
wire  [`WB_ADR_SIZE-1:2] wbm_6_adr_o;
228 
wire   [3:0] wbm_6_sel_o;
229 
wire   [2:0] wbm_6_cti_o;
230 
wire   [1:0] wbm_6_bte_o;
231 
wire         wbm_6_we_o;
232 
wire         wbm_6_stb_o;
233 
wire         wbm_6_cyc_o;
234 
wire  [31:0] wbm_6_dat_i;
235 
wire         wbm_6_ack_i;
236 
`endif
237 
`ifdef WB_GRPS_7
238 
wire  [31:0] wbm_7_dat_o;
239 
wire  [`WB_ADR_SIZE-1:2] wbm_7_adr_o;
240 
wire   [3:0] wbm_7_sel_o;
241 
wire   [2:0] wbm_7_cti_o;
242 
wire   [1:0] wbm_7_bte_o;
243 
wire         wbm_7_we_o;
244 
wire         wbm_7_stb_o;
245 
wire         wbm_7_cyc_o;
246 
wire  [31:0] wbm_7_dat_i;
247 
wire         wbm_7_ack_i;
248 
`endif
249 
`ifdef WB_GRPS_8
250 
wire  [31:0] wbm_8_dat_o;
251 
wire  [`WB_ADR_SIZE-1:2] wbm_8_adr_o;
252 
wire   [3:0] wbm_8_sel_o;
253 
wire   [2:0] wbm_8_cti_o;
254 
wire   [1:0] wbm_8_bte_o;
255 
wire         wbm_8_we_o;
256 
wire         wbm_8_stb_o;
257 
wire         wbm_8_cyc_o;
258 
wire  [31:0] wbm_8_dat_i;
259 
wire         wbm_8_ack_i;
260 
`endif
261 
wire  [31:0] wbs_dat_i;
262 
wire  [`WB_ADR_SIZE-1:2] wbs_adr_i;
263 
wire   [3:0] wbs_sel_i;
264 
wire   [2:0] wbs_cti_i;
265 
wire   [1:0] wbs_bte_i;
266 
wire         wbs_we_i;
267 
wire         wbs_stb_i;
268 
wire         wbs_cyc_i;
269 
wire  [31:0] wbs_dat_o;
270 
wire         wbs_ack_o;
271 
 
272 
`define MODULE wb3wb3_bridge
273 
 
274 
`ifdef WB1_CLK
275 
wire [31-(`WB_ADR_SIZE):0] dummy1;
276 
`VLBASE`MODULE wbwb1 (
277 
    // wishbone slave side
278 
    .wbs_dat_i(wbs_1_dat_i),
279 
    .wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_1_adr_i}),
280 
    .wbs_sel_i(wbs_1_sel_i),
281 
    .wbs_bte_i(wbs_1_bte_i),
282 
    .wbs_cti_i(wbs_1_cti_i),
283 
    .wbs_we_i (wbs_1_we_i),
284 
    .wbs_cyc_i(wbs_1_cyc_i),
285 
    .wbs_stb_i(wbs_1_stb_i),
286 
    .wbs_dat_o(wbs_1_dat_o),
287 
    .wbs_ack_o(wbs_1_ack_o),
288 
    .wbs_clk(wbs_1_clk_i),
289 
    .wbs_rst(wbs_1_rst_i),
290 
    // wishbone master side
291 
    .wbm_dat_o(wbm_1_dat_o),
292 
    .wbm_adr_o({dummy1,wbm_1_adr_o}),
293 
    .wbm_sel_o(wbm_1_sel_o),
294 
    .wbm_bte_o(wbm_1_bte_o),
295 
    .wbm_cti_o(wbm_1_cti_o),
296 
    .wbm_we_o(wbm_1_we_o),
297 
    .wbm_cyc_o(wbm_1_cyc_o),
298 
    .wbm_stb_o(wbm_1_stb_o),
299 
    .wbm_dat_i(wbm_1_dat_i),
300 
    .wbm_ack_i(wbm_1_ack_i),
301 
    .wbm_clk(mem_clk_i),
302 
    .wbm_rst(mem_rst_i));
303 
`endif
304 
`ifdef WB1_MEM_CLK
305 
    assign wbm_1_dat_o = wbs_1_dat_i;
306 
    assign wbm_1_adr_o = wbs_1_adr_i;
307 
    assign wbm_1_sel_o = wbs_1_sel_i;
308 
    assign wbm_1_bte_o = wbs_1_bte_i;
309 
    assign wbm_1_cti_o = wbs_1_cti_i;
310 
    assign wbm_1_we_o  = wbs_1_we_i;
311 
    assign wbm_1_cyc_o = wbs_1_cyc_i;
312 
    assign wbm_1_stb_o = wbs_1_stb_i;
313 
    assign wbs_1_dat_o = wbm_1_dat_i;
314 
    assign wbs_1_ack_o = wbm_1_ack_i;
315 
`endif
316 
 
317 
`ifdef WB_GRPS_2
318 
`ifdef WB2_CLK
319 
wire [31-(`WB_ADR_SIZE):0] dummy2;
320 
`VLBASE`MODULE wbwb2 (
321 
    // wishbone slave side
322 
    .wbs_dat_i(wbs_2_dat_i),
323 
    .wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_2_adr_i}),
324 
    .wbs_sel_i(wbs_2_sel_i),
325 
    .wbs_bte_i(wbs_2_bte_i),
326 
    .wbs_cti_i(wbs_2_cti_i),
327 
    .wbs_we_i (wbs_2_we_i),
328 
    .wbs_cyc_i(wbs_2_cyc_i),
329 
    .wbs_stb_i(wbs_2_stb_i),
330 
    .wbs_dat_o(wbs_2_dat_o),
331 
    .wbs_ack_o(wbs_2_ack_o),
332 
    .wbs_clk(wbs_2_clk_i),
333 
    .wbs_rst(wbs_2_rst_i),
334 
    // wishbone master side
335 
    .wbm_dat_o(wbm_2_dat_o),
336 
    .wbm_adr_o({dummy2,wbm_2_adr_o}),
337 
    .wbm_sel_o(wbm_2_sel_o),
338 
    .wbm_bte_o(wbm_2_bte_o),
339 
    .wbm_cti_o(wbm_2_cti_o),
340 
    .wbm_we_o(wbm_2_we_o),
341 
    .wbm_cyc_o(wbm_2_cyc_o),
342 
    .wbm_stb_o(wbm_2_stb_o),
343 
    .wbm_dat_i(wbm_2_dat_i),
344 
    .wbm_ack_i(wbm_2_ack_i),
345 
    .wbm_clk(mem_clk_i),
346 
    .wbm_rst(mem_rst_i));
347 
`endif
348 
`ifdef WB2_MEM_CLK
349 
    assign wbm_2_dat_o = wbs_2_dat_i;
350 
    assign wbm_2_adr_o = wbs_2_adr_i;
351 
    assign wbm_2_sel_o = wbs_2_sel_i;
352 
    assign wbm_2_bte_o = wbs_2_bte_i;
353 
    assign wbm_2_cti_o = wbs_2_cti_i;
354 
    assign wbm_2_we_o  = wbs_2_we_i;
355 
    assign wbm_2_cyc_o = wbs_2_cyc_i;
356 
    assign wbm_2_stb_o = wbs_2_stb_i;
357 
    assign wbs_2_dat_o = wbm_2_dat_i;
358 
    assign wbs_2_ack_o = wbm_2_ack_i;
359 
`endif
360 
`endif
361 
 
362 
`ifdef WB_GRPS_3
363 
`ifdef WB3_CLK
364 
wire [31-(`WB_ADR_SIZE):0] dummy3;
365 
`VLBASE`MODULE wbwb3 (
366 
    // wishbone slave side
367 
    .wbs_dat_i(wbs_3_dat_i),
368 
    .wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_3_adr_i}),
369 
    .wbs_sel_i(wbs_3_sel_i),
370 
    .wbs_bte_i(wbs_3_bte_i),
371 
    .wbs_cti_i(wbs_3_cti_i),
372 
    .wbs_we_i (wbs_3_we_i),
373 
    .wbs_cyc_i(wbs_3_cyc_i),
374 
    .wbs_stb_i(wbs_3_stb_i),
375 
    .wbs_dat_o(wbs_3_dat_o),
376 
    .wbs_ack_o(wbs_3_ack_o),
377 
    .wbs_clk(wbs_3_clk_i),
378 
    .wbs_rst(wbs_3_rst_i),
379 
    // wishbone master side
380 
    .wbm_dat_o(wbm_3_dat_o),
381 
    .wbm_adr_o({dummy3,wbm_3_adr_o}),
382 
    .wbm_sel_o(wbm_3_sel_o),
383 
    .wbm_bte_o(wbm_3_bte_o),
384 
    .wbm_cti_o(wbm_3_cti_o),
385 
    .wbm_we_o(wbm_3_we_o),
386 
    .wbm_cyc_o(wbm_3_cyc_o),
387 
    .wbm_stb_o(wbm_3_stb_o),
388 
    .wbm_dat_i(wbm_3_dat_i),
389 
    .wbm_ack_i(wbm_3_ack_i),
390 
    .wbm_clk(mem_clk_i),
391 
    .wbm_rst(mem_rst_i));
392 
`endif
393 
`ifdef WB3_MEM_CLK
394 
    assign wbm_3_dat_o = wbs_3_dat_i;
395 
    assign wbm_3_adr_o = wbs_3_adr_i;
396 
    assign wbm_3_sel_o = wbs_3_sel_i;
397 
    assign wbm_3_bte_o = wbs_3_bte_i;
398 
    assign wbm_3_cti_o = wbs_3_cti_i;
399 
    assign wbm_3_we_o  = wbs_3_we_i;
400 
    assign wbm_3_cyc_o = wbs_3_cyc_i;
401 
    assign wbm_3_stb_o = wbs_3_stb_i;
402 
    assign wbs_3_dat_o = wbm_3_dat_i;
403 
    assign wbs_3_ack_o = wbm_3_ack_i;
404 
`endif
405 
`endif
406 
 
407 
`ifdef WB_GRPS_4
408 
`ifdef WB4_CLK
409 
wire [31-(`WB_ADR_SIZE):0] dummy4;
410 
`VLBASE`MODULE wbwb4 (
411 
    // wishbone slave side
412 
    .wbs_dat_i(wbs_4_dat_i),
413 
    .wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_4_adr_i}),
414 
    .wbs_sel_i(wbs_4_sel_i),
415 
    .wbs_bte_i(wbs_4_bte_i),
416 
    .wbs_cti_i(wbs_4_cti_i),
417 
    .wbs_we_i (wbs_4_we_i),
418 
    .wbs_cyc_i(wbs_4_cyc_i),
419 
    .wbs_stb_i(wbs_4_stb_i),
420 
    .wbs_dat_o(wbs_4_dat_o),
421 
    .wbs_ack_o(wbs_4_ack_o),
422 
    .wbs_clk(wbs_4_clk_i),
423 
    .wbs_rst(wbs_4_rst_i),
424 
    // wishbone master side
425 
    .wbm_dat_o(wbm_4_dat_o),
426 
    .wbm_adr_o({dummy4,wbm_4_adr_o}),
427 
    .wbm_sel_o(wbm_4_sel_o),
428 
    .wbm_bte_o(wbm_4_bte_o),
429 
    .wbm_cti_o(wbm_4_cti_o),
430 
    .wbm_we_o(wbm_4_we_o),
431 
    .wbm_cyc_o(wbm_4_cyc_o),
432 
    .wbm_stb_o(wbm_4_stb_o),
433 
    .wbm_dat_i(wbm_4_dat_i),
434 
    .wbm_ack_i(wbm_4_ack_i),
435 
    .wbm_clk(mem_clk_i),
436 
    .wbm_rst(mem_rst_i));
437 
`endif
438 
`ifdef WB4_MEM_CLK
439 
    assign wbm_4_dat_o = wbs_4_dat_i;
440 
    assign wbm_4_adr_o = wbs_4_adr_i;
441 
    assign wbm_4_sel_o = wbs_4_sel_i;
442 
    assign wbm_4_bte_o = wbs_4_bte_i;
443 
    assign wbm_4_cti_o = wbs_4_cti_i;
444 
    assign wbm_4_we_o  = wbs_4_we_i;
445 
    assign wbm_4_cyc_o = wbs_4_cyc_i;
446 
    assign wbm_4_stb_o = wbs_4_stb_i;
447 
    assign wbs_4_dat_o = wbm_4_dat_i;
448 
    assign wbs_4_ack_o = wbm_4_ack_i;
449 
`endif
450 
`endif
451 
 
452 
`ifdef WB_GRPS_5
453 
`ifdef WB5_CLK
454 
wire [31-(`WB_ADR_SIZE):0] dummy5;
455 
`VLBASE`MODULE wbwb5 (
456 
    // wishbone slave side
457 
    .wbs_dat_i(wbs_5_dat_i),
458 
    .wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_5_adr_i}),
459 
    .wbs_sel_i(wbs_5_sel_i),
460 
    .wbs_bte_i(wbs_5_bte_i),
461 
    .wbs_cti_i(wbs_5_cti_i),
462 
    .wbs_we_i (wbs_5_we_i),
463 
    .wbs_cyc_i(wbs_5_cyc_i),
464 
    .wbs_stb_i(wbs_5_stb_i),
465 
    .wbs_dat_o(wbs_5_dat_o),
466 
    .wbs_ack_o(wbs_5_ack_o),
467 
    .wbs_clk(wbs_5_clk_i),
468 
    .wbs_rst(wbs_5_rst_i),
469 
    // wishbone master side
470 
    .wbm_dat_o(wbm_5_dat_o),
471 
    .wbm_adr_o({dummy5,wbm_5_adr_o}),
472 
    .wbm_sel_o(wbm_5_sel_o),
473 
    .wbm_bte_o(wbm_5_bte_o),
474 
    .wbm_cti_o(wbm_5_cti_o),
475 
    .wbm_we_o(wbm_5_we_o),
476 
    .wbm_cyc_o(wbm_5_cyc_o),
477 
    .wbm_stb_o(wbm_5_stb_o),
478 
    .wbm_dat_i(wbm_5_dat_i),
479 
    .wbm_ack_i(wbm_5_ack_i),
480 
    .wbm_clk(mem_clk_i),
481 
    .wbm_rst(mem_rst_i));
482 
`endif
483 
`ifdef WB5_MEM_CLK
484 
    assign wbm_5_dat_o = wbs_5_dat_i;
485 
    assign wbm_5_adr_o = wbs_5_adr_i;
486 
    assign wbm_5_sel_o = wbs_5_sel_i;
487 
    assign wbm_5_bte_o = wbs_5_bte_i;
488 
    assign wbm_5_cti_o = wbs_5_cti_i;
489 
    assign wbm_5_we_o  = wbs_5_we_i;
490 
    assign wbm_5_cyc_o = wbs_5_cyc_i;
491 
    assign wbm_5_stb_o = wbs_5_stb_i;
492 
    assign wbs_5_dat_o = wbm_5_dat_i;
493 
    assign wbs_5_ack_o = wbm_5_ack_i;
494 
`endif
495 
`endif
496 
 
497 
`ifdef WB_GRPS_6
498 
`ifdef WB6_CLK
499 
wire [31-(`WB_ADR_SIZE):0] dummy6;
500 
`VLBASE`MODULE wbwb6 (
501 
    // wishbone slave side
502 
    .wbs_dat_i(wbs_6_dat_i),
503 
    .wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_6_adr_i}),
504 
    .wbs_sel_i(wbs_6_sel_i),
505 
    .wbs_bte_i(wbs_6_bte_i),
506 
    .wbs_cti_i(wbs_6_cti_i),
507 
    .wbs_we_i (wbs_6_we_i),
508 
    .wbs_cyc_i(wbs_6_cyc_i),
509 
    .wbs_stb_i(wbs_6_stb_i),
510 
    .wbs_dat_o(wbs_6_dat_o),
511 
    .wbs_ack_o(wbs_6_ack_o),
512 
    .wbs_clk(wbs_6_clk_i),
513 
    .wbs_rst(wbs_6_rst_i),
514 
    // wishbone master side
515 
    .wbm_dat_o(wbm_6_dat_o),
516 
    .wbm_adr_o({dummy6,wbm_6_adr_o}),
517 
    .wbm_sel_o(wbm_6_sel_o),
518 
    .wbm_bte_o(wbm_6_bte_o),
519 
    .wbm_cti_o(wbm_6_cti_o),
520 
    .wbm_we_o(wbm_6_we_o),
521 
    .wbm_cyc_o(wbm_6_cyc_o),
522 
    .wbm_stb_o(wbm_6_stb_o),
523 
    .wbm_dat_i(wbm_6_dat_i),
524 
    .wbm_ack_i(wbm_6_ack_i),
525 
    .wbm_clk(mem_clk_i),
526 
    .wbm_rst(mem_rst_i));
527 
`endif
528 
`ifdef WB6_MEM_CLK
529 
    assign wbm_6_dat_o = wbs_6_dat_i;
530 
    assign wbm_6_adr_o = wbs_6_adr_i;
531 
    assign wbm_6_sel_o = wbs_6_sel_i;
532 
    assign wbm_6_bte_o = wbs_6_bte_i;
533 
    assign wbm_6_cti_o = wbs_6_cti_i;
534 
    assign wbm_6_we_o  = wbs_6_we_i;
535 
    assign wbm_6_cyc_o = wbs_6_cyc_i;
536 
    assign wbm_6_stb_o = wbs_6_stb_i;
537 
    assign wbs_6_dat_o = wbm_6_dat_i;
538 
    assign wbs_6_ack_o = wbm_6_ack_i;
539 
`endif
540 
`endif
541 
 
542 
`ifdef WB_GRPS_7
543 
`ifdef WB7_CLK
544 
wire [31-(`WB_ADR_SIZE):0] dummy7;
545 
`VLBASE`MODULE wbwb7 (
546 
    // wishbone slave side
547 
    .wbs_dat_i(wbs_7_dat_i),
548 
    .wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_7_adr_i}),
549 
    .wbs_sel_i(wbs_7_sel_i),
550 
    .wbs_bte_i(wbs_7_bte_i),
551 
    .wbs_cti_i(wbs_7_cti_i),
552 
    .wbs_we_i (wbs_7_we_i),
553 
    .wbs_cyc_i(wbs_7_cyc_i),
554 
    .wbs_stb_i(wbs_7_stb_i),
555 
    .wbs_dat_o(wbs_7_dat_o),
556 
    .wbs_ack_o(wbs_7_ack_o),
557 
    .wbs_clk(wbs_7_clk_i),
558 
    .wbs_rst(wbs_7_rst_i),
559 
    // wishbone master side
560 
    .wbm_dat_o(wbm_7_dat_o),
561 
    .wbm_adr_o({dummy7,wbm_7_adr_o}),
562 
    .wbm_sel_o(wbm_7_sel_o),
563 
    .wbm_bte_o(wbm_7_bte_o),
564 
    .wbm_cti_o(wbm_7_cti_o),
565 
    .wbm_we_o(wbm_7_we_o),
566 
    .wbm_cyc_o(wbm_7_cyc_o),
567 
    .wbm_stb_o(wbm_7_stb_o),
568 
    .wbm_dat_i(wbm_7_dat_i),
569 
    .wbm_ack_i(wbm_7_ack_i),
570 
    .wbm_clk(mem_clk_i),
571 
    .wbm_rst(mem_rst_i));
572 
`endif
573 
`ifdef WB7_MEM_CLK
574 
    assign wbm_7_dat_o = wbs_7_dat_i;
575 
    assign wbm_7_adr_o = wbs_7_adr_i;
576 
    assign wbm_7_sel_o = wbs_7_sel_i;
577 
    assign wbm_7_bte_o = wbs_7_bte_i;
578 
    assign wbm_7_cti_o = wbs_7_cti_i;
579 
    assign wbm_7_we_o  = wbs_7_we_i;
580 
    assign wbm_7_cyc_o = wbs_7_cyc_i;
581 
    assign wbm_7_stb_o = wbs_7_stb_i;
582 
    assign wbs_7_dat_o = wbm_7_dat_i;
583 
    assign wbs_7_ack_o = wbm_7_ack_i;
584 
`endif
585 
`endif
586 
 
587 
`ifdef WB_GRPS_8
588 
`ifdef WB8_CLK
589 
wire [31-(`WB_ADR_SIZE):0] dummy8;
590 
`VLBASE`MODULE wbwb8 (
591 
    // wishbone slave side
592 
    .wbs_dat_i(wbs_8_dat_i),
593 
    .wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_8_adr_i}),
594 
    .wbs_sel_i(wbs_8_sel_i),
595 
    .wbs_bte_i(wbs_8_bte_i),
596 
    .wbs_cti_i(wbs_8_cti_i),
597 
    .wbs_we_i (wbs_8_we_i),
598 
    .wbs_cyc_i(wbs_8_cyc_i),
599 
    .wbs_stb_i(wbs_8_stb_i),
600 
    .wbs_dat_o(wbs_8_dat_o),
601 
    .wbs_ack_o(wbs_8_ack_o),
602 
    .wbs_clk(wbs_8_clk_i),
603 
    .wbs_rst(wbs_8_rst_i),
604 
    // wishbone master side
605 
    .wbm_dat_o(wbm_8_dat_o),
606 
    .wbm_adr_o({dummy8,wbm_8_adr_o}),
607 
    .wbm_sel_o(wbm_8_sel_o),
608 
    .wbm_bte_o(wbm_8_bte_o),
609 
    .wbm_cti_o(wbm_8_cti_o),
610 
    .wbm_we_o(wbm_8_we_o),
611 
    .wbm_cyc_o(wbm_8_cyc_o),
612 
    .wbm_stb_o(wbm_8_stb_o),
613 
    .wbm_dat_i(wbm_8_dat_i),
614 
    .wbm_ack_i(wbm_8_ack_i),
615 
    .wbm_clk(mem_clk_i),
616 
    .wbm_rst(mem_rst_i));
617 
`endif
618 
`ifdef WB8_MEM_CLK
619 
    assign wbm_8_dat_o = wbs_8_dat_i;
620 
    assign wbm_8_adr_o = wbs_8_adr_i;
621 
    assign wbm_8_sel_o = wbs_8_sel_i;
622 
    assign wbm_8_bte_o = wbs_8_bte_i;
623 
    assign wbm_8_cti_o = wbs_8_cti_i;
624 
    assign wbm_8_we_o  = wbs_8_we_i;
625 
    assign wbm_8_cyc_o = wbs_8_cyc_i;
626 
    assign wbm_8_stb_o = wbs_8_stb_i;
627 
    assign wbs_8_dat_o = wbm_8_dat_i;
628 
    assign wbs_8_ack_o = wbm_8_ack_i;
629 
`endif
630 
`endif
631 
 
632 
`undef MODULE
633 
 
634 
`ifdef WB_GRPS_2
635 
// we have at least two ports and need an arbiter
636 
`define MODULE wb3_arbiter_type1
637 
`VLBASE`MODULE
638 
# (.nr_of_ports(`NR_OF_PORTS), .adr_size(`WB_ADR_SIZE))
639 
wb0(
640 
`undef MODULE
641 
    .wbm_dat_o({wbm_1_dat_o,wbm_2_dat_o
642 
`ifdef WB_GRPS_3
643 
    ,wbm_3_dat_o
644 
`endif
645 
`ifdef WB_GRPS_4
646 
    ,wbm_4_dat_o
647 
`endif
648 
`ifdef WB_GRPS_5
649 
    ,wbm_5_dat_o
650 
`endif
651 
`ifdef WB_GRPS_6
652 
    ,wbm_6_dat_o
653 
`endif
654 
`ifdef WB_GRPS_7
655 
    ,wbm_7_dat_o
656 
`endif
657 
`ifdef WB_GRPS_8
658 
    ,wbm_8_dat_o
659 
`endif
660 
    }),
661 
    .wbm_adr_o({wbm_1_adr_o,wbm_2_adr_o
662 
`ifdef WB_GRPS_3
663 
    ,wbm_3_adr_o
664 
`endif
665 
`ifdef WB_GRPS_4
666 
    ,wbm_4_adr_o
667 
`endif
668 
`ifdef WB_GRPS_5
669 
    ,wbm_5_adr_o
670 
`endif
671 
`ifdef WB_GRPS_6
672 
    ,wbm_6_adr_o
673 
`endif
674 
`ifdef WB_GRPS_7
675 
    ,wbm_7_adr_o
676 
`endif
677 
`ifdef WB_GRPS_8
678 
    ,wbm_8_adr_o
679 
`endif
680 
    }),
681 
    .wbm_sel_o({wbm_1_sel_o,wbm_2_sel_o
682 
`ifdef WB_GRPS_3
683 
    ,wbm_3_sel_o
684 
`endif
685 
`ifdef WB_GRPS_4
686 
    ,wbm_4_sel_o
687 
`endif
688 
`ifdef WB_GRPS_5
689 
    ,wbm_5_sel_o
690 
`endif
691 
`ifdef WB_GRPS_6
692 
    ,wbm_6_sel_o
693 
`endif
694 
`ifdef WB_GRPS_7
695 
    ,wbm_7_sel_o
696 
`endif
697 
`ifdef WB_GRPS_8
698 
    ,wbm_8_sel_o
699 
`endif
700 
    }),
701 
    .wbm_cti_o({wbm_1_cti_o,wbm_2_cti_o
702 
`ifdef WB_GRPS_3
703 
    ,wbm_3_cti_o
704 
`endif
705 
`ifdef WB_GRPS_4
706 
    ,wbm_4_cti_o
707 
`endif
708 
`ifdef WB_GRPS_5
709 
    ,wbm_5_cti_o
710 
`endif
711 
`ifdef WB_GRPS_6
712 
    ,wbm_6_cti_o
713 
`endif
714 
`ifdef WB_GRPS_7
715 
    ,wbm_7_cti_o
716 
`endif
717 
`ifdef WB_GRPS_8
718 
    ,wbm_8_cti_o
719 
`endif
720 
    }),
721 
    .wbm_bte_o({wbm_1_bte_o,wbm_2_bte_o
722 
`ifdef WB_GRPS_3
723 
    ,wbm_3_bte_o
724 
`endif
725 
`ifdef WB_GRPS_4
726 
    ,wbm_4_bte_o
727 
`endif
728 
`ifdef WB_GRPS_5
729 
    ,wbm_5_bte_o
730 
`endif
731 
`ifdef WB_GRPS_6
732 
    ,wbm_6_bte_o
733 
`endif
734 
`ifdef WB_GRPS_7
735 
    ,wbm_7_bte_o
736 
`endif
737 
`ifdef WB_GRPS_8
738 
    ,wbm_8_bte_o
739 
`endif
740 
    }),
741 
    .wbm_we_o({wbm_1_we_o,wbm_2_we_o
742 
`ifdef WB_GRPS_3
743 
    ,wbm_3_we_o
744 
`endif
745 
`ifdef WB_GRPS_4
746 
    ,wbm_4_we_o
747 
`endif
748 
`ifdef WB_GRPS_5
749 
    ,wbm_5_we_o
750 
`endif
751 
`ifdef WB_GRPS_6
752 
    ,wbm_6_we_o
753 
`endif
754 
`ifdef WB_GRPS_7
755 
    ,wbm_7_we_o
756 
`endif
757 
`ifdef WB_GRPS_8
758 
    ,wbm_8_we_o
759 
`endif
760 
    }),
761 
    .wbm_stb_o({wbm_1_stb_o,wbm_2_stb_o
762 
`ifdef WB_GRPS_3
763 
    ,wbm_3_stb_o
764 
`endif
765 
`ifdef WB_GRPS_4
766 
    ,wbm_4_stb_o
767 
`endif
768 
`ifdef WB_GRPS_5
769 
    ,wbm_5_stb_o
770 
`endif
771 
`ifdef WB_GRPS_6
772 
    ,wbm_6_stb_o
773 
`endif
774 
`ifdef WB_GRPS_7
775 
    ,wbm_7_stb_o
776 
`endif
777 
`ifdef WB_GRPS_8
778 
    ,wbm_8_stb_o
779 
`endif
780 
    }),
781 
    .wbm_cyc_o({wbm_1_cyc_o,wbm_2_cyc_o
782 
`ifdef WB_GRPS_3
783 
    ,wbm_3_cyc_o
784 
`endif
785 
`ifdef WB_GRPS_4
786 
    ,wbm_4_cyc_o
787 
`endif
788 
`ifdef WB_GRPS_5
789 
    ,wbm_5_cyc_o
790 
`endif
791 
`ifdef WB_GRPS_6
792 
    ,wbm_6_cyc_o
793 
`endif
794 
`ifdef WB_GRPS_7
795 
    ,wbm_7_cyc_o
796 
`endif
797 
`ifdef WB_GRPS_8
798 
    ,wbm_8_cyc_o
799 
`endif
800 
    }),
801 
    .wbm_dat_i({wbm_1_dat_i,wbm_2_dat_i
802 
`ifdef WB_GRPS_3
803 
    ,wbm_3_dat_i
804 
`endif
805 
`ifdef WB_GRPS_4
806 
    ,wbm_4_dat_i
807 
`endif
808 
`ifdef WB_GRPS_5
809 
    ,wbm_5_dat_i
810 
`endif
811 
`ifdef WB_GRPS_6
812 
    ,wbm_6_dat_i
813 
`endif
814 
`ifdef WB_GRPS_7
815 
    ,wbm_7_dat_i
816 
`endif
817 
`ifdef WB_GRPS_8
818 
    ,wbm_8_dat_i
819 
`endif
820 
    }),
821 
    .wbm_ack_i({wbm_1_ack_i,wbm_2_ack_i
822 
`ifdef WB_GRPS_3
823 
    ,wbm_3_ack_i
824 
`endif
825 
`ifdef WB_GRPS_4
826 
    ,wbm_4_ack_i
827 
`endif
828 
`ifdef WB_GRPS_5
829 
    ,wbm_5_ack_i
830 
`endif
831 
`ifdef WB_GRPS_6
832 
    ,wbm_6_ack_i
833 
`endif
834 
`ifdef WB_GRPS_7
835 
    ,wbm_7_ack_i
836 
`endif
837 
`ifdef WB_GRPS_8
838 
    ,wbm_8_ack_i
839 
`endif
840 
    }),
841 
    .wbm_err_i({wbm_1_err_i,wbm_2_err_i
842 
`ifdef WB_GRPS_3
843 
    ,wbm_3_err_i
844 
`endif
845 
`ifdef WB_GRPS_4
846 
    ,wbm_4_err_i
847 
`endif
848 
`ifdef WB_GRPS_5
849 
    ,wbm_5_err_i
850 
`endif
851 
`ifdef WB_GRPS_6
852 
    ,wbm_6_err_i
853 
`endif
854 
`ifdef WB_GRPS_7
855 
    ,wbm_7_err_i
856 
`endif
857 
`ifdef WB_GRPS_8
858 
    ,wbm_8_err_i
859 
`endif
860 
    }),
861 
    .wbm_rty_i({wbm_1_rty_i,wbm_2_rty_i
862 
`ifdef WB_GRPS_3
863 
    ,wbm_3_rty_i
864 
`endif
865 
`ifdef WB_GRPS_4
866 
    ,wbm_4_rty_i
867 
`endif
868 
`ifdef WB_GRPS_5
869 
    ,wbm_5_rty_i
870 
`endif
871 
`ifdef WB_GRPS_6
872 
    ,wbm_6_rty_i
873 
`endif
874 
`ifdef WB_GRPS_7
875 
    ,wbm_7_rty_i
876 
`endif
877 
`ifdef WB_GRPS_8
878 
    ,wbm_8_rty_i
879 
`endif
880 
    }),
881 
    .wbs_dat_i(wbs_dat_i),
882 
    .wbs_adr_i(wbs_adr_i),
883 
    .wbs_sel_i(wbs_sel_i),
884 
    .wbs_cti_i(wbs_cti_i),
885 
    .wbs_bte_i(wbs_bte_i),
886 
    .wbs_we_i(wbs_we_i),
887 
    .wbs_stb_i(wbs_stb_i),
888 
    .wbs_cyc_i(wbs_cyc_i),
889 
    .wbs_dat_o(wbs_dat_o),
890 
    .wbs_ack_o(wbs_ack_o),
891 
    .wbs_err_o(wbs_err_o),
892 
    .wbs_rty_o(wbs_rty_o),
893 
    .wb_clk(mem_clk),
894 
    .wb_rst(mem_clk)
895 
);
896 
 
897 
`else
898 
// only one external port an no need for arbiter
899 
assign wbs_dat_i = wbm_dat_i;
900 
assign wbs_adr_i = wbm_adr_i;
901 
assign wbs_sel_i = wbm_sel_i;
902 
assign wbs_cti_i = wbm_cti_i;
903 
assign wbs_bte_i = wbm_bte_i;
904 
assign wbs_we_i  = wbm_we_i;
905 
assign wbs_stb_i = wbm_stb_i;
906 
assign wbs_cyc_i = wbm_cyc_i;
907 
assign wbm_dat_o = wbs_dat_o;
908 
assign wbm_ack_o = wbs_ack_o;
909 
`endif
910 
 
911 112 unneback 
`ifdef SHADOW_RAM
912 
wire [31:0] wbs_ram_dat_o;
913 
wire        wbs_ram_ack_o;
914 
wire [31:0] wbs_sdram_dat_o;
915 
wire        wbs_sdram_ack_o;
916 
assign select_sdram = wbs_adr_i > (`RAM_MEM_SIZE-1);
917 
assign wbs_dat_o = select_sdram ? wbs_sdram_dat_o : wbs_ram_dat_o;
918 
assign wbs_ack_o = select_sdram ? wbs_sdram_ack_o : wbs_ram_ack_o;
919 
`endif
920 
 
921 111 unneback 
`ifdef RAM
922 
`define MODULE wb_b3_ram_be
923 
`VLBASE`MODULE
924 
`undef MODULE
925 
# (
926 
    .adr_size(`RAM_ADR_SIZE),
927 
    .mem_size(`RAM_MEM_SIZE),
928 
    .memory_init(`RAM_MEM_INIT),
929 
    .memory_file(`RAM_MEM_INIT_FILE)
930 
)
931 
ram0 (
932 
    .wbs_dat_i(wbs_dat_i),
933 
    .wbs_adr_i(wbs_adr_i),
934 
    .wbs_cti_i(wbs_cti_i),
935 
    .wbs_bte_i(wbs_bte_i),
936 
    .wbs_sel_i(wbs_sel_i),
937 
    .wbs_we_i(wbs_we_i),
938 
    .wbs_stb_i(wbs_stb_i),
939 
    .wbs_cyc_i(wbs_cyc_i),
940 
    .wbs_dat_o(wbs_dat_o),
941 
    .wbs_ack_o(wbs_ack_o),
942 
    .wb_clk(mem_clk),
943 
    .wb_rst(mem_rst));
944 112 unneback 
`else
945 
`ifdef SHADOW_RAM
946 
`define MODULE wb_b3_ram_be
947 
`VLBASE`MODULE
948 
`undef MODULE
949 
# (
950 
    .adr_size(`RAM_ADR_SIZE),
951 
    .mem_size(`RAM_MEM_SIZE),
952 
    .memory_init(`RAM_MEM_INIT),
953 
    .memory_file(`RAM_MEM_INIT_FILE)
954 
)
955 
ram0 (
956 
    .wbs_dat_i(wbs_dat_i),
957 
    .wbs_adr_i(wbs_adr_i[`WB_RAM_ADR_SIZE-2-1:0]),
958 
    .wbs_cti_i(wbs_cti_i),
959 
    .wbs_bte_i(wbs_bte_i),
960 
    .wbs_sel_i(wbs_sel_i),
961 
    .wbs_we_i(wbs_we_i),
962 
    .wbs_stb_i(wbs_stb_i),
963 
    .wbs_cyc_i(wbs_cyc_i & ~select_sdram),
964 
    .wbs_dat_o(wbs_ram_dat_o),
965 
    .wbs_ack_o(wbs_ram_ack_o),
966 
    .wb_clk(mem_clk),
967 
    .wb_rst(mem_rst));
968 111 unneback 
`endif
969 112 unneback 
`endif
970 111 unneback 
 
971 
`ifdef SDR
972 
`define MODULE sdr16
973 
`BASE`MODULE sdr16_0(
974 
`undef MODULE
975 
    // wisbone i/f
976 
    .dat_i(wbs_dat_i),
977 
    .adr_i({wbs_adr_i,1'b0}),
978 
    .sel_i(wbs_sel_i),
979 
`ifndef SDR_NO_BURST
980 
    .bte_i(wbs_bte_i),
981 
`endif
982 
    .we_i(wbs_we_i),
983 112 unneback 
`ifdef SHADOW_RAM
984 
    .cyc_i(wbs_cyc_i & select_sdram),
985 
`else
986 111 unneback 
    .cyc_i(wbs_cyc_i),
987 112 unneback 
`endif
988 111 unneback 
    .stb_i(wbs_stb_i),
989 112 unneback 
`ifdef SHADOW_RAM
990 
    .dat_o(wbs_sdram_dat_o),
991 
    .ack_o(wbs_sdram_ack_o),
992 
`else
993 111 unneback 
    .dat_o(wbs_dat_o),
994 
    .ack_o(wbs_ack_o),
995 112 unneback 
`endif
996 111 unneback 
    // SDR SDRAM
997 
    .ba(ba),
998 
    .a(a),
999 
    .cmd(cmd),
1000 
    .cke(cke),
1001 
    .cs_n(cs_n),
1002 
    .dqm(dqm),
1003 
    .dq_i(dq_i),
1004 
    .dq_o(dq_o),
1005 
    .dq_oe(dq_oe),
1006 
    // system
1007 
    .clk(mem_clk),
1008 
    .rst(mem_rst));
1009 
`endif
1010 
 
1011 
`ifdef DDR2
1012 
`endif
1013 
 
1014 
`ifdef DDR3
1015 112 unneback 
`ifdef DDR3_BOARD_2AGX125N
1016 
ddr3_2agx125n_if ddr3_0 (
1017 
    .wb_adr_i(wbs_adr_i),
1018 
    .wb_stb_i(wbs_stb_i),
1019 
`ifdef SHADOW_RAM
1020 
    .wb_cyc_i(wbs_cyc_i & select_sdram),
1021 
`else
1022 
    .wb_cyc_i(wbs_cyc_i),
1023 111 unneback 
`endif
1024 112 unneback 
    .wb_cti_i(wbs_cti_i),
1025 
    .wb_bte_i(wbs_bte_i),
1026 
    .wb_we_i (wbs_we_i),
1027 
    .wb_sel_i(wbs_sel_i),
1028 
    .wb_dat_i(wbs_dat_i),
1029 
`ifdef SHADOW_RAM
1030 
    .wb_dat_o(wbs_sdram_dat_o),
1031 
    .wb_ack_o(wbs_sdram_ack_o),
1032 
`else
1033 
    .wb_dat_o(wbs_dat_o),
1034 
    .wb_ack_o(wbs_ack_o),
1035 
`endif
1036 111 unneback 
 
1037 112 unneback 
    .mem_addr(mem_addr),
1038 
    .mem_ba(mem_ba),
1039 
    .mem_cas_n(mem_cas_n),
1040 
    .mem_cke(mem_cke),
1041 
    .mem_clk(mem_clk),
1042 
    .mem_clk_n(mem_clk_n),
1043 
    .mem_cs_n(mem_cs_n),
1044 
    .mem_dm(mem_dm),
1045 
    .mem_dq(mem_dq),
1046 
    .mem_dqs(mem_dqs),
1047 
    .mem_dqsn(mem_dqsn),
1048 
    .mem_odt(mem_odt),
1049 
    .mem_ras_n(mem_ras_n),
1050 
    .mem_reset_n(mem_reset_n),
1051 
    .mem_we_n(mem_we_n),
1052 
    .mem_ref_clk(mem_ref_clk), /* 100MHz */
1053 
 
1054 
    .wb_clk(mem_clk),
1055 
    .wb_rst(mem_rst));
1056 
`endif
1057 
`endif
1058 
 
1059 111 unneback 
endmodule

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