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1 2 sinx 
----------------------------------------------------------------------
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----                                                              ----
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----  VHDL Wishbone TESTBENCH                                     ----
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----                                                              ----
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----  This file is part of the vhdl_wb_tb project                 ----
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----  http://www.opencores.org/cores/vhdl_wb_tb/                  ----
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----                                                              ----
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----  This file contains the highest (top) module of the test     ----
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----  bench.                                                      ----
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----  It instantiates the design under test (DUT), instantiates   ----
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----  the stimulator module for test vector generation,           ----
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----  instantiates the verifier module for result comparison,     ----
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----  instantiates the test case top (testcase_top) bfm,          ----
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----  interconnects all three components, generates DUT-external  ----
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----  clocks and resets.                                          ----
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----                                                              ----
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----  To Do:                                                      ----
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----   -                                                          ----
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----                                                              ----
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----  Author(s):                                                  ----
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----      - Sinx, email@opencores.org                             ----
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----                                                              ----
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----------------------------------------------------------------------
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--    SVN information
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--
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--      $URL:  $
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-- $Revision:  $
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--     $Date:  $
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--   $Author:  $
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--       $Id:  $
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--
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----------------------------------------------------------------------
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----                                                              ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ----
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----                                                              ----
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---- This source file may be used and distributed without         ----
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---- restriction provided that this copyright statement is not    ----
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---- removed from the file and that any derivative work contains  ----
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---- the original copyright notice and the associated disclaimer. ----
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----                                                              ----
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---- This source file is free software; you can redistribute it   ----
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---- and/or modify it under the terms of the GNU Lesser General   ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any   ----
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---- later version.                                               ----
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----                                                              ----
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---- This source is distributed in the hope that it will be       ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
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---- PURPOSE.  See the GNU Lesser General Public License for more ----
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---- details.                                                     ----
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----                                                              ----
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---- You should have received a copy of the GNU Lesser General    ----
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---- Public License along with this source; if not, download it   ----
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---- from http://www.opencores.org/lgpl.shtml                     ----
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----                                                              ----
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.convert_pkg.all;
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use work.wishbone_pkg.all;
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use work.wishbone_bfm_pkg.all;
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-- entity ------------------------------------------------------------
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entity tb_top is
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  -- empty entity, since this is the simulation top and all test cases are defined
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  -- in the tc_xxx files.
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end entity tb_top;
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--=architecture===============================================================
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architecture rtl of tb_top is
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  --============================================================================
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  constant  g_wb_clock_period               : time     := 20.0 ns;   -- 50 mhz
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  --============================================================================
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  -- signal declaration
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  --============================================================================
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  -----------------------------------------------------------------------------
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  signal s_wb_bfm_out                 : wishbone_bfm_master_out_t; -- from testcase_top
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  signal s_wb_bfm_in                  : wishbone_bfm_master_in_t;  -- to testcase_top
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  signal s_wb_master_out              : wishbone_master_out_t;    -- from wb_decoder
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  signal s_wb_master_in               : wishbone_master_in_t;    -- to wb_decoder
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  constant number_of_wb_slaves_c      : integer := 2;
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  signal s_wb_slaves_in               : wishbone_slave_in_array_t (number_of_wb_slaves_c-1 downto 0);
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  signal s_wb_slaves_out              : wishbone_slave_out_array_t (number_of_wb_slaves_c-1 downto 0);
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  signal s_wb_clock                   : std_logic := '0';
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  signal s_wb_clock_locked            : std_logic := '0';
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  signal s_wb_reset_p1                : std_logic := '1';
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  signal s_wb_reset_p2                : std_logic := '1';
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  signal s_wb_reset                   : std_logic := '1';
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  constant number_of_stimulus_signals_c : integer := 8;
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  constant number_of_verify_signals_c   : integer := 8;
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  signal s_stimulus                   : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
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  signal s_verify                     : std_logic_vector(number_of_verify_signals_c-1 downto 0);
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  -----------------------------------------------------------------------------
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  -- other signals
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  -----------------------------------------------------------------------------
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begin
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  --============================================================================
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  --clocks---------------------------------------------------------------------
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  wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
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  begin
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    s_wb_clock        <= '0';
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    wait for g_wb_clock_period/2;
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    s_wb_clock        <= '1';
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    wait for g_wb_clock_period/2;
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    s_wb_clock_locked <= '1';
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  end process;
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  -----------------------------------------------------------------------------
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  synchronize_reset_proc : process(all)
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  begin
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    if (s_wb_clock_locked = '0') then
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      s_wb_reset_p1 <= '1';
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      s_wb_reset_p2 <= '1';
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    elsif (rising_edge(s_wb_clock)) then
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      s_wb_reset_p1 <= '0'; -- or s_tc_reset;
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      s_wb_reset_p2 <= s_wb_reset_p1;
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    end if;
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  end process;
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  s_wb_reset   <= s_wb_reset_p2;
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  -----------------------------------------------------------------------------
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  -- instance of test case "player"; runs tc_xxxx modules
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  testcase_top_inst : entity work.testcase_top
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    port map (
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      wb_o                => s_wb_bfm_out,
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      wb_i                => s_wb_bfm_in
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      );
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  -----------------------------------------------------------------------------
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  -- splits the test case wb bus for all stimulation and verifier modules.
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  -- decodes the given bits (g_decoded_address_msb:g_decoded_address_lsb) and#
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  -- compares them to 0..n, with n=(g_number_of_ports-1)
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  proc_readdata_decoder  : process (all)
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    begin
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      s_wb_bfm_in.dat <= (others => 'U');
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      s_wb_bfm_in.ack <= '1';
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      s_wb_bfm_in.clk <= s_wb_clock;
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      s_wb_bfm_in.int <= '0';
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      s_wb_bfm_in.rst <= s_wb_reset;
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      for I in number_of_wb_slaves_c-1 downto 0 loop
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        s_wb_slaves_in(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
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        s_wb_slaves_in(I).clk <= s_wb_clock;
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        s_wb_slaves_in(I).rst <= s_wb_reset OR s_wb_bfm_out.rst;
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        if ( s_wb_bfm_out.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
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          s_wb_bfm_in.dat <= s_wb_slaves_out(I).dat;
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          s_wb_bfm_in.ack <= s_wb_slaves_out(I).ack;
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          s_wb_slaves_in(I).dat <= s_wb_bfm_out.dat;
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          s_wb_slaves_in(I).tgd  <= s_wb_bfm_out.tgd;
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          s_wb_slaves_in(I).adr  <= s_wb_bfm_out.adr;
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          s_wb_slaves_in(I).cyc  <= s_wb_bfm_out.cyc;
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          s_wb_slaves_in(I).lock <= s_wb_bfm_out.lock;
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          s_wb_slaves_in(I).sel  <= s_wb_bfm_out.sel;
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          s_wb_slaves_in(I).stb  <= s_wb_bfm_out.stb;
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          s_wb_slaves_in(I).tga  <= s_wb_bfm_out.tga;
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          s_wb_slaves_in(I).tgc  <= s_wb_bfm_out.tgc;
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          s_wb_slaves_in(I).we   <= s_wb_bfm_out.we;
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        end if;
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      end loop;
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  end process;
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  -----------------------------------------------------------------------------
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  -- instance of design under test
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  core_top_inst : entity work.core_top
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    generic map(
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      g_number_of_in_signals              => number_of_stimulus_signals_c,
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      g_number_of_out_signals             => number_of_verify_signals_c
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      )
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    port map(
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      clock_i                             => s_wb_clock,
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      reset_i                             => s_wb_reset,
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      signals_i                           => s_stimulus,
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      signals_o                           => s_verify
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      );
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  -----------------------------------------------------------------------------
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  -- instance of stimulator
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  stimulator_inst : entity work.stimulator
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    generic map(
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      g_number_of_signals                 => number_of_stimulus_signals_c
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      )
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    port map(
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      wb_i                                => s_wb_slaves_in(0),
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      wb_o                                => s_wb_slaves_out(0),
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      signals_o                           => s_stimulus
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      );
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  -----------------------------------------------------------------------------
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  -- instance of stimulator
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  verifier_inst : entity work.verifier
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    generic map(
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      g_number_of_signals                 => number_of_verify_signals_c
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      )
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    port map(
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      wb_i                                => s_wb_slaves_in(1),
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      wb_o                                => s_wb_slaves_out(1),
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      signals_i                           => s_verify
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      );
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  -----------------------------------------------------------------------------
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  end rtl;
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--============================================================================
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-- end of file
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--============================================================================

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