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---------------------------------------------------------------------- 
----                                                              ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----                                                              ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----                                                              ---- 
----  This file contains the wishbone_bfm_pkg package and defines ----
----  wishbone transaction processes functions for simulation.    ---- 
----                                                              ---- 
----  To Do:                                                      ---- 
----   -                                                          ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----      - Sinx, sinx@opencores.org                              ---- 
----                                                              ---- 
---------------------------------------------------------------------- 
----    SVN information
----
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd $
---- $Revision: 20 $
----     $Date: 2018-08-01 11:58:41 +0200 (Wed, 01 Aug 2018) $
----   $Author: sinx $
----       $Id: wishbone_bfm_pkg.vhd 20 2018-08-01 09:58:41Z sinx $
---------------------------------------------------------------------- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- restriction provided that this copyright statement is not    ---- 
---- removed from the file and that any derivative work contains  ---- 
---- the original copyright notice and the associated disclaimer. ---- 
----                                                              ---- 
---- This source file is free software; you can redistribute it   ---- 
---- and/or modify it under the terms of the GNU Lesser General   ---- 
---- Public License as published by the Free Software Foundation; ---- 
---- either version 2.1 of the License, or (at your option) any   ---- 
---- later version.                                               ---- 
----                                                              ---- 
---- This source is distributed in the hope that it will be       ---- 
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
---- details.                                                     ---- 
----                                                              ---- 
---- You should have received a copy of the GNU Lesser General    ---- 
---- Public License along with this source; if not, download it   ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
----                                                              ---- 
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library work;
use work.my_project_pkg.all;
use work.wishbone_pkg.all;
use work.convert_pkg.all;
 
-- package -----------------------------------------------------------
package wishbone_bfm_pkg is
  -- defines output signals of wb bfm (simulation only)
  type wishbone_bfm_master_out_t is record
    -- 2.2.2 Signals Common to MASTER and SLAVE Interfaces 
    dat : wishbone_data_t; -- data []
    rst : std_logic; -- reset [mandatory RULE 3.40]
    tgd : wishbone_tag_data_t; -- data tag []
    -- 2.2.3 MASTER Signals
    adr : wishbone_address_t; -- address [optional]
    cyc : std_logic; -- cycle [mandatory RULE 3.40]
    lock: std_logic; -- lock []
    sel : wishbone_byte_select_t;
    stb : std_logic; -- strobe [mandatory RULE 3.40]
    tga : wishbone_tag_address_t; -- address tag []
    tgc : wishbone_tag_cycle_t; -- cycle tag []
    we  : std_logic; -- write enable []
  end record wishbone_bfm_master_out_t;
 
  -- defines input signals of wb bfm (simulation only)
  type wishbone_bfm_master_in_t is record
    -- 2.2.2 Signals Common to MASTER and SLAVE Interfaces 
    rst : std_logic; -- reset [mandatory RULE 3.40]
    clk : std_logic; -- clock [mandatory RULE 3.40]
    dat : wishbone_data_t; -- read data []
    tgd : wishbone_tag_data_t; -- read data tag []
    -- 2.2.4 SLAVE Signals 
    ack : std_logic; -- acknowledge [mandatory RULE 3.40]
    err : std_logic; -- error [optional PERMISSION 3.20]
    rty : std_logic; -- retry [optional PERMISSION 3.25]
    --stall : std_logic;
    int   : std_logic; -- interrupt [non WB signal]
  end record wishbone_bfm_master_in_t;
 
  -- define the idle state of wb bus
  constant wb_bfm_master_out_idle_c : wishbone_bfm_master_out_t := (
    dat  =>  wishbone_data_of_unused_address_c,
    rst  =>  '0',
    tgd  =>  (others=>'0'),
    adr  =>  (others=>'U'),
    cyc  =>  '0',
    lock =>  '0',
    sel  =>  (others=>'0'),
    stb  =>  '0',
    tga  =>  (others=>'0'),
    tgc  =>  (others=>'0'),
    we   =>  '0'
    );
  -- BUS FUNCTIONS -----------------------------------------------------
  ---------------------------------------------------------------------- 
  ---------------------------------------------------------------------- 
  -- generate single write cycle
  procedure wb_write(
    address_i                  : in  integer; -- address to write to
    data_i                     : in  integer; -- data value to be written
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- incoming wb signals
    display_error_message_i    : in  integer range 0 to 2 := 1; -- verbose mode; 2= print all activities; others: print nothing
    additional_error_message_i : in  string  := "" -- string to be added in front of generated message
    );
 
  -- generate single read cycle and verify read word with expected_data_i
  procedure wb_read(
    address_i                  : in  integer; -- address to read from
    expected_data_i            : in  integer; -- data to be compared to read data; if different an error message is generated
    signal i                   : in  wishbone_bfm_master_in_t;  -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- outgoing wb signals
    display_error_message_i    : in  integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
    additional_error_message_i : in  string  := ""; -- string to be added in front of generated message
    expected_data_mask_i       : in  integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
    );
 
  -- generate single read cycle and return read data via read_data_o
  procedure wb_read(
    address_i                  : in  integer; -- address to read from
    read_data_o                : out std_logic_vector (wishbone_data_width_c-1 downto 0); -- read data output
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t -- outgoing wb signals
    );
  ---------------------------------------------------------------------- 
end;
 
-- package body ------------------------------------------------------
package body wishbone_bfm_pkg is
  ---------------------------------------------------------------------- 
  ---------------------------------------------------------------------- 
  procedure wb_write(
    address_i                  : in  integer; -- address to write to
    data_i                     : in  integer; -- data value to be written
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- outgoing wb signals
    display_error_message_i    : in  integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
    additional_error_message_i : in  string  := "" -- string to be added in front of generated message
    ) is
    ---------------------------------------------------------------------- 
  begin
    o.adr       <= to_std_logic_vector(address_i, wishbone_address_width_c);
    o.dat       <= to_std_logic_vector(data_i, wishbone_data_width_c);
    o.we        <= '1';
    o.rst       <= '0';
    o.tgd       <= (others => '0');
    o.cyc       <= '1';
    o.lock      <= '1';
    o.sel       <= (others => '1');
    o.stb       <= '1';
    o.tga       <= (others => '0');
    o.tgc       <= (others => '0');
    if (display_error_message_i = 2) then
      report additional_error_message_i & " writing :" & to_string(data_i, 16, wishbone_data_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4);
    end if;
 
    -- ack handling
    loop
      wait until rising_edge(i.clk);
      if (i.ack = '1') then
        exit;
      end if;
    end loop;
    o           <= wb_bfm_master_out_idle_c; -- reset bus
  end wb_write;
  ----------------------------------------------------------------------
  ----------------------------------------------------------------------
  procedure wb_read(
    address_i   : in  integer;   -- address to read from
    read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0);-- read data output
    signal i    : in  wishbone_bfm_master_in_t;  -- incoming wb signals
    signal o    : out wishbone_bfm_master_out_t  -- outgoing wb signals
    ) is
    ----------------------------------------------------------------------
  begin
    o.adr       <= to_std_logic_vector(address_i, wishbone_address_width_c);
    o.dat       <= (others => 'U');
    o.we        <= '0';
    o.rst       <= '0';
    o.tgd       <= (others => '0');
    o.cyc       <= '1';
    o.lock      <= '1';
    o.sel       <= (others => '1');
    o.stb       <= '1';
    o.tga       <= (others => '0');
    o.tgc       <= (others => '0');
    -- ack handling
    loop
      wait until rising_edge(i.clk);
      read_data_o := i.dat;
      if (i.ack = '1') then
        exit;
      end if;
    end loop;
    o           <= wb_bfm_master_out_idle_c; -- reset bus
  end wb_read;
  ------------------------------------------------------------------------
  ------------------------------------------------------------------------
  procedure wb_read(
    address_i                  : in  integer; -- address to read from
    expected_data_i            : in  integer; -- data to be compared to read data; if different an error message is generated
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- outgoing wb signals
    display_error_message_i    : in  integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
    additional_error_message_i : in  string  := ""; -- string to be added in front of generated message
    expected_data_mask_i       : in  integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
    ) is
    ----------------------------------------------------------------------
    variable readdata_v : std_logic_vector (31 downto 0);
    variable diff_v     : integer;
    ----------------------------------------------------------------------
  begin
    wb_read(address_i,readdata_v,i,o); -- read from bus
 
    diff_v     := to_integer(readdata_v) - expected_data_i;
 
    if (display_error_message_i = 1) then -- output errors only
      if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
        report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
          " was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4)
          severity error;
      end if;
    elsif (display_error_message_i = 2) then  -- output all
      report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
        " was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
        severity note;
    elsif (display_error_message_i = 3) then  -- output filter
      if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_data_width_c)) /=
          to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
        report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
          " was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
          severity note;
      end if;
    elsif display_error_message_i = 4 then
      if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
        report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
          " was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
          severity error;
      end if;
    end if;
  end wb_read;
  --------------------------------------------------------------------
end package body;
----------------------------------------------------------------------
---- end of file                                                  ---- 
----------------------------------------------------------------------

Line No.	Rev	Author	Line
1	2	sinx	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- VHDL Wishbone TESTBENCH ----`
4			`---- ----`
5			`---- This file is part of the vhdl_wb_tb project ----`
6			`---- http://www.opencores.org/cores/vhdl_wb_tb/ ----`
7			`---- ----`
8			`---- This file contains the wishbone_bfm_pkg package and defines ----`
9			`---- wishbone transaction processes functions for simulation. ----`
10			`---- ----`
11			`---- To Do: ----`
12			`---- - ----`
13			`---- ----`
14			`---- Author(s): ----`
15	4	sinx	`---- - Sinx, sinx@opencores.org ----`
16	2	sinx	`---- ----`
17			`----------------------------------------------------------------------`
18	4	sinx	`---- SVN information`
19			`----`
20	14	sinx	`---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd $`
21			`---- $Revision: 20 $`
22			`---- $Date: 2018-08-01 11:58:41 +0200 (Wed, 01 Aug 2018) $`
23			`---- $Author: sinx $`
24			`---- $Id: wishbone_bfm_pkg.vhd 20 2018-08-01 09:58:41Z sinx $`
25	4	sinx	`----------------------------------------------------------------------`
26	2	sinx	`---- ----`
27			`---- Copyright (C) 2018 Authors and OPENCORES.ORG ----`
28			`---- ----`
29			`---- This source file may be used and distributed without ----`
30			`---- restriction provided that this copyright statement is not ----`
31			`---- removed from the file and that any derivative work contains ----`
32			`---- the original copyright notice and the associated disclaimer. ----`
33			`---- ----`
34			`---- This source file is free software; you can redistribute it ----`
35			`---- and/or modify it under the terms of the GNU Lesser General ----`
36			`---- Public License as published by the Free Software Foundation; ----`
37			`---- either version 2.1 of the License, or (at your option) any ----`
38			`---- later version. ----`
39			`---- ----`
40			`---- This source is distributed in the hope that it will be ----`
41			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
42			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
43			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
44			`---- details. ----`
45			`---- ----`
46			`---- You should have received a copy of the GNU Lesser General ----`
47			`---- Public License along with this source; if not, download it ----`
48			`---- from http://www.opencores.org/lgpl.shtml ----`
49			`---- ----`
50			`----------------------------------------------------------------------`
51
52			`-- library -----------------------------------------------------------`
53			`library ieee;`
54			`use ieee.std_logic_1164.all;`
55			`use ieee.numeric_std.all;`
56
57			`library work;`
58			`use work.my_project_pkg.all;`
59			`use work.wishbone_pkg.all;`
60			`use work.convert_pkg.all;`
61
62			`-- package -----------------------------------------------------------`
63			`package wishbone_bfm_pkg is`
64			`-- defines output signals of wb bfm (simulation only)`
65			`type wishbone_bfm_master_out_t is record`
66			`-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces`
67			`dat : wishbone_data_t; -- data []`
68			`rst : std_logic; -- reset [mandatory RULE 3.40]`
69			`tgd : wishbone_tag_data_t; -- data tag []`
70			`-- 2.2.3 MASTER Signals`
71			`adr : wishbone_address_t; -- address [optional]`
72			`cyc : std_logic; -- cycle [mandatory RULE 3.40]`
73			`lock: std_logic; -- lock []`
74			`sel : wishbone_byte_select_t;`
75			`stb : std_logic; -- strobe [mandatory RULE 3.40]`
76			`tga : wishbone_tag_address_t; -- address tag []`
77			`tgc : wishbone_tag_cycle_t; -- cycle tag []`
78			`we : std_logic; -- write enable []`
79			`end record wishbone_bfm_master_out_t;`
80
81			`-- defines input signals of wb bfm (simulation only)`
82			`type wishbone_bfm_master_in_t is record`
83			`-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces`
84			`rst : std_logic; -- reset [mandatory RULE 3.40]`
85			`clk : std_logic; -- clock [mandatory RULE 3.40]`
86			`dat : wishbone_data_t; -- read data []`
87			`tgd : wishbone_tag_data_t; -- read data tag []`
88			`-- 2.2.4 SLAVE Signals`
89			`ack : std_logic; -- acknowledge [mandatory RULE 3.40]`
90			`err : std_logic; -- error [optional PERMISSION 3.20]`
91			`rty : std_logic; -- retry [optional PERMISSION 3.25]`
92			`--stall : std_logic;`
93			`int : std_logic; -- interrupt [non WB signal]`
94			`end record wishbone_bfm_master_in_t;`
95
96			`-- define the idle state of wb bus`
97			`constant wb_bfm_master_out_idle_c : wishbone_bfm_master_out_t := (`
98	20	sinx	`dat => wishbone_data_of_unused_address_c,`
99			`rst => '0',`
100			`tgd => (others=>'0'),`
101			`adr => (others=>'U'),`
102			`cyc => '0',`
103			`lock => '0',`
104			`sel => (others=>'0'),`
105			`stb => '0',`
106			`tga => (others=>'0'),`
107			`tgc => (others=>'0'),`
108			`we => '0'`
109			`);`
110	2	sinx	`-- BUS FUNCTIONS -----------------------------------------------------`
111			`----------------------------------------------------------------------`
112	4	sinx	`----------------------------------------------------------------------`
113	2	sinx	`-- generate single write cycle`
114	4	sinx	`procedure wb_write(`
115			`address_i : in integer; -- address to write to`
116			`data_i : in integer; -- data value to be written`
117			`signal i : in wishbone_bfm_master_in_t; -- incoming wb signals`
118			`signal o : out wishbone_bfm_master_out_t; -- incoming wb signals`
119	20	sinx	`display_error_message_i : in integer range 0 to 2 := 1; -- verbose mode; 2= print all activities; others: print nothing`
120			`additional_error_message_i : in string := "" -- string to be added in front of generated message`
121	2	sinx	`);`
122
123			`-- generate single read cycle and verify read word with expected_data_i`
124	4	sinx	`procedure wb_read(`
125	20	sinx	`address_i : in integer; -- address to read from`
126			`expected_data_i : in integer; -- data to be compared to read data; if different an error message is generated`
127			`signal i : in wishbone_bfm_master_in_t; -- incoming wb signals`
128			`signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals`
129	4	sinx	`display_error_message_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.`
130	20	sinx	`additional_error_message_i : in string := ""; -- string to be added in front of generated message`
131			`expected_data_mask_i : in integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared`
132	2	sinx	`);`
133
134			`-- generate single read cycle and return read data via read_data_o`
135	4	sinx	`procedure wb_read(`
136	20	sinx	`address_i : in integer; -- address to read from`
137			`read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0); -- read data output`
138			`signal i : in wishbone_bfm_master_in_t; -- incoming wb signals`
139			`signal o : out wishbone_bfm_master_out_t -- outgoing wb signals`
140	2	sinx	`);`
141			`----------------------------------------------------------------------`
142			`end;`
143
144			`-- package body ------------------------------------------------------`
145			`package body wishbone_bfm_pkg is`
146			`----------------------------------------------------------------------`
147			`----------------------------------------------------------------------`
148	4	sinx	`procedure wb_write(`
149	20	sinx	`address_i : in integer; -- address to write to`
150			`data_i : in integer; -- data value to be written`
151			`signal i : in wishbone_bfm_master_in_t; -- incoming wb signals`
152			`signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals`
153			`display_error_message_i : in integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all`
154			`additional_error_message_i : in string := "" -- string to be added in front of generated message`
155	4	sinx	`) is`
156	2	sinx	`----------------------------------------------------------------------`
157	4	sinx	`begin`
158	2	sinx	`o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);`
159	20	sinx	`o.dat <= to_std_logic_vector(data_i, wishbone_data_width_c);`
160	2	sinx	`o.we <= '1';`
161			`o.rst <= '0';`
162			`o.tgd <= (others => '0');`
163			`o.cyc <= '1';`
164			`o.lock <= '1';`
165			`o.sel <= (others => '1');`
166			`o.stb <= '1';`
167			`o.tga <= (others => '0');`
168			`o.tgc <= (others => '0');`
169	4	sinx	`if (display_error_message_i = 2) then`
170	20	sinx	`report additional_error_message_i & " writing :" & to_string(data_i, 16, wishbone_data_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4);`
171	4	sinx	`end if;`
172	2	sinx
173	20	sinx	`-- ack handling`
174			`loop`
175			`wait until rising_edge(i.clk);`
176			`if (i.ack = '1') then`
177			`exit;`
178			`end if;`
179	4	sinx	`end loop;`
180	2	sinx	`o <= wb_bfm_master_out_idle_c; -- reset bus`
181	4	sinx	`end wb_write;`
182	2	sinx	`----------------------------------------------------------------------`
183			`----------------------------------------------------------------------`
184	4	sinx	`procedure wb_read(`
185	20	sinx	`address_i : in integer; -- address to read from`
186			`read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0);-- read data output`
187			`signal i : in wishbone_bfm_master_in_t; -- incoming wb signals`
188			`signal o : out wishbone_bfm_master_out_t -- outgoing wb signals`
189	4	sinx	`) is`
190	2	sinx	`----------------------------------------------------------------------`
191	4	sinx	`begin`
192	2	sinx	`o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);`
193			`o.dat <= (others => 'U');`
194			`o.we <= '0';`
195			`o.rst <= '0';`
196			`o.tgd <= (others => '0');`
197			`o.cyc <= '1';`
198			`o.lock <= '1';`
199			`o.sel <= (others => '1');`
200			`o.stb <= '1';`
201			`o.tga <= (others => '0');`
202			`o.tgc <= (others => '0');`
203			`-- ack handling`
204	20	sinx	`loop`
205			`wait until rising_edge(i.clk);`
206			`read_data_o := i.dat;`
207			`if (i.ack = '1') then`
208			`exit;`
209			`end if;`
210	4	sinx	`end loop;`
211	2	sinx	`o <= wb_bfm_master_out_idle_c; -- reset bus`
212	4	sinx	`end wb_read;`
213	2	sinx	`------------------------------------------------------------------------`
214			`------------------------------------------------------------------------`
215	4	sinx	`procedure wb_read(`
216	20	sinx	`address_i : in integer; -- address to read from`
217			`expected_data_i : in integer; -- data to be compared to read data; if different an error message is generated`
218			`signal i : in wishbone_bfm_master_in_t; -- incoming wb signals`
219			`signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals`
220			`display_error_message_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.`
221			`additional_error_message_i : in string := ""; -- string to be added in front of generated message`
222			`expected_data_mask_i : in integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared`
223	4	sinx	`) is`
224	2	sinx	`----------------------------------------------------------------------`
225	4	sinx	`variable readdata_v : std_logic_vector (31 downto 0);`
226			`variable diff_v : integer;`
227	2	sinx	`----------------------------------------------------------------------`
228	4	sinx	`begin`
229	2	sinx	`wb_read(address_i,readdata_v,i,o); -- read from bus`
230	20	sinx
231	2	sinx	`diff_v := to_integer(readdata_v) - expected_data_i;`
232
233	4	sinx	`if (display_error_message_i = 1) then -- output errors only`
234	20	sinx	`if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then`
235	4	sinx	`report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &`
236	20	sinx	`" was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4)`
237	4	sinx	`severity error;`
238			`end if;`
239			`elsif (display_error_message_i = 2) then -- output all`
240			`report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &`
241	20	sinx	`" was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)`
242	4	sinx	`severity note;`
243			`elsif (display_error_message_i = 3) then -- output filter`
244	20	sinx	`if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_data_width_c)) /=`
245			`to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then`
246	4	sinx	`report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &`
247	20	sinx	`" was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)`
248	4	sinx	`severity note;`
249			`end if;`
250			`elsif display_error_message_i = 4 then`
251	20	sinx	`if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then`
252	4	sinx	`report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &`
253	20	sinx	`" was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)`
254	4	sinx	`severity error;`
255			`end if;`
256			`end if;`
257			`end wb_read;`
258	2	sinx	`--------------------------------------------------------------------`
259			`end package body;`
260			`----------------------------------------------------------------------`
261			`---- end of file ----`
262			`----------------------------------------------------------------------`

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