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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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---- This file contains the highest (top) module of the test ----
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---- bench. ----
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---- It instantiates the design under test (DUT), instantiates ----
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---- the stimulator module for test vector generation, ----
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---- instantiates the verifier module for result comparison, ----
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---- instantiates the test case top (testcase_top) bfm, ----
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---- interconnects all three components, generates DUT-external ----
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---- clocks and resets. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Sinx, email@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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-- SVN information
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--
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-- $URL: $
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-- $Revision: $
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-- $Date: $
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-- $Author: $
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-- $Id: $
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--
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.convert_pkg.all;
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use work.wishbone_pkg.all;
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-- entity ------------------------------------------------------------
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entity top is
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port(
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clock_i : in std_logic;
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signals_i : in std_logic_vector(7 downto 0);
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signals_o : out std_logic_vector(7 downto 0)
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);
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end entity top;
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--=architecture===============================================================
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architecture rtl of top is
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--============================================================================
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-- signal declaration
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--============================================================================
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-- constant number_of_stimulus_signals_c : integer := 8;
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-- signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
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-----------------------------------------------------------------------------
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begin
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--============================================================================
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-- instance of design
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core_top_inst : entity work.core_top
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generic map(
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g_number_of_in_signals => 8,
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g_number_of_out_signals => 8
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)
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port map(
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clock_i => clock_i,
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reset_i => '0',
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signals_i => signals_i,
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signals_o => signals_o
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);
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-----------------------------------------------------------------------------
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end rtl;
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--============================================================================
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-- end of file
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--============================================================================
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