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[/] [video_stream_scaler/] [trunk/] [sim/] [rtl_sim/] [work/] [ram@fifo/] [_primary.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 tesla500
library verilog;
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use verilog.vl_types.all;
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entity ramFifo is
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    generic(
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        DATA_WIDTH      : integer := 8;
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        ADDRESS_WIDTH   : integer := 8;
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        BUFFER_SIZE     : integer := 2
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    );
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    port(
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        clk             : in     vl_logic;
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        rst             : in     vl_logic;
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        advanceRead1    : in     vl_logic;
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        advanceRead2    : in     vl_logic;
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        advanceWrite    : in     vl_logic;
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        forceRead       : in     vl_logic;
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        writeData       : in     vl_logic_vector;
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        writeAddress    : in     vl_logic_vector;
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        writeEnable     : in     vl_logic;
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        fillCount       : out    vl_logic_vector;
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        readData00      : out    vl_logic_vector;
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        readData01      : out    vl_logic_vector;
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        readData10      : out    vl_logic_vector;
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        readData11      : out    vl_logic_vector;
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        readAddress     : in     vl_logic_vector
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    );
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end ramFifo;

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