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Subversion Repositories virtual_rs232_terminal_with_lvds_lcd

[/] [virtual_rs232_terminal_with_lvds_lcd/] [trunk/] [rtl/] [ipcore_dir/] [coregen.cgc] - Blame information for rev 2

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   xilinx.com
   project
   coregen
   1.0
   
      
         LogoROM
         
         
         
         
            false
            0
            false
            false
            true
            0
            false
            false
            false
            8kx2
            0
            0
            Single_Port_ROM
            100
            false
            18
            18
            9
            false
            false
            false
            false
            false
            false
            false
            Use_ENA_Pin
            Always_Enabled
            100
            4096
            Minimum_Area
            0
            0
            Single_Bit_Error_Injection
            0
            18
            18
            CE
            CE
            false
            WRITE_FIRST
            WRITE_FIRST
            SYNC
            false
            0
            false
            D:\Dados\Energy Labs\FPGA\TFTLCD\MemoryInit\ellogo.coe
            true
            ALL
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xa3s400a
               aspartan3a
               ftg256
               -4
             
             
               BusFormatAngleBracketNotRipped
               Verilog
               true
               Foundation_ISE
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL_and_Verilog
               false
             
           
         
      
      
         fontrom
         
         
         
         
            false
            0
            false
            false
            true
            0
            false
            false
            false
            8kx2
            0
            0
            Single_Port_ROM
            100
            false
            8
            8
            9
            false
            false
            false
            false
            false
            false
            false
            Always_Enabled
            Always_Enabled
            100
            2048
            Minimum_Area
            0
            0
            Single_Bit_Error_Injection
            0
            8
            8
            CE
            CE
            false
            WRITE_FIRST
            WRITE_FIRST
            SYNC
            false
            0
            false
            D:\Dados\Energy Labs\FPGA\TFTLCD\MemoryInit\fontrom.coe
            true
            ALL
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xa3s400a
               aspartan3a
               ftg256
               -4
             
             
               BusFormatAngleBracketNotRipped
               Verilog
               true
               Foundation_ISE
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL_and_Verilog
               false
             
           
         
      
      
         textram
         
         
         
         
            false
            0
            false
            false
            true
            50
            false
            false
            false
            8kx2
            100
            0
            Simple_Dual_Port_RAM
            100
            false
            8
            8
            9
            false
            false
            false
            false
            false
            false
            false
            Use_ENA_Pin
            Use_ENB_Pin
            100
            4800
            Minimum_Area
            0
            0
            Single_Bit_Error_Injection
            0
            8
            8
            CE
            CE
            false
            READ_FIRST
            READ_FIRST
            SYNC
            false
            100
            false
            D:\Dados\Energy Labs\FPGA\TFTLCD\MemoryInit\preram.coe
            true
            ALL
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xa3s400a
               aspartan3a
               ftg256
               -4
             
             
               BusFormatAngleBracketNotRipped
               Verilog
               true
               Foundation_ISE
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL_and_Verilog
               false
             
           
            
               
                  apply_current_project_options_generator
               
               
                  customization_generator
                  
                     ./textram.mif
                     mif
                     Mon Feb 28 07:43:09 GMT 2011
                     0x943AF524
                  
               
               
                  ip_xco_generator
                  
                     ./textram.xco
                     xco
                     Mon Feb 28 07:43:10 GMT 2011
                     0xAADE01A5
                  
               
               
                  implementation_netlist_generator
                  
                     ./blk_mem_gen_ds512.pdf
                     pdf
                     Mon Feb 28 07:43:46 GMT 2011
                     0xDCFF7B3C
                  
                  
                     ./textram.asy
                     asy
                     Mon Feb 28 07:43:22 GMT 2011
                     0x5ED42EA8
                  
                  
                     ./textram.mif
                     mif
                     Mon Feb 28 07:43:29 GMT 2011
                     0x943AF524
                  
                  
                     ./textram.ngc
                     ngc
                     Mon Feb 28 07:43:52 GMT 2011
                     0xCEA19BE2
                  
                  
                     ./textram.sym
                     asy
                     unknown
                     Mon Feb 28 07:43:46 GMT 2011
                     0x73835740
                  
                  
                     ./textram.v
                     verilog
                     Mon Feb 28 07:43:46 GMT 2011
                     0x310778BB
                  
                  
                     ./textram.veo
                     veo
                     Mon Feb 28 07:43:46 GMT 2011
                     0x6AB4FB5C
                  
                  
                     ./textram.vhd
                     vhdl
                     Mon Feb 28 07:43:46 GMT 2011
                     0x9EFA9446
                  
                  
                     ./textram.vho
                     vho
                     Mon Feb 28 07:43:46 GMT 2011
                     0x781C124B
                  
               
               
                  instantiation_template_generator
                  
                     ./textram.veo
                     veo
                     Mon Feb 28 07:43:53 GMT 2011
                     0x6AB4FB5C
                  
                  
                     ./textram.vho
                     vho
                     Mon Feb 28 07:43:53 GMT 2011
                     0x781C124B
                  
               
               
                  xco_generator
                  
                     ./textram.xco
                     xco
                     Mon Feb 28 07:43:59 GMT 2011
                     0x0994CA56
                  
               
               
                  xmdf_generator
                  
                     ./textram_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Feb 28 07:43:59 GMT 2011
                     0x9ABD6823
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Feb 28 07:44:01 GMT 2011
                     0x0A4F015D
                  
                  
                     ./textram.gise
                     ignore
                     gise
                     Mon Feb 28 07:44:01 GMT 2011
                     0x8B8D396B
                  
                  
                     ./textram.xise
                     ignore
                     xise
                     Mon Feb 28 07:44:01 GMT 2011
                     0x4E3B3B5F
                  
               
               
                  deliver_readme_generator
                  
                     ./textram_readme.txt
                     ignore
                     txtReadme
                     txt
                     Mon Feb 28 07:44:01 GMT 2011
                     0x7782ECD7
                  
               
               
                  flist_generator
                  
                     ./textram_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Feb 28 07:44:01 GMT 2011
                     0xF3EF5DEA
                  
               
               
                  view_readme_generator
               
            
         
      
   
   
   
      
       
         coregen
         ./
         ./tmp/
         ./tmp/_cg
       
       
         xa3s400a
         aspartan3a
         ftg256
         -4
       
       
         BusFormatAngleBracketNotRipped
         Verilog
         true
         Foundation_ISE
         false
         false
         false
         Ngc
         false
       
       
         Behavioral
         VHDL_and_Verilog
         false
       
     
   


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Subversion Repositories virtual_rs232_terminal_with_lvds_lcd

[/] [virtual_rs232_terminal_with_lvds_lcd/] [trunk/] [rtl/] [ipcore_dir/] [coregen.cgc] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	racerxdl
2
3			`xilinx.com`
4			`project`
5			`coregen`
6			`1.0`
7
8
9			`LogoROM`
10
11
12
13
14			`false`
15			`0`
16			`false`
17			`false`
18			`true`
19			`0`
20			`false`
21			`false`
22			`false`
23			`8kx2`
24			`0`
25			`0`
26			`Single_Port_ROM`
27			`100`
28			`false`
29			`18`
30			`18`
31			`9`
32			`false`
33			`false`
34			`false`
35			`false`
36			`false`
37			`false`
38			`false`
39			`Use_ENA_Pin`
40			`Always_Enabled`
41			`100`
42			`4096`
43			`Minimum_Area`
44			`0`
45			`0`
46			`Single_Bit_Error_Injection`
47			`0`
48			`18`
49			`18`
50			`CE`
51			`CE`
52			`false`
53			`WRITE_FIRST`
54			`WRITE_FIRST`
55			`SYNC`
56			`false`
57			`0`
58			`false`
59			`D:\Dados\Energy Labs\FPGA\TFTLCD\MemoryInit\ellogo.coe`
60			`true`
61			`ALL`
62
63
64
65
66			`coregen`
67			`./`
68			`./tmp/`
69			`./tmp/_cg`
70
71
72			`xa3s400a`
73			`aspartan3a`
74			`ftg256`
75			`-4`
76
77
78			`BusFormatAngleBracketNotRipped`
79			`Verilog`
80			`true`
81			`Foundation_ISE`
82			`false`
83			`false`
84			`false`
85			`Ngc`
86			`false`
87
88
89			`Behavioral`
90			`VHDL_and_Verilog`
91			`false`
92
93
94
95
96
97			`fontrom`
98
99
100
101
102			`false`
103			`0`
104			`false`
105			`false`
106			`true`
107			`0`
108			`false`
109			`false`
110			`false`
111			`8kx2`
112			`0`
113			`0`
114			`Single_Port_ROM`
115			`100`
116			`false`
117			`8`
118			`8`
119			`9`
120			`false`
121			`false`
122			`false`
123			`false`
124			`false`
125			`false`
126			`false`
127			`Always_Enabled`
128			`Always_Enabled`
129			`100`
130			`2048`
131			`Minimum_Area`
132			`0`
133			`0`
134			`Single_Bit_Error_Injection`
135			`0`
136			`8`
137			`8`
138			`CE`
139			`CE`
140			`false`
141			`WRITE_FIRST`
142			`WRITE_FIRST`
143			`SYNC`
144			`false`
145			`0`
146			`false`
147			`D:\Dados\Energy Labs\FPGA\TFTLCD\MemoryInit\fontrom.coe`
148			`true`
149			`ALL`
150
151
152
153
154			`coregen`
155			`./`
156			`./tmp/`
157			`./tmp/_cg`
158
159
160			`xa3s400a`
161			`aspartan3a`
162			`ftg256`
163			`-4`
164
165
166			`BusFormatAngleBracketNotRipped`
167			`Verilog`
168			`true`
169			`Foundation_ISE`
170			`false`
171			`false`
172			`false`
173			`Ngc`
174			`false`
175
176
177			`Behavioral`
178			`VHDL_and_Verilog`
179			`false`
180
181
182
183
184
185			`textram`
186
187
188
189
190			`false`
191			`0`
192			`false`
193			`false`
194			`true`
195			`50`
196			`false`
197			`false`
198			`false`
199			`8kx2`
200			`100`
201			`0`
202			`Simple_Dual_Port_RAM`
203			`100`
204			`false`
205			`8`
206			`8`
207			`9`
208			`false`
209			`false`
210			`false`
211			`false`
212			`false`
213			`false`
214			`false`
215			`Use_ENA_Pin`
216			`Use_ENB_Pin`
217			`100`
218			`4800`
219			`Minimum_Area`
220			`0`
221			`0`
222			`Single_Bit_Error_Injection`
223			`0`
224			`8`
225			`8`
226			`CE`
227			`CE`
228			`false`
229			`READ_FIRST`
230			`READ_FIRST`
231			`SYNC`
232			`false`
233			`100`
234			`false`
235			`D:\Dados\Energy Labs\FPGA\TFTLCD\MemoryInit\preram.coe`
236			`true`
237			`ALL`
238
239
240
241
242			`coregen`
243			`./`
244			`./tmp/`
245			`./tmp/_cg`
246
247
248			`xa3s400a`
249			`aspartan3a`
250			`ftg256`
251			`-4`
252
253
254			`BusFormatAngleBracketNotRipped`
255			`Verilog`
256			`true`
257			`Foundation_ISE`
258			`false`
259			`false`
260			`false`
261			`Ngc`
262			`false`
263
264
265			`Behavioral`
266			`VHDL_and_Verilog`
267			`false`
268
269
270
271
272			`apply_current_project_options_generator`
273
274
275			`customization_generator`
276
277			`./textram.mif`
278			`mif`
279			`Mon Feb 28 07:43:09 GMT 2011`
280			`0x943AF524`
281
282
283
284			`ip_xco_generator`
285
286			`./textram.xco`
287			`xco`
288			`Mon Feb 28 07:43:10 GMT 2011`
289			`0xAADE01A5`
290
291
292
293			`implementation_netlist_generator`
294
295			`./blk_mem_gen_ds512.pdf`
296			`pdf`
297			`Mon Feb 28 07:43:46 GMT 2011`
298			`0xDCFF7B3C`
299
300
301			`./textram.asy`
302			`asy`
303			`Mon Feb 28 07:43:22 GMT 2011`
304			`0x5ED42EA8`
305
306
307			`./textram.mif`
308			`mif`
309			`Mon Feb 28 07:43:29 GMT 2011`
310			`0x943AF524`
311
312
313			`./textram.ngc`
314			`ngc`
315			`Mon Feb 28 07:43:52 GMT 2011`
316			`0xCEA19BE2`
317
318
319			`./textram.sym`
320			`asy`
321			`unknown`
322			`Mon Feb 28 07:43:46 GMT 2011`
323			`0x73835740`
324
325
326			`./textram.v`
327			`verilog`
328			`Mon Feb 28 07:43:46 GMT 2011`
329			`0x310778BB`
330
331
332			`./textram.veo`
333			`veo`
334			`Mon Feb 28 07:43:46 GMT 2011`
335			`0x6AB4FB5C`
336
337
338			`./textram.vhd`
339			`vhdl`
340			`Mon Feb 28 07:43:46 GMT 2011`
341			`0x9EFA9446`
342
343
344			`./textram.vho`
345			`vho`
346			`Mon Feb 28 07:43:46 GMT 2011`
347			`0x781C124B`
348
349
350
351			`instantiation_template_generator`
352
353			`./textram.veo`
354			`veo`
355			`Mon Feb 28 07:43:53 GMT 2011`
356			`0x6AB4FB5C`
357
358
359			`./textram.vho`
360			`vho`
361			`Mon Feb 28 07:43:53 GMT 2011`
362			`0x781C124B`
363
364
365
366			`xco_generator`
367
368			`./textram.xco`
369			`xco`
370			`Mon Feb 28 07:43:59 GMT 2011`
371			`0x0994CA56`
372
373
374
375			`xmdf_generator`
376
377			`./textram_xmdf.tcl`
378			`tclXmdf`
379			`tcl`
380			`Mon Feb 28 07:43:59 GMT 2011`
381			`0x9ABD6823`
382
383
384
385			`ise_generator`
386
387			`./_xmsgs/pn_parser.xmsgs`
388			`ignore`
389			`unknown`
390			`Mon Feb 28 07:44:01 GMT 2011`
391			`0x0A4F015D`
392
393
394			`./textram.gise`
395			`ignore`
396			`gise`
397			`Mon Feb 28 07:44:01 GMT 2011`
398			`0x8B8D396B`
399
400
401			`./textram.xise`
402			`ignore`
403			`xise`
404			`Mon Feb 28 07:44:01 GMT 2011`
405			`0x4E3B3B5F`
406
407
408
409			`deliver_readme_generator`
410
411			`./textram_readme.txt`
412			`ignore`
413			`txtReadme`
414			`txt`
415			`Mon Feb 28 07:44:01 GMT 2011`
416			`0x7782ECD7`
417
418
419
420			`flist_generator`
421
422			`./textram_flist.txt`
423			`ignore`
424			`txtFlist`
425			`txt`
426			`Mon Feb 28 07:44:01 GMT 2011`
427			`0xF3EF5DEA`
428
429
430
431			`view_readme_generator`
432
433
434
435
436
437
438
439
440
441			`coregen`
442			`./`
443			`./tmp/`
444			`./tmp/_cg`
445
446
447			`xa3s400a`
448			`aspartan3a`
449			`ftg256`
450			`-4`
451
452
453			`BusFormatAngleBracketNotRipped`
454			`Verilog`
455			`true`
456			`Foundation_ISE`
457			`false`
458			`false`
459			`false`
460			`Ngc`
461			`false`
462
463
464			`Behavioral`
465			`VHDL_and_Verilog`
466			`false`
467
468
469
470