Subversion Repositories virtual_rs232_terminal_with_lvds_lcd

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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

component textram

        port (

        clka: IN std_logic;

        ena: IN std_logic;

        wea: IN std_logic_VECTOR(0 downto 0);

        addra: IN std_logic_VECTOR(12 downto 0);

        dina: IN std_logic_VECTOR(7 downto 0);

        clkb: IN std_logic;

        enb: IN std_logic;

        addrb: IN std_logic_VECTOR(12 downto 0);

        doutb: OUT std_logic_VECTOR(7 downto 0));

end component;

-- Synplicity black box declaration

attribute syn_black_box : boolean;

attribute syn_black_box of textram: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : textram

                port map (

                        clka => clka,

                        ena => ena,

                        wea => wea,

                        addra => addra,

                        dina => dina,

                        clkb => clkb,

                        enb => enb,

                        addrb => addrb,

                        doutb => doutb);

-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file textram.vhd when simulating

-- the core, textram. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".