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--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief  Viterbi decoder RAM control
--! @author Markus Fehrenz
--! @date   2011/12/13
--!
--! @details Manage RAM behavior. Write and read data.
--! The decisions are sent to the traceback units
--! It is signaled if the data belongs to acquisition or window phase.
--!
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
use dec_viterbi.pkg_components.all;
 
 
entity ram_ctrl is
        port(
        clk       : in std_logic;
        rst       : in std_logic;
 
 
        --
        -- Slave data signals, delivers the LLR parity values.
        --
        s_axis_input_tvalid : in  std_logic;
        s_axis_input_tdata  : in  std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
        s_axis_input_tlast  : in  std_logic;
        s_axis_input_tready : out std_logic;
 
 
        --
        -- Master data signals for traceback units, delivers the decision vectors.
        --
        m_axis_output_tvalid       : out std_logic_vector(1 downto 0);
        m_axis_output_tdata        : out t_ram_rd_data;
        m_axis_output_tlast        : out std_logic_vector(1 downto 0);
        m_axis_output_tready       : in  std_logic_vector(1 downto 0);
 
        -- Signals the traceback unit when the decision bits do not belong to an acquisition.
        m_axis_output_window_tuser : out std_logic_vector(1 downto 0);
 
        -- Signals whether this is the last decision vector of the window.
        m_axis_output_last_tuser   : out std_logic_vector(1 downto 0);
 
 
        --
        -- Slave configuration signals, delivering the configuration data.
        --
 
        s_axis_ctrl_tvalid : in  std_logic;
        s_axis_ctrl_tdata  : in  std_logic_vector(31 downto 0);
        s_axis_ctrl_tready : out std_logic
);
end entity ram_ctrl;
 
 
architecture rtl of ram_ctrl is
 
        ------------------------
        -- Type definition
        ------------------------
 
        --
        -- Record contains runtime configuration.
        -- The input configuration is stored in a register.
        -- It is received from a AXI4-Stream interface from the top entity.
        --
        type trec_runtime_param is record
                window_length           : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
                acquisition_length      : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
        end record trec_runtime_param;
 
        -- Types for finite state machines
        type t_write_ram_fsm is (CONFIGURE, START, RUN, WAIT_FOR_TRACEBACK, WAIT_FOR_LAST_TRACEBACK);
        type t_read_ram_fsm is (WAIT_FOR_WINDOW, TRACEBACK, WAIT_FOR_RAM, FINISH);
        type t_read_ram_fsm_array is array (0 to 1) of t_read_ram_fsm;
 
        -- RAM controling types
        type t_ram_data    is array (3 downto 0) of std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
        type t_ram_addr    is array (3 downto 0) of unsigned(BW_MAX_WINDOW_LENGTH - 1  downto 0);
        type t_ram_rd_addr is array (1 downto 0) of unsigned(BW_MAX_WINDOW_LENGTH - 1  downto 0);
        type t_ram_ptr     is array (1 downto 0) of unsigned(1 downto 0);
        type t_ram_ptr_int is array (1 downto 0) of integer range 3 downto 0;
 
        type t_ram_data_cnt is array (1 downto 0) of integer range 2 * MAX_WINDOW_LENGTH downto 0;
 
 
        ------------------------
        -- Signal declaration
        ------------------------
 
        signal ram_buffer   : t_ram_rd_data;
        signal ram_buffer_full   : std_logic_vector(1 downto 0);
 
        signal config          : trec_runtime_param;
        signal write_ram_fsm   : t_write_ram_fsm;
        signal read_ram_fsm    : t_read_ram_fsm_array;
        signal wen_ram         : std_logic_vector(3 downto 0);
        signal addr            : t_ram_addr;
        signal q_reg           : t_ram_data;
 
        -- ram addess, number and data pointer
        signal write_ram_ptr  : unsigned(1 downto 0);
        signal read_ram_ptr   : t_ram_ptr;
        signal read_ram_ptr_d : t_ram_ptr;
        signal write_addr_ptr : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
        signal read_addr_ptr  : t_ram_rd_addr;
 
        -- internal signals of outputs
        signal m_axis_output_tvalid_int       : std_logic_vector(1 downto 0);
        signal m_axis_output_tlast_int       : std_logic_vector(1 downto 0);
        signal m_axis_output_window_tuser_int : std_logic_vector(1 downto 0);
        signal m_axis_output_last_tuser_int   : std_logic_vector(1 downto 0);
        signal s_axis_input_tready_int        : std_logic;
        signal s_axis_ctrl_tready_int         : std_logic;
 
        signal next_traceback : std_logic_vector(1 downto 0);
        signal write_window_complete : std_logic;
        signal write_last_window_complete : std_logic;
        signal last_of_block : std_logic;
        signal read_last_addr_ptr : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
begin
 
        m_axis_output_tvalid       <= m_axis_output_tvalid_int;
        m_axis_output_tlast        <= m_axis_output_tlast_int;
        m_axis_output_window_tuser <= m_axis_output_window_tuser_int;
        m_axis_output_last_tuser   <= m_axis_output_last_tuser_int;
        m_axis_output_tdata(0)     <= q_reg(to_integer(read_ram_ptr_d(0))) when ram_buffer_full(0) = '0' else ram_buffer(0);
        m_axis_output_tdata(1)     <= q_reg(to_integer(read_ram_ptr_d(1))) when ram_buffer_full(1) = '0' else ram_buffer(1);
 
 
        --
        -- When the output port is not ready to read the output of the RAM immediately
        -- we have to remember the output value of the RAM in an extra register.
        -- When the output is ready to read, we first use the ouput of the register
        -- and only then the output of the RAM again.
        --
        pr_buf_ram_output: process(clk) is
        begin
        if rising_edge(clk) then
                if rst = '1' then
                        ram_buffer <= (others => (others => '0'));
                        ram_buffer_full <= (others => '0');
                else
 
                        for i in 0 to 1 loop
                                if m_axis_output_tvalid_int(i) = '1' and m_axis_output_tready(i) = '0' and ram_buffer_full(i) = '0' then
                                        ram_buffer(i) <=  q_reg(to_integer(read_ram_ptr_d(i)));
                                        ram_buffer_full(i) <= '1';
                                end if;
 
                                if m_axis_output_tvalid_int(i) = '1' and m_axis_output_tready(i) = '1' and ram_buffer_full(i) = '1' then
                                        ram_buffer_full(i) <= '0';
                                end if;
                        end loop;
 
                end if;
        end if;
        end process pr_buf_ram_output;
 
        -----------------------------
        -- Manage writing from ACS --
        -----------------------------
        s_axis_input_tready_int <= '0' when (write_ram_fsm = CONFIGURE) or
                                   (write_ram_ptr = read_ram_ptr(0) and read_ram_fsm(0) /= WAIT_FOR_WINDOW) or
                                   (write_ram_ptr = read_ram_ptr(1) and read_ram_fsm(1) /= WAIT_FOR_WINDOW) or
                                    write_ram_fsm = WAIT_FOR_TRACEBACK or write_ram_fsm = WAIT_FOR_LAST_TRACEBACK else
                                   '1';
        s_axis_input_tready <= s_axis_input_tready_int;
 
        s_axis_ctrl_tready_int <= '1' when (read_ram_fsm(0) = WAIT_FOR_WINDOW and read_ram_fsm(1) = WAIT_FOR_WINDOW and write_ram_fsm = CONFIGURE) else
                                  '0';
        s_axis_ctrl_tready <= s_axis_ctrl_tready_int;
 
        -- Process for writing to the RAM
        pr_write_ram: process(clk) is
                variable v_window_length      : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
                variable v_acquisition_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
        begin
        if rising_edge(clk) then
                if rst = '1' then
                        write_ram_fsm         <= CONFIGURE;
                        write_addr_ptr        <= (others => '0');
                        write_ram_ptr         <= (others => '0');
                        wen_ram               <= (others => '0');
                        write_window_complete <= '0';
                        write_last_window_complete <= '0';
                        read_last_addr_ptr    <= (others => '0');
                else
 
                        case write_ram_fsm is
 
                        --
                        -- It is necessary to configure the decoder before each block
                        --
                        when CONFIGURE =>
                                write_window_complete <= '0';
                                write_last_window_complete <= '0';
                                if s_axis_ctrl_tvalid = '1' and s_axis_ctrl_tready_int = '1' then
                                        v_window_length           := unsigned(s_axis_ctrl_tdata(BW_MAX_WINDOW_LENGTH - 1 + 16 downto 16));
                                        v_acquisition_length      := unsigned(s_axis_ctrl_tdata(BW_MAX_WINDOW_LENGTH - 1      downto  0));
                                        write_addr_ptr            <= v_window_length - v_acquisition_length;
                                        config.window_length      <= v_window_length;
                                        config.acquisition_length <= v_acquisition_length;
                                        write_ram_fsm             <= START;
 
                                        wen_ram(to_integer(write_ram_ptr)) <= '1';
                                end if;
 
 
                        --
                        -- After the decoder is configured, the decoder is waiting for a new block.
                        -- When the AXIS handshake is there the packet transmission begins.
                        -- The first write is a special case, since writing data starts at the acquisition length.
                        -- There is no complete window available afterwards.
                        --
                        when START =>
                                if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
 
                                        if write_addr_ptr = config.window_length - 1 then
 
                                                -- When we switch to the next RAM, we reset the write addr.
                                                write_addr_ptr <= (others => '0');
 
                                                -- Switch to the next RAM.
                                                write_ram_ptr                          <= write_ram_ptr + 1;
                                                wen_ram(to_integer(write_ram_ptr))     <= '0';
                                                wen_ram(to_integer(write_ram_ptr + 1)) <= '1';
 
                                                write_ram_fsm  <= RUN;
                                        else
                                                write_addr_ptr <= write_addr_ptr + 1;
                                        end if;
                                end if;
 
 
                        --
                        -- The decoder is receiving data from the ACS.
                        --
                        when RUN =>
                                write_window_complete <= '0';
                                write_last_window_complete <= '0';
 
                                if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
                                        write_addr_ptr <= write_addr_ptr + 1;
 
                                        if write_addr_ptr = config.window_length - 1 then
 
                                                -- When we switch to the next RAM, we reset the write addr.
                                                write_addr_ptr <= (others => '0');
 
                                                -- Switch to the next RAM.
                                                write_ram_ptr                          <= write_ram_ptr + 1;
                                                wen_ram(to_integer(write_ram_ptr))     <= '0';
                                                wen_ram(to_integer(write_ram_ptr + 1)) <= '1';
 
                                                -- Indicate, that a complete window is within the RAM and traceback may start.
                                                write_window_complete <= '1';
 
                                                if read_ram_fsm(0) /= WAIT_FOR_WINDOW and read_ram_fsm(1) /= WAIT_FOR_WINDOW then
                                                        write_ram_fsm <= WAIT_FOR_TRACEBACK;
                                                end if;
 
                                        else
                                                write_addr_ptr <= write_addr_ptr + 1;
                                        end if;
 
                                        if s_axis_input_tlast = '1' then
                                                write_ram_fsm <= CONFIGURE;
                                                wen_ram       <= (others => '0');
 
                                                write_last_window_complete <= '1';
                                                if (read_ram_fsm(0) /= WAIT_FOR_WINDOW and read_ram_fsm(1) /= WAIT_FOR_WINDOW) or write_window_complete = '1' then
                                                        write_ram_fsm <= WAIT_FOR_LAST_TRACEBACK;
                                                end if;
                                                read_last_addr_ptr <= write_addr_ptr;
 
                                                write_addr_ptr <= (others => '0');
                                                write_ram_ptr                          <= write_ram_ptr + 1;
                                        end if;
                                end if;
 
                        when WAIT_FOR_TRACEBACK =>
                                if read_ram_fsm(0) = WAIT_FOR_WINDOW or read_ram_fsm(1) = WAIT_FOR_WINDOW then
                                        write_ram_fsm <= RUN;
                                        write_window_complete <= '0';
                                end if;
 
                        when WAIT_FOR_LAST_TRACEBACK =>
                                if read_ram_fsm(0) = WAIT_FOR_WINDOW or read_ram_fsm(1) = WAIT_FOR_WINDOW then
                                        write_ram_fsm <= CONFIGURE;
                                        write_last_window_complete <= '0';
                                end if;
 
                        end case;
                end if;
        end if;
        end process pr_write_ram;
 
 
        -------------------------------------------
        -- Manage reading from RAM for traceback --
        -------------------------------------------
 
        gen_read_ram: for i in 0 to 1 generate
                pr_read_ram: process(clk) is
                begin
                if rising_edge(clk) then
                        if rst = '1' then
                                read_addr_ptr(i) <= (others => '0');
                                read_ram_fsm(i)  <= WAIT_FOR_WINDOW;
                                m_axis_output_tvalid_int(i)       <= '0';
                                m_axis_output_tlast_int(i)        <= '0';
                                m_axis_output_window_tuser_int(i) <= '0';
                                m_axis_output_last_tuser_int(i)   <= '0';
                                read_ram_ptr(i)                   <= (others => '0');
                                read_ram_ptr_d(i)                 <= (others => '0');
                        else
 
                                read_ram_ptr_d(i) <= read_ram_ptr(i);
                                case read_ram_fsm(i) is
 
                                -- Wait for the next window to be ready within the RAM.
                                when WAIT_FOR_WINDOW =>
                                        read_addr_ptr(i) <= config.window_length - 1;
                                        m_axis_output_tlast_int(i) <= '0';
                                        m_axis_output_tvalid_int(i) <= '0';
                                        m_axis_output_last_tuser_int(i) <= '0';
                                        m_axis_output_window_tuser_int(i) <= '0';
                                        read_ram_ptr(i)   <= write_ram_ptr;
 
                                        -- We always start from the RAM, which was written last.
                                        if write_window_complete = '1' and next_traceback(i) = '1' then
                                                read_ram_ptr(i)   <= write_ram_ptr - 1;
                                                read_addr_ptr(i)            <= read_addr_ptr(i) - 1;
                                                read_ram_fsm(i)             <= TRACEBACK;
                                                m_axis_output_tvalid_int(i) <= '1';
                                        end if;
                                        if write_last_window_complete = '1' and next_traceback(i) = '1' then
                                                read_ram_ptr(i)   <= write_ram_ptr - 1;
                                                read_addr_ptr(i)            <= read_last_addr_ptr;
                                                read_ram_fsm(i)             <= TRACEBACK;
                                                m_axis_output_window_tuser_int(i) <= '1';
                                        end if;
 
                                -- Perform the Traceback on the RAM data of the first RAM we need for acquisition and traceback.
                                when TRACEBACK =>
                                        m_axis_output_tlast_int(i) <= '0';
                                        m_axis_output_last_tuser_int(i) <= '0';
                                        m_axis_output_tvalid_int(i) <= '1';
 
                                        if m_axis_output_tready(i) = '1' then
                                                if read_addr_ptr(i) = 0 then
                                                        if read_ram_fsm(1 - i) = TRACEBACK and read_ram_ptr(1 - i) = read_ram_ptr(i) - 1 then
                                                                read_ram_fsm(i) <= WAIT_FOR_RAM;
                                                        else
                                                                read_addr_ptr(i) <= config.window_length - 1;
                                                                read_ram_ptr(i)  <= read_ram_ptr(i) - 1;
                                                                read_ram_fsm(i)  <= FINISH;
                                                        end if;
                                                else
                                                        read_addr_ptr(i) <= read_addr_ptr(i) - 1;
                                                end if;
 
                                                -- Signal the traceback unit, acquisition is over.
                                                if read_addr_ptr(i) = config.window_length - config.acquisition_length - 1 then
                                                        m_axis_output_window_tuser_int(i) <= '1';
                                                end if;
                                        end if;
 
                                when WAIT_FOR_RAM =>
                                        m_axis_output_tvalid_int(i) <= '0';
                                        if read_ram_fsm(1 - i) /= TRACEBACK or read_ram_ptr(1 - i) /= read_ram_ptr(i) - 1 then
                                                read_addr_ptr(i) <= config.window_length - 1;
                                                read_ram_ptr(i)  <= read_ram_ptr(i) - 1;
                                                read_ram_fsm(i)  <= FINISH;
                                        end if;
 
                                -- Get the remaining values from the second RAM we need for traceback (no acquisition values in this RAM)
                                when FINISH =>
                                        if m_axis_output_tvalid_int(i) <= '0' then
                                                m_axis_output_tvalid_int(i) <= '1';
                                                read_addr_ptr(i) <= read_addr_ptr(i) - 1;
                                        end if;
                                        if m_axis_output_tready(i) = '1' then
 
                                                if read_addr_ptr(i) = config.window_length - config.acquisition_length then
                                                        m_axis_output_last_tuser_int(i) <= '1';
                                                        read_addr_ptr(i)        <= config.window_length - 1;
                                                        read_ram_fsm(i)         <= WAIT_FOR_WINDOW;
 
                                                        -- Check if the other read process finished processing.
                                                        if read_ram_fsm((i+1) mod 2) = WAIT_FOR_WINDOW and last_of_block = '1' then
                                                                m_axis_output_tlast_int(i) <= '1';
                                                        end if;
 
                                                else
                                                        read_addr_ptr(i) <= read_addr_ptr(i) - 1;
                                                end if;
                                        end if;
                                end case;
                        end if;
                end if;
                end process pr_read_ram;
        end generate gen_read_ram;
 
        -- This process decides which traceback unit is the next one to use.
        pr_next_traceback: process(clk) is
        begin
        if rising_edge(clk) then
                if rst = '1' then
                        next_traceback <= "01";
                        last_of_block  <= '0';
                else
                        if write_window_complete = '1' then
                                if next_traceback(0) = '1' then
                                        next_traceback(0) <= '0';
                                        next_traceback(1) <= '1';
                                else
                                        next_traceback(0) <= '1';
                                        next_traceback(1) <= '0';
                                end if;
                        end if;
 
                        if s_axis_input_tlast = '1' then
                                last_of_block <= '1';
                        end if;
 
                end if;
        end if;
        end process pr_next_traceback;
 
        ------------------------------
        --- Portmapping components ---
        ------------------------------
 
        gen_generic_sp_ram : for i in 0 to 3 generate
        begin
 
        addr(i) <= write_addr_ptr   when (write_ram_fsm = RUN or write_ram_fsm = START) and to_integer(write_ram_ptr) = i else
                   read_addr_ptr(0) when (to_integer(read_ram_ptr(0)) = i and (read_ram_fsm(0) = TRACEBACK or read_ram_fsm(0) = WAIT_FOR_RAM or read_ram_fsm(0) = FINISH)) or
                                         (next_traceback(0) = '1' and write_window_complete = '1' and to_integer(read_ram_ptr(0)) = i) else
                   read_addr_ptr(1);
 
        inst_generic_sp_ram : generic_sp_ram
        generic map(
                DISTR_RAM => DISTRIBUTED_RAM,
                WORDS     => MAX_WINDOW_LENGTH,
                BITWIDTH  => NUMBER_TRELLIS_STATES
        )
        port map(
                clk => clk,
                rst => rst,
                wen => wen_ram(i),
                en  => '1',
                a   => std_logic_vector(addr(i)),
                d   => s_axis_input_tdata,
                q   => q_reg(i)
        );
        end generate gen_generic_sp_ram;
 
end architecture rtl;

Line No.	Rev	Author	Line
1	2	mfehrenz	`--!`
2	6	mfehrenz	`--! Copyright (C) 2011 - 2014 Creonic GmbH`
3	2	mfehrenz	`--!`
4			`--! This file is part of the Creonic Viterbi Decoder, which is distributed`
5			`--! under the terms of the GNU General Public License version 2.`
6			`--!`
7			`--! @file`
8			`--! @brief Viterbi decoder RAM control`
9			`--! @author Markus Fehrenz`
10			`--! @date 2011/12/13`
11			`--!`
12			`--! @details Manage RAM behavior. Write and read data.`
13			`--! The decisions are sent to the traceback units`
14			`--! It is signaled if the data belongs to acquisition or window phase.`
15			`--!`
16
17			`library ieee;`
18			`use ieee.std_logic_1164.all;`
19			`use ieee.numeric_std.all;`
20
21			`library dec_viterbi;`
22			`use dec_viterbi.pkg_param.all;`
23			`use dec_viterbi.pkg_param_derived.all;`
24			`use dec_viterbi.pkg_types.all;`
25			`use dec_viterbi.pkg_components.all;`
26
27
28			`entity ram_ctrl is`
29			`port(`
30			`clk : in std_logic;`
31			`rst : in std_logic;`
32
33
34			`--`
35			`-- Slave data signals, delivers the LLR parity values.`
36			`--`
37			`s_axis_input_tvalid : in std_logic;`
38			`s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);`
39			`s_axis_input_tlast : in std_logic;`
40			`s_axis_input_tready : out std_logic;`
41
42
43			`--`
44			`-- Master data signals for traceback units, delivers the decision vectors.`
45			`--`
46			`m_axis_output_tvalid : out std_logic_vector(1 downto 0);`
47			`m_axis_output_tdata : out t_ram_rd_data;`
48			`m_axis_output_tlast : out std_logic_vector(1 downto 0);`
49			`m_axis_output_tready : in std_logic_vector(1 downto 0);`
50
51			`-- Signals the traceback unit when the decision bits do not belong to an acquisition.`
52			`m_axis_output_window_tuser : out std_logic_vector(1 downto 0);`
53
54			`-- Signals whether this is the last decision vector of the window.`
55			`m_axis_output_last_tuser : out std_logic_vector(1 downto 0);`
56
57
58			`--`
59			`-- Slave configuration signals, delivering the configuration data.`
60			`--`
61
62			`s_axis_ctrl_tvalid : in std_logic;`
63			`s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);`
64			`s_axis_ctrl_tready : out std_logic`
65			`);`
66			`end entity ram_ctrl;`
67
68
69			`architecture rtl of ram_ctrl is`
70
71			`------------------------`
72			`-- Type definition`
73			`------------------------`
74
75			`--`
76			`-- Record contains runtime configuration.`
77			`-- The input configuration is stored in a register.`
78			`-- It is received from a AXI4-Stream interface from the top entity.`
79			`--`
80			`type trec_runtime_param is record`
81			`window_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);`
82			`acquisition_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);`
83			`end record trec_runtime_param;`
84
85			`-- Types for finite state machines`
86	6	mfehrenz	`type t_write_ram_fsm is (CONFIGURE, START, RUN, WAIT_FOR_TRACEBACK, WAIT_FOR_LAST_TRACEBACK);`
87			`type t_read_ram_fsm is (WAIT_FOR_WINDOW, TRACEBACK, WAIT_FOR_RAM, FINISH);`
88			`type t_read_ram_fsm_array is array (0 to 1) of t_read_ram_fsm;`
89	2	mfehrenz
90			`-- RAM controling types`
91			`type t_ram_data is array (3 downto 0) of std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);`
92			`type t_ram_addr is array (3 downto 0) of unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);`
93			`type t_ram_rd_addr is array (1 downto 0) of unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);`
94			`type t_ram_ptr is array (1 downto 0) of unsigned(1 downto 0);`
95			`type t_ram_ptr_int is array (1 downto 0) of integer range 3 downto 0;`
96
97			`type t_ram_data_cnt is array (1 downto 0) of integer range 2 * MAX_WINDOW_LENGTH downto 0;`
98
99
100			`------------------------`
101			`-- Signal declaration`
102			`------------------------`
103
104	6	mfehrenz	`signal ram_buffer : t_ram_rd_data;`
105			`signal ram_buffer_full : std_logic_vector(1 downto 0);`
106
107	2	mfehrenz	`signal config : trec_runtime_param;`
108	6	mfehrenz	`signal write_ram_fsm : t_write_ram_fsm;`
109			`signal read_ram_fsm : t_read_ram_fsm_array;`
110			`signal wen_ram : std_logic_vector(3 downto 0);`
111	2	mfehrenz	`signal addr : t_ram_addr;`
112			`signal q_reg : t_ram_data;`
113
114			`-- ram addess, number and data pointer`
115	6	mfehrenz	`signal write_ram_ptr : unsigned(1 downto 0);`
116			`signal read_ram_ptr : t_ram_ptr;`
117			`signal read_ram_ptr_d : t_ram_ptr;`
118			`signal write_addr_ptr : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);`
119			`signal read_addr_ptr : t_ram_rd_addr;`
120	2	mfehrenz
121			`-- internal signals of outputs`
122	6	mfehrenz	`signal m_axis_output_tvalid_int : std_logic_vector(1 downto 0);`
123			`signal m_axis_output_tlast_int : std_logic_vector(1 downto 0);`
124			`signal m_axis_output_window_tuser_int : std_logic_vector(1 downto 0);`
125			`signal m_axis_output_last_tuser_int : std_logic_vector(1 downto 0);`
126			`signal s_axis_input_tready_int : std_logic;`
127			`signal s_axis_ctrl_tready_int : std_logic;`
128	2	mfehrenz
129	6	mfehrenz	`signal next_traceback : std_logic_vector(1 downto 0);`
130			`signal write_window_complete : std_logic;`
131			`signal write_last_window_complete : std_logic;`
132			`signal last_of_block : std_logic;`
133			`signal read_last_addr_ptr : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);`
134	2	mfehrenz	`begin`
135
136	6	mfehrenz	`m_axis_output_tvalid <= m_axis_output_tvalid_int;`
137			`m_axis_output_tlast <= m_axis_output_tlast_int;`
138			`m_axis_output_window_tuser <= m_axis_output_window_tuser_int;`
139			`m_axis_output_last_tuser <= m_axis_output_last_tuser_int;`
140			`m_axis_output_tdata(0) <= q_reg(to_integer(read_ram_ptr_d(0))) when ram_buffer_full(0) = '0' else ram_buffer(0);`
141			`m_axis_output_tdata(1) <= q_reg(to_integer(read_ram_ptr_d(1))) when ram_buffer_full(1) = '0' else ram_buffer(1);`
142	2	mfehrenz
143
144			`--`
145	6	mfehrenz	`-- When the output port is not ready to read the output of the RAM immediately`
146			`-- we have to remember the output value of the RAM in an extra register.`
147			`-- When the output is ready to read, we first use the ouput of the register`
148			`-- and only then the output of the RAM again.`
149	2	mfehrenz	`--`
150	6	mfehrenz	`pr_buf_ram_output: process(clk) is`
151	2	mfehrenz	`begin`
152			`if rising_edge(clk) then`
153			`if rst = '1' then`
154	6	mfehrenz	`ram_buffer <= (others => (others => '0'));`
155			`ram_buffer_full <= (others => '0');`
156			`else`
157	2	mfehrenz
158	6	mfehrenz	`for i in 0 to 1 loop`
159			`if m_axis_output_tvalid_int(i) = '1' and m_axis_output_tready(i) = '0' and ram_buffer_full(i) = '0' then`
160			`ram_buffer(i) <= q_reg(to_integer(read_ram_ptr_d(i)));`
161			`ram_buffer_full(i) <= '1';`
162			`end if;`
163	2	mfehrenz
164	6	mfehrenz	`if m_axis_output_tvalid_int(i) = '1' and m_axis_output_tready(i) = '1' and ram_buffer_full(i) = '1' then`
165			`ram_buffer_full(i) <= '0';`
166			`end if;`
167			`end loop;`
168	2	mfehrenz
169	6	mfehrenz	`end if;`
170			`end if;`
171			`end process pr_buf_ram_output;`
172	2	mfehrenz
173	6	mfehrenz	`-----------------------------`
174			`-- Manage writing from ACS --`
175			`-----------------------------`
176			`s_axis_input_tready_int <= '0' when (write_ram_fsm = CONFIGURE) or`
177			`(write_ram_ptr = read_ram_ptr(0) and read_ram_fsm(0) /= WAIT_FOR_WINDOW) or`
178			`(write_ram_ptr = read_ram_ptr(1) and read_ram_fsm(1) /= WAIT_FOR_WINDOW) or`
179			`write_ram_fsm = WAIT_FOR_TRACEBACK or write_ram_fsm = WAIT_FOR_LAST_TRACEBACK else`
180			`'1';`
181			`s_axis_input_tready <= s_axis_input_tready_int;`
182	2	mfehrenz
183	6	mfehrenz	`s_axis_ctrl_tready_int <= '1' when (read_ram_fsm(0) = WAIT_FOR_WINDOW and read_ram_fsm(1) = WAIT_FOR_WINDOW and write_ram_fsm = CONFIGURE) else`
184			`'0';`
185			`s_axis_ctrl_tready <= s_axis_ctrl_tready_int;`
186	2	mfehrenz
187	6	mfehrenz	`-- Process for writing to the RAM`
188			`pr_write_ram: process(clk) is`
189			`variable v_window_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);`
190			`variable v_acquisition_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);`
191			`begin`
192			`if rising_edge(clk) then`
193			`if rst = '1' then`
194			`write_ram_fsm <= CONFIGURE;`
195			`write_addr_ptr <= (others => '0');`
196			`write_ram_ptr <= (others => '0');`
197			`wen_ram <= (others => '0');`
198			`write_window_complete <= '0';`
199			`write_last_window_complete <= '0';`
200			`read_last_addr_ptr <= (others => '0');`
201	2	mfehrenz	`else`
202
203	6	mfehrenz	`case write_ram_fsm is`
204	2	mfehrenz
205			`--`
206			`-- It is necessary to configure the decoder before each block`
207			`--`
208			`when CONFIGURE =>`
209	6	mfehrenz	`write_window_complete <= '0';`
210			`write_last_window_complete <= '0';`
211			`if s_axis_ctrl_tvalid = '1' and s_axis_ctrl_tready_int = '1' then`
212			`v_window_length := unsigned(s_axis_ctrl_tdata(BW_MAX_WINDOW_LENGTH - 1 + 16 downto 16));`
213			`v_acquisition_length := unsigned(s_axis_ctrl_tdata(BW_MAX_WINDOW_LENGTH - 1 downto 0));`
214			`write_addr_ptr <= v_window_length - v_acquisition_length;`
215			`config.window_length <= v_window_length;`
216			`config.acquisition_length <= v_acquisition_length;`
217			`write_ram_fsm <= START;`
218
219			`wen_ram(to_integer(write_ram_ptr)) <= '1';`
220	2	mfehrenz	`end if;`
221
222	6	mfehrenz
223	2	mfehrenz	`--`
224	6	mfehrenz	`-- After the decoder is configured, the decoder is waiting for a new block.`
225			`-- When the AXIS handshake is there the packet transmission begins.`
226			`-- The first write is a special case, since writing data starts at the acquisition length.`
227			`-- There is no complete window available afterwards.`
228	2	mfehrenz	`--`
229			`when START =>`
230			`if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then`
231
232	6	mfehrenz	`if write_addr_ptr = config.window_length - 1 then`
233	2	mfehrenz
234	6	mfehrenz	`-- When we switch to the next RAM, we reset the write addr.`
235			`write_addr_ptr <= (others => '0');`
236
237			`-- Switch to the next RAM.`
238			`write_ram_ptr <= write_ram_ptr + 1;`
239			`wen_ram(to_integer(write_ram_ptr)) <= '0';`
240			`wen_ram(to_integer(write_ram_ptr + 1)) <= '1';`
241
242			`write_ram_fsm <= RUN;`
243	2	mfehrenz	`else`
244	6	mfehrenz	`write_addr_ptr <= write_addr_ptr + 1;`
245	2	mfehrenz	`end if;`
246			`end if;`
247
248	6	mfehrenz
249	2	mfehrenz	`--`
250	6	mfehrenz	`-- The decoder is receiving data from the ACS.`
251	2	mfehrenz	`--`
252	6	mfehrenz	`when RUN =>`
253			`write_window_complete <= '0';`
254			`write_last_window_complete <= '0';`
255	2	mfehrenz
256	6	mfehrenz	`if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then`
257			`write_addr_ptr <= write_addr_ptr + 1;`
258	2	mfehrenz
259	6	mfehrenz	`if write_addr_ptr = config.window_length - 1 then`
260
261			`-- When we switch to the next RAM, we reset the write addr.`
262			`write_addr_ptr <= (others => '0');`
263
264			`-- Switch to the next RAM.`
265			`write_ram_ptr <= write_ram_ptr + 1;`
266			`wen_ram(to_integer(write_ram_ptr)) <= '0';`
267			`wen_ram(to_integer(write_ram_ptr + 1)) <= '1';`
268
269			`-- Indicate, that a complete window is within the RAM and traceback may start.`
270			`write_window_complete <= '1';`
271
272			`if read_ram_fsm(0) /= WAIT_FOR_WINDOW and read_ram_fsm(1) /= WAIT_FOR_WINDOW then`
273			`write_ram_fsm <= WAIT_FOR_TRACEBACK;`
274	2	mfehrenz	`end if;`
275
276			`else`
277			`write_addr_ptr <= write_addr_ptr + 1;`
278			`end if;`
279
280	6	mfehrenz	`if s_axis_input_tlast = '1' then`
281			`write_ram_fsm <= CONFIGURE;`
282			`wen_ram <= (others => '0');`
283	2	mfehrenz
284	6	mfehrenz	`write_last_window_complete <= '1';`
285			`if (read_ram_fsm(0) /= WAIT_FOR_WINDOW and read_ram_fsm(1) /= WAIT_FOR_WINDOW) or write_window_complete = '1' then`
286			`write_ram_fsm <= WAIT_FOR_LAST_TRACEBACK;`
287	2	mfehrenz	`end if;`
288	6	mfehrenz	`read_last_addr_ptr <= write_addr_ptr;`
289	2	mfehrenz
290	6	mfehrenz	`write_addr_ptr <= (others => '0');`
291			`write_ram_ptr <= write_ram_ptr + 1;`
292			`end if;`
293			`end if;`
294	2	mfehrenz
295	6	mfehrenz	`when WAIT_FOR_TRACEBACK =>`
296			`if read_ram_fsm(0) = WAIT_FOR_WINDOW or read_ram_fsm(1) = WAIT_FOR_WINDOW then`
297			`write_ram_fsm <= RUN;`
298			`write_window_complete <= '0';`
299	2	mfehrenz	`end if;`
300
301	6	mfehrenz	`when WAIT_FOR_LAST_TRACEBACK =>`
302			`if read_ram_fsm(0) = WAIT_FOR_WINDOW or read_ram_fsm(1) = WAIT_FOR_WINDOW then`
303			`write_ram_fsm <= CONFIGURE;`
304			`write_last_window_complete <= '0';`
305			`end if;`
306	2	mfehrenz
307	6	mfehrenz	`end case;`
308			`end if;`
309			`end if;`
310			`end process pr_write_ram;`
311	2	mfehrenz
312
313	6	mfehrenz	`-------------------------------------------`
314			`-- Manage reading from RAM for traceback --`
315			`-------------------------------------------`
316	2	mfehrenz
317	6	mfehrenz	`gen_read_ram: for i in 0 to 1 generate`
318			`pr_read_ram: process(clk) is`
319			`begin`
320			`if rising_edge(clk) then`
321			`if rst = '1' then`
322			`read_addr_ptr(i) <= (others => '0');`
323			`read_ram_fsm(i) <= WAIT_FOR_WINDOW;`
324			`m_axis_output_tvalid_int(i) <= '0';`
325			`m_axis_output_tlast_int(i) <= '0';`
326			`m_axis_output_window_tuser_int(i) <= '0';`
327			`m_axis_output_last_tuser_int(i) <= '0';`
328			`read_ram_ptr(i) <= (others => '0');`
329			`read_ram_ptr_d(i) <= (others => '0');`
330			`else`
331
332			`read_ram_ptr_d(i) <= read_ram_ptr(i);`
333			`case read_ram_fsm(i) is`
334
335			`-- Wait for the next window to be ready within the RAM.`
336			`when WAIT_FOR_WINDOW =>`
337			`read_addr_ptr(i) <= config.window_length - 1;`
338			`m_axis_output_tlast_int(i) <= '0';`
339			`m_axis_output_tvalid_int(i) <= '0';`
340			`m_axis_output_last_tuser_int(i) <= '0';`
341			`m_axis_output_window_tuser_int(i) <= '0';`
342			`read_ram_ptr(i) <= write_ram_ptr;`
343
344			`-- We always start from the RAM, which was written last.`
345			`if write_window_complete = '1' and next_traceback(i) = '1' then`
346			`read_ram_ptr(i) <= write_ram_ptr - 1;`
347			`read_addr_ptr(i) <= read_addr_ptr(i) - 1;`
348			`read_ram_fsm(i) <= TRACEBACK;`
349			`m_axis_output_tvalid_int(i) <= '1';`
350	2	mfehrenz	`end if;`
351	6	mfehrenz	`if write_last_window_complete = '1' and next_traceback(i) = '1' then`
352			`read_ram_ptr(i) <= write_ram_ptr - 1;`
353			`read_addr_ptr(i) <= read_last_addr_ptr;`
354			`read_ram_fsm(i) <= TRACEBACK;`
355			`m_axis_output_window_tuser_int(i) <= '1';`
356			`end if;`
357	2	mfehrenz
358	6	mfehrenz	`-- Perform the Traceback on the RAM data of the first RAM we need for acquisition and traceback.`
359			`when TRACEBACK =>`
360			`m_axis_output_tlast_int(i) <= '0';`
361			`m_axis_output_last_tuser_int(i) <= '0';`
362			`m_axis_output_tvalid_int(i) <= '1';`
363
364			`if m_axis_output_tready(i) = '1' then`
365			`if read_addr_ptr(i) = 0 then`
366			`if read_ram_fsm(1 - i) = TRACEBACK and read_ram_ptr(1 - i) = read_ram_ptr(i) - 1 then`
367			`read_ram_fsm(i) <= WAIT_FOR_RAM;`
368			`else`
369			`read_addr_ptr(i) <= config.window_length - 1;`
370			`read_ram_ptr(i) <= read_ram_ptr(i) - 1;`
371			`read_ram_fsm(i) <= FINISH;`
372			`end if;`
373			`else`
374			`read_addr_ptr(i) <= read_addr_ptr(i) - 1;`
375			`end if;`
376
377			`-- Signal the traceback unit, acquisition is over.`
378			`if read_addr_ptr(i) = config.window_length - config.acquisition_length - 1 then`
379			`m_axis_output_window_tuser_int(i) <= '1';`
380			`end if;`
381	2	mfehrenz	`end if;`
382
383	6	mfehrenz	`when WAIT_FOR_RAM =>`
384			`m_axis_output_tvalid_int(i) <= '0';`
385			`if read_ram_fsm(1 - i) /= TRACEBACK or read_ram_ptr(1 - i) /= read_ram_ptr(i) - 1 then`
386			`read_addr_ptr(i) <= config.window_length - 1;`
387			`read_ram_ptr(i) <= read_ram_ptr(i) - 1;`
388			`read_ram_fsm(i) <= FINISH;`
389	2	mfehrenz	`end if;`
390
391	6	mfehrenz	`-- Get the remaining values from the second RAM we need for traceback (no acquisition values in this RAM)`
392			`when FINISH =>`
393			`if m_axis_output_tvalid_int(i) <= '0' then`
394			`m_axis_output_tvalid_int(i) <= '1';`
395			`read_addr_ptr(i) <= read_addr_ptr(i) - 1;`
396	2	mfehrenz	`end if;`
397	6	mfehrenz	`if m_axis_output_tready(i) = '1' then`
398	2	mfehrenz
399	6	mfehrenz	`if read_addr_ptr(i) = config.window_length - config.acquisition_length then`
400			`m_axis_output_last_tuser_int(i) <= '1';`
401			`read_addr_ptr(i) <= config.window_length - 1;`
402			`read_ram_fsm(i) <= WAIT_FOR_WINDOW;`
403
404			`-- Check if the other read process finished processing.`
405			`if read_ram_fsm((i+1) mod 2) = WAIT_FOR_WINDOW and last_of_block = '1' then`
406			`m_axis_output_tlast_int(i) <= '1';`
407			`end if;`
408
409			`else`
410			`read_addr_ptr(i) <= read_addr_ptr(i) - 1;`
411			`end if;`
412	2	mfehrenz	`end if;`
413	6	mfehrenz	`end case;`
414			`end if;`
415			`end if;`
416			`end process pr_read_ram;`
417			`end generate gen_read_ram;`
418	2	mfehrenz
419	6	mfehrenz	`-- This process decides which traceback unit is the next one to use.`
420			`pr_next_traceback: process(clk) is`
421			`begin`
422			`if rising_edge(clk) then`
423			`if rst = '1' then`
424			`next_traceback <= "01";`
425			`last_of_block <= '0';`
426			`else`
427			`if write_window_complete = '1' then`
428			`if next_traceback(0) = '1' then`
429			`next_traceback(0) <= '0';`
430			`next_traceback(1) <= '1';`
431			`else`
432			`next_traceback(0) <= '1';`
433			`next_traceback(1) <= '0';`
434	2	mfehrenz	`end if;`
435	6	mfehrenz	`end if;`
436
437			`if s_axis_input_tlast = '1' then`
438			`last_of_block <= '1';`
439			`end if;`
440
441	2	mfehrenz	`end if;`
442			`end if;`
443	6	mfehrenz	`end process pr_next_traceback;`
444	2	mfehrenz
445			`------------------------------`
446			`--- Portmapping components ---`
447			`------------------------------`
448
449			`gen_generic_sp_ram : for i in 0 to 3 generate`
450			`begin`
451	6	mfehrenz
452			`addr(i) <= write_addr_ptr when (write_ram_fsm = RUN or write_ram_fsm = START) and to_integer(write_ram_ptr) = i else`
453			`read_addr_ptr(0) when (to_integer(read_ram_ptr(0)) = i and (read_ram_fsm(0) = TRACEBACK or read_ram_fsm(0) = WAIT_FOR_RAM or read_ram_fsm(0) = FINISH)) or`
454			`(next_traceback(0) = '1' and write_window_complete = '1' and to_integer(read_ram_ptr(0)) = i) else`
455			`read_addr_ptr(1);`
456
457			`inst_generic_sp_ram : generic_sp_ram`
458	2	mfehrenz	`generic map(`
459			`DISTR_RAM => DISTRIBUTED_RAM,`
460			`WORDS => MAX_WINDOW_LENGTH,`
461			`BITWIDTH => NUMBER_TRELLIS_STATES`
462			`)`
463			`port map(`
464			`clk => clk,`
465			`rst => rst,`
466			`wen => wen_ram(i),`
467	6	mfehrenz	`en => '1',`
468	2	mfehrenz	`a => std_logic_vector(addr(i)),`
469	6	mfehrenz	`d => s_axis_input_tdata,`
470	2	mfehrenz	`q => q_reg(i)`
471			`);`
472			`end generate gen_generic_sp_ram;`
473
474			`end architecture rtl;`

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